drivers/gpu/drm/radeon/r300.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include <drm/radeon_drm.h>
  37 #include "r100_track.h"
  38 #include "r300d.h"
  39 #include "rv350d.h"
  40 #include "r300_reg_safe.h"
  41
  42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
  43  *
  44  * GPU Errata:
  45  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
  46  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
  47  *   However, scheduling such write to the ring seems harmless, i suspect
  48  *   the CP read collide with the flush somehow, or maybe the MC, hard to
  49  *   tell. (Jerome Glisse)
  50  */
  51
  52 /*
  53  * rv370,rv380 PCIE GART
  54  */
  55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  56
  57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
  58 {
  59         uint32_t tmp;
  60         int i;
  61
  62         /* Workaround HW bug do flush 2 times */
  63         for (i = 0; i < 2; i++) {
  64                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  65                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
  66                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  67                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  68         }
  69         mb();
  70 }
  71
  72 #define R300_PTE_WRITEABLE (1 << 2)
  73 #define R300_PTE_READABLE  (1 << 3)
  74
  75 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
  76                               uint64_t addr)
  77 {
  78         void __iomem *ptr = rdev->gart.ptr;
  79
  80         addr = (lower_32_bits(addr) >> 8) |
  81                ((upper_32_bits(addr) & 0xff) << 24) |
  82                R300_PTE_WRITEABLE | R300_PTE_READABLE;
  83         /* on x86 we want this to be CPU endian, on powerpc
  84          * on powerpc without HW swappers, it'll get swapped on way
  85          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
  86         writel(addr, ((void __iomem *)ptr) + (i * 4));
  87 }
  88
  89 int rv370_pcie_gart_init(struct radeon_device *rdev)
  90 {
  91         int r;
  92
  93         if (rdev->gart.robj) {
  94                 WARN(1, "RV370 PCIE GART already initialized\n");
  95                 return 0;
  96         }
  97         /* Initialize common gart structure */
  98         r = radeon_gart_init(rdev);
  99         if (r)
 100                 return r;
 101         r = rv370_debugfs_pcie_gart_info_init(rdev);
 102         if (r)
 103                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
 104         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 105         rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 106         rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 107         return radeon_gart_table_vram_alloc(rdev);
 108 }
 109
 110 int rv370_pcie_gart_enable(struct radeon_device *rdev)
 111 {
 112         uint32_t table_addr;
 113         uint32_t tmp;
 114         int r;
 115
 116         if (rdev->gart.robj == NULL) {
 117                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 118                 return -EINVAL;
 119         }
 120         r = radeon_gart_table_vram_pin(rdev);
 121         if (r)
 122                 return r;
 123         radeon_gart_restore(rdev);
 124         /* discard memory request outside of configured range */
 125         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 126         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 127         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
 128         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
 129         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
 130         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 131         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 132         table_addr = rdev->gart.table_addr;
 133         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
 134         /* FIXME: setup default page */
 135         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
 136         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
 137         /* Clear error */
 138         WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
 139         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 140         tmp |= RADEON_PCIE_TX_GART_EN;
 141         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 142         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 143         rv370_pcie_gart_tlb_flush(rdev);
 144         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 145                  (unsigned)(rdev->mc.gtt_size >> 20),
 146                  (unsigned long long)table_addr);
 147         rdev->gart.ready = true;
 148         return 0;
 149 }
 150
 151 void rv370_pcie_gart_disable(struct radeon_device *rdev)
 152 {
 153         u32 tmp;
 154
 155         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
 156         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
 157         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 158         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 159         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 160         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 161         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
 162         radeon_gart_table_vram_unpin(rdev);
 163 }
 164
 165 void rv370_pcie_gart_fini(struct radeon_device *rdev)
 166 {
 167         radeon_gart_fini(rdev);
 168         rv370_pcie_gart_disable(rdev);
 169         radeon_gart_table_vram_free(rdev);
 170 }
 171
 172 void r300_fence_ring_emit(struct radeon_device *rdev,
 173                           struct radeon_fence *fence)
 174 {
 175         struct radeon_ring *ring = &rdev->ring[fence->ring];
 176
 177         /* Who ever call radeon_fence_emit should call ring_lock and ask
 178          * for enough space (today caller are ib schedule and buffer move) */
 179         /* Write SC register so SC & US assert idle */
 180         radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
 181         radeon_ring_write(ring, 0);
 182         radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
 183         radeon_ring_write(ring, 0);
 184         /* Flush 3D cache */
 185         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 186         radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
 187         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 188         radeon_ring_write(ring, R300_ZC_FLUSH);
 189         /* Wait until IDLE & CLEAN */
 190         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 191         radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
 192                                  RADEON_WAIT_2D_IDLECLEAN |
 193                                  RADEON_WAIT_DMA_GUI_IDLE));
 194         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 195         radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
 196                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 197         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 198         radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
 199         /* Emit fence sequence & fire IRQ */
 200         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 201         radeon_ring_write(ring, fence->seq);
 202         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 203         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 204 }
 205
 206 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 207 {
 208         unsigned gb_tile_config;
 209         int r;
 210
 211         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 212         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 213         switch(rdev->num_gb_pipes) {
 214         case 2:
 215                 gb_tile_config |= R300_PIPE_COUNT_R300;
 216                 break;
 217         case 3:
 218                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 219                 break;
 220         case 4:
 221                 gb_tile_config |= R300_PIPE_COUNT_R420;
 222                 break;
 223         case 1:
 224         default:
 225                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 226                 break;
 227         }
 228
 229         r = radeon_ring_lock(rdev, ring, 64);
 230         if (r) {
 231                 return;
 232         }
 233         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 234         radeon_ring_write(ring,
 235                           RADEON_ISYNC_ANY2D_IDLE3D |
 236                           RADEON_ISYNC_ANY3D_IDLE2D |
 237                           RADEON_ISYNC_WAIT_IDLEGUI |
 238                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 239         radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
 240         radeon_ring_write(ring, gb_tile_config);
 241         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 242         radeon_ring_write(ring,
 243                           RADEON_WAIT_2D_IDLECLEAN |
 244                           RADEON_WAIT_3D_IDLECLEAN);
 245         radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
 246         radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
 247         radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
 248         radeon_ring_write(ring, 0);
 249         radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
 250         radeon_ring_write(ring, 0);
 251         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 252         radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 253         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 254         radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
 255         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 256         radeon_ring_write(ring,
 257                           RADEON_WAIT_2D_IDLECLEAN |
 258                           RADEON_WAIT_3D_IDLECLEAN);
 259         radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
 260         radeon_ring_write(ring, 0);
 261         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 262         radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 263         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 264         radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
 265         radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
 266         radeon_ring_write(ring,
 267                           ((6 << R300_MS_X0_SHIFT) |
 268                            (6 << R300_MS_Y0_SHIFT) |
 269                            (6 << R300_MS_X1_SHIFT) |
 270                            (6 << R300_MS_Y1_SHIFT) |
 271                            (6 << R300_MS_X2_SHIFT) |
 272                            (6 << R300_MS_Y2_SHIFT) |
 273                            (6 << R300_MSBD0_Y_SHIFT) |
 274                            (6 << R300_MSBD0_X_SHIFT)));
 275         radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
 276         radeon_ring_write(ring,
 277                           ((6 << R300_MS_X3_SHIFT) |
 278                            (6 << R300_MS_Y3_SHIFT) |
 279                            (6 << R300_MS_X4_SHIFT) |
 280                            (6 << R300_MS_Y4_SHIFT) |
 281                            (6 << R300_MS_X5_SHIFT) |
 282                            (6 << R300_MS_Y5_SHIFT) |
 283                            (6 << R300_MSBD1_SHIFT)));
 284         radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
 285         radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 286         radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
 287         radeon_ring_write(ring,
 288                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 289         radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
 290         radeon_ring_write(ring,
 291                           R300_GEOMETRY_ROUND_NEAREST |
 292                           R300_COLOR_ROUND_NEAREST);
 293         radeon_ring_unlock_commit(rdev, ring);
 294 }
 295
 296 static void r300_errata(struct radeon_device *rdev)
 297 {
 298         rdev->pll_errata = 0;
 299
 300         if (rdev->family == CHIP_R300 &&
 301             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
 302                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
 303         }
 304 }
 305
 306 int r300_mc_wait_for_idle(struct radeon_device *rdev)
 307 {
 308         unsigned i;
 309         uint32_t tmp;
 310
 311         for (i = 0; i < rdev->usec_timeout; i++) {
 312                 /* read MC_STATUS */
 313                 tmp = RREG32(RADEON_MC_STATUS);
 314                 if (tmp & R300_MC_IDLE) {
 315                         return 0;
 316                 }
 317                 DRM_UDELAY(1);
 318         }
 319         return -1;
 320 }
 321
 322 static void r300_gpu_init(struct radeon_device *rdev)
 323 {
 324         uint32_t gb_tile_config, tmp;
 325
 326         if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
 327             (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
 328                 /* r300,r350 */
 329                 rdev->num_gb_pipes = 2;
 330         } else {
 331                 /* rv350,rv370,rv380,r300 AD, r350 AH */
 332                 rdev->num_gb_pipes = 1;
 333         }
 334         rdev->num_z_pipes = 1;
 335         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 336         switch (rdev->num_gb_pipes) {
 337         case 2:
 338                 gb_tile_config |= R300_PIPE_COUNT_R300;
 339                 break;
 340         case 3:
 341                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 342                 break;
 343         case 4:
 344                 gb_tile_config |= R300_PIPE_COUNT_R420;
 345                 break;
 346         default:
 347         case 1:
 348                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 349                 break;
 350         }
 351         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
 352
 353         if (r100_gui_wait_for_idle(rdev)) {
 354                 printk(KERN_WARNING "Failed to wait GUI idle while "
 355                        "programming pipes. Bad things might happen.\n");
 356         }
 357
 358         tmp = RREG32(R300_DST_PIPE_CONFIG);
 359         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 360
 361         WREG32(R300_RB2D_DSTCACHE_MODE,
 362                R300_DC_AUTOFLUSH_ENABLE |
 363                R300_DC_DC_DISABLE_IGNORE_PE);
 364
 365         if (r100_gui_wait_for_idle(rdev)) {
 366                 printk(KERN_WARNING "Failed to wait GUI idle while "
 367                        "programming pipes. Bad things might happen.\n");
 368         }
 369         if (r300_mc_wait_for_idle(rdev)) {
 370                 printk(KERN_WARNING "Failed to wait MC idle while "
 371                        "programming pipes. Bad things might happen.\n");
 372         }
 373         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
 374                  rdev->num_gb_pipes, rdev->num_z_pipes);
 375 }
 376
 377 int r300_asic_reset(struct radeon_device *rdev)
 378 {
 379         struct r100_mc_save save;
 380         u32 status, tmp;
 381         int ret = 0;
 382
 383         status = RREG32(R_000E40_RBBM_STATUS);
 384         if (!G_000E40_GUI_ACTIVE(status)) {
 385                 return 0;
 386         }
 387         r100_mc_stop(rdev, &save);
 388         status = RREG32(R_000E40_RBBM_STATUS);
 389         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 390         /* stop CP */
 391         WREG32(RADEON_CP_CSQ_CNTL, 0);
 392         tmp = RREG32(RADEON_CP_RB_CNTL);
 393         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 394         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 395         WREG32(RADEON_CP_RB_WPTR, 0);
 396         WREG32(RADEON_CP_RB_CNTL, tmp);
 397         /* save PCI state */
 398         pci_save_state(rdev->pdev);
 399         /* disable bus mastering */
 400         r100_bm_disable(rdev);
 401         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 402                                         S_0000F0_SOFT_RESET_GA(1));
 403         RREG32(R_0000F0_RBBM_SOFT_RESET);
 404         mdelay(500);
 405         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 406         mdelay(1);
 407         status = RREG32(R_000E40_RBBM_STATUS);
 408         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 409         /* resetting the CP seems to be problematic sometimes it end up
 410          * hard locking the computer, but it's necessary for successful
 411          * reset more test & playing is needed on R3XX/R4XX to find a
 412          * reliable (if any solution)
 413          */
 414         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 415         RREG32(R_0000F0_RBBM_SOFT_RESET);
 416         mdelay(500);
 417         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 418         mdelay(1);
 419         status = RREG32(R_000E40_RBBM_STATUS);
 420         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 421         /* restore PCI & busmastering */
 422         pci_restore_state(rdev->pdev);
 423         r100_enable_bm(rdev);
 424         /* Check if GPU is idle */
 425         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 426                 dev_err(rdev->dev, "failed to reset GPU\n");
 427                 ret = -1;
 428         } else
 429                 dev_info(rdev->dev, "GPU reset succeed\n");
 430         r100_mc_resume(rdev, &save);
 431         return ret;
 432 }
 433
 434 /*
 435  * r300,r350,rv350,rv380 VRAM info
 436  */
 437 void r300_mc_init(struct radeon_device *rdev)
 438 {
 439         u64 base;
 440         u32 tmp;
 441
 442         /* DDR for all card after R300 & IGP */
 443         rdev->mc.vram_is_ddr = true;
 444         tmp = RREG32(RADEON_MEM_CNTL);
 445         tmp &= R300_MEM_NUM_CHANNELS_MASK;
 446         switch (tmp) {
 447         case 0: rdev->mc.vram_width = 64; break;
 448         case 1: rdev->mc.vram_width = 128; break;
 449         case 2: rdev->mc.vram_width = 256; break;
 450         default:  rdev->mc.vram_width = 128; break;
 451         }
 452         r100_vram_init_sizes(rdev);
 453         base = rdev->mc.aper_base;
 454         if (rdev->flags & RADEON_IS_IGP)
 455                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 456         radeon_vram_location(rdev, &rdev->mc, base);
 457         rdev->mc.gtt_base_align = 0;
 458         if (!(rdev->flags & RADEON_IS_AGP))
 459                 radeon_gtt_location(rdev, &rdev->mc);
 460         radeon_update_bandwidth_info(rdev);
 461 }
 462
 463 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 464 {
 465         uint32_t link_width_cntl, mask;
 466
 467         if (rdev->flags & RADEON_IS_IGP)
 468                 return;
 469
 470         if (!(rdev->flags & RADEON_IS_PCIE))
 471                 return;
 472
 473         /* FIXME wait for idle */
 474
 475         switch (lanes) {
 476         case 0:
 477                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
 478                 break;
 479         case 1:
 480                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
 481                 break;
 482         case 2:
 483                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
 484                 break;
 485         case 4:
 486                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
 487                 break;
 488         case 8:
 489                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
 490                 break;
 491         case 12:
 492                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
 493                 break;
 494         case 16:
 495         default:
 496                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
 497                 break;
 498         }
 499
 500         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 501
 502         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
 503             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
 504                 return;
 505
 506         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
 507                              RADEON_PCIE_LC_RECONFIG_NOW |
 508                              RADEON_PCIE_LC_RECONFIG_LATER |
 509                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
 510         link_width_cntl |= mask;
 511         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 512         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
 513                                                      RADEON_PCIE_LC_RECONFIG_NOW));
 514
 515         /* wait for lane set to complete */
 516         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 517         while (link_width_cntl == 0xffffffff)
 518                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 519
 520 }
 521
 522 int rv370_get_pcie_lanes(struct radeon_device *rdev)
 523 {
 524         u32 link_width_cntl;
 525
 526         if (rdev->flags & RADEON_IS_IGP)
 527                 return 0;
 528
 529         if (!(rdev->flags & RADEON_IS_PCIE))
 530                 return 0;
 531
 532         /* FIXME wait for idle */
 533
 534         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 535
 536         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
 537         case RADEON_PCIE_LC_LINK_WIDTH_X0:
 538                 return 0;
 539         case RADEON_PCIE_LC_LINK_WIDTH_X1:
 540                 return 1;
 541         case RADEON_PCIE_LC_LINK_WIDTH_X2:
 542                 return 2;
 543         case RADEON_PCIE_LC_LINK_WIDTH_X4:
 544                 return 4;
 545         case RADEON_PCIE_LC_LINK_WIDTH_X8:
 546                 return 8;
 547         case RADEON_PCIE_LC_LINK_WIDTH_X16:
 548         default:
 549                 return 16;
 550         }
 551 }
 552
 553 #if defined(CONFIG_DEBUG_FS)
 554 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
 555 {
 556         struct drm_info_node *node = (struct drm_info_node *) m->private;
 557         struct drm_device *dev = node->minor->dev;
 558         struct radeon_device *rdev = dev->dev_private;
 559         uint32_t tmp;
 560
 561         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 562         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
 563         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
 564         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
 565         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
 566         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
 567         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
 568         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
 569         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
 570         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
 571         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
 572         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
 573         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
 574         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
 575         return 0;
 576 }
 577
 578 static struct drm_info_list rv370_pcie_gart_info_list[] = {
 579         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
 580 };
 581 #endif
 582
 583 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 584 {
 585 #if defined(CONFIG_DEBUG_FS)
 586         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
 587 #else
 588         return 0;
 589 #endif
 590 }
 591
 592 static int r300_packet0_check(struct radeon_cs_parser *p,
 593                 struct radeon_cs_packet *pkt,
 594                 unsigned idx, unsigned reg)
 595 {
 596         struct radeon_cs_reloc *reloc;
 597         struct r100_cs_track *track;
 598         volatile uint32_t *ib;
 599         uint32_t tmp, tile_flags = 0;
 600         unsigned i;
 601         int r;
 602         u32 idx_value;
 603
 604         ib = p->ib.ptr;
 605         track = (struct r100_cs_track *)p->track;
 606         idx_value = radeon_get_ib_value(p, idx);
 607
 608         switch(reg) {
 609         case AVIVO_D1MODE_VLINE_START_END:
 610         case RADEON_CRTC_GUI_TRIG_VLINE:
 611                 r = r100_cs_packet_parse_vline(p);
 612                 if (r) {
 613                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 614                                         idx, reg);
 615                         radeon_cs_dump_packet(p, pkt);
 616                         return r;
 617                 }
 618                 break;
 619         case RADEON_DST_PITCH_OFFSET:
 620         case RADEON_SRC_PITCH_OFFSET:
 621                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 622                 if (r)
 623                         return r;
 624                 break;
 625         case R300_RB3D_COLOROFFSET0:
 626         case R300_RB3D_COLOROFFSET1:
 627         case R300_RB3D_COLOROFFSET2:
 628         case R300_RB3D_COLOROFFSET3:
 629                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
 630                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 631                 if (r) {
 632                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 633                                         idx, reg);
 634                         radeon_cs_dump_packet(p, pkt);
 635                         return r;
 636                 }
 637                 track->cb[i].robj = reloc->robj;
 638                 track->cb[i].offset = idx_value;
 639                 track->cb_dirty = true;
 640                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 641                 break;
 642         case R300_ZB_DEPTHOFFSET:
 643                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 644                 if (r) {
 645                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 646                                         idx, reg);
 647                         radeon_cs_dump_packet(p, pkt);
 648                         return r;
 649                 }
 650                 track->zb.robj = reloc->robj;
 651                 track->zb.offset = idx_value;
 652                 track->zb_dirty = true;
 653                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
 654                 break;
 655         case R300_TX_OFFSET_0:
 656         case R300_TX_OFFSET_0+4:
 657         case R300_TX_OFFSET_0+8:
 658         case R300_TX_OFFSET_0+12:
 659         case R300_TX_OFFSET_0+16:
 660         case R300_TX_OFFSET_0+20:
 661         case R300_TX_OFFSET_0+24:
 662         case R300_TX_OFFSET_0+28:
 663         case R300_TX_OFFSET_0+32:
 664         case R300_TX_OFFSET_0+36:
 665         case R300_TX_OFFSET_0+40:
 666         case R300_TX_OFFSET_0+44:
 667         case R300_TX_OFFSET_0+48:
 668         case R300_TX_OFFSET_0+52:
 669         case R300_TX_OFFSET_0+56:
 670         case R300_TX_OFFSET_0+60:
 671                 i = (reg - R300_TX_OFFSET_0) >> 2;
 672                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 673                 if (r) {
 674                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 675                                         idx, reg);
 676                         radeon_cs_dump_packet(p, pkt);
 677                         return r;
 678                 }
 679
 680                 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
 681                         ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
 682                                   ((idx_value & ~31) + (u32)reloc->gpu_offset);
 683                 } else {
 684                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
 685                                 tile_flags |= R300_TXO_MACRO_TILE;
 686                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
 687                                 tile_flags |= R300_TXO_MICRO_TILE;
 688                         else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
 689                                 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
 690
 691                         tmp = idx_value + ((u32)reloc->gpu_offset);
 692                         tmp |= tile_flags;
 693                         ib[idx] = tmp;
 694                 }
 695                 track->textures[i].robj = reloc->robj;
 696                 track->tex_dirty = true;
 697                 break;
 698         /* Tracked registers */
 699         case 0x2084:
 700                 /* VAP_VF_CNTL */
 701                 track->vap_vf_cntl = idx_value;
 702                 break;
 703         case 0x20B4:
 704                 /* VAP_VTX_SIZE */
 705                 track->vtx_size = idx_value & 0x7F;
 706                 break;
 707         case 0x2134:
 708                 /* VAP_VF_MAX_VTX_INDX */
 709                 track->max_indx = idx_value & 0x00FFFFFFUL;
 710                 break;
 711         case 0x2088:
 712                 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
 713                 if (p->rdev->family < CHIP_RV515)
 714                         goto fail;
 715                 track->vap_alt_nverts = idx_value & 0xFFFFFF;
 716                 break;
 717         case 0x43E4:
 718                 /* SC_SCISSOR1 */
 719                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
 720                 if (p->rdev->family < CHIP_RV515) {
 721                         track->maxy -= 1440;
 722                 }
 723                 track->cb_dirty = true;
 724                 track->zb_dirty = true;
 725                 break;
 726         case 0x4E00:
 727                 /* RB3D_CCTL */
 728                 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
 729                     p->rdev->cmask_filp != p->filp) {
 730                         DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
 731                         return -EINVAL;
 732                 }
 733                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
 734                 track->cb_dirty = true;
 735                 break;
 736         case 0x4E38:
 737         case 0x4E3C:
 738         case 0x4E40:
 739         case 0x4E44:
 740                 /* RB3D_COLORPITCH0 */
 741                 /* RB3D_COLORPITCH1 */
 742                 /* RB3D_COLORPITCH2 */
 743                 /* RB3D_COLORPITCH3 */
 744                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 745                         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 746                         if (r) {
 747                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 748                                           idx, reg);
 749                                 radeon_cs_dump_packet(p, pkt);
 750                                 return r;
 751                         }
 752
 753                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
 754                                 tile_flags |= R300_COLOR_TILE_ENABLE;
 755                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
 756                                 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
 757                         else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
 758                                 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 759
 760                         tmp = idx_value & ~(0x7 << 16);
 761                         tmp |= tile_flags;
 762                         ib[idx] = tmp;
 763                 }
 764                 i = (reg - 0x4E38) >> 2;
 765                 track->cb[i].pitch = idx_value & 0x3FFE;
 766                 switch (((idx_value >> 21) & 0xF)) {
 767                 case 9:
 768                 case 11:
 769                 case 12:
 770                         track->cb[i].cpp = 1;
 771                         break;
 772                 case 3:
 773                 case 4:
 774                 case 13:
 775                 case 15:
 776                         track->cb[i].cpp = 2;
 777                         break;
 778                 case 5:
 779                         if (p->rdev->family < CHIP_RV515) {
 780                                 DRM_ERROR("Invalid color buffer format (%d)!\n",
 781                                           ((idx_value >> 21) & 0xF));
 782                                 return -EINVAL;
 783                         }
 784                         /* Pass through. */
 785                 case 6:
 786                         track->cb[i].cpp = 4;
 787                         break;
 788                 case 10:
 789                         track->cb[i].cpp = 8;
 790                         break;
 791                 case 7:
 792                         track->cb[i].cpp = 16;
 793                         break;
 794                 default:
 795                         DRM_ERROR("Invalid color buffer format (%d) !\n",
 796                                   ((idx_value >> 21) & 0xF));
 797                         return -EINVAL;
 798                 }
 799                 track->cb_dirty = true;
 800                 break;
 801         case 0x4F00:
 802                 /* ZB_CNTL */
 803                 if (idx_value & 2) {
 804                         track->z_enabled = true;
 805                 } else {
 806                         track->z_enabled = false;
 807                 }
 808                 track->zb_dirty = true;
 809                 break;
 810         case 0x4F10:
 811                 /* ZB_FORMAT */
 812                 switch ((idx_value & 0xF)) {
 813                 case 0:
 814                 case 1:
 815                         track->zb.cpp = 2;
 816                         break;
 817                 case 2:
 818                         track->zb.cpp = 4;
 819                         break;
 820                 default:
 821                         DRM_ERROR("Invalid z buffer format (%d) !\n",
 822                                   (idx_value & 0xF));
 823                         return -EINVAL;
 824                 }
 825                 track->zb_dirty = true;
 826                 break;
 827         case 0x4F24:
 828                 /* ZB_DEPTHPITCH */
 829                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 830                         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 831                         if (r) {
 832                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 833                                           idx, reg);
 834                                 radeon_cs_dump_packet(p, pkt);
 835                                 return r;
 836                         }
 837
 838                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
 839                                 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
 840                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
 841                                 tile_flags |= R300_DEPTHMICROTILE_TILED;
 842                         else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
 843                                 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 844
 845                         tmp = idx_value & ~(0x7 << 16);
 846                         tmp |= tile_flags;
 847                         ib[idx] = tmp;
 848                 }
 849                 track->zb.pitch = idx_value & 0x3FFC;
 850                 track->zb_dirty = true;
 851                 break;
 852         case 0x4104:
 853                 /* TX_ENABLE */
 854                 for (i = 0; i < 16; i++) {
 855                         bool enabled;
 856
 857                         enabled = !!(idx_value & (1 << i));
 858                         track->textures[i].enabled = enabled;
 859                 }
 860                 track->tex_dirty = true;
 861                 break;
 862         case 0x44C0:
 863         case 0x44C4:
 864         case 0x44C8:
 865         case 0x44CC:
 866         case 0x44D0:
 867         case 0x44D4:
 868         case 0x44D8:
 869         case 0x44DC:
 870         case 0x44E0:
 871         case 0x44E4:
 872         case 0x44E8:
 873         case 0x44EC:
 874         case 0x44F0:
 875         case 0x44F4:
 876         case 0x44F8:
 877         case 0x44FC:
 878                 /* TX_FORMAT1_[0-15] */
 879                 i = (reg - 0x44C0) >> 2;
 880                 tmp = (idx_value >> 25) & 0x3;
 881                 track->textures[i].tex_coord_type = tmp;
 882                 switch ((idx_value & 0x1F)) {
 883                 case R300_TX_FORMAT_X8:
 884                 case R300_TX_FORMAT_Y4X4:
 885                 case R300_TX_FORMAT_Z3Y3X2:
 886                         track->textures[i].cpp = 1;
 887                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 888                         break;
 889                 case R300_TX_FORMAT_X16:
 890                 case R300_TX_FORMAT_FL_I16:
 891                 case R300_TX_FORMAT_Y8X8:
 892                 case R300_TX_FORMAT_Z5Y6X5:
 893                 case R300_TX_FORMAT_Z6Y5X5:
 894                 case R300_TX_FORMAT_W4Z4Y4X4:
 895                 case R300_TX_FORMAT_W1Z5Y5X5:
 896                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
 897                 case R300_TX_FORMAT_B8G8_B8G8:
 898                 case R300_TX_FORMAT_G8R8_G8B8:
 899                         track->textures[i].cpp = 2;
 900                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 901                         break;
 902                 case R300_TX_FORMAT_Y16X16:
 903                 case R300_TX_FORMAT_FL_I16A16:
 904                 case R300_TX_FORMAT_Z11Y11X10:
 905                 case R300_TX_FORMAT_Z10Y11X11:
 906                 case R300_TX_FORMAT_W8Z8Y8X8:
 907                 case R300_TX_FORMAT_W2Z10Y10X10:
 908                 case 0x17:
 909                 case R300_TX_FORMAT_FL_I32:
 910                 case 0x1e:
 911                         track->textures[i].cpp = 4;
 912                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 913                         break;
 914                 case R300_TX_FORMAT_W16Z16Y16X16:
 915                 case R300_TX_FORMAT_FL_R16G16B16A16:
 916                 case R300_TX_FORMAT_FL_I32A32:
 917                         track->textures[i].cpp = 8;
 918                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 919                         break;
 920                 case R300_TX_FORMAT_FL_R32G32B32A32:
 921                         track->textures[i].cpp = 16;
 922                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 923                         break;
 924                 case R300_TX_FORMAT_DXT1:
 925                         track->textures[i].cpp = 1;
 926                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
 927                         break;
 928                 case R300_TX_FORMAT_ATI2N:
 929                         if (p->rdev->family < CHIP_R420) {
 930                                 DRM_ERROR("Invalid texture format %u\n",
 931                                           (idx_value & 0x1F));
 932                                 return -EINVAL;
 933                         }
 934                         /* The same rules apply as for DXT3/5. */
 935                         /* Pass through. */
 936                 case R300_TX_FORMAT_DXT3:
 937                 case R300_TX_FORMAT_DXT5:
 938                         track->textures[i].cpp = 1;
 939                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
 940                         break;
 941                 default:
 942                         DRM_ERROR("Invalid texture format %u\n",
 943                                   (idx_value & 0x1F));
 944                         return -EINVAL;
 945                 }
 946                 track->tex_dirty = true;
 947                 break;
 948         case 0x4400:
 949         case 0x4404:
 950         case 0x4408:
 951         case 0x440C:
 952         case 0x4410:
 953         case 0x4414:
 954         case 0x4418:
 955         case 0x441C:
 956         case 0x4420:
 957         case 0x4424:
 958         case 0x4428:
 959         case 0x442C:
 960         case 0x4430:
 961         case 0x4434:
 962         case 0x4438:
 963         case 0x443C:
 964                 /* TX_FILTER0_[0-15] */
 965                 i = (reg - 0x4400) >> 2;
 966                 tmp = idx_value & 0x7;
 967                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 968                         track->textures[i].roundup_w = false;
 969                 }
 970                 tmp = (idx_value >> 3) & 0x7;
 971                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 972                         track->textures[i].roundup_h = false;
 973                 }
 974                 track->tex_dirty = true;
 975                 break;
 976         case 0x4500:
 977         case 0x4504:
 978         case 0x4508:
 979         case 0x450C:
 980         case 0x4510:
 981         case 0x4514:
 982         case 0x4518:
 983         case 0x451C:
 984         case 0x4520:
 985         case 0x4524:
 986         case 0x4528:
 987         case 0x452C:
 988         case 0x4530:
 989         case 0x4534:
 990         case 0x4538:
 991         case 0x453C:
 992                 /* TX_FORMAT2_[0-15] */
 993                 i = (reg - 0x4500) >> 2;
 994                 tmp = idx_value & 0x3FFF;
 995                 track->textures[i].pitch = tmp + 1;
 996                 if (p->rdev->family >= CHIP_RV515) {
 997                         tmp = ((idx_value >> 15) & 1) << 11;
 998                         track->textures[i].width_11 = tmp;
 999                         tmp = ((idx_value >> 16) & 1) << 11;
1000                         track->textures[i].height_11 = tmp;
1001
1002                         /* ATI1N */
1003                         if (idx_value & (1 << 14)) {
1004                                 /* The same rules apply as for DXT1. */
1005                                 track->textures[i].compress_format =
1006                                         R100_TRACK_COMP_DXT1;
1007                         }
1008                 } else if (idx_value & (1 << 14)) {
1009                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1010                         return -EINVAL;
1011                 }
1012                 track->tex_dirty = true;
1013                 break;
1014         case 0x4480:
1015         case 0x4484:
1016         case 0x4488:
1017         case 0x448C:
1018         case 0x4490:
1019         case 0x4494:
1020         case 0x4498:
1021         case 0x449C:
1022         case 0x44A0:
1023         case 0x44A4:
1024         case 0x44A8:
1025         case 0x44AC:
1026         case 0x44B0:
1027         case 0x44B4:
1028         case 0x44B8:
1029         case 0x44BC:
1030                 /* TX_FORMAT0_[0-15] */
1031                 i = (reg - 0x4480) >> 2;
1032                 tmp = idx_value & 0x7FF;
1033                 track->textures[i].width = tmp + 1;
1034                 tmp = (idx_value >> 11) & 0x7FF;
1035                 track->textures[i].height = tmp + 1;
1036                 tmp = (idx_value >> 26) & 0xF;
1037                 track->textures[i].num_levels = tmp;
1038                 tmp = idx_value & (1 << 31);
1039                 track->textures[i].use_pitch = !!tmp;
1040                 tmp = (idx_value >> 22) & 0xF;
1041                 track->textures[i].txdepth = tmp;
1042                 track->tex_dirty = true;
1043                 break;
1044         case R300_ZB_ZPASS_ADDR:
1045                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1046                 if (r) {
1047                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1048                                         idx, reg);
1049                         radeon_cs_dump_packet(p, pkt);
1050                         return r;
1051                 }
1052                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1053                 break;
1054         case 0x4e0c:
1055                 /* RB3D_COLOR_CHANNEL_MASK */
1056                 track->color_channel_mask = idx_value;
1057                 track->cb_dirty = true;
1058                 break;
1059         case 0x43a4:
1060                 /* SC_HYPERZ_EN */
1061                 /* r300c emits this register - we need to disable hyperz for it
1062                  * without complaining */
1063                 if (p->rdev->hyperz_filp != p->filp) {
1064                         if (idx_value & 0x1)
1065                                 ib[idx] = idx_value & ~1;
1066                 }
1067                 break;
1068         case 0x4f1c:
1069                 /* ZB_BW_CNTL */
1070                 track->zb_cb_clear = !!(idx_value & (1 << 5));
1071                 track->cb_dirty = true;
1072                 track->zb_dirty = true;
1073                 if (p->rdev->hyperz_filp != p->filp) {
1074                         if (idx_value & (R300_HIZ_ENABLE |
1075                                          R300_RD_COMP_ENABLE |
1076                                          R300_WR_COMP_ENABLE |
1077                                          R300_FAST_FILL_ENABLE))
1078                                 goto fail;
1079                 }
1080                 break;
1081         case 0x4e04:
1082                 /* RB3D_BLENDCNTL */
1083                 track->blend_read_enable = !!(idx_value & (1 << 2));
1084                 track->cb_dirty = true;
1085                 break;
1086         case R300_RB3D_AARESOLVE_OFFSET:
1087                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1088                 if (r) {
1089                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1090                                   idx, reg);
1091                         radeon_cs_dump_packet(p, pkt);
1092                         return r;
1093                 }
1094                 track->aa.robj = reloc->robj;
1095                 track->aa.offset = idx_value;
1096                 track->aa_dirty = true;
1097                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1098                 break;
1099         case R300_RB3D_AARESOLVE_PITCH:
1100                 track->aa.pitch = idx_value & 0x3FFE;
1101                 track->aa_dirty = true;
1102                 break;
1103         case R300_RB3D_AARESOLVE_CTL:
1104                 track->aaresolve = idx_value & 0x1;
1105                 track->aa_dirty = true;
1106                 break;
1107         case 0x4f30: /* ZB_MASK_OFFSET */
1108         case 0x4f34: /* ZB_ZMASK_PITCH */
1109         case 0x4f44: /* ZB_HIZ_OFFSET */
1110         case 0x4f54: /* ZB_HIZ_PITCH */
1111                 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1112                         goto fail;
1113                 break;
1114         case 0x4028:
1115                 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1116                         goto fail;
1117                 /* GB_Z_PEQ_CONFIG */
1118                 if (p->rdev->family >= CHIP_RV350)
1119                         break;
1120                 goto fail;
1121                 break;
1122         case 0x4be8:
1123                 /* valid register only on RV530 */
1124                 if (p->rdev->family == CHIP_RV530)
1125                         break;
1126                 /* fallthrough do not move */
1127         default:
1128                 goto fail;
1129         }
1130         return 0;
1131 fail:
1132         printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1133                reg, idx, idx_value);
1134         return -EINVAL;
1135 }
1136
1137 static int r300_packet3_check(struct radeon_cs_parser *p,
1138                               struct radeon_cs_packet *pkt)
1139 {
1140         struct radeon_cs_reloc *reloc;
1141         struct r100_cs_track *track;
1142         volatile uint32_t *ib;
1143         unsigned idx;
1144         int r;
1145
1146         ib = p->ib.ptr;
1147         idx = pkt->idx + 1;
1148         track = (struct r100_cs_track *)p->track;
1149         switch(pkt->opcode) {
1150         case PACKET3_3D_LOAD_VBPNTR:
1151                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1152                 if (r)
1153                         return r;
1154                 break;
1155         case PACKET3_INDX_BUFFER:
1156                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1157                 if (r) {
1158                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1159                         radeon_cs_dump_packet(p, pkt);
1160                         return r;
1161                 }
1162                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1163                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1164                 if (r) {
1165                         return r;
1166                 }
1167                 break;
1168         /* Draw packet */
1169         case PACKET3_3D_DRAW_IMMD:
1170                 /* Number of dwords is vtx_size * (num_vertices - 1)
1171                  * PRIM_WALK must be equal to 3 vertex data in embedded
1172                  * in cmd stream */
1173                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1174                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1175                         return -EINVAL;
1176                 }
1177                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1178                 track->immd_dwords = pkt->count - 1;
1179                 r = r100_cs_track_check(p->rdev, track);
1180                 if (r) {
1181                         return r;
1182                 }
1183                 break;
1184         case PACKET3_3D_DRAW_IMMD_2:
1185                 /* Number of dwords is vtx_size * (num_vertices - 1)
1186                  * PRIM_WALK must be equal to 3 vertex data in embedded
1187                  * in cmd stream */
1188                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1189                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1190                         return -EINVAL;
1191                 }
1192                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1193                 track->immd_dwords = pkt->count;
1194                 r = r100_cs_track_check(p->rdev, track);
1195                 if (r) {
1196                         return r;
1197                 }
1198                 break;
1199         case PACKET3_3D_DRAW_VBUF:
1200                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1201                 r = r100_cs_track_check(p->rdev, track);
1202                 if (r) {
1203                         return r;
1204                 }
1205                 break;
1206         case PACKET3_3D_DRAW_VBUF_2:
1207                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1208                 r = r100_cs_track_check(p->rdev, track);
1209                 if (r) {
1210                         return r;
1211                 }
1212                 break;
1213         case PACKET3_3D_DRAW_INDX:
1214                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1215                 r = r100_cs_track_check(p->rdev, track);
1216                 if (r) {
1217                         return r;
1218                 }
1219                 break;
1220         case PACKET3_3D_DRAW_INDX_2:
1221                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1222                 r = r100_cs_track_check(p->rdev, track);
1223                 if (r) {
1224                         return r;
1225                 }
1226                 break;
1227         case PACKET3_3D_CLEAR_HIZ:
1228         case PACKET3_3D_CLEAR_ZMASK:
1229                 if (p->rdev->hyperz_filp != p->filp)
1230                         return -EINVAL;
1231                 break;
1232         case PACKET3_3D_CLEAR_CMASK:
1233                 if (p->rdev->cmask_filp != p->filp)
1234                         return -EINVAL;
1235                 break;
1236         case PACKET3_NOP:
1237                 break;
1238         default:
1239                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1240                 return -EINVAL;
1241         }
1242         return 0;
1243 }
1244
1245 int r300_cs_parse(struct radeon_cs_parser *p)
1246 {
1247         struct radeon_cs_packet pkt;
1248         struct r100_cs_track *track;
1249         int r;
1250
1251         track = kzalloc(sizeof(*track), GFP_KERNEL);
1252         if (track == NULL)
1253                 return -ENOMEM;
1254         r100_cs_track_clear(p->rdev, track);
1255         p->track = track;
1256         do {
1257                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
1258                 if (r) {
1259                         return r;
1260                 }
1261                 p->idx += pkt.count + 2;
1262                 switch (pkt.type) {
1263                 case RADEON_PACKET_TYPE0:
1264                         r = r100_cs_parse_packet0(p, &pkt,
1265                                                   p->rdev->config.r300.reg_safe_bm,
1266                                                   p->rdev->config.r300.reg_safe_bm_size,
1267                                                   &r300_packet0_check);
1268                         break;
1269                 case RADEON_PACKET_TYPE2:
1270                         break;
1271                 case RADEON_PACKET_TYPE3:
1272                         r = r300_packet3_check(p, &pkt);
1273                         break;
1274                 default:
1275                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1276                         return -EINVAL;
1277                 }
1278                 if (r) {
1279                         return r;
1280                 }
1281         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1282         return 0;
1283 }
1284
1285 void r300_set_reg_safe(struct radeon_device *rdev)
1286 {
1287         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1288         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1289 }
1290
1291 void r300_mc_program(struct radeon_device *rdev)
1292 {
1293         struct r100_mc_save save;
1294         int r;
1295
1296         r = r100_debugfs_mc_info_init(rdev);
1297         if (r) {
1298                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1299         }
1300
1301         /* Stops all mc clients */
1302         r100_mc_stop(rdev, &save);
1303         if (rdev->flags & RADEON_IS_AGP) {
1304                 WREG32(R_00014C_MC_AGP_LOCATION,
1305                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1306                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1307                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1308                 WREG32(R_00015C_AGP_BASE_2,
1309                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1310         } else {
1311                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1312                 WREG32(R_000170_AGP_BASE, 0);
1313                 WREG32(R_00015C_AGP_BASE_2, 0);
1314         }
1315         /* Wait for mc idle */
1316         if (r300_mc_wait_for_idle(rdev))
1317                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1318         /* Program MC, should be a 32bits limited address space */
1319         WREG32(R_000148_MC_FB_LOCATION,
1320                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1321                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1322         r100_mc_resume(rdev, &save);
1323 }
1324
1325 void r300_clock_startup(struct radeon_device *rdev)
1326 {
1327         u32 tmp;
1328
1329         if (radeon_dynclks != -1 && radeon_dynclks)
1330                 radeon_legacy_set_clock_gating(rdev, 1);
1331         /* We need to force on some of the block */
1332         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1333         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1334         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1335                 tmp |= S_00000D_FORCE_VAP(1);
1336         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1337 }
1338
1339 static int r300_startup(struct radeon_device *rdev)
1340 {
1341         int r;
1342
1343         /* set common regs */
1344         r100_set_common_regs(rdev);
1345         /* program mc */
1346         r300_mc_program(rdev);
1347         /* Resume clock */
1348         r300_clock_startup(rdev);
1349         /* Initialize GPU configuration (# pipes, ...) */
1350         r300_gpu_init(rdev);
1351         /* Initialize GART (initialize after TTM so we can allocate
1352          * memory through TTM but finalize after TTM) */
1353         if (rdev->flags & RADEON_IS_PCIE) {
1354                 r = rv370_pcie_gart_enable(rdev);
1355                 if (r)
1356                         return r;
1357         }
1358
1359         if (rdev->family == CHIP_R300 ||
1360             rdev->family == CHIP_R350 ||
1361             rdev->family == CHIP_RV350)
1362                 r100_enable_bm(rdev);
1363
1364         if (rdev->flags & RADEON_IS_PCI) {
1365                 r = r100_pci_gart_enable(rdev);
1366                 if (r)
1367                         return r;
1368         }
1369
1370         /* allocate wb buffer */
1371         r = radeon_wb_init(rdev);
1372         if (r)
1373                 return r;
1374
1375         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1376         if (r) {
1377                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1378                 return r;
1379         }
1380
1381         /* Enable IRQ */
1382         if (!rdev->irq.installed) {
1383                 r = radeon_irq_kms_init(rdev);
1384                 if (r)
1385                         return r;
1386         }
1387
1388         r100_irq_set(rdev);
1389         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1390         /* 1M ring buffer */
1391         r = r100_cp_init(rdev, 1024 * 1024);
1392         if (r) {
1393                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1394                 return r;
1395         }
1396
1397         r = radeon_ib_pool_init(rdev);
1398         if (r) {
1399                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1400                 return r;
1401         }
1402
1403         return 0;
1404 }
1405
1406 int r300_resume(struct radeon_device *rdev)
1407 {
1408         int r;
1409
1410         /* Make sur GART are not working */
1411         if (rdev->flags & RADEON_IS_PCIE)
1412                 rv370_pcie_gart_disable(rdev);
1413         if (rdev->flags & RADEON_IS_PCI)
1414                 r100_pci_gart_disable(rdev);
1415         /* Resume clock before doing reset */
1416         r300_clock_startup(rdev);
1417         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1418         if (radeon_asic_reset(rdev)) {
1419                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1420                         RREG32(R_000E40_RBBM_STATUS),
1421                         RREG32(R_0007C0_CP_STAT));
1422         }
1423         /* post */
1424         radeon_combios_asic_init(rdev->ddev);
1425         /* Resume clock after posting */
1426         r300_clock_startup(rdev);
1427         /* Initialize surface registers */
1428         radeon_surface_init(rdev);
1429
1430         rdev->accel_working = true;
1431         r = r300_startup(rdev);
1432         if (r) {
1433                 rdev->accel_working = false;
1434         }
1435         return r;
1436 }
1437
1438 int r300_suspend(struct radeon_device *rdev)
1439 {
1440         radeon_pm_suspend(rdev);
1441         r100_cp_disable(rdev);
1442         radeon_wb_disable(rdev);
1443         r100_irq_disable(rdev);
1444         if (rdev->flags & RADEON_IS_PCIE)
1445                 rv370_pcie_gart_disable(rdev);
1446         if (rdev->flags & RADEON_IS_PCI)
1447                 r100_pci_gart_disable(rdev);
1448         return 0;
1449 }
1450
1451 void r300_fini(struct radeon_device *rdev)
1452 {
1453         radeon_pm_fini(rdev);
1454         r100_cp_fini(rdev);
1455         radeon_wb_fini(rdev);
1456         radeon_ib_pool_fini(rdev);
1457         radeon_gem_fini(rdev);
1458         if (rdev->flags & RADEON_IS_PCIE)
1459                 rv370_pcie_gart_fini(rdev);
1460         if (rdev->flags & RADEON_IS_PCI)
1461                 r100_pci_gart_fini(rdev);
1462         radeon_agp_fini(rdev);
1463         radeon_irq_kms_fini(rdev);
1464         radeon_fence_driver_fini(rdev);
1465         radeon_bo_fini(rdev);
1466         radeon_atombios_fini(rdev);
1467         kfree(rdev->bios);
1468         rdev->bios = NULL;
1469 }
1470
1471 int r300_init(struct radeon_device *rdev)
1472 {
1473         int r;
1474
1475         /* Disable VGA */
1476         r100_vga_render_disable(rdev);
1477         /* Initialize scratch registers */
1478         radeon_scratch_init(rdev);
1479         /* Initialize surface registers */
1480         radeon_surface_init(rdev);
1481         /* TODO: disable VGA need to use VGA request */
1482         /* restore some register to sane defaults */
1483         r100_restore_sanity(rdev);
1484         /* BIOS*/
1485         if (!radeon_get_bios(rdev)) {
1486                 if (ASIC_IS_AVIVO(rdev))
1487                         return -EINVAL;
1488         }
1489         if (rdev->is_atom_bios) {
1490                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1491                 return -EINVAL;
1492         } else {
1493                 r = radeon_combios_init(rdev);
1494                 if (r)
1495                         return r;
1496         }
1497         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1498         if (radeon_asic_reset(rdev)) {
1499                 dev_warn(rdev->dev,
1500                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1501                         RREG32(R_000E40_RBBM_STATUS),
1502                         RREG32(R_0007C0_CP_STAT));
1503         }
1504         /* check if cards are posted or not */
1505         if (radeon_boot_test_post_card(rdev) == false)
1506                 return -EINVAL;
1507         /* Set asic errata */
1508         r300_errata(rdev);
1509         /* Initialize clocks */
1510         radeon_get_clock_info(rdev->ddev);
1511         /* initialize AGP */
1512         if (rdev->flags & RADEON_IS_AGP) {
1513                 r = radeon_agp_init(rdev);
1514                 if (r) {
1515                         radeon_agp_disable(rdev);
1516                 }
1517         }
1518         /* initialize memory controller */
1519         r300_mc_init(rdev);
1520         /* Fence driver */
1521         r = radeon_fence_driver_init(rdev);
1522         if (r)
1523                 return r;
1524         /* Memory manager */
1525         r = radeon_bo_init(rdev);
1526         if (r)
1527                 return r;
1528         if (rdev->flags & RADEON_IS_PCIE) {
1529                 r = rv370_pcie_gart_init(rdev);
1530                 if (r)
1531                         return r;
1532         }
1533         if (rdev->flags & RADEON_IS_PCI) {
1534                 r = r100_pci_gart_init(rdev);
1535                 if (r)
1536                         return r;
1537         }
1538         r300_set_reg_safe(rdev);
1539
1540         /* Initialize power management */
1541         radeon_pm_init(rdev);
1542
1543         rdev->accel_working = true;
1544         r = r300_startup(rdev);
1545         if (r) {
1546                 /* Something went wrong with the accel init, so stop accel */
1547                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1548                 r100_cp_fini(rdev);
1549                 radeon_wb_fini(rdev);
1550                 radeon_ib_pool_fini(rdev);
1551                 radeon_irq_kms_fini(rdev);
1552                 if (rdev->flags & RADEON_IS_PCIE)
1553                         rv370_pcie_gart_fini(rdev);
1554                 if (rdev->flags & RADEON_IS_PCI)
1555                         r100_pci_gart_fini(rdev);
1556                 radeon_agp_fini(rdev);
1557                 rdev->accel_working = false;
1558         }
1559         return 0;
1560 }