2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include <drm/drm_crtc_helper.h>
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
36 #include <drm/radeon_drm.h>
37 #include "r100_track.h"
40 #include "r300_reg_safe.h"
42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
45 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
46 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
47 * However, scheduling such write to the ring seems harmless, i suspect
48 * the CP read collide with the flush somehow, or maybe the MC, hard to
49 * tell. (Jerome Glisse)
53 * Indirect registers accessor
55 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
60 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
61 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
62 r = RREG32(RADEON_PCIE_DATA);
63 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
67 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
72 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
73 WREG32(RADEON_PCIE_DATA, (v));
74 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
78 * rv370,rv380 PCIE GART
80 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
82 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
87 /* Workaround HW bug do flush 2 times */
88 for (i = 0; i < 2; i++) {
89 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
90 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
91 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
92 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
97 #define R300_PTE_UNSNOOPED (1 << 0)
98 #define R300_PTE_WRITEABLE (1 << 2)
99 #define R300_PTE_READABLE (1 << 3)
101 uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags)
103 addr = (lower_32_bits(addr) >> 8) |
104 ((upper_32_bits(addr) & 0xff) << 24);
105 if (flags & RADEON_GART_PAGE_READ)
106 addr |= R300_PTE_READABLE;
107 if (flags & RADEON_GART_PAGE_WRITE)
108 addr |= R300_PTE_WRITEABLE;
109 if (!(flags & RADEON_GART_PAGE_SNOOP))
110 addr |= R300_PTE_UNSNOOPED;
114 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
117 void __iomem *ptr = rdev->gart.ptr;
119 /* on x86 we want this to be CPU endian, on powerpc
120 * on powerpc without HW swappers, it'll get swapped on way
121 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
122 writel(entry, ((void __iomem *)ptr) + (i * 4));
125 int rv370_pcie_gart_init(struct radeon_device *rdev)
129 if (rdev->gart.robj) {
130 WARN(1, "RV370 PCIE GART already initialized\n");
133 /* Initialize common gart structure */
134 r = radeon_gart_init(rdev);
137 r = rv370_debugfs_pcie_gart_info_init(rdev);
139 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
140 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
141 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
142 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
143 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
144 return radeon_gart_table_vram_alloc(rdev);
147 int rv370_pcie_gart_enable(struct radeon_device *rdev)
153 if (rdev->gart.robj == NULL) {
154 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
157 r = radeon_gart_table_vram_pin(rdev);
160 /* discard memory request outside of configured range */
161 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
162 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
163 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
164 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
165 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
166 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
167 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
168 table_addr = rdev->gart.table_addr;
169 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
170 /* FIXME: setup default page */
171 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
172 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
174 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
175 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
176 tmp |= RADEON_PCIE_TX_GART_EN;
177 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
178 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
179 rv370_pcie_gart_tlb_flush(rdev);
180 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
181 (unsigned)(rdev->mc.gtt_size >> 20),
182 (unsigned long long)table_addr);
183 rdev->gart.ready = true;
187 void rv370_pcie_gart_disable(struct radeon_device *rdev)
191 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
192 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
193 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
194 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
195 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
196 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
197 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
198 radeon_gart_table_vram_unpin(rdev);
201 void rv370_pcie_gart_fini(struct radeon_device *rdev)
203 radeon_gart_fini(rdev);
204 rv370_pcie_gart_disable(rdev);
205 radeon_gart_table_vram_free(rdev);
208 void r300_fence_ring_emit(struct radeon_device *rdev,
209 struct radeon_fence *fence)
211 struct radeon_ring *ring = &rdev->ring[fence->ring];
213 /* Who ever call radeon_fence_emit should call ring_lock and ask
214 * for enough space (today caller are ib schedule and buffer move) */
215 /* Write SC register so SC & US assert idle */
216 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
217 radeon_ring_write(ring, 0);
218 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
219 radeon_ring_write(ring, 0);
221 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
222 radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
223 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
224 radeon_ring_write(ring, R300_ZC_FLUSH);
225 /* Wait until IDLE & CLEAN */
226 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
227 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
228 RADEON_WAIT_2D_IDLECLEAN |
229 RADEON_WAIT_DMA_GUI_IDLE));
230 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
231 radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
232 RADEON_HDP_READ_BUFFER_INVALIDATE);
233 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
234 radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
235 /* Emit fence sequence & fire IRQ */
236 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
237 radeon_ring_write(ring, fence->seq);
238 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
239 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
242 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
244 unsigned gb_tile_config;
247 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
248 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
249 switch(rdev->num_gb_pipes) {
251 gb_tile_config |= R300_PIPE_COUNT_R300;
254 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
257 gb_tile_config |= R300_PIPE_COUNT_R420;
261 gb_tile_config |= R300_PIPE_COUNT_RV350;
265 r = radeon_ring_lock(rdev, ring, 64);
269 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
270 radeon_ring_write(ring,
271 RADEON_ISYNC_ANY2D_IDLE3D |
272 RADEON_ISYNC_ANY3D_IDLE2D |
273 RADEON_ISYNC_WAIT_IDLEGUI |
274 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
275 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
276 radeon_ring_write(ring, gb_tile_config);
277 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
278 radeon_ring_write(ring,
279 RADEON_WAIT_2D_IDLECLEAN |
280 RADEON_WAIT_3D_IDLECLEAN);
281 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
282 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
283 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
284 radeon_ring_write(ring, 0);
285 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
286 radeon_ring_write(ring, 0);
287 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
288 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
289 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
290 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
291 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
292 radeon_ring_write(ring,
293 RADEON_WAIT_2D_IDLECLEAN |
294 RADEON_WAIT_3D_IDLECLEAN);
295 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
296 radeon_ring_write(ring, 0);
297 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
298 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
299 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
300 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
301 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
302 radeon_ring_write(ring,
303 ((6 << R300_MS_X0_SHIFT) |
304 (6 << R300_MS_Y0_SHIFT) |
305 (6 << R300_MS_X1_SHIFT) |
306 (6 << R300_MS_Y1_SHIFT) |
307 (6 << R300_MS_X2_SHIFT) |
308 (6 << R300_MS_Y2_SHIFT) |
309 (6 << R300_MSBD0_Y_SHIFT) |
310 (6 << R300_MSBD0_X_SHIFT)));
311 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
312 radeon_ring_write(ring,
313 ((6 << R300_MS_X3_SHIFT) |
314 (6 << R300_MS_Y3_SHIFT) |
315 (6 << R300_MS_X4_SHIFT) |
316 (6 << R300_MS_Y4_SHIFT) |
317 (6 << R300_MS_X5_SHIFT) |
318 (6 << R300_MS_Y5_SHIFT) |
319 (6 << R300_MSBD1_SHIFT)));
320 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
321 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
322 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
323 radeon_ring_write(ring,
324 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
325 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
326 radeon_ring_write(ring,
327 R300_GEOMETRY_ROUND_NEAREST |
328 R300_COLOR_ROUND_NEAREST);
329 radeon_ring_unlock_commit(rdev, ring, false);
332 static void r300_errata(struct radeon_device *rdev)
334 rdev->pll_errata = 0;
336 if (rdev->family == CHIP_R300 &&
337 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
338 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
342 int r300_mc_wait_for_idle(struct radeon_device *rdev)
347 for (i = 0; i < rdev->usec_timeout; i++) {
349 tmp = RREG32(RADEON_MC_STATUS);
350 if (tmp & R300_MC_IDLE) {
358 static void r300_gpu_init(struct radeon_device *rdev)
360 uint32_t gb_tile_config, tmp;
362 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
363 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
365 rdev->num_gb_pipes = 2;
367 /* rv350,rv370,rv380,r300 AD, r350 AH */
368 rdev->num_gb_pipes = 1;
370 rdev->num_z_pipes = 1;
371 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
372 switch (rdev->num_gb_pipes) {
374 gb_tile_config |= R300_PIPE_COUNT_R300;
377 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
380 gb_tile_config |= R300_PIPE_COUNT_R420;
384 gb_tile_config |= R300_PIPE_COUNT_RV350;
387 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
389 if (r100_gui_wait_for_idle(rdev)) {
390 printk(KERN_WARNING "Failed to wait GUI idle while "
391 "programming pipes. Bad things might happen.\n");
394 tmp = RREG32(R300_DST_PIPE_CONFIG);
395 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
397 WREG32(R300_RB2D_DSTCACHE_MODE,
398 R300_DC_AUTOFLUSH_ENABLE |
399 R300_DC_DC_DISABLE_IGNORE_PE);
401 if (r100_gui_wait_for_idle(rdev)) {
402 printk(KERN_WARNING "Failed to wait GUI idle while "
403 "programming pipes. Bad things might happen.\n");
405 if (r300_mc_wait_for_idle(rdev)) {
406 printk(KERN_WARNING "Failed to wait MC idle while "
407 "programming pipes. Bad things might happen.\n");
409 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
410 rdev->num_gb_pipes, rdev->num_z_pipes);
413 int r300_asic_reset(struct radeon_device *rdev)
415 struct r100_mc_save save;
419 status = RREG32(R_000E40_RBBM_STATUS);
420 if (!G_000E40_GUI_ACTIVE(status)) {
423 r100_mc_stop(rdev, &save);
424 status = RREG32(R_000E40_RBBM_STATUS);
425 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
427 WREG32(RADEON_CP_CSQ_CNTL, 0);
428 tmp = RREG32(RADEON_CP_RB_CNTL);
429 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
430 WREG32(RADEON_CP_RB_RPTR_WR, 0);
431 WREG32(RADEON_CP_RB_WPTR, 0);
432 WREG32(RADEON_CP_RB_CNTL, tmp);
434 pci_save_state(rdev->pdev);
435 /* disable bus mastering */
436 r100_bm_disable(rdev);
437 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
438 S_0000F0_SOFT_RESET_GA(1));
439 RREG32(R_0000F0_RBBM_SOFT_RESET);
441 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
443 status = RREG32(R_000E40_RBBM_STATUS);
444 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
445 /* resetting the CP seems to be problematic sometimes it end up
446 * hard locking the computer, but it's necessary for successful
447 * reset more test & playing is needed on R3XX/R4XX to find a
448 * reliable (if any solution)
450 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
451 RREG32(R_0000F0_RBBM_SOFT_RESET);
453 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
455 status = RREG32(R_000E40_RBBM_STATUS);
456 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
457 /* restore PCI & busmastering */
458 pci_restore_state(rdev->pdev);
459 r100_enable_bm(rdev);
460 /* Check if GPU is idle */
461 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
462 dev_err(rdev->dev, "failed to reset GPU\n");
465 dev_info(rdev->dev, "GPU reset succeed\n");
466 r100_mc_resume(rdev, &save);
471 * r300,r350,rv350,rv380 VRAM info
473 void r300_mc_init(struct radeon_device *rdev)
478 /* DDR for all card after R300 & IGP */
479 rdev->mc.vram_is_ddr = true;
480 tmp = RREG32(RADEON_MEM_CNTL);
481 tmp &= R300_MEM_NUM_CHANNELS_MASK;
483 case 0: rdev->mc.vram_width = 64; break;
484 case 1: rdev->mc.vram_width = 128; break;
485 case 2: rdev->mc.vram_width = 256; break;
486 default: rdev->mc.vram_width = 128; break;
488 r100_vram_init_sizes(rdev);
489 base = rdev->mc.aper_base;
490 if (rdev->flags & RADEON_IS_IGP)
491 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
492 radeon_vram_location(rdev, &rdev->mc, base);
493 rdev->mc.gtt_base_align = 0;
494 if (!(rdev->flags & RADEON_IS_AGP))
495 radeon_gtt_location(rdev, &rdev->mc);
496 radeon_update_bandwidth_info(rdev);
499 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
501 uint32_t link_width_cntl, mask;
503 if (rdev->flags & RADEON_IS_IGP)
506 if (!(rdev->flags & RADEON_IS_PCIE))
509 /* FIXME wait for idle */
513 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
516 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
519 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
522 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
525 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
528 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
532 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
536 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
538 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
539 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
542 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
543 RADEON_PCIE_LC_RECONFIG_NOW |
544 RADEON_PCIE_LC_RECONFIG_LATER |
545 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
546 link_width_cntl |= mask;
547 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
548 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
549 RADEON_PCIE_LC_RECONFIG_NOW));
551 /* wait for lane set to complete */
552 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
553 while (link_width_cntl == 0xffffffff)
554 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
558 int rv370_get_pcie_lanes(struct radeon_device *rdev)
562 if (rdev->flags & RADEON_IS_IGP)
565 if (!(rdev->flags & RADEON_IS_PCIE))
568 /* FIXME wait for idle */
570 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
572 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
573 case RADEON_PCIE_LC_LINK_WIDTH_X0:
575 case RADEON_PCIE_LC_LINK_WIDTH_X1:
577 case RADEON_PCIE_LC_LINK_WIDTH_X2:
579 case RADEON_PCIE_LC_LINK_WIDTH_X4:
581 case RADEON_PCIE_LC_LINK_WIDTH_X8:
583 case RADEON_PCIE_LC_LINK_WIDTH_X16:
589 #if defined(CONFIG_DEBUG_FS)
590 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
592 struct drm_info_node *node = (struct drm_info_node *) m->private;
593 struct drm_device *dev = node->minor->dev;
594 struct radeon_device *rdev = dev->dev_private;
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
598 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
600 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
601 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
602 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
603 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
604 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
605 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
606 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
607 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
608 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
609 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
610 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
614 static struct drm_info_list rv370_pcie_gart_info_list[] = {
615 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
619 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
621 #if defined(CONFIG_DEBUG_FS)
622 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
628 static int r300_packet0_check(struct radeon_cs_parser *p,
629 struct radeon_cs_packet *pkt,
630 unsigned idx, unsigned reg)
632 struct radeon_bo_list *reloc;
633 struct r100_cs_track *track;
634 volatile uint32_t *ib;
635 uint32_t tmp, tile_flags = 0;
641 track = (struct r100_cs_track *)p->track;
642 idx_value = radeon_get_ib_value(p, idx);
645 case AVIVO_D1MODE_VLINE_START_END:
646 case RADEON_CRTC_GUI_TRIG_VLINE:
647 r = r100_cs_packet_parse_vline(p);
649 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
651 radeon_cs_dump_packet(p, pkt);
655 case RADEON_DST_PITCH_OFFSET:
656 case RADEON_SRC_PITCH_OFFSET:
657 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
661 case R300_RB3D_COLOROFFSET0:
662 case R300_RB3D_COLOROFFSET1:
663 case R300_RB3D_COLOROFFSET2:
664 case R300_RB3D_COLOROFFSET3:
665 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
666 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
668 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
670 radeon_cs_dump_packet(p, pkt);
673 track->cb[i].robj = reloc->robj;
674 track->cb[i].offset = idx_value;
675 track->cb_dirty = true;
676 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
678 case R300_ZB_DEPTHOFFSET:
679 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
681 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
683 radeon_cs_dump_packet(p, pkt);
686 track->zb.robj = reloc->robj;
687 track->zb.offset = idx_value;
688 track->zb_dirty = true;
689 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
691 case R300_TX_OFFSET_0:
692 case R300_TX_OFFSET_0+4:
693 case R300_TX_OFFSET_0+8:
694 case R300_TX_OFFSET_0+12:
695 case R300_TX_OFFSET_0+16:
696 case R300_TX_OFFSET_0+20:
697 case R300_TX_OFFSET_0+24:
698 case R300_TX_OFFSET_0+28:
699 case R300_TX_OFFSET_0+32:
700 case R300_TX_OFFSET_0+36:
701 case R300_TX_OFFSET_0+40:
702 case R300_TX_OFFSET_0+44:
703 case R300_TX_OFFSET_0+48:
704 case R300_TX_OFFSET_0+52:
705 case R300_TX_OFFSET_0+56:
706 case R300_TX_OFFSET_0+60:
707 i = (reg - R300_TX_OFFSET_0) >> 2;
708 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
710 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
712 radeon_cs_dump_packet(p, pkt);
716 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
717 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
718 ((idx_value & ~31) + (u32)reloc->gpu_offset);
720 if (reloc->tiling_flags & RADEON_TILING_MACRO)
721 tile_flags |= R300_TXO_MACRO_TILE;
722 if (reloc->tiling_flags & RADEON_TILING_MICRO)
723 tile_flags |= R300_TXO_MICRO_TILE;
724 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
725 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
727 tmp = idx_value + ((u32)reloc->gpu_offset);
731 track->textures[i].robj = reloc->robj;
732 track->tex_dirty = true;
734 /* Tracked registers */
737 track->vap_vf_cntl = idx_value;
741 track->vtx_size = idx_value & 0x7F;
744 /* VAP_VF_MAX_VTX_INDX */
745 track->max_indx = idx_value & 0x00FFFFFFUL;
748 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
749 if (p->rdev->family < CHIP_RV515)
751 track->vap_alt_nverts = idx_value & 0xFFFFFF;
755 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
756 if (p->rdev->family < CHIP_RV515) {
759 track->cb_dirty = true;
760 track->zb_dirty = true;
764 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
765 p->rdev->cmask_filp != p->filp) {
766 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
769 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
770 track->cb_dirty = true;
776 /* RB3D_COLORPITCH0 */
777 /* RB3D_COLORPITCH1 */
778 /* RB3D_COLORPITCH2 */
779 /* RB3D_COLORPITCH3 */
780 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
781 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
783 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
785 radeon_cs_dump_packet(p, pkt);
789 if (reloc->tiling_flags & RADEON_TILING_MACRO)
790 tile_flags |= R300_COLOR_TILE_ENABLE;
791 if (reloc->tiling_flags & RADEON_TILING_MICRO)
792 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
793 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
794 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
796 tmp = idx_value & ~(0x7 << 16);
800 i = (reg - 0x4E38) >> 2;
801 track->cb[i].pitch = idx_value & 0x3FFE;
802 switch (((idx_value >> 21) & 0xF)) {
806 track->cb[i].cpp = 1;
812 track->cb[i].cpp = 2;
815 if (p->rdev->family < CHIP_RV515) {
816 DRM_ERROR("Invalid color buffer format (%d)!\n",
817 ((idx_value >> 21) & 0xF));
822 track->cb[i].cpp = 4;
825 track->cb[i].cpp = 8;
828 track->cb[i].cpp = 16;
831 DRM_ERROR("Invalid color buffer format (%d) !\n",
832 ((idx_value >> 21) & 0xF));
835 track->cb_dirty = true;
840 track->z_enabled = true;
842 track->z_enabled = false;
844 track->zb_dirty = true;
848 switch ((idx_value & 0xF)) {
857 DRM_ERROR("Invalid z buffer format (%d) !\n",
861 track->zb_dirty = true;
865 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
866 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
868 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
870 radeon_cs_dump_packet(p, pkt);
874 if (reloc->tiling_flags & RADEON_TILING_MACRO)
875 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
876 if (reloc->tiling_flags & RADEON_TILING_MICRO)
877 tile_flags |= R300_DEPTHMICROTILE_TILED;
878 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
879 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
881 tmp = idx_value & ~(0x7 << 16);
885 track->zb.pitch = idx_value & 0x3FFC;
886 track->zb_dirty = true;
890 for (i = 0; i < 16; i++) {
893 enabled = !!(idx_value & (1 << i));
894 track->textures[i].enabled = enabled;
896 track->tex_dirty = true;
914 /* TX_FORMAT1_[0-15] */
915 i = (reg - 0x44C0) >> 2;
916 tmp = (idx_value >> 25) & 0x3;
917 track->textures[i].tex_coord_type = tmp;
918 switch ((idx_value & 0x1F)) {
919 case R300_TX_FORMAT_X8:
920 case R300_TX_FORMAT_Y4X4:
921 case R300_TX_FORMAT_Z3Y3X2:
922 track->textures[i].cpp = 1;
923 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
925 case R300_TX_FORMAT_X16:
926 case R300_TX_FORMAT_FL_I16:
927 case R300_TX_FORMAT_Y8X8:
928 case R300_TX_FORMAT_Z5Y6X5:
929 case R300_TX_FORMAT_Z6Y5X5:
930 case R300_TX_FORMAT_W4Z4Y4X4:
931 case R300_TX_FORMAT_W1Z5Y5X5:
932 case R300_TX_FORMAT_D3DMFT_CxV8U8:
933 case R300_TX_FORMAT_B8G8_B8G8:
934 case R300_TX_FORMAT_G8R8_G8B8:
935 track->textures[i].cpp = 2;
936 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
938 case R300_TX_FORMAT_Y16X16:
939 case R300_TX_FORMAT_FL_I16A16:
940 case R300_TX_FORMAT_Z11Y11X10:
941 case R300_TX_FORMAT_Z10Y11X11:
942 case R300_TX_FORMAT_W8Z8Y8X8:
943 case R300_TX_FORMAT_W2Z10Y10X10:
945 case R300_TX_FORMAT_FL_I32:
947 track->textures[i].cpp = 4;
948 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
950 case R300_TX_FORMAT_W16Z16Y16X16:
951 case R300_TX_FORMAT_FL_R16G16B16A16:
952 case R300_TX_FORMAT_FL_I32A32:
953 track->textures[i].cpp = 8;
954 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
956 case R300_TX_FORMAT_FL_R32G32B32A32:
957 track->textures[i].cpp = 16;
958 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
960 case R300_TX_FORMAT_DXT1:
961 track->textures[i].cpp = 1;
962 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
964 case R300_TX_FORMAT_ATI2N:
965 if (p->rdev->family < CHIP_R420) {
966 DRM_ERROR("Invalid texture format %u\n",
970 /* The same rules apply as for DXT3/5. */
972 case R300_TX_FORMAT_DXT3:
973 case R300_TX_FORMAT_DXT5:
974 track->textures[i].cpp = 1;
975 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
978 DRM_ERROR("Invalid texture format %u\n",
982 track->tex_dirty = true;
1000 /* TX_FILTER0_[0-15] */
1001 i = (reg - 0x4400) >> 2;
1002 tmp = idx_value & 0x7;
1003 if (tmp == 2 || tmp == 4 || tmp == 6) {
1004 track->textures[i].roundup_w = false;
1006 tmp = (idx_value >> 3) & 0x7;
1007 if (tmp == 2 || tmp == 4 || tmp == 6) {
1008 track->textures[i].roundup_h = false;
1010 track->tex_dirty = true;
1028 /* TX_FORMAT2_[0-15] */
1029 i = (reg - 0x4500) >> 2;
1030 tmp = idx_value & 0x3FFF;
1031 track->textures[i].pitch = tmp + 1;
1032 if (p->rdev->family >= CHIP_RV515) {
1033 tmp = ((idx_value >> 15) & 1) << 11;
1034 track->textures[i].width_11 = tmp;
1035 tmp = ((idx_value >> 16) & 1) << 11;
1036 track->textures[i].height_11 = tmp;
1039 if (idx_value & (1 << 14)) {
1040 /* The same rules apply as for DXT1. */
1041 track->textures[i].compress_format =
1042 R100_TRACK_COMP_DXT1;
1044 } else if (idx_value & (1 << 14)) {
1045 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1048 track->tex_dirty = true;
1066 /* TX_FORMAT0_[0-15] */
1067 i = (reg - 0x4480) >> 2;
1068 tmp = idx_value & 0x7FF;
1069 track->textures[i].width = tmp + 1;
1070 tmp = (idx_value >> 11) & 0x7FF;
1071 track->textures[i].height = tmp + 1;
1072 tmp = (idx_value >> 26) & 0xF;
1073 track->textures[i].num_levels = tmp;
1074 tmp = idx_value & (1 << 31);
1075 track->textures[i].use_pitch = !!tmp;
1076 tmp = (idx_value >> 22) & 0xF;
1077 track->textures[i].txdepth = tmp;
1078 track->tex_dirty = true;
1080 case R300_ZB_ZPASS_ADDR:
1081 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1083 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1085 radeon_cs_dump_packet(p, pkt);
1088 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1091 /* RB3D_COLOR_CHANNEL_MASK */
1092 track->color_channel_mask = idx_value;
1093 track->cb_dirty = true;
1097 /* r300c emits this register - we need to disable hyperz for it
1098 * without complaining */
1099 if (p->rdev->hyperz_filp != p->filp) {
1100 if (idx_value & 0x1)
1101 ib[idx] = idx_value & ~1;
1106 track->zb_cb_clear = !!(idx_value & (1 << 5));
1107 track->cb_dirty = true;
1108 track->zb_dirty = true;
1109 if (p->rdev->hyperz_filp != p->filp) {
1110 if (idx_value & (R300_HIZ_ENABLE |
1111 R300_RD_COMP_ENABLE |
1112 R300_WR_COMP_ENABLE |
1113 R300_FAST_FILL_ENABLE))
1118 /* RB3D_BLENDCNTL */
1119 track->blend_read_enable = !!(idx_value & (1 << 2));
1120 track->cb_dirty = true;
1122 case R300_RB3D_AARESOLVE_OFFSET:
1123 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1125 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1127 radeon_cs_dump_packet(p, pkt);
1130 track->aa.robj = reloc->robj;
1131 track->aa.offset = idx_value;
1132 track->aa_dirty = true;
1133 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1135 case R300_RB3D_AARESOLVE_PITCH:
1136 track->aa.pitch = idx_value & 0x3FFE;
1137 track->aa_dirty = true;
1139 case R300_RB3D_AARESOLVE_CTL:
1140 track->aaresolve = idx_value & 0x1;
1141 track->aa_dirty = true;
1143 case 0x4f30: /* ZB_MASK_OFFSET */
1144 case 0x4f34: /* ZB_ZMASK_PITCH */
1145 case 0x4f44: /* ZB_HIZ_OFFSET */
1146 case 0x4f54: /* ZB_HIZ_PITCH */
1147 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1151 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1153 /* GB_Z_PEQ_CONFIG */
1154 if (p->rdev->family >= CHIP_RV350)
1159 /* valid register only on RV530 */
1160 if (p->rdev->family == CHIP_RV530)
1162 /* fallthrough do not move */
1168 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1169 reg, idx, idx_value);
1173 static int r300_packet3_check(struct radeon_cs_parser *p,
1174 struct radeon_cs_packet *pkt)
1176 struct radeon_bo_list *reloc;
1177 struct r100_cs_track *track;
1178 volatile uint32_t *ib;
1184 track = (struct r100_cs_track *)p->track;
1185 switch(pkt->opcode) {
1186 case PACKET3_3D_LOAD_VBPNTR:
1187 r = r100_packet3_load_vbpntr(p, pkt, idx);
1191 case PACKET3_INDX_BUFFER:
1192 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1194 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1195 radeon_cs_dump_packet(p, pkt);
1198 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1199 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1205 case PACKET3_3D_DRAW_IMMD:
1206 /* Number of dwords is vtx_size * (num_vertices - 1)
1207 * PRIM_WALK must be equal to 3 vertex data in embedded
1209 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1210 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1213 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1214 track->immd_dwords = pkt->count - 1;
1215 r = r100_cs_track_check(p->rdev, track);
1220 case PACKET3_3D_DRAW_IMMD_2:
1221 /* Number of dwords is vtx_size * (num_vertices - 1)
1222 * PRIM_WALK must be equal to 3 vertex data in embedded
1224 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1225 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1228 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1229 track->immd_dwords = pkt->count;
1230 r = r100_cs_track_check(p->rdev, track);
1235 case PACKET3_3D_DRAW_VBUF:
1236 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1237 r = r100_cs_track_check(p->rdev, track);
1242 case PACKET3_3D_DRAW_VBUF_2:
1243 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1244 r = r100_cs_track_check(p->rdev, track);
1249 case PACKET3_3D_DRAW_INDX:
1250 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1251 r = r100_cs_track_check(p->rdev, track);
1256 case PACKET3_3D_DRAW_INDX_2:
1257 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1258 r = r100_cs_track_check(p->rdev, track);
1263 case PACKET3_3D_CLEAR_HIZ:
1264 case PACKET3_3D_CLEAR_ZMASK:
1265 if (p->rdev->hyperz_filp != p->filp)
1268 case PACKET3_3D_CLEAR_CMASK:
1269 if (p->rdev->cmask_filp != p->filp)
1275 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1281 int r300_cs_parse(struct radeon_cs_parser *p)
1283 struct radeon_cs_packet pkt;
1284 struct r100_cs_track *track;
1287 track = kzalloc(sizeof(*track), GFP_KERNEL);
1290 r100_cs_track_clear(p->rdev, track);
1293 r = radeon_cs_packet_parse(p, &pkt, p->idx);
1297 p->idx += pkt.count + 2;
1299 case RADEON_PACKET_TYPE0:
1300 r = r100_cs_parse_packet0(p, &pkt,
1301 p->rdev->config.r300.reg_safe_bm,
1302 p->rdev->config.r300.reg_safe_bm_size,
1303 &r300_packet0_check);
1305 case RADEON_PACKET_TYPE2:
1307 case RADEON_PACKET_TYPE3:
1308 r = r300_packet3_check(p, &pkt);
1311 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1317 } while (p->idx < p->chunk_ib->length_dw);
1321 void r300_set_reg_safe(struct radeon_device *rdev)
1323 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1324 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1327 void r300_mc_program(struct radeon_device *rdev)
1329 struct r100_mc_save save;
1332 r = r100_debugfs_mc_info_init(rdev);
1334 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1337 /* Stops all mc clients */
1338 r100_mc_stop(rdev, &save);
1339 if (rdev->flags & RADEON_IS_AGP) {
1340 WREG32(R_00014C_MC_AGP_LOCATION,
1341 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1342 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1343 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1344 WREG32(R_00015C_AGP_BASE_2,
1345 upper_32_bits(rdev->mc.agp_base) & 0xff);
1347 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1348 WREG32(R_000170_AGP_BASE, 0);
1349 WREG32(R_00015C_AGP_BASE_2, 0);
1351 /* Wait for mc idle */
1352 if (r300_mc_wait_for_idle(rdev))
1353 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1354 /* Program MC, should be a 32bits limited address space */
1355 WREG32(R_000148_MC_FB_LOCATION,
1356 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1357 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1358 r100_mc_resume(rdev, &save);
1361 void r300_clock_startup(struct radeon_device *rdev)
1365 if (radeon_dynclks != -1 && radeon_dynclks)
1366 radeon_legacy_set_clock_gating(rdev, 1);
1367 /* We need to force on some of the block */
1368 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1369 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1370 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1371 tmp |= S_00000D_FORCE_VAP(1);
1372 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1375 static int r300_startup(struct radeon_device *rdev)
1379 /* set common regs */
1380 r100_set_common_regs(rdev);
1382 r300_mc_program(rdev);
1384 r300_clock_startup(rdev);
1385 /* Initialize GPU configuration (# pipes, ...) */
1386 r300_gpu_init(rdev);
1387 /* Initialize GART (initialize after TTM so we can allocate
1388 * memory through TTM but finalize after TTM) */
1389 if (rdev->flags & RADEON_IS_PCIE) {
1390 r = rv370_pcie_gart_enable(rdev);
1395 if (rdev->family == CHIP_R300 ||
1396 rdev->family == CHIP_R350 ||
1397 rdev->family == CHIP_RV350)
1398 r100_enable_bm(rdev);
1400 if (rdev->flags & RADEON_IS_PCI) {
1401 r = r100_pci_gart_enable(rdev);
1406 /* allocate wb buffer */
1407 r = radeon_wb_init(rdev);
1411 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1413 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1418 if (!rdev->irq.installed) {
1419 r = radeon_irq_kms_init(rdev);
1425 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1426 /* 1M ring buffer */
1427 r = r100_cp_init(rdev, 1024 * 1024);
1429 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1433 r = radeon_ib_pool_init(rdev);
1435 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1442 int r300_resume(struct radeon_device *rdev)
1446 /* Make sur GART are not working */
1447 if (rdev->flags & RADEON_IS_PCIE)
1448 rv370_pcie_gart_disable(rdev);
1449 if (rdev->flags & RADEON_IS_PCI)
1450 r100_pci_gart_disable(rdev);
1451 /* Resume clock before doing reset */
1452 r300_clock_startup(rdev);
1453 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1454 if (radeon_asic_reset(rdev)) {
1455 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1456 RREG32(R_000E40_RBBM_STATUS),
1457 RREG32(R_0007C0_CP_STAT));
1460 radeon_combios_asic_init(rdev->ddev);
1461 /* Resume clock after posting */
1462 r300_clock_startup(rdev);
1463 /* Initialize surface registers */
1464 radeon_surface_init(rdev);
1466 rdev->accel_working = true;
1467 r = r300_startup(rdev);
1469 rdev->accel_working = false;
1474 int r300_suspend(struct radeon_device *rdev)
1476 radeon_pm_suspend(rdev);
1477 r100_cp_disable(rdev);
1478 radeon_wb_disable(rdev);
1479 r100_irq_disable(rdev);
1480 if (rdev->flags & RADEON_IS_PCIE)
1481 rv370_pcie_gart_disable(rdev);
1482 if (rdev->flags & RADEON_IS_PCI)
1483 r100_pci_gart_disable(rdev);
1487 void r300_fini(struct radeon_device *rdev)
1489 radeon_pm_fini(rdev);
1491 radeon_wb_fini(rdev);
1492 radeon_ib_pool_fini(rdev);
1493 radeon_gem_fini(rdev);
1494 if (rdev->flags & RADEON_IS_PCIE)
1495 rv370_pcie_gart_fini(rdev);
1496 if (rdev->flags & RADEON_IS_PCI)
1497 r100_pci_gart_fini(rdev);
1498 radeon_agp_fini(rdev);
1499 radeon_irq_kms_fini(rdev);
1500 radeon_fence_driver_fini(rdev);
1501 radeon_bo_fini(rdev);
1502 radeon_atombios_fini(rdev);
1507 int r300_init(struct radeon_device *rdev)
1512 r100_vga_render_disable(rdev);
1513 /* Initialize scratch registers */
1514 radeon_scratch_init(rdev);
1515 /* Initialize surface registers */
1516 radeon_surface_init(rdev);
1517 /* TODO: disable VGA need to use VGA request */
1518 /* restore some register to sane defaults */
1519 r100_restore_sanity(rdev);
1521 if (!radeon_get_bios(rdev)) {
1522 if (ASIC_IS_AVIVO(rdev))
1525 if (rdev->is_atom_bios) {
1526 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1529 r = radeon_combios_init(rdev);
1533 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1534 if (radeon_asic_reset(rdev)) {
1536 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1537 RREG32(R_000E40_RBBM_STATUS),
1538 RREG32(R_0007C0_CP_STAT));
1540 /* check if cards are posted or not */
1541 if (radeon_boot_test_post_card(rdev) == false)
1543 /* Set asic errata */
1545 /* Initialize clocks */
1546 radeon_get_clock_info(rdev->ddev);
1547 /* initialize AGP */
1548 if (rdev->flags & RADEON_IS_AGP) {
1549 r = radeon_agp_init(rdev);
1551 radeon_agp_disable(rdev);
1554 /* initialize memory controller */
1557 r = radeon_fence_driver_init(rdev);
1560 /* Memory manager */
1561 r = radeon_bo_init(rdev);
1564 if (rdev->flags & RADEON_IS_PCIE) {
1565 r = rv370_pcie_gart_init(rdev);
1569 if (rdev->flags & RADEON_IS_PCI) {
1570 r = r100_pci_gart_init(rdev);
1574 r300_set_reg_safe(rdev);
1576 /* Initialize power management */
1577 radeon_pm_init(rdev);
1579 rdev->accel_working = true;
1580 r = r300_startup(rdev);
1582 /* Something went wrong with the accel init, so stop accel */
1583 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1585 radeon_wb_fini(rdev);
1586 radeon_ib_pool_fini(rdev);
1587 radeon_irq_kms_fini(rdev);
1588 if (rdev->flags & RADEON_IS_PCIE)
1589 rv370_pcie_gart_fini(rdev);
1590 if (rdev->flags & RADEON_IS_PCI)
1591 r100_pci_gart_fini(rdev);
1592 radeon_agp_fini(rdev);
1593 rdev->accel_working = false;