b188aae764cc39a7cd812cb52419e74450be4343
[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / radeon / r300.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33 #include "radeon_drm.h"
34 #include "r100_track.h"
35 #include "r300d.h"
36 #include "rv350d.h"
37 #include "r300_reg_safe.h"
38
39 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
40  *
41  * GPU Errata:
42  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
43  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
44  *   However, scheduling such write to the ring seems harmless, i suspect
45  *   the CP read collide with the flush somehow, or maybe the MC, hard to
46  *   tell. (Jerome Glisse)
47  */
48
49 /*
50  * rv370,rv380 PCIE GART
51  */
52 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
53
54 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
55 {
56         uint32_t tmp;
57         int i;
58
59         /* Workaround HW bug do flush 2 times */
60         for (i = 0; i < 2; i++) {
61                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
62                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
63                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
65         }
66         mb();
67 }
68
69 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
70 {
71         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
72
73         if (i < 0 || i > rdev->gart.num_gpu_pages) {
74                 return -EINVAL;
75         }
76         addr = (lower_32_bits(addr) >> 8) |
77                ((upper_32_bits(addr) & 0xff) << 24) |
78                0xc;
79         /* on x86 we want this to be CPU endian, on powerpc
80          * on powerpc without HW swappers, it'll get swapped on way
81          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
82         writel(addr, ((void __iomem *)ptr) + (i * 4));
83         return 0;
84 }
85
86 int rv370_pcie_gart_init(struct radeon_device *rdev)
87 {
88         int r;
89
90         if (rdev->gart.table.vram.robj) {
91                 WARN(1, "RV370 PCIE GART already initialized.\n");
92                 return 0;
93         }
94         /* Initialize common gart structure */
95         r = radeon_gart_init(rdev);
96         if (r)
97                 return r;
98         r = rv370_debugfs_pcie_gart_info_init(rdev);
99         if (r)
100                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
101         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
102         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
103         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
104         return radeon_gart_table_vram_alloc(rdev);
105 }
106
107 int rv370_pcie_gart_enable(struct radeon_device *rdev)
108 {
109         uint32_t table_addr;
110         uint32_t tmp;
111         int r;
112
113         if (rdev->gart.table.vram.robj == NULL) {
114                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
115                 return -EINVAL;
116         }
117         r = radeon_gart_table_vram_pin(rdev);
118         if (r)
119                 return r;
120         radeon_gart_restore(rdev);
121         /* discard memory request outside of configured range */
122         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
123         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
124         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
125         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
126         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
127         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
128         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
129         table_addr = rdev->gart.table_addr;
130         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
131         /* FIXME: setup default page */
132         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
133         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
134         /* Clear error */
135         WREG32_PCIE(0x18, 0);
136         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
137         tmp |= RADEON_PCIE_TX_GART_EN;
138         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
139         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
140         rv370_pcie_gart_tlb_flush(rdev);
141         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
142                  (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
143         rdev->gart.ready = true;
144         return 0;
145 }
146
147 void rv370_pcie_gart_disable(struct radeon_device *rdev)
148 {
149         u32 tmp;
150         int r;
151
152         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
153         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
154         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
155         if (rdev->gart.table.vram.robj) {
156                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
157                 if (likely(r == 0)) {
158                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
159                         radeon_bo_unpin(rdev->gart.table.vram.robj);
160                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
161                 }
162         }
163 }
164
165 void rv370_pcie_gart_fini(struct radeon_device *rdev)
166 {
167         rv370_pcie_gart_disable(rdev);
168         radeon_gart_table_vram_free(rdev);
169         radeon_gart_fini(rdev);
170 }
171
172 void r300_fence_ring_emit(struct radeon_device *rdev,
173                           struct radeon_fence *fence)
174 {
175         /* Who ever call radeon_fence_emit should call ring_lock and ask
176          * for enough space (today caller are ib schedule and buffer move) */
177         /* Write SC register so SC & US assert idle */
178         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
179         radeon_ring_write(rdev, 0);
180         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
181         radeon_ring_write(rdev, 0);
182         /* Flush 3D cache */
183         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
184         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
185         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
186         radeon_ring_write(rdev, R300_ZC_FLUSH);
187         /* Wait until IDLE & CLEAN */
188         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
189         radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
190                                  RADEON_WAIT_2D_IDLECLEAN |
191                                  RADEON_WAIT_DMA_GUI_IDLE));
192         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
193         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
194                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
195         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
196         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
197         /* Emit fence sequence & fire IRQ */
198         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
199         radeon_ring_write(rdev, fence->seq);
200         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
201         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
202 }
203
204 void r300_ring_start(struct radeon_device *rdev)
205 {
206         unsigned gb_tile_config;
207         int r;
208
209         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
210         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
211         switch(rdev->num_gb_pipes) {
212         case 2:
213                 gb_tile_config |= R300_PIPE_COUNT_R300;
214                 break;
215         case 3:
216                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
217                 break;
218         case 4:
219                 gb_tile_config |= R300_PIPE_COUNT_R420;
220                 break;
221         case 1:
222         default:
223                 gb_tile_config |= R300_PIPE_COUNT_RV350;
224                 break;
225         }
226
227         r = radeon_ring_lock(rdev, 64);
228         if (r) {
229                 return;
230         }
231         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
232         radeon_ring_write(rdev,
233                           RADEON_ISYNC_ANY2D_IDLE3D |
234                           RADEON_ISYNC_ANY3D_IDLE2D |
235                           RADEON_ISYNC_WAIT_IDLEGUI |
236                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
237         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
238         radeon_ring_write(rdev, gb_tile_config);
239         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
240         radeon_ring_write(rdev,
241                           RADEON_WAIT_2D_IDLECLEAN |
242                           RADEON_WAIT_3D_IDLECLEAN);
243         radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
244         radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
245         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
246         radeon_ring_write(rdev, 0);
247         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
248         radeon_ring_write(rdev, 0);
249         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
250         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
251         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
252         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
253         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
254         radeon_ring_write(rdev,
255                           RADEON_WAIT_2D_IDLECLEAN |
256                           RADEON_WAIT_3D_IDLECLEAN);
257         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
258         radeon_ring_write(rdev, 0);
259         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
260         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
261         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
262         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
263         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
264         radeon_ring_write(rdev,
265                           ((6 << R300_MS_X0_SHIFT) |
266                            (6 << R300_MS_Y0_SHIFT) |
267                            (6 << R300_MS_X1_SHIFT) |
268                            (6 << R300_MS_Y1_SHIFT) |
269                            (6 << R300_MS_X2_SHIFT) |
270                            (6 << R300_MS_Y2_SHIFT) |
271                            (6 << R300_MSBD0_Y_SHIFT) |
272                            (6 << R300_MSBD0_X_SHIFT)));
273         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
274         radeon_ring_write(rdev,
275                           ((6 << R300_MS_X3_SHIFT) |
276                            (6 << R300_MS_Y3_SHIFT) |
277                            (6 << R300_MS_X4_SHIFT) |
278                            (6 << R300_MS_Y4_SHIFT) |
279                            (6 << R300_MS_X5_SHIFT) |
280                            (6 << R300_MS_Y5_SHIFT) |
281                            (6 << R300_MSBD1_SHIFT)));
282         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
283         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
284         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
285         radeon_ring_write(rdev,
286                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
287         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
288         radeon_ring_write(rdev,
289                           R300_GEOMETRY_ROUND_NEAREST |
290                           R300_COLOR_ROUND_NEAREST);
291         radeon_ring_unlock_commit(rdev);
292 }
293
294 void r300_errata(struct radeon_device *rdev)
295 {
296         rdev->pll_errata = 0;
297
298         if (rdev->family == CHIP_R300 &&
299             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
300                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
301         }
302 }
303
304 int r300_mc_wait_for_idle(struct radeon_device *rdev)
305 {
306         unsigned i;
307         uint32_t tmp;
308
309         for (i = 0; i < rdev->usec_timeout; i++) {
310                 /* read MC_STATUS */
311                 tmp = RREG32(RADEON_MC_STATUS);
312                 if (tmp & R300_MC_IDLE) {
313                         return 0;
314                 }
315                 DRM_UDELAY(1);
316         }
317         return -1;
318 }
319
320 void r300_gpu_init(struct radeon_device *rdev)
321 {
322         uint32_t gb_tile_config, tmp;
323
324         r100_hdp_reset(rdev);
325         /* FIXME: rv380 one pipes ? */
326         if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
327                 /* r300,r350 */
328                 rdev->num_gb_pipes = 2;
329         } else {
330                 /* rv350,rv370,rv380 */
331                 rdev->num_gb_pipes = 1;
332         }
333         rdev->num_z_pipes = 1;
334         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
335         switch (rdev->num_gb_pipes) {
336         case 2:
337                 gb_tile_config |= R300_PIPE_COUNT_R300;
338                 break;
339         case 3:
340                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
341                 break;
342         case 4:
343                 gb_tile_config |= R300_PIPE_COUNT_R420;
344                 break;
345         default:
346         case 1:
347                 gb_tile_config |= R300_PIPE_COUNT_RV350;
348                 break;
349         }
350         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
351
352         if (r100_gui_wait_for_idle(rdev)) {
353                 printk(KERN_WARNING "Failed to wait GUI idle while "
354                        "programming pipes. Bad things might happen.\n");
355         }
356
357         tmp = RREG32(R300_DST_PIPE_CONFIG);
358         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
359
360         WREG32(R300_RB2D_DSTCACHE_MODE,
361                R300_DC_AUTOFLUSH_ENABLE |
362                R300_DC_DC_DISABLE_IGNORE_PE);
363
364         if (r100_gui_wait_for_idle(rdev)) {
365                 printk(KERN_WARNING "Failed to wait GUI idle while "
366                        "programming pipes. Bad things might happen.\n");
367         }
368         if (r300_mc_wait_for_idle(rdev)) {
369                 printk(KERN_WARNING "Failed to wait MC idle while "
370                        "programming pipes. Bad things might happen.\n");
371         }
372         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
373                  rdev->num_gb_pipes, rdev->num_z_pipes);
374 }
375
376 int r300_ga_reset(struct radeon_device *rdev)
377 {
378         uint32_t tmp;
379         bool reinit_cp;
380         int i;
381
382         reinit_cp = rdev->cp.ready;
383         rdev->cp.ready = false;
384         for (i = 0; i < rdev->usec_timeout; i++) {
385                 WREG32(RADEON_CP_CSQ_MODE, 0);
386                 WREG32(RADEON_CP_CSQ_CNTL, 0);
387                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
388                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
389                 udelay(200);
390                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
391                 /* Wait to prevent race in RBBM_STATUS */
392                 mdelay(1);
393                 tmp = RREG32(RADEON_RBBM_STATUS);
394                 if (tmp & ((1 << 20) | (1 << 26))) {
395                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
396                         /* GA still busy soft reset it */
397                         WREG32(0x429C, 0x200);
398                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
399                         WREG32(R300_RE_SCISSORS_TL, 0);
400                         WREG32(R300_RE_SCISSORS_BR, 0);
401                         WREG32(0x24AC, 0);
402                 }
403                 /* Wait to prevent race in RBBM_STATUS */
404                 mdelay(1);
405                 tmp = RREG32(RADEON_RBBM_STATUS);
406                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
407                         break;
408                 }
409         }
410         for (i = 0; i < rdev->usec_timeout; i++) {
411                 tmp = RREG32(RADEON_RBBM_STATUS);
412                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
413                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
414                                  tmp);
415                         if (reinit_cp) {
416                                 return r100_cp_init(rdev, rdev->cp.ring_size);
417                         }
418                         return 0;
419                 }
420                 DRM_UDELAY(1);
421         }
422         tmp = RREG32(RADEON_RBBM_STATUS);
423         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
424         return -1;
425 }
426
427 int r300_gpu_reset(struct radeon_device *rdev)
428 {
429         uint32_t status;
430
431         /* reset order likely matter */
432         status = RREG32(RADEON_RBBM_STATUS);
433         /* reset HDP */
434         r100_hdp_reset(rdev);
435         /* reset rb2d */
436         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
437                 r100_rb2d_reset(rdev);
438         }
439         /* reset GA */
440         if (status & ((1 << 20) | (1 << 26))) {
441                 r300_ga_reset(rdev);
442         }
443         /* reset CP */
444         status = RREG32(RADEON_RBBM_STATUS);
445         if (status & (1 << 16)) {
446                 r100_cp_reset(rdev);
447         }
448         /* Check if GPU is idle */
449         status = RREG32(RADEON_RBBM_STATUS);
450         if (status & RADEON_RBBM_ACTIVE) {
451                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
452                 return -1;
453         }
454         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
455         return 0;
456 }
457
458
459 /*
460  * r300,r350,rv350,rv380 VRAM info
461  */
462 void r300_mc_init(struct radeon_device *rdev)
463 {
464         u64 base;
465         u32 tmp;
466
467         /* DDR for all card after R300 & IGP */
468         rdev->mc.vram_is_ddr = true;
469         tmp = RREG32(RADEON_MEM_CNTL);
470         tmp &= R300_MEM_NUM_CHANNELS_MASK;
471         switch (tmp) {
472         case 0: rdev->mc.vram_width = 64; break;
473         case 1: rdev->mc.vram_width = 128; break;
474         case 2: rdev->mc.vram_width = 256; break;
475         default:  rdev->mc.vram_width = 128; break;
476         }
477         r100_vram_init_sizes(rdev);
478         base = rdev->mc.aper_base;
479         if (rdev->flags & RADEON_IS_IGP)
480                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
481         radeon_vram_location(rdev, &rdev->mc, base);
482         if (!(rdev->flags & RADEON_IS_AGP))
483                 radeon_gtt_location(rdev, &rdev->mc);
484 }
485
486 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
487 {
488         uint32_t link_width_cntl, mask;
489
490         if (rdev->flags & RADEON_IS_IGP)
491                 return;
492
493         if (!(rdev->flags & RADEON_IS_PCIE))
494                 return;
495
496         /* FIXME wait for idle */
497
498         switch (lanes) {
499         case 0:
500                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
501                 break;
502         case 1:
503                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
504                 break;
505         case 2:
506                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
507                 break;
508         case 4:
509                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
510                 break;
511         case 8:
512                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
513                 break;
514         case 12:
515                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
516                 break;
517         case 16:
518         default:
519                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
520                 break;
521         }
522
523         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
524
525         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
526             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
527                 return;
528
529         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
530                              RADEON_PCIE_LC_RECONFIG_NOW |
531                              RADEON_PCIE_LC_RECONFIG_LATER |
532                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
533         link_width_cntl |= mask;
534         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
535         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
536                                                      RADEON_PCIE_LC_RECONFIG_NOW));
537
538         /* wait for lane set to complete */
539         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
540         while (link_width_cntl == 0xffffffff)
541                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
542
543 }
544
545 int rv370_get_pcie_lanes(struct radeon_device *rdev)
546 {
547         u32 link_width_cntl;
548
549         if (rdev->flags & RADEON_IS_IGP)
550                 return 0;
551
552         if (!(rdev->flags & RADEON_IS_PCIE))
553                 return 0;
554
555         /* FIXME wait for idle */
556
557         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
558
559         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
560         case RADEON_PCIE_LC_LINK_WIDTH_X0:
561                 return 0;
562         case RADEON_PCIE_LC_LINK_WIDTH_X1:
563                 return 1;
564         case RADEON_PCIE_LC_LINK_WIDTH_X2:
565                 return 2;
566         case RADEON_PCIE_LC_LINK_WIDTH_X4:
567                 return 4;
568         case RADEON_PCIE_LC_LINK_WIDTH_X8:
569                 return 8;
570         case RADEON_PCIE_LC_LINK_WIDTH_X16:
571         default:
572                 return 16;
573         }
574 }
575
576 #if defined(CONFIG_DEBUG_FS)
577 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
578 {
579         struct drm_info_node *node = (struct drm_info_node *) m->private;
580         struct drm_device *dev = node->minor->dev;
581         struct radeon_device *rdev = dev->dev_private;
582         uint32_t tmp;
583
584         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
585         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
586         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
587         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
588         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
589         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
590         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
591         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
592         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
593         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
594         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
595         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
596         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
597         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
598         return 0;
599 }
600
601 static struct drm_info_list rv370_pcie_gart_info_list[] = {
602         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
603 };
604 #endif
605
606 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
607 {
608 #if defined(CONFIG_DEBUG_FS)
609         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
610 #else
611         return 0;
612 #endif
613 }
614
615 static int r300_packet0_check(struct radeon_cs_parser *p,
616                 struct radeon_cs_packet *pkt,
617                 unsigned idx, unsigned reg)
618 {
619         struct radeon_cs_reloc *reloc;
620         struct r100_cs_track *track;
621         volatile uint32_t *ib;
622         uint32_t tmp, tile_flags = 0;
623         unsigned i;
624         int r;
625         u32 idx_value;
626
627         ib = p->ib->ptr;
628         track = (struct r100_cs_track *)p->track;
629         idx_value = radeon_get_ib_value(p, idx);
630
631         switch(reg) {
632         case AVIVO_D1MODE_VLINE_START_END:
633         case RADEON_CRTC_GUI_TRIG_VLINE:
634                 r = r100_cs_packet_parse_vline(p);
635                 if (r) {
636                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
637                                         idx, reg);
638                         r100_cs_dump_packet(p, pkt);
639                         return r;
640                 }
641                 break;
642         case RADEON_DST_PITCH_OFFSET:
643         case RADEON_SRC_PITCH_OFFSET:
644                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
645                 if (r)
646                         return r;
647                 break;
648         case R300_RB3D_COLOROFFSET0:
649         case R300_RB3D_COLOROFFSET1:
650         case R300_RB3D_COLOROFFSET2:
651         case R300_RB3D_COLOROFFSET3:
652                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
653                 r = r100_cs_packet_next_reloc(p, &reloc);
654                 if (r) {
655                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
656                                         idx, reg);
657                         r100_cs_dump_packet(p, pkt);
658                         return r;
659                 }
660                 track->cb[i].robj = reloc->robj;
661                 track->cb[i].offset = idx_value;
662                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
663                 break;
664         case R300_ZB_DEPTHOFFSET:
665                 r = r100_cs_packet_next_reloc(p, &reloc);
666                 if (r) {
667                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
668                                         idx, reg);
669                         r100_cs_dump_packet(p, pkt);
670                         return r;
671                 }
672                 track->zb.robj = reloc->robj;
673                 track->zb.offset = idx_value;
674                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
675                 break;
676         case R300_TX_OFFSET_0:
677         case R300_TX_OFFSET_0+4:
678         case R300_TX_OFFSET_0+8:
679         case R300_TX_OFFSET_0+12:
680         case R300_TX_OFFSET_0+16:
681         case R300_TX_OFFSET_0+20:
682         case R300_TX_OFFSET_0+24:
683         case R300_TX_OFFSET_0+28:
684         case R300_TX_OFFSET_0+32:
685         case R300_TX_OFFSET_0+36:
686         case R300_TX_OFFSET_0+40:
687         case R300_TX_OFFSET_0+44:
688         case R300_TX_OFFSET_0+48:
689         case R300_TX_OFFSET_0+52:
690         case R300_TX_OFFSET_0+56:
691         case R300_TX_OFFSET_0+60:
692                 i = (reg - R300_TX_OFFSET_0) >> 2;
693                 r = r100_cs_packet_next_reloc(p, &reloc);
694                 if (r) {
695                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
696                                         idx, reg);
697                         r100_cs_dump_packet(p, pkt);
698                         return r;
699                 }
700
701                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
702                         tile_flags |= R300_TXO_MACRO_TILE;
703                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
704                         tile_flags |= R300_TXO_MICRO_TILE;
705
706                 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
707                 tmp |= tile_flags;
708                 ib[idx] = tmp;
709                 track->textures[i].robj = reloc->robj;
710                 break;
711         /* Tracked registers */
712         case 0x2084:
713                 /* VAP_VF_CNTL */
714                 track->vap_vf_cntl = idx_value;
715                 break;
716         case 0x20B4:
717                 /* VAP_VTX_SIZE */
718                 track->vtx_size = idx_value & 0x7F;
719                 break;
720         case 0x2134:
721                 /* VAP_VF_MAX_VTX_INDX */
722                 track->max_indx = idx_value & 0x00FFFFFFUL;
723                 break;
724         case 0x43E4:
725                 /* SC_SCISSOR1 */
726                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
727                 if (p->rdev->family < CHIP_RV515) {
728                         track->maxy -= 1440;
729                 }
730                 break;
731         case 0x4E00:
732                 /* RB3D_CCTL */
733                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
734                 break;
735         case 0x4E38:
736         case 0x4E3C:
737         case 0x4E40:
738         case 0x4E44:
739                 /* RB3D_COLORPITCH0 */
740                 /* RB3D_COLORPITCH1 */
741                 /* RB3D_COLORPITCH2 */
742                 /* RB3D_COLORPITCH3 */
743                 r = r100_cs_packet_next_reloc(p, &reloc);
744                 if (r) {
745                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
746                                   idx, reg);
747                         r100_cs_dump_packet(p, pkt);
748                         return r;
749                 }
750
751                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
752                         tile_flags |= R300_COLOR_TILE_ENABLE;
753                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
754                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
755
756                 tmp = idx_value & ~(0x7 << 16);
757                 tmp |= tile_flags;
758                 ib[idx] = tmp;
759
760                 i = (reg - 0x4E38) >> 2;
761                 track->cb[i].pitch = idx_value & 0x3FFE;
762                 switch (((idx_value >> 21) & 0xF)) {
763                 case 9:
764                 case 11:
765                 case 12:
766                         track->cb[i].cpp = 1;
767                         break;
768                 case 3:
769                 case 4:
770                 case 13:
771                 case 15:
772                         track->cb[i].cpp = 2;
773                         break;
774                 case 6:
775                         track->cb[i].cpp = 4;
776                         break;
777                 case 10:
778                         track->cb[i].cpp = 8;
779                         break;
780                 case 7:
781                         track->cb[i].cpp = 16;
782                         break;
783                 default:
784                         DRM_ERROR("Invalid color buffer format (%d) !\n",
785                                   ((idx_value >> 21) & 0xF));
786                         return -EINVAL;
787                 }
788                 break;
789         case 0x4F00:
790                 /* ZB_CNTL */
791                 if (idx_value & 2) {
792                         track->z_enabled = true;
793                 } else {
794                         track->z_enabled = false;
795                 }
796                 break;
797         case 0x4F10:
798                 /* ZB_FORMAT */
799                 switch ((idx_value & 0xF)) {
800                 case 0:
801                 case 1:
802                         track->zb.cpp = 2;
803                         break;
804                 case 2:
805                         track->zb.cpp = 4;
806                         break;
807                 default:
808                         DRM_ERROR("Invalid z buffer format (%d) !\n",
809                                   (idx_value & 0xF));
810                         return -EINVAL;
811                 }
812                 break;
813         case 0x4F24:
814                 /* ZB_DEPTHPITCH */
815                 r = r100_cs_packet_next_reloc(p, &reloc);
816                 if (r) {
817                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
818                                   idx, reg);
819                         r100_cs_dump_packet(p, pkt);
820                         return r;
821                 }
822
823                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
824                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
825                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
826                         tile_flags |= R300_DEPTHMICROTILE_TILED;;
827
828                 tmp = idx_value & ~(0x7 << 16);
829                 tmp |= tile_flags;
830                 ib[idx] = tmp;
831
832                 track->zb.pitch = idx_value & 0x3FFC;
833                 break;
834         case 0x4104:
835                 for (i = 0; i < 16; i++) {
836                         bool enabled;
837
838                         enabled = !!(idx_value & (1 << i));
839                         track->textures[i].enabled = enabled;
840                 }
841                 break;
842         case 0x44C0:
843         case 0x44C4:
844         case 0x44C8:
845         case 0x44CC:
846         case 0x44D0:
847         case 0x44D4:
848         case 0x44D8:
849         case 0x44DC:
850         case 0x44E0:
851         case 0x44E4:
852         case 0x44E8:
853         case 0x44EC:
854         case 0x44F0:
855         case 0x44F4:
856         case 0x44F8:
857         case 0x44FC:
858                 /* TX_FORMAT1_[0-15] */
859                 i = (reg - 0x44C0) >> 2;
860                 tmp = (idx_value >> 25) & 0x3;
861                 track->textures[i].tex_coord_type = tmp;
862                 switch ((idx_value & 0x1F)) {
863                 case R300_TX_FORMAT_X8:
864                 case R300_TX_FORMAT_Y4X4:
865                 case R300_TX_FORMAT_Z3Y3X2:
866                         track->textures[i].cpp = 1;
867                         break;
868                 case R300_TX_FORMAT_X16:
869                 case R300_TX_FORMAT_Y8X8:
870                 case R300_TX_FORMAT_Z5Y6X5:
871                 case R300_TX_FORMAT_Z6Y5X5:
872                 case R300_TX_FORMAT_W4Z4Y4X4:
873                 case R300_TX_FORMAT_W1Z5Y5X5:
874                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
875                 case R300_TX_FORMAT_B8G8_B8G8:
876                 case R300_TX_FORMAT_G8R8_G8B8:
877                         track->textures[i].cpp = 2;
878                         break;
879                 case R300_TX_FORMAT_Y16X16:
880                 case R300_TX_FORMAT_Z11Y11X10:
881                 case R300_TX_FORMAT_Z10Y11X11:
882                 case R300_TX_FORMAT_W8Z8Y8X8:
883                 case R300_TX_FORMAT_W2Z10Y10X10:
884                 case 0x17:
885                 case R300_TX_FORMAT_FL_I32:
886                 case 0x1e:
887                         track->textures[i].cpp = 4;
888                         break;
889                 case R300_TX_FORMAT_W16Z16Y16X16:
890                 case R300_TX_FORMAT_FL_R16G16B16A16:
891                 case R300_TX_FORMAT_FL_I32A32:
892                         track->textures[i].cpp = 8;
893                         break;
894                 case R300_TX_FORMAT_FL_R32G32B32A32:
895                         track->textures[i].cpp = 16;
896                         break;
897                 case R300_TX_FORMAT_DXT1:
898                         track->textures[i].cpp = 1;
899                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
900                         break;
901                 case R300_TX_FORMAT_ATI2N:
902                         if (p->rdev->family < CHIP_R420) {
903                                 DRM_ERROR("Invalid texture format %u\n",
904                                           (idx_value & 0x1F));
905                                 return -EINVAL;
906                         }
907                         /* The same rules apply as for DXT3/5. */
908                         /* Pass through. */
909                 case R300_TX_FORMAT_DXT3:
910                 case R300_TX_FORMAT_DXT5:
911                         track->textures[i].cpp = 1;
912                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
913                         break;
914                 default:
915                         DRM_ERROR("Invalid texture format %u\n",
916                                   (idx_value & 0x1F));
917                         return -EINVAL;
918                         break;
919                 }
920                 break;
921         case 0x4400:
922         case 0x4404:
923         case 0x4408:
924         case 0x440C:
925         case 0x4410:
926         case 0x4414:
927         case 0x4418:
928         case 0x441C:
929         case 0x4420:
930         case 0x4424:
931         case 0x4428:
932         case 0x442C:
933         case 0x4430:
934         case 0x4434:
935         case 0x4438:
936         case 0x443C:
937                 /* TX_FILTER0_[0-15] */
938                 i = (reg - 0x4400) >> 2;
939                 tmp = idx_value & 0x7;
940                 if (tmp == 2 || tmp == 4 || tmp == 6) {
941                         track->textures[i].roundup_w = false;
942                 }
943                 tmp = (idx_value >> 3) & 0x7;
944                 if (tmp == 2 || tmp == 4 || tmp == 6) {
945                         track->textures[i].roundup_h = false;
946                 }
947                 break;
948         case 0x4500:
949         case 0x4504:
950         case 0x4508:
951         case 0x450C:
952         case 0x4510:
953         case 0x4514:
954         case 0x4518:
955         case 0x451C:
956         case 0x4520:
957         case 0x4524:
958         case 0x4528:
959         case 0x452C:
960         case 0x4530:
961         case 0x4534:
962         case 0x4538:
963         case 0x453C:
964                 /* TX_FORMAT2_[0-15] */
965                 i = (reg - 0x4500) >> 2;
966                 tmp = idx_value & 0x3FFF;
967                 track->textures[i].pitch = tmp + 1;
968                 if (p->rdev->family >= CHIP_RV515) {
969                         tmp = ((idx_value >> 15) & 1) << 11;
970                         track->textures[i].width_11 = tmp;
971                         tmp = ((idx_value >> 16) & 1) << 11;
972                         track->textures[i].height_11 = tmp;
973
974                         /* ATI1N */
975                         if (idx_value & (1 << 14)) {
976                                 /* The same rules apply as for DXT1. */
977                                 track->textures[i].compress_format =
978                                         R100_TRACK_COMP_DXT1;
979                         }
980                 } else if (idx_value & (1 << 14)) {
981                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
982                         return -EINVAL;
983                 }
984                 break;
985         case 0x4480:
986         case 0x4484:
987         case 0x4488:
988         case 0x448C:
989         case 0x4490:
990         case 0x4494:
991         case 0x4498:
992         case 0x449C:
993         case 0x44A0:
994         case 0x44A4:
995         case 0x44A8:
996         case 0x44AC:
997         case 0x44B0:
998         case 0x44B4:
999         case 0x44B8:
1000         case 0x44BC:
1001                 /* TX_FORMAT0_[0-15] */
1002                 i = (reg - 0x4480) >> 2;
1003                 tmp = idx_value & 0x7FF;
1004                 track->textures[i].width = tmp + 1;
1005                 tmp = (idx_value >> 11) & 0x7FF;
1006                 track->textures[i].height = tmp + 1;
1007                 tmp = (idx_value >> 26) & 0xF;
1008                 track->textures[i].num_levels = tmp;
1009                 tmp = idx_value & (1 << 31);
1010                 track->textures[i].use_pitch = !!tmp;
1011                 tmp = (idx_value >> 22) & 0xF;
1012                 track->textures[i].txdepth = tmp;
1013                 break;
1014         case R300_ZB_ZPASS_ADDR:
1015                 r = r100_cs_packet_next_reloc(p, &reloc);
1016                 if (r) {
1017                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1018                                         idx, reg);
1019                         r100_cs_dump_packet(p, pkt);
1020                         return r;
1021                 }
1022                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1023                 break;
1024         case 0x4e0c:
1025                 /* RB3D_COLOR_CHANNEL_MASK */
1026                 track->color_channel_mask = idx_value;
1027                 break;
1028         case 0x4d1c:
1029                 /* ZB_BW_CNTL */
1030                 track->fastfill = !!(idx_value & (1 << 2));
1031                 break;
1032         case 0x4e04:
1033                 /* RB3D_BLENDCNTL */
1034                 track->blend_read_enable = !!(idx_value & (1 << 2));
1035                 break;
1036         case 0x4be8:
1037                 /* valid register only on RV530 */
1038                 if (p->rdev->family == CHIP_RV530)
1039                         break;
1040                 /* fallthrough do not move */
1041         default:
1042                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1043                        reg, idx);
1044                 return -EINVAL;
1045         }
1046         return 0;
1047 }
1048
1049 static int r300_packet3_check(struct radeon_cs_parser *p,
1050                               struct radeon_cs_packet *pkt)
1051 {
1052         struct radeon_cs_reloc *reloc;
1053         struct r100_cs_track *track;
1054         volatile uint32_t *ib;
1055         unsigned idx;
1056         int r;
1057
1058         ib = p->ib->ptr;
1059         idx = pkt->idx + 1;
1060         track = (struct r100_cs_track *)p->track;
1061         switch(pkt->opcode) {
1062         case PACKET3_3D_LOAD_VBPNTR:
1063                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1064                 if (r)
1065                         return r;
1066                 break;
1067         case PACKET3_INDX_BUFFER:
1068                 r = r100_cs_packet_next_reloc(p, &reloc);
1069                 if (r) {
1070                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1071                         r100_cs_dump_packet(p, pkt);
1072                         return r;
1073                 }
1074                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1075                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1076                 if (r) {
1077                         return r;
1078                 }
1079                 break;
1080         /* Draw packet */
1081         case PACKET3_3D_DRAW_IMMD:
1082                 /* Number of dwords is vtx_size * (num_vertices - 1)
1083                  * PRIM_WALK must be equal to 3 vertex data in embedded
1084                  * in cmd stream */
1085                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1086                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1087                         return -EINVAL;
1088                 }
1089                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1090                 track->immd_dwords = pkt->count - 1;
1091                 r = r100_cs_track_check(p->rdev, track);
1092                 if (r) {
1093                         return r;
1094                 }
1095                 break;
1096         case PACKET3_3D_DRAW_IMMD_2:
1097                 /* Number of dwords is vtx_size * (num_vertices - 1)
1098                  * PRIM_WALK must be equal to 3 vertex data in embedded
1099                  * in cmd stream */
1100                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1101                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1102                         return -EINVAL;
1103                 }
1104                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1105                 track->immd_dwords = pkt->count;
1106                 r = r100_cs_track_check(p->rdev, track);
1107                 if (r) {
1108                         return r;
1109                 }
1110                 break;
1111         case PACKET3_3D_DRAW_VBUF:
1112                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1113                 r = r100_cs_track_check(p->rdev, track);
1114                 if (r) {
1115                         return r;
1116                 }
1117                 break;
1118         case PACKET3_3D_DRAW_VBUF_2:
1119                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1120                 r = r100_cs_track_check(p->rdev, track);
1121                 if (r) {
1122                         return r;
1123                 }
1124                 break;
1125         case PACKET3_3D_DRAW_INDX:
1126                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1127                 r = r100_cs_track_check(p->rdev, track);
1128                 if (r) {
1129                         return r;
1130                 }
1131                 break;
1132         case PACKET3_3D_DRAW_INDX_2:
1133                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1134                 r = r100_cs_track_check(p->rdev, track);
1135                 if (r) {
1136                         return r;
1137                 }
1138                 break;
1139         case PACKET3_NOP:
1140                 break;
1141         default:
1142                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1143                 return -EINVAL;
1144         }
1145         return 0;
1146 }
1147
1148 int r300_cs_parse(struct radeon_cs_parser *p)
1149 {
1150         struct radeon_cs_packet pkt;
1151         struct r100_cs_track *track;
1152         int r;
1153
1154         track = kzalloc(sizeof(*track), GFP_KERNEL);
1155         r100_cs_track_clear(p->rdev, track);
1156         p->track = track;
1157         do {
1158                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1159                 if (r) {
1160                         return r;
1161                 }
1162                 p->idx += pkt.count + 2;
1163                 switch (pkt.type) {
1164                 case PACKET_TYPE0:
1165                         r = r100_cs_parse_packet0(p, &pkt,
1166                                                   p->rdev->config.r300.reg_safe_bm,
1167                                                   p->rdev->config.r300.reg_safe_bm_size,
1168                                                   &r300_packet0_check);
1169                         break;
1170                 case PACKET_TYPE2:
1171                         break;
1172                 case PACKET_TYPE3:
1173                         r = r300_packet3_check(p, &pkt);
1174                         break;
1175                 default:
1176                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1177                         return -EINVAL;
1178                 }
1179                 if (r) {
1180                         return r;
1181                 }
1182         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1183         return 0;
1184 }
1185
1186 void r300_set_reg_safe(struct radeon_device *rdev)
1187 {
1188         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1189         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1190 }
1191
1192 void r300_mc_program(struct radeon_device *rdev)
1193 {
1194         struct r100_mc_save save;
1195         int r;
1196
1197         r = r100_debugfs_mc_info_init(rdev);
1198         if (r) {
1199                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1200         }
1201
1202         /* Stops all mc clients */
1203         r100_mc_stop(rdev, &save);
1204         if (rdev->flags & RADEON_IS_AGP) {
1205                 WREG32(R_00014C_MC_AGP_LOCATION,
1206                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1207                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1208                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1209                 WREG32(R_00015C_AGP_BASE_2,
1210                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1211         } else {
1212                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1213                 WREG32(R_000170_AGP_BASE, 0);
1214                 WREG32(R_00015C_AGP_BASE_2, 0);
1215         }
1216         /* Wait for mc idle */
1217         if (r300_mc_wait_for_idle(rdev))
1218                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1219         /* Program MC, should be a 32bits limited address space */
1220         WREG32(R_000148_MC_FB_LOCATION,
1221                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1222                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1223         r100_mc_resume(rdev, &save);
1224 }
1225
1226 void r300_clock_startup(struct radeon_device *rdev)
1227 {
1228         u32 tmp;
1229
1230         if (radeon_dynclks != -1 && radeon_dynclks)
1231                 radeon_legacy_set_clock_gating(rdev, 1);
1232         /* We need to force on some of the block */
1233         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1234         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1235         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1236                 tmp |= S_00000D_FORCE_VAP(1);
1237         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1238 }
1239
1240 static int r300_startup(struct radeon_device *rdev)
1241 {
1242         int r;
1243
1244         /* set common regs */
1245         r100_set_common_regs(rdev);
1246         /* program mc */
1247         r300_mc_program(rdev);
1248         /* Resume clock */
1249         r300_clock_startup(rdev);
1250         /* Initialize GPU configuration (# pipes, ...) */
1251         r300_gpu_init(rdev);
1252         /* Initialize GART (initialize after TTM so we can allocate
1253          * memory through TTM but finalize after TTM) */
1254         if (rdev->flags & RADEON_IS_PCIE) {
1255                 r = rv370_pcie_gart_enable(rdev);
1256                 if (r)
1257                         return r;
1258         }
1259
1260         if (rdev->family == CHIP_R300 ||
1261             rdev->family == CHIP_R350 ||
1262             rdev->family == CHIP_RV350)
1263                 r100_enable_bm(rdev);
1264
1265         if (rdev->flags & RADEON_IS_PCI) {
1266                 r = r100_pci_gart_enable(rdev);
1267                 if (r)
1268                         return r;
1269         }
1270         /* Enable IRQ */
1271         r100_irq_set(rdev);
1272         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1273         /* 1M ring buffer */
1274         r = r100_cp_init(rdev, 1024 * 1024);
1275         if (r) {
1276                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1277                 return r;
1278         }
1279         r = r100_wb_init(rdev);
1280         if (r)
1281                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1282         r = r100_ib_init(rdev);
1283         if (r) {
1284                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1285                 return r;
1286         }
1287         return 0;
1288 }
1289
1290 int r300_resume(struct radeon_device *rdev)
1291 {
1292         /* Make sur GART are not working */
1293         if (rdev->flags & RADEON_IS_PCIE)
1294                 rv370_pcie_gart_disable(rdev);
1295         if (rdev->flags & RADEON_IS_PCI)
1296                 r100_pci_gart_disable(rdev);
1297         /* Resume clock before doing reset */
1298         r300_clock_startup(rdev);
1299         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1300         if (radeon_gpu_reset(rdev)) {
1301                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1302                         RREG32(R_000E40_RBBM_STATUS),
1303                         RREG32(R_0007C0_CP_STAT));
1304         }
1305         /* post */
1306         radeon_combios_asic_init(rdev->ddev);
1307         /* Resume clock after posting */
1308         r300_clock_startup(rdev);
1309         /* Initialize surface registers */
1310         radeon_surface_init(rdev);
1311         return r300_startup(rdev);
1312 }
1313
1314 int r300_suspend(struct radeon_device *rdev)
1315 {
1316         r100_cp_disable(rdev);
1317         r100_wb_disable(rdev);
1318         r100_irq_disable(rdev);
1319         if (rdev->flags & RADEON_IS_PCIE)
1320                 rv370_pcie_gart_disable(rdev);
1321         if (rdev->flags & RADEON_IS_PCI)
1322                 r100_pci_gart_disable(rdev);
1323         return 0;
1324 }
1325
1326 void r300_fini(struct radeon_device *rdev)
1327 {
1328         r100_cp_fini(rdev);
1329         r100_wb_fini(rdev);
1330         r100_ib_fini(rdev);
1331         radeon_gem_fini(rdev);
1332         if (rdev->flags & RADEON_IS_PCIE)
1333                 rv370_pcie_gart_fini(rdev);
1334         if (rdev->flags & RADEON_IS_PCI)
1335                 r100_pci_gart_fini(rdev);
1336         radeon_agp_fini(rdev);
1337         radeon_irq_kms_fini(rdev);
1338         radeon_fence_driver_fini(rdev);
1339         radeon_bo_fini(rdev);
1340         radeon_atombios_fini(rdev);
1341         kfree(rdev->bios);
1342         rdev->bios = NULL;
1343 }
1344
1345 int r300_init(struct radeon_device *rdev)
1346 {
1347         int r;
1348
1349         /* Disable VGA */
1350         r100_vga_render_disable(rdev);
1351         /* Initialize scratch registers */
1352         radeon_scratch_init(rdev);
1353         /* Initialize surface registers */
1354         radeon_surface_init(rdev);
1355         /* TODO: disable VGA need to use VGA request */
1356         /* BIOS*/
1357         if (!radeon_get_bios(rdev)) {
1358                 if (ASIC_IS_AVIVO(rdev))
1359                         return -EINVAL;
1360         }
1361         if (rdev->is_atom_bios) {
1362                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1363                 return -EINVAL;
1364         } else {
1365                 r = radeon_combios_init(rdev);
1366                 if (r)
1367                         return r;
1368         }
1369         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1370         if (radeon_gpu_reset(rdev)) {
1371                 dev_warn(rdev->dev,
1372                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1373                         RREG32(R_000E40_RBBM_STATUS),
1374                         RREG32(R_0007C0_CP_STAT));
1375         }
1376         /* check if cards are posted or not */
1377         if (radeon_boot_test_post_card(rdev) == false)
1378                 return -EINVAL;
1379         /* Set asic errata */
1380         r300_errata(rdev);
1381         /* Initialize clocks */
1382         radeon_get_clock_info(rdev->ddev);
1383         /* Initialize power management */
1384         radeon_pm_init(rdev);
1385         /* initialize AGP */
1386         if (rdev->flags & RADEON_IS_AGP) {
1387                 r = radeon_agp_init(rdev);
1388                 if (r) {
1389                         radeon_agp_disable(rdev);
1390                 }
1391         }
1392         /* initialize memory controller */
1393         r300_mc_init(rdev);
1394         /* Fence driver */
1395         r = radeon_fence_driver_init(rdev);
1396         if (r)
1397                 return r;
1398         r = radeon_irq_kms_init(rdev);
1399         if (r)
1400                 return r;
1401         /* Memory manager */
1402         r = radeon_bo_init(rdev);
1403         if (r)
1404                 return r;
1405         if (rdev->flags & RADEON_IS_PCIE) {
1406                 r = rv370_pcie_gart_init(rdev);
1407                 if (r)
1408                         return r;
1409         }
1410         if (rdev->flags & RADEON_IS_PCI) {
1411                 r = r100_pci_gart_init(rdev);
1412                 if (r)
1413                         return r;
1414         }
1415         r300_set_reg_safe(rdev);
1416         rdev->accel_working = true;
1417         r = r300_startup(rdev);
1418         if (r) {
1419                 /* Somethings want wront with the accel init stop accel */
1420                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1421                 r100_cp_fini(rdev);
1422                 r100_wb_fini(rdev);
1423                 r100_ib_fini(rdev);
1424                 radeon_irq_kms_fini(rdev);
1425                 if (rdev->flags & RADEON_IS_PCIE)
1426                         rv370_pcie_gart_fini(rdev);
1427                 if (rdev->flags & RADEON_IS_PCI)
1428                         r100_pci_gart_fini(rdev);
1429                 radeon_agp_fini(rdev);
1430                 rdev->accel_working = false;
1431         }
1432         return 0;
1433 }