2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_reg.h"
33 #include "radeon_drm.h"
34 #include "r100_track.h"
37 #include "r300_reg_safe.h"
39 /* r300,r350,rv350,rv370,rv380 depends on : */
40 void r100_hdp_reset(struct radeon_device *rdev);
41 int r100_cp_reset(struct radeon_device *rdev);
42 int r100_rb2d_reset(struct radeon_device *rdev);
43 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
44 int r100_pci_gart_enable(struct radeon_device *rdev);
45 void r100_mc_setup(struct radeon_device *rdev);
46 void r100_mc_disable_clients(struct radeon_device *rdev);
47 int r100_gui_wait_for_idle(struct radeon_device *rdev);
48 int r100_cs_packet_parse(struct radeon_cs_parser *p,
49 struct radeon_cs_packet *pkt,
51 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
52 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
53 struct radeon_cs_packet *pkt,
54 const unsigned *auth, unsigned n,
55 radeon_packet0_check_t check);
56 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
57 struct radeon_cs_packet *pkt,
58 struct radeon_object *robj);
60 /* This files gather functions specifics to:
61 * r300,r350,rv350,rv370,rv380
63 * Some of these functions might be used by newer ASICs.
65 void r300_gpu_init(struct radeon_device *rdev);
66 int r300_mc_wait_for_idle(struct radeon_device *rdev);
67 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
71 * rv370,rv380 PCIE GART
73 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
78 /* Workaround HW bug do flush 2 times */
79 for (i = 0; i < 2; i++) {
80 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
81 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
82 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
83 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
88 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
90 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
92 if (i < 0 || i > rdev->gart.num_gpu_pages) {
95 addr = (lower_32_bits(addr) >> 8) |
96 ((upper_32_bits(addr) & 0xff) << 24) |
98 /* on x86 we want this to be CPU endian, on powerpc
99 * on powerpc without HW swappers, it'll get swapped on way
100 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
101 writel(addr, ((void __iomem *)ptr) + (i * 4));
105 int rv370_pcie_gart_init(struct radeon_device *rdev)
109 if (rdev->gart.table.vram.robj) {
110 WARN(1, "RV370 PCIE GART already initialized.\n");
113 /* Initialize common gart structure */
114 r = radeon_gart_init(rdev);
117 r = rv370_debugfs_pcie_gart_info_init(rdev);
119 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
120 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
121 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
122 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
123 return radeon_gart_table_vram_alloc(rdev);
126 int rv370_pcie_gart_enable(struct radeon_device *rdev)
132 if (rdev->gart.table.vram.robj == NULL) {
133 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
136 r = radeon_gart_table_vram_pin(rdev);
139 /* discard memory request outside of configured range */
140 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
141 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
142 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
143 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096;
144 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
145 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
146 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
147 table_addr = rdev->gart.table_addr;
148 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
149 /* FIXME: setup default page */
150 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
151 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
153 WREG32_PCIE(0x18, 0);
154 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
155 tmp |= RADEON_PCIE_TX_GART_EN;
156 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
157 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
158 rv370_pcie_gart_tlb_flush(rdev);
159 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
160 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
161 rdev->gart.ready = true;
165 void rv370_pcie_gart_disable(struct radeon_device *rdev)
169 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
170 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
171 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
172 if (rdev->gart.table.vram.robj) {
173 radeon_object_kunmap(rdev->gart.table.vram.robj);
174 radeon_object_unpin(rdev->gart.table.vram.robj);
178 void rv370_pcie_gart_fini(struct radeon_device *rdev)
180 rv370_pcie_gart_disable(rdev);
181 radeon_gart_table_vram_free(rdev);
182 radeon_gart_fini(rdev);
188 int r300_mc_init(struct radeon_device *rdev)
192 if (r100_debugfs_rbbm_init(rdev)) {
193 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
197 r100_pci_gart_disable(rdev);
198 if (rdev->flags & RADEON_IS_PCIE) {
199 rv370_pcie_gart_disable(rdev);
202 /* Setup GPU memory space */
203 rdev->mc.vram_location = 0xFFFFFFFFUL;
204 rdev->mc.gtt_location = 0xFFFFFFFFUL;
205 if (rdev->flags & RADEON_IS_AGP) {
206 r = radeon_agp_init(rdev);
208 printk(KERN_WARNING "[drm] Disabling AGP\n");
209 rdev->flags &= ~RADEON_IS_AGP;
210 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
212 rdev->mc.gtt_location = rdev->mc.agp_base;
215 r = radeon_mc_setup(rdev);
220 /* Program GPU memory space */
221 r100_mc_disable_clients(rdev);
222 if (r300_mc_wait_for_idle(rdev)) {
223 printk(KERN_WARNING "Failed to wait MC idle while "
224 "programming pipes. Bad things might happen.\n");
230 void r300_mc_fini(struct radeon_device *rdev)
238 void r300_fence_ring_emit(struct radeon_device *rdev,
239 struct radeon_fence *fence)
241 /* Who ever call radeon_fence_emit should call ring_lock and ask
242 * for enough space (today caller are ib schedule and buffer move) */
243 /* Write SC register so SC & US assert idle */
244 radeon_ring_write(rdev, PACKET0(0x43E0, 0));
245 radeon_ring_write(rdev, 0);
246 radeon_ring_write(rdev, PACKET0(0x43E4, 0));
247 radeon_ring_write(rdev, 0);
249 radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
250 radeon_ring_write(rdev, (2 << 0));
251 radeon_ring_write(rdev, PACKET0(0x4F18, 0));
252 radeon_ring_write(rdev, (1 << 0));
253 /* Wait until IDLE & CLEAN */
254 radeon_ring_write(rdev, PACKET0(0x1720, 0));
255 radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9));
256 /* Emit fence sequence & fire IRQ */
257 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
258 radeon_ring_write(rdev, fence->seq);
259 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
260 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
265 * Global GPU functions
267 int r300_copy_dma(struct radeon_device *rdev,
271 struct radeon_fence *fence)
278 /* radeon pitch is /64 */
279 size = num_pages << PAGE_SHIFT;
280 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
281 r = radeon_ring_lock(rdev, num_loops * 4 + 64);
283 DRM_ERROR("radeon: moving bo (%d).\n", r);
286 /* Must wait for 2D idle & clean before DMA or hangs might happen */
287 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
288 radeon_ring_write(rdev, (1 << 16));
289 for (i = 0; i < num_loops; i++) {
291 if (cur_size > 0x1FFFFF) {
295 radeon_ring_write(rdev, PACKET0(0x720, 2));
296 radeon_ring_write(rdev, src_offset);
297 radeon_ring_write(rdev, dst_offset);
298 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
299 src_offset += cur_size;
300 dst_offset += cur_size;
302 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
303 radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
305 r = radeon_fence_emit(rdev, fence);
307 radeon_ring_unlock_commit(rdev);
311 void r300_ring_start(struct radeon_device *rdev)
313 unsigned gb_tile_config;
316 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
317 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
318 switch(rdev->num_gb_pipes) {
320 gb_tile_config |= R300_PIPE_COUNT_R300;
323 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
326 gb_tile_config |= R300_PIPE_COUNT_R420;
330 gb_tile_config |= R300_PIPE_COUNT_RV350;
334 r = radeon_ring_lock(rdev, 64);
338 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
339 radeon_ring_write(rdev,
340 RADEON_ISYNC_ANY2D_IDLE3D |
341 RADEON_ISYNC_ANY3D_IDLE2D |
342 RADEON_ISYNC_WAIT_IDLEGUI |
343 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
344 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
345 radeon_ring_write(rdev, gb_tile_config);
346 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
347 radeon_ring_write(rdev,
348 RADEON_WAIT_2D_IDLECLEAN |
349 RADEON_WAIT_3D_IDLECLEAN);
350 radeon_ring_write(rdev, PACKET0(0x170C, 0));
351 radeon_ring_write(rdev, 1 << 31);
352 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
353 radeon_ring_write(rdev, 0);
354 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
355 radeon_ring_write(rdev, 0);
356 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
357 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
358 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
359 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
360 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
361 radeon_ring_write(rdev,
362 RADEON_WAIT_2D_IDLECLEAN |
363 RADEON_WAIT_3D_IDLECLEAN);
364 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
365 radeon_ring_write(rdev, 0);
366 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
367 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
368 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
369 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
370 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
371 radeon_ring_write(rdev,
372 ((6 << R300_MS_X0_SHIFT) |
373 (6 << R300_MS_Y0_SHIFT) |
374 (6 << R300_MS_X1_SHIFT) |
375 (6 << R300_MS_Y1_SHIFT) |
376 (6 << R300_MS_X2_SHIFT) |
377 (6 << R300_MS_Y2_SHIFT) |
378 (6 << R300_MSBD0_Y_SHIFT) |
379 (6 << R300_MSBD0_X_SHIFT)));
380 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
381 radeon_ring_write(rdev,
382 ((6 << R300_MS_X3_SHIFT) |
383 (6 << R300_MS_Y3_SHIFT) |
384 (6 << R300_MS_X4_SHIFT) |
385 (6 << R300_MS_Y4_SHIFT) |
386 (6 << R300_MS_X5_SHIFT) |
387 (6 << R300_MS_Y5_SHIFT) |
388 (6 << R300_MSBD1_SHIFT)));
389 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
390 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
391 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
392 radeon_ring_write(rdev,
393 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
394 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
395 radeon_ring_write(rdev,
396 R300_GEOMETRY_ROUND_NEAREST |
397 R300_COLOR_ROUND_NEAREST);
398 radeon_ring_unlock_commit(rdev);
401 void r300_errata(struct radeon_device *rdev)
403 rdev->pll_errata = 0;
405 if (rdev->family == CHIP_R300 &&
406 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
407 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
411 int r300_mc_wait_for_idle(struct radeon_device *rdev)
416 for (i = 0; i < rdev->usec_timeout; i++) {
418 tmp = RREG32(0x0150);
419 if (tmp & (1 << 4)) {
427 void r300_gpu_init(struct radeon_device *rdev)
429 uint32_t gb_tile_config, tmp;
431 r100_hdp_reset(rdev);
432 /* FIXME: rv380 one pipes ? */
433 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
435 rdev->num_gb_pipes = 2;
437 /* rv350,rv370,rv380 */
438 rdev->num_gb_pipes = 1;
440 rdev->num_z_pipes = 1;
441 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
442 switch (rdev->num_gb_pipes) {
444 gb_tile_config |= R300_PIPE_COUNT_R300;
447 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
450 gb_tile_config |= R300_PIPE_COUNT_R420;
454 gb_tile_config |= R300_PIPE_COUNT_RV350;
457 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
459 if (r100_gui_wait_for_idle(rdev)) {
460 printk(KERN_WARNING "Failed to wait GUI idle while "
461 "programming pipes. Bad things might happen.\n");
464 tmp = RREG32(0x170C);
465 WREG32(0x170C, tmp | (1 << 31));
467 WREG32(R300_RB2D_DSTCACHE_MODE,
468 R300_DC_AUTOFLUSH_ENABLE |
469 R300_DC_DC_DISABLE_IGNORE_PE);
471 if (r100_gui_wait_for_idle(rdev)) {
472 printk(KERN_WARNING "Failed to wait GUI idle while "
473 "programming pipes. Bad things might happen.\n");
475 if (r300_mc_wait_for_idle(rdev)) {
476 printk(KERN_WARNING "Failed to wait MC idle while "
477 "programming pipes. Bad things might happen.\n");
479 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
480 rdev->num_gb_pipes, rdev->num_z_pipes);
483 int r300_ga_reset(struct radeon_device *rdev)
489 reinit_cp = rdev->cp.ready;
490 rdev->cp.ready = false;
491 for (i = 0; i < rdev->usec_timeout; i++) {
492 WREG32(RADEON_CP_CSQ_MODE, 0);
493 WREG32(RADEON_CP_CSQ_CNTL, 0);
494 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
495 (void)RREG32(RADEON_RBBM_SOFT_RESET);
497 WREG32(RADEON_RBBM_SOFT_RESET, 0);
498 /* Wait to prevent race in RBBM_STATUS */
500 tmp = RREG32(RADEON_RBBM_STATUS);
501 if (tmp & ((1 << 20) | (1 << 26))) {
502 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
503 /* GA still busy soft reset it */
504 WREG32(0x429C, 0x200);
505 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
510 /* Wait to prevent race in RBBM_STATUS */
512 tmp = RREG32(RADEON_RBBM_STATUS);
513 if (!(tmp & ((1 << 20) | (1 << 26)))) {
517 for (i = 0; i < rdev->usec_timeout; i++) {
518 tmp = RREG32(RADEON_RBBM_STATUS);
519 if (!(tmp & ((1 << 20) | (1 << 26)))) {
520 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
523 return r100_cp_init(rdev, rdev->cp.ring_size);
529 tmp = RREG32(RADEON_RBBM_STATUS);
530 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
534 int r300_gpu_reset(struct radeon_device *rdev)
538 /* reset order likely matter */
539 status = RREG32(RADEON_RBBM_STATUS);
541 r100_hdp_reset(rdev);
543 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
544 r100_rb2d_reset(rdev);
547 if (status & ((1 << 20) | (1 << 26))) {
551 status = RREG32(RADEON_RBBM_STATUS);
552 if (status & (1 << 16)) {
555 /* Check if GPU is idle */
556 status = RREG32(RADEON_RBBM_STATUS);
557 if (status & (1 << 31)) {
558 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
561 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
567 * r300,r350,rv350,rv380 VRAM info
569 void r300_vram_info(struct radeon_device *rdev)
573 /* DDR for all card after R300 & IGP */
574 rdev->mc.vram_is_ddr = true;
575 tmp = RREG32(RADEON_MEM_CNTL);
576 if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
577 rdev->mc.vram_width = 128;
579 rdev->mc.vram_width = 64;
582 r100_vram_init_sizes(rdev);
590 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
592 uint32_t link_width_cntl, mask;
594 if (rdev->flags & RADEON_IS_IGP)
597 if (!(rdev->flags & RADEON_IS_PCIE))
600 /* FIXME wait for idle */
604 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
607 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
610 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
613 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
616 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
619 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
623 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
627 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
629 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
630 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
633 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
634 RADEON_PCIE_LC_RECONFIG_NOW |
635 RADEON_PCIE_LC_RECONFIG_LATER |
636 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
637 link_width_cntl |= mask;
638 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
639 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
640 RADEON_PCIE_LC_RECONFIG_NOW));
642 /* wait for lane set to complete */
643 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
644 while (link_width_cntl == 0xffffffff)
645 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
653 #if defined(CONFIG_DEBUG_FS)
654 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
656 struct drm_info_node *node = (struct drm_info_node *) m->private;
657 struct drm_device *dev = node->minor->dev;
658 struct radeon_device *rdev = dev->dev_private;
661 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
662 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
663 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
664 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
665 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
666 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
667 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
668 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
669 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
670 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
671 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
672 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
673 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
674 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
678 static struct drm_info_list rv370_pcie_gart_info_list[] = {
679 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
683 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
685 #if defined(CONFIG_DEBUG_FS)
686 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
696 static int r300_packet0_check(struct radeon_cs_parser *p,
697 struct radeon_cs_packet *pkt,
698 unsigned idx, unsigned reg)
700 struct radeon_cs_chunk *ib_chunk;
701 struct radeon_cs_reloc *reloc;
702 struct r100_cs_track *track;
703 volatile uint32_t *ib;
704 uint32_t tmp, tile_flags = 0;
709 ib_chunk = &p->chunks[p->chunk_ib_idx];
710 track = (struct r100_cs_track *)p->track;
712 case AVIVO_D1MODE_VLINE_START_END:
713 case RADEON_CRTC_GUI_TRIG_VLINE:
714 r = r100_cs_packet_parse_vline(p);
716 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
718 r100_cs_dump_packet(p, pkt);
722 case RADEON_DST_PITCH_OFFSET:
723 case RADEON_SRC_PITCH_OFFSET:
724 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
728 case R300_RB3D_COLOROFFSET0:
729 case R300_RB3D_COLOROFFSET1:
730 case R300_RB3D_COLOROFFSET2:
731 case R300_RB3D_COLOROFFSET3:
732 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
733 r = r100_cs_packet_next_reloc(p, &reloc);
735 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
737 r100_cs_dump_packet(p, pkt);
740 track->cb[i].robj = reloc->robj;
741 track->cb[i].offset = ib_chunk->kdata[idx];
742 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
744 case R300_ZB_DEPTHOFFSET:
745 r = r100_cs_packet_next_reloc(p, &reloc);
747 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
749 r100_cs_dump_packet(p, pkt);
752 track->zb.robj = reloc->robj;
753 track->zb.offset = ib_chunk->kdata[idx];
754 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
756 case R300_TX_OFFSET_0:
757 case R300_TX_OFFSET_0+4:
758 case R300_TX_OFFSET_0+8:
759 case R300_TX_OFFSET_0+12:
760 case R300_TX_OFFSET_0+16:
761 case R300_TX_OFFSET_0+20:
762 case R300_TX_OFFSET_0+24:
763 case R300_TX_OFFSET_0+28:
764 case R300_TX_OFFSET_0+32:
765 case R300_TX_OFFSET_0+36:
766 case R300_TX_OFFSET_0+40:
767 case R300_TX_OFFSET_0+44:
768 case R300_TX_OFFSET_0+48:
769 case R300_TX_OFFSET_0+52:
770 case R300_TX_OFFSET_0+56:
771 case R300_TX_OFFSET_0+60:
772 i = (reg - R300_TX_OFFSET_0) >> 2;
773 r = r100_cs_packet_next_reloc(p, &reloc);
775 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
777 r100_cs_dump_packet(p, pkt);
780 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
781 track->textures[i].robj = reloc->robj;
783 /* Tracked registers */
786 track->vap_vf_cntl = ib_chunk->kdata[idx];
790 track->vtx_size = ib_chunk->kdata[idx] & 0x7F;
793 /* VAP_VF_MAX_VTX_INDX */
794 track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
798 track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1;
799 if (p->rdev->family < CHIP_RV515) {
805 track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1;
811 /* RB3D_COLORPITCH0 */
812 /* RB3D_COLORPITCH1 */
813 /* RB3D_COLORPITCH2 */
814 /* RB3D_COLORPITCH3 */
815 r = r100_cs_packet_next_reloc(p, &reloc);
817 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
819 r100_cs_dump_packet(p, pkt);
823 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
824 tile_flags |= R300_COLOR_TILE_ENABLE;
825 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
826 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
828 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
832 i = (reg - 0x4E38) >> 2;
833 track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE;
834 switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) {
838 track->cb[i].cpp = 1;
844 track->cb[i].cpp = 2;
847 track->cb[i].cpp = 4;
850 track->cb[i].cpp = 8;
853 track->cb[i].cpp = 16;
856 DRM_ERROR("Invalid color buffer format (%d) !\n",
857 ((ib_chunk->kdata[idx] >> 21) & 0xF));
863 if (ib_chunk->kdata[idx] & 2) {
864 track->z_enabled = true;
866 track->z_enabled = false;
871 switch ((ib_chunk->kdata[idx] & 0xF)) {
880 DRM_ERROR("Invalid z buffer format (%d) !\n",
881 (ib_chunk->kdata[idx] & 0xF));
887 r = r100_cs_packet_next_reloc(p, &reloc);
889 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
891 r100_cs_dump_packet(p, pkt);
895 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
896 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
897 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
898 tile_flags |= R300_DEPTHMICROTILE_TILED;;
900 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
904 track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC;
907 for (i = 0; i < 16; i++) {
910 enabled = !!(ib_chunk->kdata[idx] & (1 << i));
911 track->textures[i].enabled = enabled;
930 /* TX_FORMAT1_[0-15] */
931 i = (reg - 0x44C0) >> 2;
932 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
933 track->textures[i].tex_coord_type = tmp;
934 switch ((ib_chunk->kdata[idx] & 0x1F)) {
935 case R300_TX_FORMAT_X8:
936 case R300_TX_FORMAT_Y4X4:
937 case R300_TX_FORMAT_Z3Y3X2:
938 track->textures[i].cpp = 1;
940 case R300_TX_FORMAT_X16:
941 case R300_TX_FORMAT_Y8X8:
942 case R300_TX_FORMAT_Z5Y6X5:
943 case R300_TX_FORMAT_Z6Y5X5:
944 case R300_TX_FORMAT_W4Z4Y4X4:
945 case R300_TX_FORMAT_W1Z5Y5X5:
946 case R300_TX_FORMAT_DXT1:
947 case R300_TX_FORMAT_D3DMFT_CxV8U8:
948 case R300_TX_FORMAT_B8G8_B8G8:
949 case R300_TX_FORMAT_G8R8_G8B8:
950 track->textures[i].cpp = 2;
952 case R300_TX_FORMAT_Y16X16:
953 case R300_TX_FORMAT_Z11Y11X10:
954 case R300_TX_FORMAT_Z10Y11X11:
955 case R300_TX_FORMAT_W8Z8Y8X8:
956 case R300_TX_FORMAT_W2Z10Y10X10:
958 case R300_TX_FORMAT_FL_I32:
960 case R300_TX_FORMAT_DXT3:
961 case R300_TX_FORMAT_DXT5:
962 track->textures[i].cpp = 4;
964 case R300_TX_FORMAT_W16Z16Y16X16:
965 case R300_TX_FORMAT_FL_R16G16B16A16:
966 case R300_TX_FORMAT_FL_I32A32:
967 track->textures[i].cpp = 8;
969 case R300_TX_FORMAT_FL_R32G32B32A32:
970 track->textures[i].cpp = 16;
973 DRM_ERROR("Invalid texture format %u\n",
974 (ib_chunk->kdata[idx] & 0x1F));
995 /* TX_FILTER0_[0-15] */
996 i = (reg - 0x4400) >> 2;
997 tmp = ib_chunk->kdata[idx] & 0x7;
998 if (tmp == 2 || tmp == 4 || tmp == 6) {
999 track->textures[i].roundup_w = false;
1001 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;
1002 if (tmp == 2 || tmp == 4 || tmp == 6) {
1003 track->textures[i].roundup_h = false;
1022 /* TX_FORMAT2_[0-15] */
1023 i = (reg - 0x4500) >> 2;
1024 tmp = ib_chunk->kdata[idx] & 0x3FFF;
1025 track->textures[i].pitch = tmp + 1;
1026 if (p->rdev->family >= CHIP_RV515) {
1027 tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11;
1028 track->textures[i].width_11 = tmp;
1029 tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11;
1030 track->textures[i].height_11 = tmp;
1049 /* TX_FORMAT0_[0-15] */
1050 i = (reg - 0x4480) >> 2;
1051 tmp = ib_chunk->kdata[idx] & 0x7FF;
1052 track->textures[i].width = tmp + 1;
1053 tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF;
1054 track->textures[i].height = tmp + 1;
1055 tmp = (ib_chunk->kdata[idx] >> 26) & 0xF;
1056 track->textures[i].num_levels = tmp;
1057 tmp = ib_chunk->kdata[idx] & (1 << 31);
1058 track->textures[i].use_pitch = !!tmp;
1059 tmp = (ib_chunk->kdata[idx] >> 22) & 0xF;
1060 track->textures[i].txdepth = tmp;
1062 case R300_ZB_ZPASS_ADDR:
1063 r = r100_cs_packet_next_reloc(p, &reloc);
1065 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1067 r100_cs_dump_packet(p, pkt);
1070 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1073 /* valid register only on RV530 */
1074 if (p->rdev->family == CHIP_RV530)
1076 /* fallthrough do not move */
1078 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1085 static int r300_packet3_check(struct radeon_cs_parser *p,
1086 struct radeon_cs_packet *pkt)
1088 struct radeon_cs_chunk *ib_chunk;
1090 struct radeon_cs_reloc *reloc;
1091 struct r100_cs_track *track;
1092 volatile uint32_t *ib;
1098 ib_chunk = &p->chunks[p->chunk_ib_idx];
1100 track = (struct r100_cs_track *)p->track;
1101 switch(pkt->opcode) {
1102 case PACKET3_3D_LOAD_VBPNTR:
1103 c = ib_chunk->kdata[idx++] & 0x1F;
1104 track->num_arrays = c;
1105 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1106 r = r100_cs_packet_next_reloc(p, &reloc);
1108 DRM_ERROR("No reloc for packet3 %d\n",
1110 r100_cs_dump_packet(p, pkt);
1113 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1114 track->arrays[i + 0].robj = reloc->robj;
1115 track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1116 track->arrays[i + 0].esize &= 0x7F;
1117 r = r100_cs_packet_next_reloc(p, &reloc);
1119 DRM_ERROR("No reloc for packet3 %d\n",
1121 r100_cs_dump_packet(p, pkt);
1124 ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1125 track->arrays[i + 1].robj = reloc->robj;
1126 track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24;
1127 track->arrays[i + 1].esize &= 0x7F;
1130 r = r100_cs_packet_next_reloc(p, &reloc);
1132 DRM_ERROR("No reloc for packet3 %d\n",
1134 r100_cs_dump_packet(p, pkt);
1137 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1138 track->arrays[i + 0].robj = reloc->robj;
1139 track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1140 track->arrays[i + 0].esize &= 0x7F;
1143 case PACKET3_INDX_BUFFER:
1144 r = r100_cs_packet_next_reloc(p, &reloc);
1146 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1147 r100_cs_dump_packet(p, pkt);
1150 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1151 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1157 case PACKET3_3D_DRAW_IMMD:
1158 /* Number of dwords is vtx_size * (num_vertices - 1)
1159 * PRIM_WALK must be equal to 3 vertex data in embedded
1161 if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) {
1162 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1165 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1166 track->immd_dwords = pkt->count - 1;
1167 r = r100_cs_track_check(p->rdev, track);
1172 case PACKET3_3D_DRAW_IMMD_2:
1173 /* Number of dwords is vtx_size * (num_vertices - 1)
1174 * PRIM_WALK must be equal to 3 vertex data in embedded
1176 if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) {
1177 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1180 track->vap_vf_cntl = ib_chunk->kdata[idx];
1181 track->immd_dwords = pkt->count;
1182 r = r100_cs_track_check(p->rdev, track);
1187 case PACKET3_3D_DRAW_VBUF:
1188 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1189 r = r100_cs_track_check(p->rdev, track);
1194 case PACKET3_3D_DRAW_VBUF_2:
1195 track->vap_vf_cntl = ib_chunk->kdata[idx];
1196 r = r100_cs_track_check(p->rdev, track);
1201 case PACKET3_3D_DRAW_INDX:
1202 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1203 r = r100_cs_track_check(p->rdev, track);
1208 case PACKET3_3D_DRAW_INDX_2:
1209 track->vap_vf_cntl = ib_chunk->kdata[idx];
1210 r = r100_cs_track_check(p->rdev, track);
1218 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1224 int r300_cs_parse(struct radeon_cs_parser *p)
1226 struct radeon_cs_packet pkt;
1227 struct r100_cs_track *track;
1230 track = kzalloc(sizeof(*track), GFP_KERNEL);
1231 r100_cs_track_clear(p->rdev, track);
1234 r = r100_cs_packet_parse(p, &pkt, p->idx);
1238 p->idx += pkt.count + 2;
1241 r = r100_cs_parse_packet0(p, &pkt,
1242 p->rdev->config.r300.reg_safe_bm,
1243 p->rdev->config.r300.reg_safe_bm_size,
1244 &r300_packet0_check);
1249 r = r300_packet3_check(p, &pkt);
1252 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1258 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1262 void r300_set_reg_safe(struct radeon_device *rdev)
1264 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1265 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1268 int r300_init(struct radeon_device *rdev)
1270 r300_set_reg_safe(rdev);
1274 void r300_mc_program(struct radeon_device *rdev)
1276 struct r100_mc_save save;
1279 r = r100_debugfs_mc_info_init(rdev);
1281 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1284 /* Stops all mc clients */
1285 r100_mc_stop(rdev, &save);
1286 if (rdev->flags & RADEON_IS_AGP) {
1287 WREG32(R_00014C_MC_AGP_LOCATION,
1288 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1289 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1290 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1291 WREG32(R_00015C_AGP_BASE_2,
1292 upper_32_bits(rdev->mc.agp_base) & 0xff);
1294 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1295 WREG32(R_000170_AGP_BASE, 0);
1296 WREG32(R_00015C_AGP_BASE_2, 0);
1298 /* Wait for mc idle */
1299 if (r300_mc_wait_for_idle(rdev))
1300 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1301 /* Program MC, should be a 32bits limited address space */
1302 WREG32(R_000148_MC_FB_LOCATION,
1303 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1304 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1305 r100_mc_resume(rdev, &save);