2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
31 #include "radeon_reg.h"
33 #include "radeon_asic.h"
37 #include "r420_reg_safe.h"
39 void r420_pm_init_profile(struct radeon_device *rdev)
42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
60 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
75 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
78 static void r420_set_reg_safe(struct radeon_device *rdev)
80 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
81 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
84 void r420_pipes_init(struct radeon_device *rdev)
87 unsigned gb_pipe_select;
90 /* GA_ENHANCE workaround TCL deadlock issue */
91 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
93 /* add idle wait as per freedesktop.org bug 24041 */
94 if (r100_gui_wait_for_idle(rdev)) {
95 printk(KERN_WARNING "Failed to wait GUI idle while "
96 "programming pipes. Bad things might happen.\n");
98 /* get max number of pipes */
99 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
100 num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
102 /* SE chips have 1 pipe */
103 if ((rdev->pdev->device == 0x5e4c) ||
104 (rdev->pdev->device == 0x5e4f))
107 rdev->num_gb_pipes = num_pipes;
111 /* force to 1 pipe */
126 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
127 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
128 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
129 WREG32(R300_GB_TILE_CONFIG, tmp);
130 if (r100_gui_wait_for_idle(rdev)) {
131 printk(KERN_WARNING "Failed to wait GUI idle while "
132 "programming pipes. Bad things might happen.\n");
135 tmp = RREG32(R300_DST_PIPE_CONFIG);
136 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
138 WREG32(R300_RB2D_DSTCACHE_MODE,
139 RREG32(R300_RB2D_DSTCACHE_MODE) |
140 R300_DC_AUTOFLUSH_ENABLE |
141 R300_DC_DC_DISABLE_IGNORE_PE);
143 if (r100_gui_wait_for_idle(rdev)) {
144 printk(KERN_WARNING "Failed to wait GUI idle while "
145 "programming pipes. Bad things might happen.\n");
148 if (rdev->family == CHIP_RV530) {
149 tmp = RREG32(RV530_GB_PIPE_SELECT2);
151 rdev->num_z_pipes = 2;
153 rdev->num_z_pipes = 1;
155 rdev->num_z_pipes = 1;
157 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
158 rdev->num_gb_pipes, rdev->num_z_pipes);
161 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
165 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
166 r = RREG32(R_0001FC_MC_IND_DATA);
170 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
172 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
173 S_0001F8_MC_IND_WR_EN(1));
174 WREG32(R_0001FC_MC_IND_DATA, v);
177 static void r420_debugfs(struct radeon_device *rdev)
179 if (r100_debugfs_rbbm_init(rdev)) {
180 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
182 if (r420_debugfs_pipes_info_init(rdev)) {
183 DRM_ERROR("Failed to register debugfs file for pipes !\n");
187 static void r420_clock_resume(struct radeon_device *rdev)
191 if (radeon_dynclks != -1 && radeon_dynclks)
192 radeon_atom_set_clock_gating(rdev, 1);
193 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
194 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
195 if (rdev->family == CHIP_R420)
196 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
197 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
200 static void r420_cp_errata_init(struct radeon_device *rdev)
202 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
204 /* RV410 and R420 can lock up if CP DMA to host memory happens
205 * while the 2D engine is busy.
207 * The proper workaround is to queue a RESYNC at the beginning
208 * of the CP init, apparently.
210 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
211 radeon_ring_lock(rdev, ring, 8);
212 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
213 radeon_ring_write(ring, rdev->config.r300.resync_scratch);
214 radeon_ring_write(ring, 0xDEADBEEF);
215 radeon_ring_unlock_commit(rdev, ring);
218 static void r420_cp_errata_fini(struct radeon_device *rdev)
220 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
222 /* Catch the RESYNC we dispatched all the way back,
223 * at the very beginning of the CP init.
225 radeon_ring_lock(rdev, ring, 8);
226 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
227 radeon_ring_write(ring, R300_RB3D_DC_FINISH);
228 radeon_ring_unlock_commit(rdev, ring);
229 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
232 static int r420_startup(struct radeon_device *rdev)
236 /* set common regs */
237 r100_set_common_regs(rdev);
239 r300_mc_program(rdev);
241 r420_clock_resume(rdev);
242 /* Initialize GART (initialize after TTM so we can allocate
243 * memory through TTM but finalize after TTM) */
244 if (rdev->flags & RADEON_IS_PCIE) {
245 r = rv370_pcie_gart_enable(rdev);
249 if (rdev->flags & RADEON_IS_PCI) {
250 r = r100_pci_gart_enable(rdev);
254 r420_pipes_init(rdev);
256 /* allocate wb buffer */
257 r = radeon_wb_init(rdev);
261 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
263 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
268 if (!rdev->irq.installed) {
269 r = radeon_irq_kms_init(rdev);
275 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
277 r = r100_cp_init(rdev, 1024 * 1024);
279 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
282 r420_cp_errata_init(rdev);
284 r = radeon_ib_pool_init(rdev);
286 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
293 int r420_resume(struct radeon_device *rdev)
297 /* Make sur GART are not working */
298 if (rdev->flags & RADEON_IS_PCIE)
299 rv370_pcie_gart_disable(rdev);
300 if (rdev->flags & RADEON_IS_PCI)
301 r100_pci_gart_disable(rdev);
302 /* Resume clock before doing reset */
303 r420_clock_resume(rdev);
304 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
305 if (radeon_asic_reset(rdev)) {
306 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
307 RREG32(R_000E40_RBBM_STATUS),
308 RREG32(R_0007C0_CP_STAT));
310 /* check if cards are posted or not */
311 if (rdev->is_atom_bios) {
312 atom_asic_init(rdev->mode_info.atom_context);
314 radeon_combios_asic_init(rdev->ddev);
316 /* Resume clock after posting */
317 r420_clock_resume(rdev);
318 /* Initialize surface registers */
319 radeon_surface_init(rdev);
321 rdev->accel_working = true;
322 r = r420_startup(rdev);
324 rdev->accel_working = false;
329 int r420_suspend(struct radeon_device *rdev)
331 r420_cp_errata_fini(rdev);
332 r100_cp_disable(rdev);
333 radeon_wb_disable(rdev);
334 r100_irq_disable(rdev);
335 if (rdev->flags & RADEON_IS_PCIE)
336 rv370_pcie_gart_disable(rdev);
337 if (rdev->flags & RADEON_IS_PCI)
338 r100_pci_gart_disable(rdev);
342 void r420_fini(struct radeon_device *rdev)
345 radeon_wb_fini(rdev);
346 radeon_ib_pool_fini(rdev);
347 radeon_gem_fini(rdev);
348 if (rdev->flags & RADEON_IS_PCIE)
349 rv370_pcie_gart_fini(rdev);
350 if (rdev->flags & RADEON_IS_PCI)
351 r100_pci_gart_fini(rdev);
352 radeon_agp_fini(rdev);
353 radeon_irq_kms_fini(rdev);
354 radeon_fence_driver_fini(rdev);
355 radeon_bo_fini(rdev);
356 if (rdev->is_atom_bios) {
357 radeon_atombios_fini(rdev);
359 radeon_combios_fini(rdev);
365 int r420_init(struct radeon_device *rdev)
369 /* Initialize scratch registers */
370 radeon_scratch_init(rdev);
371 /* Initialize surface registers */
372 radeon_surface_init(rdev);
373 /* TODO: disable VGA need to use VGA request */
374 /* restore some register to sane defaults */
375 r100_restore_sanity(rdev);
377 if (!radeon_get_bios(rdev)) {
378 if (ASIC_IS_AVIVO(rdev))
381 if (rdev->is_atom_bios) {
382 r = radeon_atombios_init(rdev);
387 r = radeon_combios_init(rdev);
392 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
393 if (radeon_asic_reset(rdev)) {
395 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
396 RREG32(R_000E40_RBBM_STATUS),
397 RREG32(R_0007C0_CP_STAT));
399 /* check if cards are posted or not */
400 if (radeon_boot_test_post_card(rdev) == false)
403 /* Initialize clocks */
404 radeon_get_clock_info(rdev->ddev);
406 if (rdev->flags & RADEON_IS_AGP) {
407 r = radeon_agp_init(rdev);
409 radeon_agp_disable(rdev);
412 /* initialize memory controller */
416 r = radeon_fence_driver_init(rdev);
421 r = radeon_bo_init(rdev);
425 if (rdev->family == CHIP_R420)
426 r100_enable_bm(rdev);
428 if (rdev->flags & RADEON_IS_PCIE) {
429 r = rv370_pcie_gart_init(rdev);
433 if (rdev->flags & RADEON_IS_PCI) {
434 r = r100_pci_gart_init(rdev);
438 r420_set_reg_safe(rdev);
440 rdev->accel_working = true;
441 r = r420_startup(rdev);
443 /* Somethings want wront with the accel init stop accel */
444 dev_err(rdev->dev, "Disabling GPU acceleration\n");
446 radeon_wb_fini(rdev);
447 radeon_ib_pool_fini(rdev);
448 radeon_irq_kms_fini(rdev);
449 if (rdev->flags & RADEON_IS_PCIE)
450 rv370_pcie_gart_fini(rdev);
451 if (rdev->flags & RADEON_IS_PCI)
452 r100_pci_gart_fini(rdev);
453 radeon_agp_fini(rdev);
454 rdev->accel_working = false;
462 #if defined(CONFIG_DEBUG_FS)
463 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
465 struct drm_info_node *node = (struct drm_info_node *) m->private;
466 struct drm_device *dev = node->minor->dev;
467 struct radeon_device *rdev = dev->dev_private;
470 tmp = RREG32(R400_GB_PIPE_SELECT);
471 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
472 tmp = RREG32(R300_GB_TILE_CONFIG);
473 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
474 tmp = RREG32(R300_DST_PIPE_CONFIG);
475 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
479 static struct drm_info_list r420_pipes_info_list[] = {
480 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
484 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
486 #if defined(CONFIG_DEBUG_FS)
487 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);