drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/radeon_drm.h>
  35 #include "radeon.h"
  36 #include "radeon_asic.h"
  37 #include "radeon_mode.h"
  38 #include "r600d.h"
  39 #include "atom.h"
  40 #include "avivod.h"
  41
  42 #define PFP_UCODE_SIZE 576
  43 #define PM4_UCODE_SIZE 1792
  44 #define RLC_UCODE_SIZE 768
  45 #define R700_PFP_UCODE_SIZE 848
  46 #define R700_PM4_UCODE_SIZE 1360
  47 #define R700_RLC_UCODE_SIZE 1024
  48 #define EVERGREEN_PFP_UCODE_SIZE 1120
  49 #define EVERGREEN_PM4_UCODE_SIZE 1376
  50 #define EVERGREEN_RLC_UCODE_SIZE 768
  51 #define CAYMAN_RLC_UCODE_SIZE 1024
  52 #define ARUBA_RLC_UCODE_SIZE 1536
  53
  54 /* Firmware Names */
  55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  56 MODULE_FIRMWARE("radeon/R600_me.bin");
  57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV610_me.bin");
  59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RV630_me.bin");
  61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV620_me.bin");
  63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV635_me.bin");
  65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RV670_me.bin");
  67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  68 MODULE_FIRMWARE("radeon/RS780_me.bin");
  69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  70 MODULE_FIRMWARE("radeon/RV770_me.bin");
  71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  72 MODULE_FIRMWARE("radeon/RV730_me.bin");
  73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  74 MODULE_FIRMWARE("radeon/RV710_me.bin");
  75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  90 MODULE_FIRMWARE("radeon/PALM_me.bin");
  91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  96
  97 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  98
  99 /* r600,rv610,rv630,rv620,rv635,rv670 */
 100 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 101 static void r600_gpu_init(struct radeon_device *rdev);
 102 void r600_fini(struct radeon_device *rdev);
 103 void r600_irq_disable(struct radeon_device *rdev);
 104 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 105
 106 /* get temperature in millidegrees */
 107 int rv6xx_get_temp(struct radeon_device *rdev)
 108 {
 109         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 110                 ASIC_T_SHIFT;
 111         int actual_temp = temp & 0xff;
 112
 113         if (temp & 0x100)
 114                 actual_temp -= 256;
 115
 116         return actual_temp * 1000;
 117 }
 118
 119 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 120 {
 121         int i;
 122
 123         rdev->pm.dynpm_can_upclock = true;
 124         rdev->pm.dynpm_can_downclock = true;
 125
 126         /* power state array is low to high, default is first */
 127         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 128                 int min_power_state_index = 0;
 129
 130                 if (rdev->pm.num_power_states > 2)
 131                         min_power_state_index = 1;
 132
 133                 switch (rdev->pm.dynpm_planned_action) {
 134                 case DYNPM_ACTION_MINIMUM:
 135                         rdev->pm.requested_power_state_index = min_power_state_index;
 136                         rdev->pm.requested_clock_mode_index = 0;
 137                         rdev->pm.dynpm_can_downclock = false;
 138                         break;
 139                 case DYNPM_ACTION_DOWNCLOCK:
 140                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 141                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 142                                 rdev->pm.dynpm_can_downclock = false;
 143                         } else {
 144                                 if (rdev->pm.active_crtc_count > 1) {
 145                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 146                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 147                                                         continue;
 148                                                 else if (i >= rdev->pm.current_power_state_index) {
 149                                                         rdev->pm.requested_power_state_index =
 150                                                                 rdev->pm.current_power_state_index;
 151                                                         break;
 152                                                 } else {
 153                                                         rdev->pm.requested_power_state_index = i;
 154                                                         break;
 155                                                 }
 156                                         }
 157                                 } else {
 158                                         if (rdev->pm.current_power_state_index == 0)
 159                                                 rdev->pm.requested_power_state_index =
 160                                                         rdev->pm.num_power_states - 1;
 161                                         else
 162                                                 rdev->pm.requested_power_state_index =
 163                                                         rdev->pm.current_power_state_index - 1;
 164                                 }
 165                         }
 166                         rdev->pm.requested_clock_mode_index = 0;
 167                         /* don't use the power state if crtcs are active and no display flag is set */
 168                         if ((rdev->pm.active_crtc_count > 0) &&
 169                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 170                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 171                              RADEON_PM_MODE_NO_DISPLAY)) {
 172                                 rdev->pm.requested_power_state_index++;
 173                         }
 174                         break;
 175                 case DYNPM_ACTION_UPCLOCK:
 176                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 177                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 178                                 rdev->pm.dynpm_can_upclock = false;
 179                         } else {
 180                                 if (rdev->pm.active_crtc_count > 1) {
 181                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 182                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 183                                                         continue;
 184                                                 else if (i <= rdev->pm.current_power_state_index) {
 185                                                         rdev->pm.requested_power_state_index =
 186                                                                 rdev->pm.current_power_state_index;
 187                                                         break;
 188                                                 } else {
 189                                                         rdev->pm.requested_power_state_index = i;
 190                                                         break;
 191                                                 }
 192                                         }
 193                                 } else
 194                                         rdev->pm.requested_power_state_index =
 195                                                 rdev->pm.current_power_state_index + 1;
 196                         }
 197                         rdev->pm.requested_clock_mode_index = 0;
 198                         break;
 199                 case DYNPM_ACTION_DEFAULT:
 200                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 201                         rdev->pm.requested_clock_mode_index = 0;
 202                         rdev->pm.dynpm_can_upclock = false;
 203                         break;
 204                 case DYNPM_ACTION_NONE:
 205                 default:
 206                         DRM_ERROR("Requested mode for not defined action\n");
 207                         return;
 208                 }
 209         } else {
 210                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 211                 /* for now just select the first power state and switch between clock modes */
 212                 /* power state array is low to high, default is first (0) */
 213                 if (rdev->pm.active_crtc_count > 1) {
 214                         rdev->pm.requested_power_state_index = -1;
 215                         /* start at 1 as we don't want the default mode */
 216                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 217                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 218                                         continue;
 219                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 220                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 221                                         rdev->pm.requested_power_state_index = i;
 222                                         break;
 223                                 }
 224                         }
 225                         /* if nothing selected, grab the default state. */
 226                         if (rdev->pm.requested_power_state_index == -1)
 227                                 rdev->pm.requested_power_state_index = 0;
 228                 } else
 229                         rdev->pm.requested_power_state_index = 1;
 230
 231                 switch (rdev->pm.dynpm_planned_action) {
 232                 case DYNPM_ACTION_MINIMUM:
 233                         rdev->pm.requested_clock_mode_index = 0;
 234                         rdev->pm.dynpm_can_downclock = false;
 235                         break;
 236                 case DYNPM_ACTION_DOWNCLOCK:
 237                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 238                                 if (rdev->pm.current_clock_mode_index == 0) {
 239                                         rdev->pm.requested_clock_mode_index = 0;
 240                                         rdev->pm.dynpm_can_downclock = false;
 241                                 } else
 242                                         rdev->pm.requested_clock_mode_index =
 243                                                 rdev->pm.current_clock_mode_index - 1;
 244                         } else {
 245                                 rdev->pm.requested_clock_mode_index = 0;
 246                                 rdev->pm.dynpm_can_downclock = false;
 247                         }
 248                         /* don't use the power state if crtcs are active and no display flag is set */
 249                         if ((rdev->pm.active_crtc_count > 0) &&
 250                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 251                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 252                              RADEON_PM_MODE_NO_DISPLAY)) {
 253                                 rdev->pm.requested_clock_mode_index++;
 254                         }
 255                         break;
 256                 case DYNPM_ACTION_UPCLOCK:
 257                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 258                                 if (rdev->pm.current_clock_mode_index ==
 259                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 260                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 261                                         rdev->pm.dynpm_can_upclock = false;
 262                                 } else
 263                                         rdev->pm.requested_clock_mode_index =
 264                                                 rdev->pm.current_clock_mode_index + 1;
 265                         } else {
 266                                 rdev->pm.requested_clock_mode_index =
 267                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 268                                 rdev->pm.dynpm_can_upclock = false;
 269                         }
 270                         break;
 271                 case DYNPM_ACTION_DEFAULT:
 272                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 273                         rdev->pm.requested_clock_mode_index = 0;
 274                         rdev->pm.dynpm_can_upclock = false;
 275                         break;
 276                 case DYNPM_ACTION_NONE:
 277                 default:
 278                         DRM_ERROR("Requested mode for not defined action\n");
 279                         return;
 280                 }
 281         }
 282
 283         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 284                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 285                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 286                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 287                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 288                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 289                   pcie_lanes);
 290 }
 291
 292 void rs780_pm_init_profile(struct radeon_device *rdev)
 293 {
 294         if (rdev->pm.num_power_states == 2) {
 295                 /* default */
 296                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 297                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 298                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 299                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 300                 /* low sh */
 301                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 302                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 303                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 304                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 305                 /* mid sh */
 306                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 307                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 309                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 310                 /* high sh */
 311                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 312                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 313                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 314                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 315                 /* low mh */
 316                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 317                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 319                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 320                 /* mid mh */
 321                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 322                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 325                 /* high mh */
 326                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 327                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 328                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 330         } else if (rdev->pm.num_power_states == 3) {
 331                 /* default */
 332                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 333                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 334                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 336                 /* low sh */
 337                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 338                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 339                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 340                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 341                 /* mid sh */
 342                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 343                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 344                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 345                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 346                 /* high sh */
 347                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 348                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 349                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 350                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 351                 /* low mh */
 352                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 353                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 354                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 355                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 356                 /* mid mh */
 357                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 358                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 359                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 360                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 361                 /* high mh */
 362                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 363                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 364                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 365                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 366         } else {
 367                 /* default */
 368                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 369                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 370                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 371                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 372                 /* low sh */
 373                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 374                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 375                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 376                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 377                 /* mid sh */
 378                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 379                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 380                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 381                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 382                 /* high sh */
 383                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 384                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 385                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 386                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 387                 /* low mh */
 388                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 389                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 391                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 392                 /* mid mh */
 393                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 394                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 395                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 396                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 397                 /* high mh */
 398                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 399                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 400                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 401                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 402         }
 403 }
 404
 405 void r600_pm_init_profile(struct radeon_device *rdev)
 406 {
 407         int idx;
 408
 409         if (rdev->family == CHIP_R600) {
 410                 /* XXX */
 411                 /* default */
 412                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 413                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 414                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 415                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 416                 /* low sh */
 417                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 418                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 419                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 420                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 421                 /* mid sh */
 422                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 423                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 424                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 425                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 426                 /* high sh */
 427                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 428                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 429                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 430                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 431                 /* low mh */
 432                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 433                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 434                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 435                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 436                 /* mid mh */
 437                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 438                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 439                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 440                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 441                 /* high mh */
 442                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 443                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 444                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 445                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 446         } else {
 447                 if (rdev->pm.num_power_states < 4) {
 448                         /* default */
 449                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 450                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 451                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 452                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 453                         /* low sh */
 454                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 455                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 456                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 457                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 458                         /* mid sh */
 459                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 460                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 461                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 462                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 463                         /* high sh */
 464                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 465                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 466                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 467                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 468                         /* low mh */
 469                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 470                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 471                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 472                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 473                         /* low mh */
 474                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 475                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 476                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 477                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 478                         /* high mh */
 479                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 480                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 481                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 482                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 483                 } else {
 484                         /* default */
 485                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 486                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 487                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 488                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 489                         /* low sh */
 490                         if (rdev->flags & RADEON_IS_MOBILITY)
 491                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 492                         else
 493                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 494                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 495                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 496                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 497                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 498                         /* mid sh */
 499                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 500                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 501                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 502                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 503                         /* high sh */
 504                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 505                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 506                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 507                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 508                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 509                         /* low mh */
 510                         if (rdev->flags & RADEON_IS_MOBILITY)
 511                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 512                         else
 513                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 514                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 515                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 516                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 517                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 518                         /* mid mh */
 519                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 520                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 521                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 522                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 523                         /* high mh */
 524                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 525                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 526                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 527                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 528                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 529                 }
 530         }
 531 }
 532
 533 void r600_pm_misc(struct radeon_device *rdev)
 534 {
 535         int req_ps_idx = rdev->pm.requested_power_state_index;
 536         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 537         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 538         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 539
 540         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 541                 /* 0xff01 is a flag rather then an actual voltage */
 542                 if (voltage->voltage == 0xff01)
 543                         return;
 544                 if (voltage->voltage != rdev->pm.current_vddc) {
 545                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 546                         rdev->pm.current_vddc = voltage->voltage;
 547                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 548                 }
 549         }
 550 }
 551
 552 bool r600_gui_idle(struct radeon_device *rdev)
 553 {
 554         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 555                 return false;
 556         else
 557                 return true;
 558 }
 559
 560 /* hpd for digital panel detect/disconnect */
 561 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 562 {
 563         bool connected = false;
 564
 565         if (ASIC_IS_DCE3(rdev)) {
 566                 switch (hpd) {
 567                 case RADEON_HPD_1:
 568                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 569                                 connected = true;
 570                         break;
 571                 case RADEON_HPD_2:
 572                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 573                                 connected = true;
 574                         break;
 575                 case RADEON_HPD_3:
 576                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 577                                 connected = true;
 578                         break;
 579                 case RADEON_HPD_4:
 580                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 581                                 connected = true;
 582                         break;
 583                         /* DCE 3.2 */
 584                 case RADEON_HPD_5:
 585                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 586                                 connected = true;
 587                         break;
 588                 case RADEON_HPD_6:
 589                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 590                                 connected = true;
 591                         break;
 592                 default:
 593                         break;
 594                 }
 595         } else {
 596                 switch (hpd) {
 597                 case RADEON_HPD_1:
 598                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 599                                 connected = true;
 600                         break;
 601                 case RADEON_HPD_2:
 602                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 603                                 connected = true;
 604                         break;
 605                 case RADEON_HPD_3:
 606                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 607                                 connected = true;
 608                         break;
 609                 default:
 610                         break;
 611                 }
 612         }
 613         return connected;
 614 }
 615
 616 void r600_hpd_set_polarity(struct radeon_device *rdev,
 617                            enum radeon_hpd_id hpd)
 618 {
 619         u32 tmp;
 620         bool connected = r600_hpd_sense(rdev, hpd);
 621
 622         if (ASIC_IS_DCE3(rdev)) {
 623                 switch (hpd) {
 624                 case RADEON_HPD_1:
 625                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 626                         if (connected)
 627                                 tmp &= ~DC_HPDx_INT_POLARITY;
 628                         else
 629                                 tmp |= DC_HPDx_INT_POLARITY;
 630                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 631                         break;
 632                 case RADEON_HPD_2:
 633                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 634                         if (connected)
 635                                 tmp &= ~DC_HPDx_INT_POLARITY;
 636                         else
 637                                 tmp |= DC_HPDx_INT_POLARITY;
 638                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 639                         break;
 640                 case RADEON_HPD_3:
 641                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 642                         if (connected)
 643                                 tmp &= ~DC_HPDx_INT_POLARITY;
 644                         else
 645                                 tmp |= DC_HPDx_INT_POLARITY;
 646                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 647                         break;
 648                 case RADEON_HPD_4:
 649                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 650                         if (connected)
 651                                 tmp &= ~DC_HPDx_INT_POLARITY;
 652                         else
 653                                 tmp |= DC_HPDx_INT_POLARITY;
 654                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 655                         break;
 656                 case RADEON_HPD_5:
 657                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 658                         if (connected)
 659                                 tmp &= ~DC_HPDx_INT_POLARITY;
 660                         else
 661                                 tmp |= DC_HPDx_INT_POLARITY;
 662                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 663                         break;
 664                         /* DCE 3.2 */
 665                 case RADEON_HPD_6:
 666                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 667                         if (connected)
 668                                 tmp &= ~DC_HPDx_INT_POLARITY;
 669                         else
 670                                 tmp |= DC_HPDx_INT_POLARITY;
 671                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 672                         break;
 673                 default:
 674                         break;
 675                 }
 676         } else {
 677                 switch (hpd) {
 678                 case RADEON_HPD_1:
 679                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 680                         if (connected)
 681                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 682                         else
 683                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 684                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 685                         break;
 686                 case RADEON_HPD_2:
 687                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 688                         if (connected)
 689                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 690                         else
 691                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 692                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 693                         break;
 694                 case RADEON_HPD_3:
 695                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 696                         if (connected)
 697                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 698                         else
 699                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 700                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 701                         break;
 702                 default:
 703                         break;
 704                 }
 705         }
 706 }
 707
 708 void r600_hpd_init(struct radeon_device *rdev)
 709 {
 710         struct drm_device *dev = rdev->ddev;
 711         struct drm_connector *connector;
 712         unsigned enable = 0;
 713
 714         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 715                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 716
 717                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 718                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 719                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 720                          * aux dp channel on imac and help (but not completely fix)
 721                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 722                          */
 723                         continue;
 724                 }
 725                 if (ASIC_IS_DCE3(rdev)) {
 726                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 727                         if (ASIC_IS_DCE32(rdev))
 728                                 tmp |= DC_HPDx_EN;
 729
 730                         switch (radeon_connector->hpd.hpd) {
 731                         case RADEON_HPD_1:
 732                                 WREG32(DC_HPD1_CONTROL, tmp);
 733                                 break;
 734                         case RADEON_HPD_2:
 735                                 WREG32(DC_HPD2_CONTROL, tmp);
 736                                 break;
 737                         case RADEON_HPD_3:
 738                                 WREG32(DC_HPD3_CONTROL, tmp);
 739                                 break;
 740                         case RADEON_HPD_4:
 741                                 WREG32(DC_HPD4_CONTROL, tmp);
 742                                 break;
 743                                 /* DCE 3.2 */
 744                         case RADEON_HPD_5:
 745                                 WREG32(DC_HPD5_CONTROL, tmp);
 746                                 break;
 747                         case RADEON_HPD_6:
 748                                 WREG32(DC_HPD6_CONTROL, tmp);
 749                                 break;
 750                         default:
 751                                 break;
 752                         }
 753                 } else {
 754                         switch (radeon_connector->hpd.hpd) {
 755                         case RADEON_HPD_1:
 756                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 757                                 break;
 758                         case RADEON_HPD_2:
 759                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 760                                 break;
 761                         case RADEON_HPD_3:
 762                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 763                                 break;
 764                         default:
 765                                 break;
 766                         }
 767                 }
 768                 enable |= 1 << radeon_connector->hpd.hpd;
 769                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 770         }
 771         radeon_irq_kms_enable_hpd(rdev, enable);
 772 }
 773
 774 void r600_hpd_fini(struct radeon_device *rdev)
 775 {
 776         struct drm_device *dev = rdev->ddev;
 777         struct drm_connector *connector;
 778         unsigned disable = 0;
 779
 780         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 781                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 782                 if (ASIC_IS_DCE3(rdev)) {
 783                         switch (radeon_connector->hpd.hpd) {
 784                         case RADEON_HPD_1:
 785                                 WREG32(DC_HPD1_CONTROL, 0);
 786                                 break;
 787                         case RADEON_HPD_2:
 788                                 WREG32(DC_HPD2_CONTROL, 0);
 789                                 break;
 790                         case RADEON_HPD_3:
 791                                 WREG32(DC_HPD3_CONTROL, 0);
 792                                 break;
 793                         case RADEON_HPD_4:
 794                                 WREG32(DC_HPD4_CONTROL, 0);
 795                                 break;
 796                                 /* DCE 3.2 */
 797                         case RADEON_HPD_5:
 798                                 WREG32(DC_HPD5_CONTROL, 0);
 799                                 break;
 800                         case RADEON_HPD_6:
 801                                 WREG32(DC_HPD6_CONTROL, 0);
 802                                 break;
 803                         default:
 804                                 break;
 805                         }
 806                 } else {
 807                         switch (radeon_connector->hpd.hpd) {
 808                         case RADEON_HPD_1:
 809                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 810                                 break;
 811                         case RADEON_HPD_2:
 812                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 813                                 break;
 814                         case RADEON_HPD_3:
 815                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 816                                 break;
 817                         default:
 818                                 break;
 819                         }
 820                 }
 821                 disable |= 1 << radeon_connector->hpd.hpd;
 822         }
 823         radeon_irq_kms_disable_hpd(rdev, disable);
 824 }
 825
 826 /*
 827  * R600 PCIE GART
 828  */
 829 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 830 {
 831         unsigned i;
 832         u32 tmp;
 833
 834         /* flush hdp cache so updates hit vram */
 835         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 836             !(rdev->flags & RADEON_IS_AGP)) {
 837                 void __iomem *ptr = (void *)rdev->gart.ptr;
 838                 u32 tmp;
 839
 840                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 841                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 842                  * This seems to cause problems on some AGP cards. Just use the old
 843                  * method for them.
 844                  */
 845                 WREG32(HDP_DEBUG1, 0);
 846                 tmp = readl((void __iomem *)ptr);
 847         } else
 848                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 849
 850         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 851         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 852         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 853         for (i = 0; i < rdev->usec_timeout; i++) {
 854                 /* read MC_STATUS */
 855                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 856                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 857                 if (tmp == 2) {
 858                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 859                         return;
 860                 }
 861                 if (tmp) {
 862                         return;
 863                 }
 864                 udelay(1);
 865         }
 866 }
 867
 868 int r600_pcie_gart_init(struct radeon_device *rdev)
 869 {
 870         int r;
 871
 872         if (rdev->gart.robj) {
 873                 WARN(1, "R600 PCIE GART already initialized\n");
 874                 return 0;
 875         }
 876         /* Initialize common gart structure */
 877         r = radeon_gart_init(rdev);
 878         if (r)
 879                 return r;
 880         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 881         return radeon_gart_table_vram_alloc(rdev);
 882 }
 883
 884 static int r600_pcie_gart_enable(struct radeon_device *rdev)
 885 {
 886         u32 tmp;
 887         int r, i;
 888
 889         if (rdev->gart.robj == NULL) {
 890                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 891                 return -EINVAL;
 892         }
 893         r = radeon_gart_table_vram_pin(rdev);
 894         if (r)
 895                 return r;
 896         radeon_gart_restore(rdev);
 897
 898         /* Setup L2 cache */
 899         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 900                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 901                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 902         WREG32(VM_L2_CNTL2, 0);
 903         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 904         /* Setup TLB control */
 905         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 906                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 907                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 908                 ENABLE_WAIT_L2_QUERY;
 909         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 910         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 911         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 912         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 913         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 914         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 915         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 916         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 917         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 918         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 919         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 920         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 921         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 922         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 923         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 924         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 925         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 926         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 927                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 928         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 929                         (u32)(rdev->dummy_page.addr >> 12));
 930         for (i = 1; i < 7; i++)
 931                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 932
 933         r600_pcie_gart_tlb_flush(rdev);
 934         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 935                  (unsigned)(rdev->mc.gtt_size >> 20),
 936                  (unsigned long long)rdev->gart.table_addr);
 937         rdev->gart.ready = true;
 938         return 0;
 939 }
 940
 941 static void r600_pcie_gart_disable(struct radeon_device *rdev)
 942 {
 943         u32 tmp;
 944         int i;
 945
 946         /* Disable all tables */
 947         for (i = 0; i < 7; i++)
 948                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 949
 950         /* Disable L2 cache */
 951         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 952                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 953         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 954         /* Setup L1 TLB control */
 955         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 956                 ENABLE_WAIT_L2_QUERY;
 957         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 958         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 959         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 960         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 961         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 962         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 963         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 966         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 967         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 968         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 971         radeon_gart_table_vram_unpin(rdev);
 972 }
 973
 974 static void r600_pcie_gart_fini(struct radeon_device *rdev)
 975 {
 976         radeon_gart_fini(rdev);
 977         r600_pcie_gart_disable(rdev);
 978         radeon_gart_table_vram_free(rdev);
 979 }
 980
 981 static void r600_agp_enable(struct radeon_device *rdev)
 982 {
 983         u32 tmp;
 984         int i;
 985
 986         /* Setup L2 cache */
 987         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 988                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 989                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 990         WREG32(VM_L2_CNTL2, 0);
 991         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 992         /* Setup TLB control */
 993         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 994                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 995                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 996                 ENABLE_WAIT_L2_QUERY;
 997         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 998         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 999         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1000         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1001         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1002         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1003         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1004         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1005         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1006         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1007         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1008         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1010         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1011         for (i = 0; i < 7; i++)
1012                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1013 }
1014
1015 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1016 {
1017         unsigned i;
1018         u32 tmp;
1019
1020         for (i = 0; i < rdev->usec_timeout; i++) {
1021                 /* read MC_STATUS */
1022                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1023                 if (!tmp)
1024                         return 0;
1025                 udelay(1);
1026         }
1027         return -1;
1028 }
1029
1030 static void r600_mc_program(struct radeon_device *rdev)
1031 {
1032         struct rv515_mc_save save;
1033         u32 tmp;
1034         int i, j;
1035
1036         /* Initialize HDP */
1037         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1038                 WREG32((0x2c14 + j), 0x00000000);
1039                 WREG32((0x2c18 + j), 0x00000000);
1040                 WREG32((0x2c1c + j), 0x00000000);
1041                 WREG32((0x2c20 + j), 0x00000000);
1042                 WREG32((0x2c24 + j), 0x00000000);
1043         }
1044         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1045
1046         rv515_mc_stop(rdev, &save);
1047         if (r600_mc_wait_for_idle(rdev)) {
1048                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1049         }
1050         /* Lockout access through VGA aperture (doesn't exist before R600) */
1051         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1052         /* Update configuration */
1053         if (rdev->flags & RADEON_IS_AGP) {
1054                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1055                         /* VRAM before AGP */
1056                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1057                                 rdev->mc.vram_start >> 12);
1058                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1059                                 rdev->mc.gtt_end >> 12);
1060                 } else {
1061                         /* VRAM after AGP */
1062                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1063                                 rdev->mc.gtt_start >> 12);
1064                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1065                                 rdev->mc.vram_end >> 12);
1066                 }
1067         } else {
1068                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1069                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1070         }
1071         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1072         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1073         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1074         WREG32(MC_VM_FB_LOCATION, tmp);
1075         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1076         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1077         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1078         if (rdev->flags & RADEON_IS_AGP) {
1079                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1080                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1081                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1082         } else {
1083                 WREG32(MC_VM_AGP_BASE, 0);
1084                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1085                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1086         }
1087         if (r600_mc_wait_for_idle(rdev)) {
1088                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1089         }
1090         rv515_mc_resume(rdev, &save);
1091         /* we need to own VRAM, so turn off the VGA renderer here
1092          * to stop it overwriting our objects */
1093         rv515_vga_render_disable(rdev);
1094 }
1095
1096 /**
1097  * r600_vram_gtt_location - try to find VRAM & GTT location
1098  * @rdev: radeon device structure holding all necessary informations
1099  * @mc: memory controller structure holding memory informations
1100  *
1101  * Function will place try to place VRAM at same place as in CPU (PCI)
1102  * address space as some GPU seems to have issue when we reprogram at
1103  * different address space.
1104  *
1105  * If there is not enough space to fit the unvisible VRAM after the
1106  * aperture then we limit the VRAM size to the aperture.
1107  *
1108  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1109  * them to be in one from GPU point of view so that we can program GPU to
1110  * catch access outside them (weird GPU policy see ??).
1111  *
1112  * This function will never fails, worst case are limiting VRAM or GTT.
1113  *
1114  * Note: GTT start, end, size should be initialized before calling this
1115  * function on AGP platform.
1116  */
1117 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1118 {
1119         u64 size_bf, size_af;
1120
1121         if (mc->mc_vram_size > 0xE0000000) {
1122                 /* leave room for at least 512M GTT */
1123                 dev_warn(rdev->dev, "limiting VRAM\n");
1124                 mc->real_vram_size = 0xE0000000;
1125                 mc->mc_vram_size = 0xE0000000;
1126         }
1127         if (rdev->flags & RADEON_IS_AGP) {
1128                 size_bf = mc->gtt_start;
1129                 size_af = 0xFFFFFFFF - mc->gtt_end;
1130                 if (size_bf > size_af) {
1131                         if (mc->mc_vram_size > size_bf) {
1132                                 dev_warn(rdev->dev, "limiting VRAM\n");
1133                                 mc->real_vram_size = size_bf;
1134                                 mc->mc_vram_size = size_bf;
1135                         }
1136                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1137                 } else {
1138                         if (mc->mc_vram_size > size_af) {
1139                                 dev_warn(rdev->dev, "limiting VRAM\n");
1140                                 mc->real_vram_size = size_af;
1141                                 mc->mc_vram_size = size_af;
1142                         }
1143                         mc->vram_start = mc->gtt_end + 1;
1144                 }
1145                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1146                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1147                                 mc->mc_vram_size >> 20, mc->vram_start,
1148                                 mc->vram_end, mc->real_vram_size >> 20);
1149         } else {
1150                 u64 base = 0;
1151                 if (rdev->flags & RADEON_IS_IGP) {
1152                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1153                         base <<= 24;
1154                 }
1155                 radeon_vram_location(rdev, &rdev->mc, base);
1156                 rdev->mc.gtt_base_align = 0;
1157                 radeon_gtt_location(rdev, mc);
1158         }
1159 }
1160
1161 static int r600_mc_init(struct radeon_device *rdev)
1162 {
1163         u32 tmp;
1164         int chansize, numchan;
1165
1166         /* Get VRAM informations */
1167         rdev->mc.vram_is_ddr = true;
1168         tmp = RREG32(RAMCFG);
1169         if (tmp & CHANSIZE_OVERRIDE) {
1170                 chansize = 16;
1171         } else if (tmp & CHANSIZE_MASK) {
1172                 chansize = 64;
1173         } else {
1174                 chansize = 32;
1175         }
1176         tmp = RREG32(CHMAP);
1177         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1178         case 0:
1179         default:
1180                 numchan = 1;
1181                 break;
1182         case 1:
1183                 numchan = 2;
1184                 break;
1185         case 2:
1186                 numchan = 4;
1187                 break;
1188         case 3:
1189                 numchan = 8;
1190                 break;
1191         }
1192         rdev->mc.vram_width = numchan * chansize;
1193         /* Could aper size report 0 ? */
1194         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1195         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1196         /* Setup GPU memory space */
1197         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1198         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1199         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1200         r600_vram_gtt_location(rdev, &rdev->mc);
1201
1202         if (rdev->flags & RADEON_IS_IGP) {
1203                 rs690_pm_info(rdev);
1204                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1205         }
1206         radeon_update_bandwidth_info(rdev);
1207         return 0;
1208 }
1209
1210 int r600_vram_scratch_init(struct radeon_device *rdev)
1211 {
1212         int r;
1213
1214         if (rdev->vram_scratch.robj == NULL) {
1215                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1216                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1217                                      NULL, &rdev->vram_scratch.robj);
1218                 if (r) {
1219                         return r;
1220                 }
1221         }
1222
1223         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1224         if (unlikely(r != 0))
1225                 return r;
1226         r = radeon_bo_pin(rdev->vram_scratch.robj,
1227                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1228         if (r) {
1229                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1230                 return r;
1231         }
1232         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1233                                 (void **)&rdev->vram_scratch.ptr);
1234         if (r)
1235                 radeon_bo_unpin(rdev->vram_scratch.robj);
1236         radeon_bo_unreserve(rdev->vram_scratch.robj);
1237
1238         return r;
1239 }
1240
1241 void r600_vram_scratch_fini(struct radeon_device *rdev)
1242 {
1243         int r;
1244
1245         if (rdev->vram_scratch.robj == NULL) {
1246                 return;
1247         }
1248         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1249         if (likely(r == 0)) {
1250                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1251                 radeon_bo_unpin(rdev->vram_scratch.robj);
1252                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1253         }
1254         radeon_bo_unref(&rdev->vram_scratch.robj);
1255 }
1256
1257 /* We doesn't check that the GPU really needs a reset we simply do the
1258  * reset, it's up to the caller to determine if the GPU needs one. We
1259  * might add an helper function to check that.
1260  */
1261 static int r600_gpu_soft_reset(struct radeon_device *rdev)
1262 {
1263         struct rv515_mc_save save;
1264         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1265                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1266                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1267                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1268                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1269                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1270                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1271                                 S_008010_GUI_ACTIVE(1);
1272         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1273                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1274                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1275                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1276                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1277                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1278                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1279                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1280         u32 tmp;
1281
1282         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1283                 return 0;
1284
1285         dev_info(rdev->dev, "GPU softreset \n");
1286         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1287                 RREG32(R_008010_GRBM_STATUS));
1288         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1289                 RREG32(R_008014_GRBM_STATUS2));
1290         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1291                 RREG32(R_000E50_SRBM_STATUS));
1292         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1293                 RREG32(CP_STALLED_STAT1));
1294         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1295                 RREG32(CP_STALLED_STAT2));
1296         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1297                 RREG32(CP_BUSY_STAT));
1298         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1299                 RREG32(CP_STAT));
1300         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1301                 RREG32(DMA_STATUS_REG));
1302         rv515_mc_stop(rdev, &save);
1303         if (r600_mc_wait_for_idle(rdev)) {
1304                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1305         }
1306
1307         /* Disable CP parsing/prefetching */
1308         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1309
1310         /* Disable DMA */
1311         tmp = RREG32(DMA_RB_CNTL);
1312         tmp &= ~DMA_RB_ENABLE;
1313         WREG32(DMA_RB_CNTL, tmp);
1314
1315         /* Reset dma */
1316         if (rdev->family >= CHIP_RV770)
1317                 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
1318         else
1319                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
1320         RREG32(SRBM_SOFT_RESET);
1321         udelay(50);
1322         WREG32(SRBM_SOFT_RESET, 0);
1323
1324         /* Check if any of the rendering block is busy and reset it */
1325         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1326             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1327                 tmp = S_008020_SOFT_RESET_CR(1) |
1328                         S_008020_SOFT_RESET_DB(1) |
1329                         S_008020_SOFT_RESET_CB(1) |
1330                         S_008020_SOFT_RESET_PA(1) |
1331                         S_008020_SOFT_RESET_SC(1) |
1332                         S_008020_SOFT_RESET_SMX(1) |
1333                         S_008020_SOFT_RESET_SPI(1) |
1334                         S_008020_SOFT_RESET_SX(1) |
1335                         S_008020_SOFT_RESET_SH(1) |
1336                         S_008020_SOFT_RESET_TC(1) |
1337                         S_008020_SOFT_RESET_TA(1) |
1338                         S_008020_SOFT_RESET_VC(1) |
1339                         S_008020_SOFT_RESET_VGT(1);
1340                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1341                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1342                 RREG32(R_008020_GRBM_SOFT_RESET);
1343                 mdelay(15);
1344                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1345         }
1346         /* Reset CP (we always reset CP) */
1347         tmp = S_008020_SOFT_RESET_CP(1);
1348         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1349         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1350         RREG32(R_008020_GRBM_SOFT_RESET);
1351         mdelay(15);
1352         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1353         /* Wait a little for things to settle down */
1354         mdelay(1);
1355         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1356                 RREG32(R_008010_GRBM_STATUS));
1357         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1358                 RREG32(R_008014_GRBM_STATUS2));
1359         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1360                 RREG32(R_000E50_SRBM_STATUS));
1361         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1362                 RREG32(CP_STALLED_STAT1));
1363         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1364                 RREG32(CP_STALLED_STAT2));
1365         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1366                 RREG32(CP_BUSY_STAT));
1367         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1368                 RREG32(CP_STAT));
1369         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1370                 RREG32(DMA_STATUS_REG));
1371         rv515_mc_resume(rdev, &save);
1372         return 0;
1373 }
1374
1375 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1376 {
1377         u32 srbm_status;
1378         u32 grbm_status;
1379         u32 grbm_status2;
1380
1381         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1382         grbm_status = RREG32(R_008010_GRBM_STATUS);
1383         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1384         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1385                 radeon_ring_lockup_update(ring);
1386                 return false;
1387         }
1388         /* force CP activities */
1389         radeon_ring_force_activity(rdev, ring);
1390         return radeon_ring_test_lockup(rdev, ring);
1391 }
1392
1393 /**
1394  * r600_dma_is_lockup - Check if the DMA engine is locked up
1395  *
1396  * @rdev: radeon_device pointer
1397  * @ring: radeon_ring structure holding ring information
1398  *
1399  * Check if the async DMA engine is locked up (r6xx-evergreen).
1400  * Returns true if the engine appears to be locked up, false if not.
1401  */
1402 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1403 {
1404         u32 dma_status_reg;
1405
1406         dma_status_reg = RREG32(DMA_STATUS_REG);
1407         if (dma_status_reg & DMA_IDLE) {
1408                 radeon_ring_lockup_update(ring);
1409                 return false;
1410         }
1411         /* force ring activities */
1412         radeon_ring_force_activity(rdev, ring);
1413         return radeon_ring_test_lockup(rdev, ring);
1414 }
1415
1416 int r600_asic_reset(struct radeon_device *rdev)
1417 {
1418         return r600_gpu_soft_reset(rdev);
1419 }
1420
1421 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1422                               u32 tiling_pipe_num,
1423                               u32 max_rb_num,
1424                               u32 total_max_rb_num,
1425                               u32 disabled_rb_mask)
1426 {
1427         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1428         u32 pipe_rb_ratio, pipe_rb_remain;
1429         u32 data = 0, mask = 1 << (max_rb_num - 1);
1430         unsigned i, j;
1431
1432         /* mask out the RBs that don't exist on that asic */
1433         disabled_rb_mask |= (0xff << max_rb_num) & 0xff;
1434
1435         rendering_pipe_num = 1 << tiling_pipe_num;
1436         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1437         BUG_ON(rendering_pipe_num < req_rb_num);
1438
1439         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1440         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1441
1442         if (rdev->family <= CHIP_RV740) {
1443                 /* r6xx/r7xx */
1444                 rb_num_width = 2;
1445         } else {
1446                 /* eg+ */
1447                 rb_num_width = 4;
1448         }
1449
1450         for (i = 0; i < max_rb_num; i++) {
1451                 if (!(mask & disabled_rb_mask)) {
1452                         for (j = 0; j < pipe_rb_ratio; j++) {
1453                                 data <<= rb_num_width;
1454                                 data |= max_rb_num - i - 1;
1455                         }
1456                         if (pipe_rb_remain) {
1457                                 data <<= rb_num_width;
1458                                 data |= max_rb_num - i - 1;
1459                                 pipe_rb_remain--;
1460                         }
1461                 }
1462                 mask >>= 1;
1463         }
1464
1465         return data;
1466 }
1467
1468 int r600_count_pipe_bits(uint32_t val)
1469 {
1470         return hweight32(val);
1471 }
1472
1473 static void r600_gpu_init(struct radeon_device *rdev)
1474 {
1475         u32 tiling_config;
1476         u32 ramcfg;
1477         u32 cc_rb_backend_disable;
1478         u32 cc_gc_shader_pipe_config;
1479         u32 tmp;
1480         int i, j;
1481         u32 sq_config;
1482         u32 sq_gpr_resource_mgmt_1 = 0;
1483         u32 sq_gpr_resource_mgmt_2 = 0;
1484         u32 sq_thread_resource_mgmt = 0;
1485         u32 sq_stack_resource_mgmt_1 = 0;
1486         u32 sq_stack_resource_mgmt_2 = 0;
1487         u32 disabled_rb_mask;
1488
1489         rdev->config.r600.tiling_group_size = 256;
1490         switch (rdev->family) {
1491         case CHIP_R600:
1492                 rdev->config.r600.max_pipes = 4;
1493                 rdev->config.r600.max_tile_pipes = 8;
1494                 rdev->config.r600.max_simds = 4;
1495                 rdev->config.r600.max_backends = 4;
1496                 rdev->config.r600.max_gprs = 256;
1497                 rdev->config.r600.max_threads = 192;
1498                 rdev->config.r600.max_stack_entries = 256;
1499                 rdev->config.r600.max_hw_contexts = 8;
1500                 rdev->config.r600.max_gs_threads = 16;
1501                 rdev->config.r600.sx_max_export_size = 128;
1502                 rdev->config.r600.sx_max_export_pos_size = 16;
1503                 rdev->config.r600.sx_max_export_smx_size = 128;
1504                 rdev->config.r600.sq_num_cf_insts = 2;
1505                 break;
1506         case CHIP_RV630:
1507         case CHIP_RV635:
1508                 rdev->config.r600.max_pipes = 2;
1509                 rdev->config.r600.max_tile_pipes = 2;
1510                 rdev->config.r600.max_simds = 3;
1511                 rdev->config.r600.max_backends = 1;
1512                 rdev->config.r600.max_gprs = 128;
1513                 rdev->config.r600.max_threads = 192;
1514                 rdev->config.r600.max_stack_entries = 128;
1515                 rdev->config.r600.max_hw_contexts = 8;
1516                 rdev->config.r600.max_gs_threads = 4;
1517                 rdev->config.r600.sx_max_export_size = 128;
1518                 rdev->config.r600.sx_max_export_pos_size = 16;
1519                 rdev->config.r600.sx_max_export_smx_size = 128;
1520                 rdev->config.r600.sq_num_cf_insts = 2;
1521                 break;
1522         case CHIP_RV610:
1523         case CHIP_RV620:
1524         case CHIP_RS780:
1525         case CHIP_RS880:
1526                 rdev->config.r600.max_pipes = 1;
1527                 rdev->config.r600.max_tile_pipes = 1;
1528                 rdev->config.r600.max_simds = 2;
1529                 rdev->config.r600.max_backends = 1;
1530                 rdev->config.r600.max_gprs = 128;
1531                 rdev->config.r600.max_threads = 192;
1532                 rdev->config.r600.max_stack_entries = 128;
1533                 rdev->config.r600.max_hw_contexts = 4;
1534                 rdev->config.r600.max_gs_threads = 4;
1535                 rdev->config.r600.sx_max_export_size = 128;
1536                 rdev->config.r600.sx_max_export_pos_size = 16;
1537                 rdev->config.r600.sx_max_export_smx_size = 128;
1538                 rdev->config.r600.sq_num_cf_insts = 1;
1539                 break;
1540         case CHIP_RV670:
1541                 rdev->config.r600.max_pipes = 4;
1542                 rdev->config.r600.max_tile_pipes = 4;
1543                 rdev->config.r600.max_simds = 4;
1544                 rdev->config.r600.max_backends = 4;
1545                 rdev->config.r600.max_gprs = 192;
1546                 rdev->config.r600.max_threads = 192;
1547                 rdev->config.r600.max_stack_entries = 256;
1548                 rdev->config.r600.max_hw_contexts = 8;
1549                 rdev->config.r600.max_gs_threads = 16;
1550                 rdev->config.r600.sx_max_export_size = 128;
1551                 rdev->config.r600.sx_max_export_pos_size = 16;
1552                 rdev->config.r600.sx_max_export_smx_size = 128;
1553                 rdev->config.r600.sq_num_cf_insts = 2;
1554                 break;
1555         default:
1556                 break;
1557         }
1558
1559         /* Initialize HDP */
1560         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1561                 WREG32((0x2c14 + j), 0x00000000);
1562                 WREG32((0x2c18 + j), 0x00000000);
1563                 WREG32((0x2c1c + j), 0x00000000);
1564                 WREG32((0x2c20 + j), 0x00000000);
1565                 WREG32((0x2c24 + j), 0x00000000);
1566         }
1567
1568         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1569
1570         /* Setup tiling */
1571         tiling_config = 0;
1572         ramcfg = RREG32(RAMCFG);
1573         switch (rdev->config.r600.max_tile_pipes) {
1574         case 1:
1575                 tiling_config |= PIPE_TILING(0);
1576                 break;
1577         case 2:
1578                 tiling_config |= PIPE_TILING(1);
1579                 break;
1580         case 4:
1581                 tiling_config |= PIPE_TILING(2);
1582                 break;
1583         case 8:
1584                 tiling_config |= PIPE_TILING(3);
1585                 break;
1586         default:
1587                 break;
1588         }
1589         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1590         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1591         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1592         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1593
1594         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1595         if (tmp > 3) {
1596                 tiling_config |= ROW_TILING(3);
1597                 tiling_config |= SAMPLE_SPLIT(3);
1598         } else {
1599                 tiling_config |= ROW_TILING(tmp);
1600                 tiling_config |= SAMPLE_SPLIT(tmp);
1601         }
1602         tiling_config |= BANK_SWAPS(1);
1603
1604         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1605         tmp = R6XX_MAX_BACKENDS -
1606                 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1607         if (tmp < rdev->config.r600.max_backends) {
1608                 rdev->config.r600.max_backends = tmp;
1609         }
1610
1611         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1612         tmp = R6XX_MAX_PIPES -
1613                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1614         if (tmp < rdev->config.r600.max_pipes) {
1615                 rdev->config.r600.max_pipes = tmp;
1616         }
1617         tmp = R6XX_MAX_SIMDS -
1618                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1619         if (tmp < rdev->config.r600.max_simds) {
1620                 rdev->config.r600.max_simds = tmp;
1621         }
1622
1623         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1624         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1625         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1626                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
1627         tiling_config |= tmp << 16;
1628         rdev->config.r600.backend_map = tmp;
1629
1630         rdev->config.r600.tile_config = tiling_config;
1631         WREG32(GB_TILING_CONFIG, tiling_config);
1632         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1633         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1634         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1635
1636         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1637         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1638         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1639
1640         /* Setup some CP states */
1641         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1642         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1643
1644         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1645                              SYNC_WALKER | SYNC_ALIGNER));
1646         /* Setup various GPU states */
1647         if (rdev->family == CHIP_RV670)
1648                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1649
1650         tmp = RREG32(SX_DEBUG_1);
1651         tmp |= SMX_EVENT_RELEASE;
1652         if ((rdev->family > CHIP_R600))
1653                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1654         WREG32(SX_DEBUG_1, tmp);
1655
1656         if (((rdev->family) == CHIP_R600) ||
1657             ((rdev->family) == CHIP_RV630) ||
1658             ((rdev->family) == CHIP_RV610) ||
1659             ((rdev->family) == CHIP_RV620) ||
1660             ((rdev->family) == CHIP_RS780) ||
1661             ((rdev->family) == CHIP_RS880)) {
1662                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1663         } else {
1664                 WREG32(DB_DEBUG, 0);
1665         }
1666         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1667                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1668
1669         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1670         WREG32(VGT_NUM_INSTANCES, 0);
1671
1672         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1673         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1674
1675         tmp = RREG32(SQ_MS_FIFO_SIZES);
1676         if (((rdev->family) == CHIP_RV610) ||
1677             ((rdev->family) == CHIP_RV620) ||
1678             ((rdev->family) == CHIP_RS780) ||
1679             ((rdev->family) == CHIP_RS880)) {
1680                 tmp = (CACHE_FIFO_SIZE(0xa) |
1681                        FETCH_FIFO_HIWATER(0xa) |
1682                        DONE_FIFO_HIWATER(0xe0) |
1683                        ALU_UPDATE_FIFO_HIWATER(0x8));
1684         } else if (((rdev->family) == CHIP_R600) ||
1685                    ((rdev->family) == CHIP_RV630)) {
1686                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1687                 tmp |= DONE_FIFO_HIWATER(0x4);
1688         }
1689         WREG32(SQ_MS_FIFO_SIZES, tmp);
1690
1691         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1692          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1693          */
1694         sq_config = RREG32(SQ_CONFIG);
1695         sq_config &= ~(PS_PRIO(3) |
1696                        VS_PRIO(3) |
1697                        GS_PRIO(3) |
1698                        ES_PRIO(3));
1699         sq_config |= (DX9_CONSTS |
1700                       VC_ENABLE |
1701                       PS_PRIO(0) |
1702                       VS_PRIO(1) |
1703                       GS_PRIO(2) |
1704                       ES_PRIO(3));
1705
1706         if ((rdev->family) == CHIP_R600) {
1707                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1708                                           NUM_VS_GPRS(124) |
1709                                           NUM_CLAUSE_TEMP_GPRS(4));
1710                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1711                                           NUM_ES_GPRS(0));
1712                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1713                                            NUM_VS_THREADS(48) |
1714                                            NUM_GS_THREADS(4) |
1715                                            NUM_ES_THREADS(4));
1716                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1717                                             NUM_VS_STACK_ENTRIES(128));
1718                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1719                                             NUM_ES_STACK_ENTRIES(0));
1720         } else if (((rdev->family) == CHIP_RV610) ||
1721                    ((rdev->family) == CHIP_RV620) ||
1722                    ((rdev->family) == CHIP_RS780) ||
1723                    ((rdev->family) == CHIP_RS880)) {
1724                 /* no vertex cache */
1725                 sq_config &= ~VC_ENABLE;
1726
1727                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1728                                           NUM_VS_GPRS(44) |
1729                                           NUM_CLAUSE_TEMP_GPRS(2));
1730                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1731                                           NUM_ES_GPRS(17));
1732                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1733                                            NUM_VS_THREADS(78) |
1734                                            NUM_GS_THREADS(4) |
1735                                            NUM_ES_THREADS(31));
1736                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1737                                             NUM_VS_STACK_ENTRIES(40));
1738                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1739                                             NUM_ES_STACK_ENTRIES(16));
1740         } else if (((rdev->family) == CHIP_RV630) ||
1741                    ((rdev->family) == CHIP_RV635)) {
1742                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1743                                           NUM_VS_GPRS(44) |
1744                                           NUM_CLAUSE_TEMP_GPRS(2));
1745                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1746                                           NUM_ES_GPRS(18));
1747                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1748                                            NUM_VS_THREADS(78) |
1749                                            NUM_GS_THREADS(4) |
1750                                            NUM_ES_THREADS(31));
1751                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1752                                             NUM_VS_STACK_ENTRIES(40));
1753                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1754                                             NUM_ES_STACK_ENTRIES(16));
1755         } else if ((rdev->family) == CHIP_RV670) {
1756                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1757                                           NUM_VS_GPRS(44) |
1758                                           NUM_CLAUSE_TEMP_GPRS(2));
1759                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1760                                           NUM_ES_GPRS(17));
1761                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1762                                            NUM_VS_THREADS(78) |
1763                                            NUM_GS_THREADS(4) |
1764                                            NUM_ES_THREADS(31));
1765                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1766                                             NUM_VS_STACK_ENTRIES(64));
1767                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1768                                             NUM_ES_STACK_ENTRIES(64));
1769         }
1770
1771         WREG32(SQ_CONFIG, sq_config);
1772         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1773         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1774         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1775         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1776         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1777
1778         if (((rdev->family) == CHIP_RV610) ||
1779             ((rdev->family) == CHIP_RV620) ||
1780             ((rdev->family) == CHIP_RS780) ||
1781             ((rdev->family) == CHIP_RS880)) {
1782                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1783         } else {
1784                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1785         }
1786
1787         /* More default values. 2D/3D driver should adjust as needed */
1788         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1789                                          S1_X(0x4) | S1_Y(0xc)));
1790         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1791                                          S1_X(0x2) | S1_Y(0x2) |
1792                                          S2_X(0xa) | S2_Y(0x6) |
1793                                          S3_X(0x6) | S3_Y(0xa)));
1794         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1795                                              S1_X(0x4) | S1_Y(0xc) |
1796                                              S2_X(0x1) | S2_Y(0x6) |
1797                                              S3_X(0xa) | S3_Y(0xe)));
1798         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1799                                              S5_X(0x0) | S5_Y(0x0) |
1800                                              S6_X(0xb) | S6_Y(0x4) |
1801                                              S7_X(0x7) | S7_Y(0x8)));
1802
1803         WREG32(VGT_STRMOUT_EN, 0);
1804         tmp = rdev->config.r600.max_pipes * 16;
1805         switch (rdev->family) {
1806         case CHIP_RV610:
1807         case CHIP_RV620:
1808         case CHIP_RS780:
1809         case CHIP_RS880:
1810                 tmp += 32;
1811                 break;
1812         case CHIP_RV670:
1813                 tmp += 128;
1814                 break;
1815         default:
1816                 break;
1817         }
1818         if (tmp > 256) {
1819                 tmp = 256;
1820         }
1821         WREG32(VGT_ES_PER_GS, 128);
1822         WREG32(VGT_GS_PER_ES, tmp);
1823         WREG32(VGT_GS_PER_VS, 2);
1824         WREG32(VGT_GS_VERTEX_REUSE, 16);
1825
1826         /* more default values. 2D/3D driver should adjust as needed */
1827         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1828         WREG32(VGT_STRMOUT_EN, 0);
1829         WREG32(SX_MISC, 0);
1830         WREG32(PA_SC_MODE_CNTL, 0);
1831         WREG32(PA_SC_AA_CONFIG, 0);
1832         WREG32(PA_SC_LINE_STIPPLE, 0);
1833         WREG32(SPI_INPUT_Z, 0);
1834         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1835         WREG32(CB_COLOR7_FRAG, 0);
1836
1837         /* Clear render buffer base addresses */
1838         WREG32(CB_COLOR0_BASE, 0);
1839         WREG32(CB_COLOR1_BASE, 0);
1840         WREG32(CB_COLOR2_BASE, 0);
1841         WREG32(CB_COLOR3_BASE, 0);
1842         WREG32(CB_COLOR4_BASE, 0);
1843         WREG32(CB_COLOR5_BASE, 0);
1844         WREG32(CB_COLOR6_BASE, 0);
1845         WREG32(CB_COLOR7_BASE, 0);
1846         WREG32(CB_COLOR7_FRAG, 0);
1847
1848         switch (rdev->family) {
1849         case CHIP_RV610:
1850         case CHIP_RV620:
1851         case CHIP_RS780:
1852         case CHIP_RS880:
1853                 tmp = TC_L2_SIZE(8);
1854                 break;
1855         case CHIP_RV630:
1856         case CHIP_RV635:
1857                 tmp = TC_L2_SIZE(4);
1858                 break;
1859         case CHIP_R600:
1860                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1861                 break;
1862         default:
1863                 tmp = TC_L2_SIZE(0);
1864                 break;
1865         }
1866         WREG32(TC_CNTL, tmp);
1867
1868         tmp = RREG32(HDP_HOST_PATH_CNTL);
1869         WREG32(HDP_HOST_PATH_CNTL, tmp);
1870
1871         tmp = RREG32(ARB_POP);
1872         tmp |= ENABLE_TC128;
1873         WREG32(ARB_POP, tmp);
1874
1875         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1876         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1877                                NUM_CLIP_SEQ(3)));
1878         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1879         WREG32(VC_ENHANCE, 0);
1880 }
1881
1882
1883 /*
1884  * Indirect registers accessor
1885  */
1886 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1887 {
1888         u32 r;
1889
1890         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1891         (void)RREG32(PCIE_PORT_INDEX);
1892         r = RREG32(PCIE_PORT_DATA);
1893         return r;
1894 }
1895
1896 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1897 {
1898         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1899         (void)RREG32(PCIE_PORT_INDEX);
1900         WREG32(PCIE_PORT_DATA, (v));
1901         (void)RREG32(PCIE_PORT_DATA);
1902 }
1903
1904 /*
1905  * CP & Ring
1906  */
1907 void r600_cp_stop(struct radeon_device *rdev)
1908 {
1909         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1910         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1911         WREG32(SCRATCH_UMSK, 0);
1912         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1913 }
1914
1915 int r600_init_microcode(struct radeon_device *rdev)
1916 {
1917         struct platform_device *pdev;
1918         const char *chip_name;
1919         const char *rlc_chip_name;
1920         size_t pfp_req_size, me_req_size, rlc_req_size;
1921         char fw_name[30];
1922         int err;
1923
1924         DRM_DEBUG("\n");
1925
1926         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1927         err = IS_ERR(pdev);
1928         if (err) {
1929                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1930                 return -EINVAL;
1931         }
1932
1933         switch (rdev->family) {
1934         case CHIP_R600:
1935                 chip_name = "R600";
1936                 rlc_chip_name = "R600";
1937                 break;
1938         case CHIP_RV610:
1939                 chip_name = "RV610";
1940                 rlc_chip_name = "R600";
1941                 break;
1942         case CHIP_RV630:
1943                 chip_name = "RV630";
1944                 rlc_chip_name = "R600";
1945                 break;
1946         case CHIP_RV620:
1947                 chip_name = "RV620";
1948                 rlc_chip_name = "R600";
1949                 break;
1950         case CHIP_RV635:
1951                 chip_name = "RV635";
1952                 rlc_chip_name = "R600";
1953                 break;
1954         case CHIP_RV670:
1955                 chip_name = "RV670";
1956                 rlc_chip_name = "R600";
1957                 break;
1958         case CHIP_RS780:
1959         case CHIP_RS880:
1960                 chip_name = "RS780";
1961                 rlc_chip_name = "R600";
1962                 break;
1963         case CHIP_RV770:
1964                 chip_name = "RV770";
1965                 rlc_chip_name = "R700";
1966                 break;
1967         case CHIP_RV730:
1968         case CHIP_RV740:
1969                 chip_name = "RV730";
1970                 rlc_chip_name = "R700";
1971                 break;
1972         case CHIP_RV710:
1973                 chip_name = "RV710";
1974                 rlc_chip_name = "R700";
1975                 break;
1976         case CHIP_CEDAR:
1977                 chip_name = "CEDAR";
1978                 rlc_chip_name = "CEDAR";
1979                 break;
1980         case CHIP_REDWOOD:
1981                 chip_name = "REDWOOD";
1982                 rlc_chip_name = "REDWOOD";
1983                 break;
1984         case CHIP_JUNIPER:
1985                 chip_name = "JUNIPER";
1986                 rlc_chip_name = "JUNIPER";
1987                 break;
1988         case CHIP_CYPRESS:
1989         case CHIP_HEMLOCK:
1990                 chip_name = "CYPRESS";
1991                 rlc_chip_name = "CYPRESS";
1992                 break;
1993         case CHIP_PALM:
1994                 chip_name = "PALM";
1995                 rlc_chip_name = "SUMO";
1996                 break;
1997         case CHIP_SUMO:
1998                 chip_name = "SUMO";
1999                 rlc_chip_name = "SUMO";
2000                 break;
2001         case CHIP_SUMO2:
2002                 chip_name = "SUMO2";
2003                 rlc_chip_name = "SUMO";
2004                 break;
2005         default: BUG();
2006         }
2007
2008         if (rdev->family >= CHIP_CEDAR) {
2009                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2010                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2011                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2012         } else if (rdev->family >= CHIP_RV770) {
2013                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2014                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2015                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2016         } else {
2017                 pfp_req_size = PFP_UCODE_SIZE * 4;
2018                 me_req_size = PM4_UCODE_SIZE * 12;
2019                 rlc_req_size = RLC_UCODE_SIZE * 4;
2020         }
2021
2022         DRM_INFO("Loading %s Microcode\n", chip_name);
2023
2024         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2025         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2026         if (err)
2027                 goto out;
2028         if (rdev->pfp_fw->size != pfp_req_size) {
2029                 printk(KERN_ERR
2030                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2031                        rdev->pfp_fw->size, fw_name);
2032                 err = -EINVAL;
2033                 goto out;
2034         }
2035
2036         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2037         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2038         if (err)
2039                 goto out;
2040         if (rdev->me_fw->size != me_req_size) {
2041                 printk(KERN_ERR
2042                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2043                        rdev->me_fw->size, fw_name);
2044                 err = -EINVAL;
2045         }
2046
2047         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2048         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2049         if (err)
2050                 goto out;
2051         if (rdev->rlc_fw->size != rlc_req_size) {
2052                 printk(KERN_ERR
2053                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2054                        rdev->rlc_fw->size, fw_name);
2055                 err = -EINVAL;
2056         }
2057
2058 out:
2059         platform_device_unregister(pdev);
2060
2061         if (err) {
2062                 if (err != -EINVAL)
2063                         printk(KERN_ERR
2064                                "r600_cp: Failed to load firmware \"%s\"\n",
2065                                fw_name);
2066                 release_firmware(rdev->pfp_fw);
2067                 rdev->pfp_fw = NULL;
2068                 release_firmware(rdev->me_fw);
2069                 rdev->me_fw = NULL;
2070                 release_firmware(rdev->rlc_fw);
2071                 rdev->rlc_fw = NULL;
2072         }
2073         return err;
2074 }
2075
2076 static int r600_cp_load_microcode(struct radeon_device *rdev)
2077 {
2078         const __be32 *fw_data;
2079         int i;
2080
2081         if (!rdev->me_fw || !rdev->pfp_fw)
2082                 return -EINVAL;
2083
2084         r600_cp_stop(rdev);
2085
2086         WREG32(CP_RB_CNTL,
2087 #ifdef __BIG_ENDIAN
2088                BUF_SWAP_32BIT |
2089 #endif
2090                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2091
2092         /* Reset cp */
2093         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2094         RREG32(GRBM_SOFT_RESET);
2095         mdelay(15);
2096         WREG32(GRBM_SOFT_RESET, 0);
2097
2098         WREG32(CP_ME_RAM_WADDR, 0);
2099
2100         fw_data = (const __be32 *)rdev->me_fw->data;
2101         WREG32(CP_ME_RAM_WADDR, 0);
2102         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2103                 WREG32(CP_ME_RAM_DATA,
2104                        be32_to_cpup(fw_data++));
2105
2106         fw_data = (const __be32 *)rdev->pfp_fw->data;
2107         WREG32(CP_PFP_UCODE_ADDR, 0);
2108         for (i = 0; i < PFP_UCODE_SIZE; i++)
2109                 WREG32(CP_PFP_UCODE_DATA,
2110                        be32_to_cpup(fw_data++));
2111
2112         WREG32(CP_PFP_UCODE_ADDR, 0);
2113         WREG32(CP_ME_RAM_WADDR, 0);
2114         WREG32(CP_ME_RAM_RADDR, 0);
2115         return 0;
2116 }
2117
2118 int r600_cp_start(struct radeon_device *rdev)
2119 {
2120         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2121         int r;
2122         uint32_t cp_me;
2123
2124         r = radeon_ring_lock(rdev, ring, 7);
2125         if (r) {
2126                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2127                 return r;
2128         }
2129         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2130         radeon_ring_write(ring, 0x1);
2131         if (rdev->family >= CHIP_RV770) {
2132                 radeon_ring_write(ring, 0x0);
2133                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2134         } else {
2135                 radeon_ring_write(ring, 0x3);
2136                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2137         }
2138         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2139         radeon_ring_write(ring, 0);
2140         radeon_ring_write(ring, 0);
2141         radeon_ring_unlock_commit(rdev, ring);
2142
2143         cp_me = 0xff;
2144         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2145         return 0;
2146 }
2147
2148 int r600_cp_resume(struct radeon_device *rdev)
2149 {
2150         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2151         u32 tmp;
2152         u32 rb_bufsz;
2153         int r;
2154
2155         /* Reset cp */
2156         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2157         RREG32(GRBM_SOFT_RESET);
2158         mdelay(15);
2159         WREG32(GRBM_SOFT_RESET, 0);
2160
2161         /* Set ring buffer size */
2162         rb_bufsz = drm_order(ring->ring_size / 8);
2163         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2164 #ifdef __BIG_ENDIAN
2165         tmp |= BUF_SWAP_32BIT;
2166 #endif
2167         WREG32(CP_RB_CNTL, tmp);
2168         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2169
2170         /* Set the write pointer delay */
2171         WREG32(CP_RB_WPTR_DELAY, 0);
2172
2173         /* Initialize the ring buffer's read and write pointers */
2174         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2175         WREG32(CP_RB_RPTR_WR, 0);
2176         ring->wptr = 0;
2177         WREG32(CP_RB_WPTR, ring->wptr);
2178
2179         /* set the wb address whether it's enabled or not */
2180         WREG32(CP_RB_RPTR_ADDR,
2181                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2182         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2183         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2184
2185         if (rdev->wb.enabled)
2186                 WREG32(SCRATCH_UMSK, 0xff);
2187         else {
2188                 tmp |= RB_NO_UPDATE;
2189                 WREG32(SCRATCH_UMSK, 0);
2190         }
2191
2192         mdelay(1);
2193         WREG32(CP_RB_CNTL, tmp);
2194
2195         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2196         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2197
2198         ring->rptr = RREG32(CP_RB_RPTR);
2199
2200         r600_cp_start(rdev);
2201         ring->ready = true;
2202         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2203         if (r) {
2204                 ring->ready = false;
2205                 return r;
2206         }
2207         return 0;
2208 }
2209
2210 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2211 {
2212         u32 rb_bufsz;
2213         int r;
2214
2215         /* Align ring size */
2216         rb_bufsz = drm_order(ring_size / 8);
2217         ring_size = (1 << (rb_bufsz + 1)) * 4;
2218         ring->ring_size = ring_size;
2219         ring->align_mask = 16 - 1;
2220
2221         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2222                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2223                 if (r) {
2224                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2225                         ring->rptr_save_reg = 0;
2226                 }
2227         }
2228 }
2229
2230 void r600_cp_fini(struct radeon_device *rdev)
2231 {
2232         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2233         r600_cp_stop(rdev);
2234         radeon_ring_fini(rdev, ring);
2235         radeon_scratch_free(rdev, ring->rptr_save_reg);
2236 }
2237
2238 /*
2239  * DMA
2240  * Starting with R600, the GPU has an asynchronous
2241  * DMA engine.  The programming model is very similar
2242  * to the 3D engine (ring buffer, IBs, etc.), but the
2243  * DMA controller has it's own packet format that is
2244  * different form the PM4 format used by the 3D engine.
2245  * It supports copying data, writing embedded data,
2246  * solid fills, and a number of other things.  It also
2247  * has support for tiling/detiling of buffers.
2248  */
2249 /**
2250  * r600_dma_stop - stop the async dma engine
2251  *
2252  * @rdev: radeon_device pointer
2253  *
2254  * Stop the async dma engine (r6xx-evergreen).
2255  */
2256 void r600_dma_stop(struct radeon_device *rdev)
2257 {
2258         u32 rb_cntl = RREG32(DMA_RB_CNTL);
2259
2260         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2261
2262         rb_cntl &= ~DMA_RB_ENABLE;
2263         WREG32(DMA_RB_CNTL, rb_cntl);
2264
2265         rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2266 }
2267
2268 /**
2269  * r600_dma_resume - setup and start the async dma engine
2270  *
2271  * @rdev: radeon_device pointer
2272  *
2273  * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2274  * Returns 0 for success, error for failure.
2275  */
2276 int r600_dma_resume(struct radeon_device *rdev)
2277 {
2278         struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2279         u32 rb_cntl, dma_cntl;
2280         u32 rb_bufsz;
2281         int r;
2282
2283         /* Reset dma */
2284         if (rdev->family >= CHIP_RV770)
2285                 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2286         else
2287                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2288         RREG32(SRBM_SOFT_RESET);
2289         udelay(50);
2290         WREG32(SRBM_SOFT_RESET, 0);
2291
2292         WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2293         WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2294
2295         /* Set ring buffer size in dwords */
2296         rb_bufsz = drm_order(ring->ring_size / 4);
2297         rb_cntl = rb_bufsz << 1;
2298 #ifdef __BIG_ENDIAN
2299         rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2300 #endif
2301         WREG32(DMA_RB_CNTL, rb_cntl);
2302
2303         /* Initialize the ring buffer's read and write pointers */
2304         WREG32(DMA_RB_RPTR, 0);
2305         WREG32(DMA_RB_WPTR, 0);
2306
2307         /* set the wb address whether it's enabled or not */
2308         WREG32(DMA_RB_RPTR_ADDR_HI,
2309                upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2310         WREG32(DMA_RB_RPTR_ADDR_LO,
2311                ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2312
2313         if (rdev->wb.enabled)
2314                 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2315
2316         WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2317
2318         /* enable DMA IBs */
2319         WREG32(DMA_IB_CNTL, DMA_IB_ENABLE);
2320
2321         dma_cntl = RREG32(DMA_CNTL);
2322         dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2323         WREG32(DMA_CNTL, dma_cntl);
2324
2325         if (rdev->family >= CHIP_RV770)
2326                 WREG32(DMA_MODE, 1);
2327
2328         ring->wptr = 0;
2329         WREG32(DMA_RB_WPTR, ring->wptr << 2);
2330
2331         ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2332
2333         WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2334
2335         ring->ready = true;
2336
2337         r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2338         if (r) {
2339                 ring->ready = false;
2340                 return r;
2341         }
2342
2343         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2344
2345         return 0;
2346 }
2347
2348 /**
2349  * r600_dma_fini - tear down the async dma engine
2350  *
2351  * @rdev: radeon_device pointer
2352  *
2353  * Stop the async dma engine and free the ring (r6xx-evergreen).
2354  */
2355 void r600_dma_fini(struct radeon_device *rdev)
2356 {
2357         r600_dma_stop(rdev);
2358         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2359 }
2360
2361 /*
2362  * GPU scratch registers helpers function.
2363  */
2364 void r600_scratch_init(struct radeon_device *rdev)
2365 {
2366         int i;
2367
2368         rdev->scratch.num_reg = 7;
2369         rdev->scratch.reg_base = SCRATCH_REG0;
2370         for (i = 0; i < rdev->scratch.num_reg; i++) {
2371                 rdev->scratch.free[i] = true;
2372                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2373         }
2374 }
2375
2376 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2377 {
2378         uint32_t scratch;
2379         uint32_t tmp = 0;
2380         unsigned i;
2381         int r;
2382
2383         r = radeon_scratch_get(rdev, &scratch);
2384         if (r) {
2385                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2386                 return r;
2387         }
2388         WREG32(scratch, 0xCAFEDEAD);
2389         r = radeon_ring_lock(rdev, ring, 3);
2390         if (r) {
2391                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2392                 radeon_scratch_free(rdev, scratch);
2393                 return r;
2394         }
2395         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2396         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2397         radeon_ring_write(ring, 0xDEADBEEF);
2398         radeon_ring_unlock_commit(rdev, ring);
2399         for (i = 0; i < rdev->usec_timeout; i++) {
2400                 tmp = RREG32(scratch);
2401                 if (tmp == 0xDEADBEEF)
2402                         break;
2403                 DRM_UDELAY(1);
2404         }
2405         if (i < rdev->usec_timeout) {
2406                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2407         } else {
2408                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2409                           ring->idx, scratch, tmp);
2410                 r = -EINVAL;
2411         }
2412         radeon_scratch_free(rdev, scratch);
2413         return r;
2414 }
2415
2416 /**
2417  * r600_dma_ring_test - simple async dma engine test
2418  *
2419  * @rdev: radeon_device pointer
2420  * @ring: radeon_ring structure holding ring information
2421  *
2422  * Test the DMA engine by writing using it to write an
2423  * value to memory. (r6xx-SI).
2424  * Returns 0 for success, error for failure.
2425  */
2426 int r600_dma_ring_test(struct radeon_device *rdev,
2427                        struct radeon_ring *ring)
2428 {
2429         unsigned i;
2430         int r;
2431         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2432         u32 tmp;
2433
2434         if (!ptr) {
2435                 DRM_ERROR("invalid vram scratch pointer\n");
2436                 return -EINVAL;
2437         }
2438
2439         tmp = 0xCAFEDEAD;
2440         writel(tmp, ptr);
2441
2442         r = radeon_ring_lock(rdev, ring, 4);
2443         if (r) {
2444                 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2445                 return r;
2446         }
2447         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2448         radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2449         radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2450         radeon_ring_write(ring, 0xDEADBEEF);
2451         radeon_ring_unlock_commit(rdev, ring);
2452
2453         for (i = 0; i < rdev->usec_timeout; i++) {
2454                 tmp = readl(ptr);
2455                 if (tmp == 0xDEADBEEF)
2456                         break;
2457                 DRM_UDELAY(1);
2458         }
2459
2460         if (i < rdev->usec_timeout) {
2461                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2462         } else {
2463                 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2464                           ring->idx, tmp);
2465                 r = -EINVAL;
2466         }
2467         return r;
2468 }
2469
2470 /*
2471  * CP fences/semaphores
2472  */
2473
2474 void r600_fence_ring_emit(struct radeon_device *rdev,
2475                           struct radeon_fence *fence)
2476 {
2477         struct radeon_ring *ring = &rdev->ring[fence->ring];
2478
2479         if (rdev->wb.use_event) {
2480                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2481                 /* flush read cache over gart */
2482                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2483                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2484                                         PACKET3_VC_ACTION_ENA |
2485                                         PACKET3_SH_ACTION_ENA);
2486                 radeon_ring_write(ring, 0xFFFFFFFF);
2487                 radeon_ring_write(ring, 0);
2488                 radeon_ring_write(ring, 10); /* poll interval */
2489                 /* EVENT_WRITE_EOP - flush caches, send int */
2490                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2491                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2492                 radeon_ring_write(ring, addr & 0xffffffff);
2493                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2494                 radeon_ring_write(ring, fence->seq);
2495                 radeon_ring_write(ring, 0);
2496         } else {
2497                 /* flush read cache over gart */
2498                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2499                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2500                                         PACKET3_VC_ACTION_ENA |
2501                                         PACKET3_SH_ACTION_ENA);
2502                 radeon_ring_write(ring, 0xFFFFFFFF);
2503                 radeon_ring_write(ring, 0);
2504                 radeon_ring_write(ring, 10); /* poll interval */
2505                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2506                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2507                 /* wait for 3D idle clean */
2508                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2509                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2510                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2511                 /* Emit fence sequence & fire IRQ */
2512                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2513                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2514                 radeon_ring_write(ring, fence->seq);
2515                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2516                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2517                 radeon_ring_write(ring, RB_INT_STAT);
2518         }
2519 }
2520
2521 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2522                               struct radeon_ring *ring,
2523                               struct radeon_semaphore *semaphore,
2524                               bool emit_wait)
2525 {
2526         uint64_t addr = semaphore->gpu_addr;
2527         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2528
2529         if (rdev->family < CHIP_CAYMAN)
2530                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2531
2532         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2533         radeon_ring_write(ring, addr & 0xffffffff);
2534         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2535 }
2536
2537 /*
2538  * DMA fences/semaphores
2539  */
2540
2541 /**
2542  * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2543  *
2544  * @rdev: radeon_device pointer
2545  * @fence: radeon fence object
2546  *
2547  * Add a DMA fence packet to the ring to write
2548  * the fence seq number and DMA trap packet to generate
2549  * an interrupt if needed (r6xx-r7xx).
2550  */
2551 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
2552                               struct radeon_fence *fence)
2553 {
2554         struct radeon_ring *ring = &rdev->ring[fence->ring];
2555         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2556
2557         /* write the fence */
2558         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
2559         radeon_ring_write(ring, addr & 0xfffffffc);
2560         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
2561         radeon_ring_write(ring, lower_32_bits(fence->seq));
2562         /* generate an interrupt */
2563         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
2564 }
2565
2566 /**
2567  * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
2568  *
2569  * @rdev: radeon_device pointer
2570  * @ring: radeon_ring structure holding ring information
2571  * @semaphore: radeon semaphore object
2572  * @emit_wait: wait or signal semaphore
2573  *
2574  * Add a DMA semaphore packet to the ring wait on or signal
2575  * other rings (r6xx-SI).
2576  */
2577 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2578                                   struct radeon_ring *ring,
2579                                   struct radeon_semaphore *semaphore,
2580                                   bool emit_wait)
2581 {
2582         u64 addr = semaphore->gpu_addr;
2583         u32 s = emit_wait ? 0 : 1;
2584
2585         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
2586         radeon_ring_write(ring, addr & 0xfffffffc);
2587         radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2588 }
2589
2590 int r600_copy_blit(struct radeon_device *rdev,
2591                    uint64_t src_offset,
2592                    uint64_t dst_offset,
2593                    unsigned num_gpu_pages,
2594                    struct radeon_fence **fence)
2595 {
2596         struct radeon_semaphore *sem = NULL;
2597         struct radeon_sa_bo *vb = NULL;
2598         int r;
2599
2600         r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
2601         if (r) {
2602                 return r;
2603         }
2604         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
2605         r600_blit_done_copy(rdev, fence, vb, sem);
2606         return 0;
2607 }
2608
2609 /**
2610  * r600_copy_dma - copy pages using the DMA engine
2611  *
2612  * @rdev: radeon_device pointer
2613  * @src_offset: src GPU address
2614  * @dst_offset: dst GPU address
2615  * @num_gpu_pages: number of GPU pages to xfer
2616  * @fence: radeon fence object
2617  *
2618  * Copy GPU paging using the DMA engine (r6xx-r7xx).
2619  * Used by the radeon ttm implementation to move pages if
2620  * registered as the asic copy callback.
2621  */
2622 int r600_copy_dma(struct radeon_device *rdev,
2623                   uint64_t src_offset, uint64_t dst_offset,
2624                   unsigned num_gpu_pages,
2625                   struct radeon_fence **fence)
2626 {
2627         struct radeon_semaphore *sem = NULL;
2628         int ring_index = rdev->asic->copy.dma_ring_index;
2629         struct radeon_ring *ring = &rdev->ring[ring_index];
2630         u32 size_in_dw, cur_size_in_dw;
2631         int i, num_loops;
2632         int r = 0;
2633
2634         r = radeon_semaphore_create(rdev, &sem);
2635         if (r) {
2636                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2637                 return r;
2638         }
2639
2640         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
2641         num_loops = DIV_ROUND_UP(size_in_dw, 0xffff);
2642         r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
2643         if (r) {
2644                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2645                 radeon_semaphore_free(rdev, &sem, NULL);
2646                 return r;
2647         }
2648
2649         if (radeon_fence_need_sync(*fence, ring->idx)) {
2650                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2651                                             ring->idx);
2652                 radeon_fence_note_sync(*fence, ring->idx);
2653         } else {
2654                 radeon_semaphore_free(rdev, &sem, NULL);
2655         }
2656
2657         for (i = 0; i < num_loops; i++) {
2658                 cur_size_in_dw = size_in_dw;
2659                 if (cur_size_in_dw > 0xFFFE)
2660                         cur_size_in_dw = 0xFFFE;
2661                 size_in_dw -= cur_size_in_dw;
2662                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2663                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2664                 radeon_ring_write(ring, src_offset & 0xfffffffc);
2665                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2666                 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
2667                 src_offset += cur_size_in_dw * 4;
2668                 dst_offset += cur_size_in_dw * 4;
2669         }
2670
2671         r = radeon_fence_emit(rdev, fence, ring->idx);
2672         if (r) {
2673                 radeon_ring_unlock_undo(rdev, ring);
2674                 return r;
2675         }
2676
2677         radeon_ring_unlock_commit(rdev, ring);
2678         radeon_semaphore_free(rdev, &sem, *fence);
2679
2680         return r;
2681 }
2682
2683 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2684                          uint32_t tiling_flags, uint32_t pitch,
2685                          uint32_t offset, uint32_t obj_size)
2686 {
2687         /* FIXME: implement */
2688         return 0;
2689 }
2690
2691 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2692 {
2693         /* FIXME: implement */
2694 }
2695
2696 static int r600_startup(struct radeon_device *rdev)
2697 {
2698         struct radeon_ring *ring;
2699         int r;
2700
2701         /* enable pcie gen2 link */
2702         r600_pcie_gen2_enable(rdev);
2703
2704         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2705                 r = r600_init_microcode(rdev);
2706                 if (r) {
2707                         DRM_ERROR("Failed to load firmware!\n");
2708                         return r;
2709                 }
2710         }
2711
2712         r = r600_vram_scratch_init(rdev);
2713         if (r)
2714                 return r;
2715
2716         r600_mc_program(rdev);
2717         if (rdev->flags & RADEON_IS_AGP) {
2718                 r600_agp_enable(rdev);
2719         } else {
2720                 r = r600_pcie_gart_enable(rdev);
2721                 if (r)
2722                         return r;
2723         }
2724         r600_gpu_init(rdev);
2725         r = r600_blit_init(rdev);
2726         if (r) {
2727                 r600_blit_fini(rdev);
2728                 rdev->asic->copy.copy = NULL;
2729                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2730         }
2731
2732         /* allocate wb buffer */
2733         r = radeon_wb_init(rdev);
2734         if (r)
2735                 return r;
2736
2737         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2738         if (r) {
2739                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2740                 return r;
2741         }
2742
2743         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2744         if (r) {
2745                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2746                 return r;
2747         }
2748
2749         /* Enable IRQ */
2750         r = r600_irq_init(rdev);
2751         if (r) {
2752                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2753                 radeon_irq_kms_fini(rdev);
2754                 return r;
2755         }
2756         r600_irq_set(rdev);
2757
2758         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2759         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2760                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2761                              0, 0xfffff, RADEON_CP_PACKET2);
2762         if (r)
2763                 return r;
2764
2765         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2766         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2767                              DMA_RB_RPTR, DMA_RB_WPTR,
2768                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2769         if (r)
2770                 return r;
2771
2772         r = r600_cp_load_microcode(rdev);
2773         if (r)
2774                 return r;
2775         r = r600_cp_resume(rdev);
2776         if (r)
2777                 return r;
2778
2779         r = r600_dma_resume(rdev);
2780         if (r)
2781                 return r;
2782
2783         r = radeon_ib_pool_init(rdev);
2784         if (r) {
2785                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2786                 return r;
2787         }
2788
2789         r = r600_audio_init(rdev);
2790         if (r) {
2791                 DRM_ERROR("radeon: audio init failed\n");
2792                 return r;
2793         }
2794
2795         return 0;
2796 }
2797
2798 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2799 {
2800         uint32_t temp;
2801
2802         temp = RREG32(CONFIG_CNTL);
2803         if (state == false) {
2804                 temp &= ~(1<<0);
2805                 temp |= (1<<1);
2806         } else {
2807                 temp &= ~(1<<1);
2808         }
2809         WREG32(CONFIG_CNTL, temp);
2810 }
2811
2812 int r600_resume(struct radeon_device *rdev)
2813 {
2814         int r;
2815
2816         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2817          * posting will perform necessary task to bring back GPU into good
2818          * shape.
2819          */
2820         /* post card */
2821         atom_asic_init(rdev->mode_info.atom_context);
2822
2823         rdev->accel_working = true;
2824         r = r600_startup(rdev);
2825         if (r) {
2826                 DRM_ERROR("r600 startup failed on resume\n");
2827                 rdev->accel_working = false;
2828                 return r;
2829         }
2830
2831         return r;
2832 }
2833
2834 int r600_suspend(struct radeon_device *rdev)
2835 {
2836         r600_audio_fini(rdev);
2837         r600_cp_stop(rdev);
2838         r600_dma_stop(rdev);
2839         r600_irq_suspend(rdev);
2840         radeon_wb_disable(rdev);
2841         r600_pcie_gart_disable(rdev);
2842
2843         return 0;
2844 }
2845
2846 /* Plan is to move initialization in that function and use
2847  * helper function so that radeon_device_init pretty much
2848  * do nothing more than calling asic specific function. This
2849  * should also allow to remove a bunch of callback function
2850  * like vram_info.
2851  */
2852 int r600_init(struct radeon_device *rdev)
2853 {
2854         int r;
2855
2856         if (r600_debugfs_mc_info_init(rdev)) {
2857                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2858         }
2859         /* Read BIOS */
2860         if (!radeon_get_bios(rdev)) {
2861                 if (ASIC_IS_AVIVO(rdev))
2862                         return -EINVAL;
2863         }
2864         /* Must be an ATOMBIOS */
2865         if (!rdev->is_atom_bios) {
2866                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2867                 return -EINVAL;
2868         }
2869         r = radeon_atombios_init(rdev);
2870         if (r)
2871                 return r;
2872         /* Post card if necessary */
2873         if (!radeon_card_posted(rdev)) {
2874                 if (!rdev->bios) {
2875                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2876                         return -EINVAL;
2877                 }
2878                 DRM_INFO("GPU not posted. posting now...\n");
2879                 atom_asic_init(rdev->mode_info.atom_context);
2880         }
2881         /* Initialize scratch registers */
2882         r600_scratch_init(rdev);
2883         /* Initialize surface registers */
2884         radeon_surface_init(rdev);
2885         /* Initialize clocks */
2886         radeon_get_clock_info(rdev->ddev);
2887         /* Fence driver */
2888         r = radeon_fence_driver_init(rdev);
2889         if (r)
2890                 return r;
2891         if (rdev->flags & RADEON_IS_AGP) {
2892                 r = radeon_agp_init(rdev);
2893                 if (r)
2894                         radeon_agp_disable(rdev);
2895         }
2896         r = r600_mc_init(rdev);
2897         if (r)
2898                 return r;
2899         /* Memory manager */
2900         r = radeon_bo_init(rdev);
2901         if (r)
2902                 return r;
2903
2904         r = radeon_irq_kms_init(rdev);
2905         if (r)
2906                 return r;
2907
2908         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2909         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2910
2911         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2912         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2913
2914         rdev->ih.ring_obj = NULL;
2915         r600_ih_ring_init(rdev, 64 * 1024);
2916
2917         r = r600_pcie_gart_init(rdev);
2918         if (r)
2919                 return r;
2920
2921         rdev->accel_working = true;
2922         r = r600_startup(rdev);
2923         if (r) {
2924                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2925                 r600_cp_fini(rdev);
2926                 r600_dma_fini(rdev);
2927                 r600_irq_fini(rdev);
2928                 radeon_wb_fini(rdev);
2929                 radeon_ib_pool_fini(rdev);
2930                 radeon_irq_kms_fini(rdev);
2931                 r600_pcie_gart_fini(rdev);
2932                 rdev->accel_working = false;
2933         }
2934
2935         return 0;
2936 }
2937
2938 void r600_fini(struct radeon_device *rdev)
2939 {
2940         r600_audio_fini(rdev);
2941         r600_blit_fini(rdev);
2942         r600_cp_fini(rdev);
2943         r600_dma_fini(rdev);
2944         r600_irq_fini(rdev);
2945         radeon_wb_fini(rdev);
2946         radeon_ib_pool_fini(rdev);
2947         radeon_irq_kms_fini(rdev);
2948         r600_pcie_gart_fini(rdev);
2949         r600_vram_scratch_fini(rdev);
2950         radeon_agp_fini(rdev);
2951         radeon_gem_fini(rdev);
2952         radeon_fence_driver_fini(rdev);
2953         radeon_bo_fini(rdev);
2954         radeon_atombios_fini(rdev);
2955         kfree(rdev->bios);
2956         rdev->bios = NULL;
2957 }
2958
2959
2960 /*
2961  * CS stuff
2962  */
2963 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2964 {
2965         struct radeon_ring *ring = &rdev->ring[ib->ring];
2966         u32 next_rptr;
2967
2968         if (ring->rptr_save_reg) {
2969                 next_rptr = ring->wptr + 3 + 4;
2970                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2971                 radeon_ring_write(ring, ((ring->rptr_save_reg -
2972                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2973                 radeon_ring_write(ring, next_rptr);
2974         } else if (rdev->wb.enabled) {
2975                 next_rptr = ring->wptr + 5 + 4;
2976                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
2977                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2978                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
2979                 radeon_ring_write(ring, next_rptr);
2980                 radeon_ring_write(ring, 0);
2981         }
2982
2983         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2984         radeon_ring_write(ring,
2985 #ifdef __BIG_ENDIAN
2986                           (2 << 0) |
2987 #endif
2988                           (ib->gpu_addr & 0xFFFFFFFC));
2989         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2990         radeon_ring_write(ring, ib->length_dw);
2991 }
2992
2993 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
2994 {
2995         struct radeon_ib ib;
2996         uint32_t scratch;
2997         uint32_t tmp = 0;
2998         unsigned i;
2999         int r;
3000
3001         r = radeon_scratch_get(rdev, &scratch);
3002         if (r) {
3003                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3004                 return r;
3005         }
3006         WREG32(scratch, 0xCAFEDEAD);
3007         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3008         if (r) {
3009                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3010                 goto free_scratch;
3011         }
3012         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3013         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3014         ib.ptr[2] = 0xDEADBEEF;
3015         ib.length_dw = 3;
3016         r = radeon_ib_schedule(rdev, &ib, NULL);
3017         if (r) {
3018                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3019                 goto free_ib;
3020         }
3021         r = radeon_fence_wait(ib.fence, false);
3022         if (r) {
3023                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3024                 goto free_ib;
3025         }
3026         for (i = 0; i < rdev->usec_timeout; i++) {
3027                 tmp = RREG32(scratch);
3028                 if (tmp == 0xDEADBEEF)
3029                         break;
3030                 DRM_UDELAY(1);
3031         }
3032         if (i < rdev->usec_timeout) {
3033                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3034         } else {
3035                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3036                           scratch, tmp);
3037                 r = -EINVAL;
3038         }
3039 free_ib:
3040         radeon_ib_free(rdev, &ib);
3041 free_scratch:
3042         radeon_scratch_free(rdev, scratch);
3043         return r;
3044 }
3045
3046 /**
3047  * r600_dma_ib_test - test an IB on the DMA engine
3048  *
3049  * @rdev: radeon_device pointer
3050  * @ring: radeon_ring structure holding ring information
3051  *
3052  * Test a simple IB in the DMA ring (r6xx-SI).
3053  * Returns 0 on success, error on failure.
3054  */
3055 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3056 {
3057         struct radeon_ib ib;
3058         unsigned i;
3059         int r;
3060         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3061         u32 tmp = 0;
3062
3063         if (!ptr) {
3064                 DRM_ERROR("invalid vram scratch pointer\n");
3065                 return -EINVAL;
3066         }
3067
3068         tmp = 0xCAFEDEAD;
3069         writel(tmp, ptr);
3070
3071         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3072         if (r) {
3073                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3074                 return r;
3075         }
3076
3077         ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3078         ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3079         ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3080         ib.ptr[3] = 0xDEADBEEF;
3081         ib.length_dw = 4;
3082
3083         r = radeon_ib_schedule(rdev, &ib, NULL);
3084         if (r) {
3085                 radeon_ib_free(rdev, &ib);
3086                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3087                 return r;
3088         }
3089         r = radeon_fence_wait(ib.fence, false);
3090         if (r) {
3091                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3092                 return r;
3093         }
3094         for (i = 0; i < rdev->usec_timeout; i++) {
3095                 tmp = readl(ptr);
3096                 if (tmp == 0xDEADBEEF)
3097                         break;
3098                 DRM_UDELAY(1);
3099         }
3100         if (i < rdev->usec_timeout) {
3101                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3102         } else {
3103                 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3104                 r = -EINVAL;
3105         }
3106         radeon_ib_free(rdev, &ib);
3107         return r;
3108 }
3109
3110 /**
3111  * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3112  *
3113  * @rdev: radeon_device pointer
3114  * @ib: IB object to schedule
3115  *
3116  * Schedule an IB in the DMA ring (r6xx-r7xx).
3117  */
3118 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3119 {
3120         struct radeon_ring *ring = &rdev->ring[ib->ring];
3121
3122         if (rdev->wb.enabled) {
3123                 u32 next_rptr = ring->wptr + 4;
3124                 while ((next_rptr & 7) != 5)
3125                         next_rptr++;
3126                 next_rptr += 3;
3127                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3128                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3129                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3130                 radeon_ring_write(ring, next_rptr);
3131         }
3132
3133         /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3134          * Pad as necessary with NOPs.
3135          */
3136         while ((ring->wptr & 7) != 5)
3137                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3138         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3139         radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3140         radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3141
3142 }
3143
3144 /*
3145  * Interrupts
3146  *
3147  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3148  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3149  * writing to the ring and the GPU consuming, the GPU writes to the ring
3150  * and host consumes.  As the host irq handler processes interrupts, it
3151  * increments the rptr.  When the rptr catches up with the wptr, all the
3152  * current interrupts have been processed.
3153  */
3154
3155 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3156 {
3157         u32 rb_bufsz;
3158
3159         /* Align ring size */
3160         rb_bufsz = drm_order(ring_size / 4);
3161         ring_size = (1 << rb_bufsz) * 4;
3162         rdev->ih.ring_size = ring_size;
3163         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3164         rdev->ih.rptr = 0;
3165 }
3166
3167 int r600_ih_ring_alloc(struct radeon_device *rdev)
3168 {
3169         int r;
3170
3171         /* Allocate ring buffer */
3172         if (rdev->ih.ring_obj == NULL) {
3173                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3174                                      PAGE_SIZE, true,
3175                                      RADEON_GEM_DOMAIN_GTT,
3176                                      NULL, &rdev->ih.ring_obj);
3177                 if (r) {
3178                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3179                         return r;
3180                 }
3181                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3182                 if (unlikely(r != 0))
3183                         return r;
3184                 r = radeon_bo_pin(rdev->ih.ring_obj,
3185                                   RADEON_GEM_DOMAIN_GTT,
3186                                   &rdev->ih.gpu_addr);
3187                 if (r) {
3188                         radeon_bo_unreserve(rdev->ih.ring_obj);
3189                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3190                         return r;
3191                 }
3192                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3193                                    (void **)&rdev->ih.ring);
3194                 radeon_bo_unreserve(rdev->ih.ring_obj);
3195                 if (r) {
3196                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3197                         return r;
3198                 }
3199         }
3200         return 0;
3201 }
3202
3203 void r600_ih_ring_fini(struct radeon_device *rdev)
3204 {
3205         int r;
3206         if (rdev->ih.ring_obj) {
3207                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3208                 if (likely(r == 0)) {
3209                         radeon_bo_kunmap(rdev->ih.ring_obj);
3210                         radeon_bo_unpin(rdev->ih.ring_obj);
3211                         radeon_bo_unreserve(rdev->ih.ring_obj);
3212                 }
3213                 radeon_bo_unref(&rdev->ih.ring_obj);
3214                 rdev->ih.ring = NULL;
3215                 rdev->ih.ring_obj = NULL;
3216         }
3217 }
3218
3219 void r600_rlc_stop(struct radeon_device *rdev)
3220 {
3221
3222         if ((rdev->family >= CHIP_RV770) &&
3223             (rdev->family <= CHIP_RV740)) {
3224                 /* r7xx asics need to soft reset RLC before halting */
3225                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3226                 RREG32(SRBM_SOFT_RESET);
3227                 mdelay(15);
3228                 WREG32(SRBM_SOFT_RESET, 0);
3229                 RREG32(SRBM_SOFT_RESET);
3230         }
3231
3232         WREG32(RLC_CNTL, 0);
3233 }
3234
3235 static void r600_rlc_start(struct radeon_device *rdev)
3236 {
3237         WREG32(RLC_CNTL, RLC_ENABLE);
3238 }
3239
3240 static int r600_rlc_init(struct radeon_device *rdev)
3241 {
3242         u32 i;
3243         const __be32 *fw_data;
3244
3245         if (!rdev->rlc_fw)
3246                 return -EINVAL;
3247
3248         r600_rlc_stop(rdev);
3249
3250         WREG32(RLC_HB_CNTL, 0);
3251
3252         if (rdev->family == CHIP_ARUBA) {
3253                 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3254                 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3255         }
3256         if (rdev->family <= CHIP_CAYMAN) {
3257                 WREG32(RLC_HB_BASE, 0);
3258                 WREG32(RLC_HB_RPTR, 0);
3259                 WREG32(RLC_HB_WPTR, 0);
3260         }
3261         if (rdev->family <= CHIP_CAICOS) {
3262                 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3263                 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3264         }
3265         WREG32(RLC_MC_CNTL, 0);
3266         WREG32(RLC_UCODE_CNTL, 0);
3267
3268         fw_data = (const __be32 *)rdev->rlc_fw->data;
3269         if (rdev->family >= CHIP_ARUBA) {
3270                 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3271                         WREG32(RLC_UCODE_ADDR, i);
3272                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3273                 }
3274         } else if (rdev->family >= CHIP_CAYMAN) {
3275                 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3276                         WREG32(RLC_UCODE_ADDR, i);
3277                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3278                 }
3279         } else if (rdev->family >= CHIP_CEDAR) {
3280                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3281                         WREG32(RLC_UCODE_ADDR, i);
3282                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3283                 }
3284         } else if (rdev->family >= CHIP_RV770) {
3285                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3286                         WREG32(RLC_UCODE_ADDR, i);
3287                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3288                 }
3289         } else {
3290                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
3291                         WREG32(RLC_UCODE_ADDR, i);
3292                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3293                 }
3294         }
3295         WREG32(RLC_UCODE_ADDR, 0);
3296
3297         r600_rlc_start(rdev);
3298
3299         return 0;
3300 }
3301
3302 static void r600_enable_interrupts(struct radeon_device *rdev)
3303 {
3304         u32 ih_cntl = RREG32(IH_CNTL);
3305         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3306
3307         ih_cntl |= ENABLE_INTR;
3308         ih_rb_cntl |= IH_RB_ENABLE;
3309         WREG32(IH_CNTL, ih_cntl);
3310         WREG32(IH_RB_CNTL, ih_rb_cntl);
3311         rdev->ih.enabled = true;
3312 }
3313
3314 void r600_disable_interrupts(struct radeon_device *rdev)
3315 {
3316         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3317         u32 ih_cntl = RREG32(IH_CNTL);
3318
3319         ih_rb_cntl &= ~IH_RB_ENABLE;
3320         ih_cntl &= ~ENABLE_INTR;
3321         WREG32(IH_RB_CNTL, ih_rb_cntl);
3322         WREG32(IH_CNTL, ih_cntl);
3323         /* set rptr, wptr to 0 */
3324         WREG32(IH_RB_RPTR, 0);
3325         WREG32(IH_RB_WPTR, 0);
3326         rdev->ih.enabled = false;
3327         rdev->ih.rptr = 0;
3328 }
3329
3330 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3331 {
3332         u32 tmp;
3333
3334         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3335         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3336         WREG32(DMA_CNTL, tmp);
3337         WREG32(GRBM_INT_CNTL, 0);
3338         WREG32(DxMODE_INT_MASK, 0);
3339         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3340         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3341         if (ASIC_IS_DCE3(rdev)) {
3342                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3343                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3344                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3345                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3346                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3347                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3348                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3349                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3350                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3351                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3352                 if (ASIC_IS_DCE32(rdev)) {
3353                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3354                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3355                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3356                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3357                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3358                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3359                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3360                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3361                 } else {
3362                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3363                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3364                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3365                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3366                 }
3367         } else {
3368                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3369                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3370                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3371                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3372                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3373                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3374                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3375                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3376                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3377                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3378                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3379                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3380         }
3381 }
3382
3383 int r600_irq_init(struct radeon_device *rdev)
3384 {
3385         int ret = 0;
3386         int rb_bufsz;
3387         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3388
3389         /* allocate ring */
3390         ret = r600_ih_ring_alloc(rdev);
3391         if (ret)
3392                 return ret;
3393
3394         /* disable irqs */
3395         r600_disable_interrupts(rdev);
3396
3397         /* init rlc */
3398         ret = r600_rlc_init(rdev);
3399         if (ret) {
3400                 r600_ih_ring_fini(rdev);
3401                 return ret;
3402         }
3403
3404         /* setup interrupt control */
3405         /* set dummy read address to ring address */
3406         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3407         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3408         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3409          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3410          */
3411         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3412         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3413         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3414         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3415
3416         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3417         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3418
3419         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3420                       IH_WPTR_OVERFLOW_CLEAR |
3421                       (rb_bufsz << 1));
3422
3423         if (rdev->wb.enabled)
3424                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3425
3426         /* set the writeback address whether it's enabled or not */
3427         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3428         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3429
3430         WREG32(IH_RB_CNTL, ih_rb_cntl);
3431
3432         /* set rptr, wptr to 0 */
3433         WREG32(IH_RB_RPTR, 0);
3434         WREG32(IH_RB_WPTR, 0);
3435
3436         /* Default settings for IH_CNTL (disabled at first) */
3437         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3438         /* RPTR_REARM only works if msi's are enabled */
3439         if (rdev->msi_enabled)
3440                 ih_cntl |= RPTR_REARM;
3441         WREG32(IH_CNTL, ih_cntl);
3442
3443         /* force the active interrupt state to all disabled */
3444         if (rdev->family >= CHIP_CEDAR)
3445                 evergreen_disable_interrupt_state(rdev);
3446         else
3447                 r600_disable_interrupt_state(rdev);
3448
3449         /* at this point everything should be setup correctly to enable master */
3450         pci_set_master(rdev->pdev);
3451
3452         /* enable irqs */
3453         r600_enable_interrupts(rdev);
3454
3455         return ret;
3456 }
3457
3458 void r600_irq_suspend(struct radeon_device *rdev)
3459 {
3460         r600_irq_disable(rdev);
3461         r600_rlc_stop(rdev);
3462 }
3463
3464 void r600_irq_fini(struct radeon_device *rdev)
3465 {
3466         r600_irq_suspend(rdev);
3467         r600_ih_ring_fini(rdev);
3468 }
3469
3470 int r600_irq_set(struct radeon_device *rdev)
3471 {
3472         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3473         u32 mode_int = 0;
3474         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3475         u32 grbm_int_cntl = 0;
3476         u32 hdmi0, hdmi1;
3477         u32 d1grph = 0, d2grph = 0;
3478         u32 dma_cntl;
3479
3480         if (!rdev->irq.installed) {
3481                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3482                 return -EINVAL;
3483         }
3484         /* don't enable anything if the ih is disabled */
3485         if (!rdev->ih.enabled) {
3486                 r600_disable_interrupts(rdev);
3487                 /* force the active interrupt state to all disabled */
3488                 r600_disable_interrupt_state(rdev);
3489                 return 0;
3490         }
3491
3492         if (ASIC_IS_DCE3(rdev)) {
3493                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3494                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3495                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3496                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3497                 if (ASIC_IS_DCE32(rdev)) {
3498                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3499                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3500                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3501                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3502                 } else {
3503                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3504                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3505                 }
3506         } else {
3507                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3508                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3509                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3510                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3511                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3512         }
3513         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3514
3515         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3516                 DRM_DEBUG("r600_irq_set: sw int\n");
3517                 cp_int_cntl |= RB_INT_ENABLE;
3518                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3519         }
3520
3521         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3522                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3523                 dma_cntl |= TRAP_ENABLE;
3524         }
3525
3526         if (rdev->irq.crtc_vblank_int[0] ||
3527             atomic_read(&rdev->irq.pflip[0])) {
3528                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3529                 mode_int |= D1MODE_VBLANK_INT_MASK;
3530         }
3531         if (rdev->irq.crtc_vblank_int[1] ||
3532             atomic_read(&rdev->irq.pflip[1])) {
3533                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3534                 mode_int |= D2MODE_VBLANK_INT_MASK;
3535         }
3536         if (rdev->irq.hpd[0]) {
3537                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3538                 hpd1 |= DC_HPDx_INT_EN;
3539         }
3540         if (rdev->irq.hpd[1]) {
3541                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3542                 hpd2 |= DC_HPDx_INT_EN;
3543         }
3544         if (rdev->irq.hpd[2]) {
3545                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3546                 hpd3 |= DC_HPDx_INT_EN;
3547         }
3548         if (rdev->irq.hpd[3]) {
3549                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3550                 hpd4 |= DC_HPDx_INT_EN;
3551         }
3552         if (rdev->irq.hpd[4]) {
3553                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3554                 hpd5 |= DC_HPDx_INT_EN;
3555         }
3556         if (rdev->irq.hpd[5]) {
3557                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3558                 hpd6 |= DC_HPDx_INT_EN;
3559         }
3560         if (rdev->irq.afmt[0]) {
3561                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3562                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3563         }
3564         if (rdev->irq.afmt[1]) {
3565                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3566                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3567         }
3568
3569         WREG32(CP_INT_CNTL, cp_int_cntl);
3570         WREG32(DMA_CNTL, dma_cntl);
3571         WREG32(DxMODE_INT_MASK, mode_int);
3572         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3573         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3574         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3575         if (ASIC_IS_DCE3(rdev)) {
3576                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3577                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3578                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3579                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3580                 if (ASIC_IS_DCE32(rdev)) {
3581                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3582                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3583                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3584                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3585                 } else {
3586                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3587                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3588                 }
3589         } else {
3590                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3591                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3592                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3593                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3594                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3595         }
3596
3597         return 0;
3598 }
3599
3600 static void r600_irq_ack(struct radeon_device *rdev)
3601 {
3602         u32 tmp;
3603
3604         if (ASIC_IS_DCE3(rdev)) {
3605                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3606                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3607                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3608                 if (ASIC_IS_DCE32(rdev)) {
3609                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3610                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3611                 } else {
3612                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3613                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3614                 }
3615         } else {
3616                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3617                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3618                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3619                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3620                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3621         }
3622         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3623         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3624
3625         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3626                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3627         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3628                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3629         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3630                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3631         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3632                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3633         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3634                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3635         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3636                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3637         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3638                 if (ASIC_IS_DCE3(rdev)) {
3639                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3640                         tmp |= DC_HPDx_INT_ACK;
3641                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3642                 } else {
3643                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3644                         tmp |= DC_HPDx_INT_ACK;
3645                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3646                 }
3647         }
3648         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3649                 if (ASIC_IS_DCE3(rdev)) {
3650                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3651                         tmp |= DC_HPDx_INT_ACK;
3652                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3653                 } else {
3654                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3655                         tmp |= DC_HPDx_INT_ACK;
3656                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3657                 }
3658         }
3659         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3660                 if (ASIC_IS_DCE3(rdev)) {
3661                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3662                         tmp |= DC_HPDx_INT_ACK;
3663                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3664                 } else {
3665                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3666                         tmp |= DC_HPDx_INT_ACK;
3667                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3668                 }
3669         }
3670         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3671                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3672                 tmp |= DC_HPDx_INT_ACK;
3673                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3674         }
3675         if (ASIC_IS_DCE32(rdev)) {
3676                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3677                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3678                         tmp |= DC_HPDx_INT_ACK;
3679                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3680                 }
3681                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3682                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3683                         tmp |= DC_HPDx_INT_ACK;
3684                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3685                 }
3686                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3687                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3688                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3689                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3690                 }
3691                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3692                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3693                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3694                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3695                 }
3696         } else {
3697                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3698                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3699                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3700                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3701                 }
3702                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3703                         if (ASIC_IS_DCE3(rdev)) {
3704                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3705                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3706                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3707                         } else {
3708                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3709                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3710                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3711                         }
3712                 }
3713         }
3714 }
3715
3716 void r600_irq_disable(struct radeon_device *rdev)
3717 {
3718         r600_disable_interrupts(rdev);
3719         /* Wait and acknowledge irq */
3720         mdelay(1);
3721         r600_irq_ack(rdev);
3722         r600_disable_interrupt_state(rdev);
3723 }
3724
3725 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3726 {
3727         u32 wptr, tmp;
3728
3729         if (rdev->wb.enabled)
3730                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3731         else
3732                 wptr = RREG32(IH_RB_WPTR);
3733
3734         if (wptr & RB_OVERFLOW) {
3735                 /* When a ring buffer overflow happen start parsing interrupt
3736                  * from the last not overwritten vector (wptr + 16). Hopefully
3737                  * this should allow us to catchup.
3738                  */
3739                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3740                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3741                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3742                 tmp = RREG32(IH_RB_CNTL);
3743                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3744                 WREG32(IH_RB_CNTL, tmp);
3745         }
3746         return (wptr & rdev->ih.ptr_mask);
3747 }
3748
3749 /*        r600 IV Ring
3750  * Each IV ring entry is 128 bits:
3751  * [7:0]    - interrupt source id
3752  * [31:8]   - reserved
3753  * [59:32]  - interrupt source data
3754  * [127:60]  - reserved
3755  *
3756  * The basic interrupt vector entries
3757  * are decoded as follows:
3758  * src_id  src_data  description
3759  *      1         0  D1 Vblank
3760  *      1         1  D1 Vline
3761  *      5         0  D2 Vblank
3762  *      5         1  D2 Vline
3763  *     19         0  FP Hot plug detection A
3764  *     19         1  FP Hot plug detection B
3765  *     19         2  DAC A auto-detection
3766  *     19         3  DAC B auto-detection
3767  *     21         4  HDMI block A
3768  *     21         5  HDMI block B
3769  *    176         -  CP_INT RB
3770  *    177         -  CP_INT IB1
3771  *    178         -  CP_INT IB2
3772  *    181         -  EOP Interrupt
3773  *    233         -  GUI Idle
3774  *
3775  * Note, these are based on r600 and may need to be
3776  * adjusted or added to on newer asics
3777  */
3778
3779 int r600_irq_process(struct radeon_device *rdev)
3780 {
3781         u32 wptr;
3782         u32 rptr;
3783         u32 src_id, src_data;
3784         u32 ring_index;
3785         bool queue_hotplug = false;
3786         bool queue_hdmi = false;
3787
3788         if (!rdev->ih.enabled || rdev->shutdown)
3789                 return IRQ_NONE;
3790
3791         /* No MSIs, need a dummy read to flush PCI DMAs */
3792         if (!rdev->msi_enabled)
3793                 RREG32(IH_RB_WPTR);
3794
3795         wptr = r600_get_ih_wptr(rdev);
3796
3797 restart_ih:
3798         /* is somebody else already processing irqs? */
3799         if (atomic_xchg(&rdev->ih.lock, 1))
3800                 return IRQ_NONE;
3801
3802         rptr = rdev->ih.rptr;
3803         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3804
3805         /* Order reading of wptr vs. reading of IH ring data */
3806         rmb();
3807
3808         /* display interrupts */
3809         r600_irq_ack(rdev);
3810
3811         while (rptr != wptr) {
3812                 /* wptr/rptr are in bytes! */
3813                 ring_index = rptr / 4;
3814                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3815                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3816
3817                 switch (src_id) {
3818                 case 1: /* D1 vblank/vline */
3819                         switch (src_data) {
3820                         case 0: /* D1 vblank */
3821                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3822                                         if (rdev->irq.crtc_vblank_int[0]) {
3823                                                 drm_handle_vblank(rdev->ddev, 0);
3824                                                 rdev->pm.vblank_sync = true;
3825                                                 wake_up(&rdev->irq.vblank_queue);
3826                                         }
3827                                         if (atomic_read(&rdev->irq.pflip[0]))
3828                                                 radeon_crtc_handle_flip(rdev, 0);
3829                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3830                                         DRM_DEBUG("IH: D1 vblank\n");
3831                                 }
3832                                 break;
3833                         case 1: /* D1 vline */
3834                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3835                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3836                                         DRM_DEBUG("IH: D1 vline\n");
3837                                 }
3838                                 break;
3839                         default:
3840                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3841                                 break;
3842                         }
3843                         break;
3844                 case 5: /* D2 vblank/vline */
3845                         switch (src_data) {
3846                         case 0: /* D2 vblank */
3847                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3848                                         if (rdev->irq.crtc_vblank_int[1]) {
3849                                                 drm_handle_vblank(rdev->ddev, 1);
3850                                                 rdev->pm.vblank_sync = true;
3851                                                 wake_up(&rdev->irq.vblank_queue);
3852                                         }
3853                                         if (atomic_read(&rdev->irq.pflip[1]))
3854                                                 radeon_crtc_handle_flip(rdev, 1);
3855                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3856                                         DRM_DEBUG("IH: D2 vblank\n");
3857                                 }
3858                                 break;
3859                         case 1: /* D1 vline */
3860                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3861                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3862                                         DRM_DEBUG("IH: D2 vline\n");
3863                                 }
3864                                 break;
3865                         default:
3866                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3867                                 break;
3868                         }
3869                         break;
3870                 case 19: /* HPD/DAC hotplug */
3871                         switch (src_data) {
3872                         case 0:
3873                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3874                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3875                                         queue_hotplug = true;
3876                                         DRM_DEBUG("IH: HPD1\n");
3877                                 }
3878                                 break;
3879                         case 1:
3880                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3881                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3882                                         queue_hotplug = true;
3883                                         DRM_DEBUG("IH: HPD2\n");
3884                                 }
3885                                 break;
3886                         case 4:
3887                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3888                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3889                                         queue_hotplug = true;
3890                                         DRM_DEBUG("IH: HPD3\n");
3891                                 }
3892                                 break;
3893                         case 5:
3894                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3895                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3896                                         queue_hotplug = true;
3897                                         DRM_DEBUG("IH: HPD4\n");
3898                                 }
3899                                 break;
3900                         case 10:
3901                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3902                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3903                                         queue_hotplug = true;
3904                                         DRM_DEBUG("IH: HPD5\n");
3905                                 }
3906                                 break;
3907                         case 12:
3908                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3909                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3910                                         queue_hotplug = true;
3911                                         DRM_DEBUG("IH: HPD6\n");
3912                                 }
3913                                 break;
3914                         default:
3915                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3916                                 break;
3917                         }
3918                         break;
3919                 case 21: /* hdmi */
3920                         switch (src_data) {
3921                         case 4:
3922                                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3923                                         rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3924                                         queue_hdmi = true;
3925                                         DRM_DEBUG("IH: HDMI0\n");
3926                                 }
3927                                 break;
3928                         case 5:
3929                                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3930                                         rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3931                                         queue_hdmi = true;
3932                                         DRM_DEBUG("IH: HDMI1\n");
3933                                 }
3934                                 break;
3935                         default:
3936                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3937                                 break;
3938                         }
3939                         break;
3940                 case 176: /* CP_INT in ring buffer */
3941                 case 177: /* CP_INT in IB1 */
3942                 case 178: /* CP_INT in IB2 */
3943                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3944                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3945                         break;
3946                 case 181: /* CP EOP event */
3947                         DRM_DEBUG("IH: CP EOP\n");
3948                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3949                         break;
3950                 case 224: /* DMA trap event */
3951                         DRM_DEBUG("IH: DMA trap\n");
3952                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3953                         break;
3954                 case 233: /* GUI IDLE */
3955                         DRM_DEBUG("IH: GUI idle\n");
3956                         break;
3957                 default:
3958                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3959                         break;
3960                 }
3961
3962                 /* wptr/rptr are in bytes! */
3963                 rptr += 16;
3964                 rptr &= rdev->ih.ptr_mask;
3965         }
3966         if (queue_hotplug)
3967                 schedule_work(&rdev->hotplug_work);
3968         if (queue_hdmi)
3969                 schedule_work(&rdev->audio_work);
3970         rdev->ih.rptr = rptr;
3971         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3972         atomic_set(&rdev->ih.lock, 0);
3973
3974         /* make sure wptr hasn't changed while processing */
3975         wptr = r600_get_ih_wptr(rdev);
3976         if (wptr != rptr)
3977                 goto restart_ih;
3978
3979         return IRQ_HANDLED;
3980 }
3981
3982 /*
3983  * Debugfs info
3984  */
3985 #if defined(CONFIG_DEBUG_FS)
3986
3987 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3988 {
3989         struct drm_info_node *node = (struct drm_info_node *) m->private;
3990         struct drm_device *dev = node->minor->dev;
3991         struct radeon_device *rdev = dev->dev_private;
3992
3993         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3994         DREG32_SYS(m, rdev, VM_L2_STATUS);
3995         return 0;
3996 }
3997
3998 static struct drm_info_list r600_mc_info_list[] = {
3999         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4000 };
4001 #endif
4002
4003 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4004 {
4005 #if defined(CONFIG_DEBUG_FS)
4006         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4007 #else
4008         return 0;
4009 #endif
4010 }
4011
4012 /**
4013  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4014  * rdev: radeon device structure
4015  * bo: buffer object struct which userspace is waiting for idle
4016  *
4017  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4018  * through ring buffer, this leads to corruption in rendering, see
4019  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4020  * directly perform HDP flush by writing register through MMIO.
4021  */
4022 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4023 {
4024         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4025          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4026          * This seems to cause problems on some AGP cards. Just use the old
4027          * method for them.
4028          */
4029         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4030             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4031                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4032                 u32 tmp;
4033
4034                 WREG32(HDP_DEBUG1, 0);
4035                 tmp = readl((void __iomem *)ptr);
4036         } else
4037                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4038 }
4039
4040 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4041 {
4042         u32 link_width_cntl, mask, target_reg;
4043
4044         if (rdev->flags & RADEON_IS_IGP)
4045                 return;
4046
4047         if (!(rdev->flags & RADEON_IS_PCIE))
4048                 return;
4049
4050         /* x2 cards have a special sequence */
4051         if (ASIC_IS_X2(rdev))
4052                 return;
4053
4054         /* FIXME wait for idle */
4055
4056         switch (lanes) {
4057         case 0:
4058                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4059                 break;
4060         case 1:
4061                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4062                 break;
4063         case 2:
4064                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4065                 break;
4066         case 4:
4067                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4068                 break;
4069         case 8:
4070                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4071                 break;
4072         case 12:
4073                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4074                 break;
4075         case 16:
4076         default:
4077                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4078                 break;
4079         }
4080
4081         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4082
4083         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4084             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4085                 return;
4086
4087         if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4088                 return;
4089
4090         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
4091                              RADEON_PCIE_LC_RECONFIG_NOW |
4092                              R600_PCIE_LC_RENEGOTIATE_EN |
4093                              R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4094         link_width_cntl |= mask;
4095
4096         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4097
4098         /* some northbridges can renegotiate the link rather than requiring
4099          * a complete re-config.
4100          * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4101          */
4102         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4103                 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4104         else
4105                 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4106
4107         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4108                                                        RADEON_PCIE_LC_RECONFIG_NOW));
4109
4110         if (rdev->family >= CHIP_RV770)
4111                 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4112         else
4113                 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4114
4115         /* wait for lane set to complete */
4116         link_width_cntl = RREG32(target_reg);
4117         while (link_width_cntl == 0xffffffff)
4118                 link_width_cntl = RREG32(target_reg);
4119
4120 }
4121
4122 int r600_get_pcie_lanes(struct radeon_device *rdev)
4123 {
4124         u32 link_width_cntl;
4125
4126         if (rdev->flags & RADEON_IS_IGP)
4127                 return 0;
4128
4129         if (!(rdev->flags & RADEON_IS_PCIE))
4130                 return 0;
4131
4132         /* x2 cards have a special sequence */
4133         if (ASIC_IS_X2(rdev))
4134                 return 0;
4135
4136         /* FIXME wait for idle */
4137
4138         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4139
4140         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4141         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4142                 return 0;
4143         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4144                 return 1;
4145         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4146                 return 2;
4147         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4148                 return 4;
4149         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4150                 return 8;
4151         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4152         default:
4153                 return 16;
4154         }
4155 }
4156
4157 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4158 {
4159         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4160         u16 link_cntl2;
4161         u32 mask;
4162         int ret;
4163
4164         if (radeon_pcie_gen2 == 0)
4165                 return;
4166
4167         if (rdev->flags & RADEON_IS_IGP)
4168                 return;
4169
4170         if (!(rdev->flags & RADEON_IS_PCIE))
4171                 return;
4172
4173         /* x2 cards have a special sequence */
4174         if (ASIC_IS_X2(rdev))
4175                 return;
4176
4177         /* only RV6xx+ chips are supported */
4178         if (rdev->family <= CHIP_R600)
4179                 return;
4180
4181         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
4182         if (ret != 0)
4183                 return;
4184
4185         if (!(mask & DRM_PCIE_SPEED_50))
4186                 return;
4187
4188         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4189         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4190                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4191                 return;
4192         }
4193
4194         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4195
4196         /* 55 nm r6xx asics */
4197         if ((rdev->family == CHIP_RV670) ||
4198             (rdev->family == CHIP_RV620) ||
4199             (rdev->family == CHIP_RV635)) {
4200                 /* advertise upconfig capability */
4201                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4202                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4203                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4204                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4205                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4206                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4207                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4208                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4209                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4210                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4211                 } else {
4212                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4213                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4214                 }
4215         }
4216
4217         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4218         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4219             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4220
4221                 /* 55 nm r6xx asics */
4222                 if ((rdev->family == CHIP_RV670) ||
4223                     (rdev->family == CHIP_RV620) ||
4224                     (rdev->family == CHIP_RV635)) {
4225                         WREG32(MM_CFGREGS_CNTL, 0x8);
4226                         link_cntl2 = RREG32(0x4088);
4227                         WREG32(MM_CFGREGS_CNTL, 0);
4228                         /* not supported yet */
4229                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4230                                 return;
4231                 }
4232
4233                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4234                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4235                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4236                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4237                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4238                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4239
4240                 tmp = RREG32(0x541c);
4241                 WREG32(0x541c, tmp | 0x8);
4242                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4243                 link_cntl2 = RREG16(0x4088);
4244                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4245                 link_cntl2 |= 0x2;
4246                 WREG16(0x4088, link_cntl2);
4247                 WREG32(MM_CFGREGS_CNTL, 0);
4248
4249                 if ((rdev->family == CHIP_RV670) ||
4250                     (rdev->family == CHIP_RV620) ||
4251                     (rdev->family == CHIP_RV635)) {
4252                         training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
4253                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4254                         WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
4255                 } else {
4256                         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4257                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4258                         WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4259                 }
4260
4261                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4262                 speed_cntl |= LC_GEN2_EN_STRAP;
4263                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4264
4265         } else {
4266                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4267                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4268                 if (1)
4269                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4270                 else
4271                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4272                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4273         }
4274 }
4275
4276 /**
4277  * r600_get_gpu_clock - return GPU clock counter snapshot
4278  *
4279  * @rdev: radeon_device pointer
4280  *
4281  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4282  * Returns the 64 bit clock counter snapshot.
4283  */
4284 uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
4285 {
4286         uint64_t clock;
4287
4288         mutex_lock(&rdev->gpu_clock_mutex);
4289         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4290         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4291                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4292         mutex_unlock(&rdev->gpu_clock_mutex);
4293         return clock;
4294 }