drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/module.h>
  32 #include <drm/drmP.h>
  33 #include <drm/radeon_drm.h>
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40 #include "radeon_ucode.h"
  41
  42 /* Firmware Names */
  43 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  44 MODULE_FIRMWARE("radeon/R600_me.bin");
  45 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  46 MODULE_FIRMWARE("radeon/RV610_me.bin");
  47 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  48 MODULE_FIRMWARE("radeon/RV630_me.bin");
  49 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  50 MODULE_FIRMWARE("radeon/RV620_me.bin");
  51 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  52 MODULE_FIRMWARE("radeon/RV635_me.bin");
  53 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  54 MODULE_FIRMWARE("radeon/RV670_me.bin");
  55 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RS780_me.bin");
  57 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV770_me.bin");
  59 MODULE_FIRMWARE("radeon/RV770_smc.bin");
  60 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV730_me.bin");
  62 MODULE_FIRMWARE("radeon/RV730_smc.bin");
  63 MODULE_FIRMWARE("radeon/RV740_smc.bin");
  64 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RV710_me.bin");
  66 MODULE_FIRMWARE("radeon/RV710_smc.bin");
  67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  69 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  70 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  71 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  72 MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
  73 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  74 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  75 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  76 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
  77 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  78 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  79 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
  81 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  82 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
  85 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  86 MODULE_FIRMWARE("radeon/PALM_me.bin");
  87 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  88 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  89 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  90 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  91 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  92
  93 static const u32 crtc_offsets[2] =
  94 {
  95         0,
  96         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  97 };
  98
  99 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
 100
 101 /* r600,rv610,rv630,rv620,rv635,rv670 */
 102 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 103 static void r600_gpu_init(struct radeon_device *rdev);
 104 void r600_fini(struct radeon_device *rdev);
 105 void r600_irq_disable(struct radeon_device *rdev);
 106 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 107 extern int evergreen_rlc_resume(struct radeon_device *rdev);
 108
 109 /**
 110  * r600_get_xclk - get the xclk
 111  *
 112  * @rdev: radeon_device pointer
 113  *
 114  * Returns the reference clock used by the gfx engine
 115  * (r6xx, IGPs, APUs).
 116  */
 117 u32 r600_get_xclk(struct radeon_device *rdev)
 118 {
 119         return rdev->clock.spll.reference_freq;
 120 }
 121
 122 /* get temperature in millidegrees */
 123 int rv6xx_get_temp(struct radeon_device *rdev)
 124 {
 125         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 126                 ASIC_T_SHIFT;
 127         int actual_temp = temp & 0xff;
 128
 129         if (temp & 0x100)
 130                 actual_temp -= 256;
 131
 132         return actual_temp * 1000;
 133 }
 134
 135 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 136 {
 137         int i;
 138
 139         rdev->pm.dynpm_can_upclock = true;
 140         rdev->pm.dynpm_can_downclock = true;
 141
 142         /* power state array is low to high, default is first */
 143         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 144                 int min_power_state_index = 0;
 145
 146                 if (rdev->pm.num_power_states > 2)
 147                         min_power_state_index = 1;
 148
 149                 switch (rdev->pm.dynpm_planned_action) {
 150                 case DYNPM_ACTION_MINIMUM:
 151                         rdev->pm.requested_power_state_index = min_power_state_index;
 152                         rdev->pm.requested_clock_mode_index = 0;
 153                         rdev->pm.dynpm_can_downclock = false;
 154                         break;
 155                 case DYNPM_ACTION_DOWNCLOCK:
 156                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 157                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 158                                 rdev->pm.dynpm_can_downclock = false;
 159                         } else {
 160                                 if (rdev->pm.active_crtc_count > 1) {
 161                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 162                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 163                                                         continue;
 164                                                 else if (i >= rdev->pm.current_power_state_index) {
 165                                                         rdev->pm.requested_power_state_index =
 166                                                                 rdev->pm.current_power_state_index;
 167                                                         break;
 168                                                 } else {
 169                                                         rdev->pm.requested_power_state_index = i;
 170                                                         break;
 171                                                 }
 172                                         }
 173                                 } else {
 174                                         if (rdev->pm.current_power_state_index == 0)
 175                                                 rdev->pm.requested_power_state_index =
 176                                                         rdev->pm.num_power_states - 1;
 177                                         else
 178                                                 rdev->pm.requested_power_state_index =
 179                                                         rdev->pm.current_power_state_index - 1;
 180                                 }
 181                         }
 182                         rdev->pm.requested_clock_mode_index = 0;
 183                         /* don't use the power state if crtcs are active and no display flag is set */
 184                         if ((rdev->pm.active_crtc_count > 0) &&
 185                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 186                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 187                              RADEON_PM_MODE_NO_DISPLAY)) {
 188                                 rdev->pm.requested_power_state_index++;
 189                         }
 190                         break;
 191                 case DYNPM_ACTION_UPCLOCK:
 192                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 193                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 194                                 rdev->pm.dynpm_can_upclock = false;
 195                         } else {
 196                                 if (rdev->pm.active_crtc_count > 1) {
 197                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 198                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 199                                                         continue;
 200                                                 else if (i <= rdev->pm.current_power_state_index) {
 201                                                         rdev->pm.requested_power_state_index =
 202                                                                 rdev->pm.current_power_state_index;
 203                                                         break;
 204                                                 } else {
 205                                                         rdev->pm.requested_power_state_index = i;
 206                                                         break;
 207                                                 }
 208                                         }
 209                                 } else
 210                                         rdev->pm.requested_power_state_index =
 211                                                 rdev->pm.current_power_state_index + 1;
 212                         }
 213                         rdev->pm.requested_clock_mode_index = 0;
 214                         break;
 215                 case DYNPM_ACTION_DEFAULT:
 216                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 217                         rdev->pm.requested_clock_mode_index = 0;
 218                         rdev->pm.dynpm_can_upclock = false;
 219                         break;
 220                 case DYNPM_ACTION_NONE:
 221                 default:
 222                         DRM_ERROR("Requested mode for not defined action\n");
 223                         return;
 224                 }
 225         } else {
 226                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 227                 /* for now just select the first power state and switch between clock modes */
 228                 /* power state array is low to high, default is first (0) */
 229                 if (rdev->pm.active_crtc_count > 1) {
 230                         rdev->pm.requested_power_state_index = -1;
 231                         /* start at 1 as we don't want the default mode */
 232                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 233                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 234                                         continue;
 235                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 236                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 237                                         rdev->pm.requested_power_state_index = i;
 238                                         break;
 239                                 }
 240                         }
 241                         /* if nothing selected, grab the default state. */
 242                         if (rdev->pm.requested_power_state_index == -1)
 243                                 rdev->pm.requested_power_state_index = 0;
 244                 } else
 245                         rdev->pm.requested_power_state_index = 1;
 246
 247                 switch (rdev->pm.dynpm_planned_action) {
 248                 case DYNPM_ACTION_MINIMUM:
 249                         rdev->pm.requested_clock_mode_index = 0;
 250                         rdev->pm.dynpm_can_downclock = false;
 251                         break;
 252                 case DYNPM_ACTION_DOWNCLOCK:
 253                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 254                                 if (rdev->pm.current_clock_mode_index == 0) {
 255                                         rdev->pm.requested_clock_mode_index = 0;
 256                                         rdev->pm.dynpm_can_downclock = false;
 257                                 } else
 258                                         rdev->pm.requested_clock_mode_index =
 259                                                 rdev->pm.current_clock_mode_index - 1;
 260                         } else {
 261                                 rdev->pm.requested_clock_mode_index = 0;
 262                                 rdev->pm.dynpm_can_downclock = false;
 263                         }
 264                         /* don't use the power state if crtcs are active and no display flag is set */
 265                         if ((rdev->pm.active_crtc_count > 0) &&
 266                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 267                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 268                              RADEON_PM_MODE_NO_DISPLAY)) {
 269                                 rdev->pm.requested_clock_mode_index++;
 270                         }
 271                         break;
 272                 case DYNPM_ACTION_UPCLOCK:
 273                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 274                                 if (rdev->pm.current_clock_mode_index ==
 275                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 276                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 277                                         rdev->pm.dynpm_can_upclock = false;
 278                                 } else
 279                                         rdev->pm.requested_clock_mode_index =
 280                                                 rdev->pm.current_clock_mode_index + 1;
 281                         } else {
 282                                 rdev->pm.requested_clock_mode_index =
 283                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 284                                 rdev->pm.dynpm_can_upclock = false;
 285                         }
 286                         break;
 287                 case DYNPM_ACTION_DEFAULT:
 288                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 289                         rdev->pm.requested_clock_mode_index = 0;
 290                         rdev->pm.dynpm_can_upclock = false;
 291                         break;
 292                 case DYNPM_ACTION_NONE:
 293                 default:
 294                         DRM_ERROR("Requested mode for not defined action\n");
 295                         return;
 296                 }
 297         }
 298
 299         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 300                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 301                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 302                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 303                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 304                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 305                   pcie_lanes);
 306 }
 307
 308 void rs780_pm_init_profile(struct radeon_device *rdev)
 309 {
 310         if (rdev->pm.num_power_states == 2) {
 311                 /* default */
 312                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 313                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 314                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 315                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 316                 /* low sh */
 317                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 319                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 320                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 321                 /* mid sh */
 322                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 325                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 326                 /* high sh */
 327                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 328                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 329                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 330                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 331                 /* low mh */
 332                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 333                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 334                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 336                 /* mid mh */
 337                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 338                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 339                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 340                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 341                 /* high mh */
 342                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 343                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 344                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 345                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 346         } else if (rdev->pm.num_power_states == 3) {
 347                 /* default */
 348                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 349                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 350                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 351                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 352                 /* low sh */
 353                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 354                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 355                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 356                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 357                 /* mid sh */
 358                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 359                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 360                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 361                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 362                 /* high sh */
 363                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 364                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 365                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 366                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 367                 /* low mh */
 368                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 369                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 370                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 371                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 372                 /* mid mh */
 373                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 374                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 375                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 376                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 377                 /* high mh */
 378                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 379                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 380                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 381                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 382         } else {
 383                 /* default */
 384                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 385                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 386                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 387                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 388                 /* low sh */
 389                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 390                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 391                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 392                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 393                 /* mid sh */
 394                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 395                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 396                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 397                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 398                 /* high sh */
 399                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 400                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 401                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 402                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 403                 /* low mh */
 404                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 405                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 406                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 407                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 408                 /* mid mh */
 409                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 410                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 411                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 412                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 413                 /* high mh */
 414                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 415                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 416                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 417                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 418         }
 419 }
 420
 421 void r600_pm_init_profile(struct radeon_device *rdev)
 422 {
 423         int idx;
 424
 425         if (rdev->family == CHIP_R600) {
 426                 /* XXX */
 427                 /* default */
 428                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 429                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 430                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 431                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 432                 /* low sh */
 433                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 434                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 435                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 436                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 437                 /* mid sh */
 438                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 439                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 440                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 441                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 442                 /* high sh */
 443                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 444                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 445                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 446                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 447                 /* low mh */
 448                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 449                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 450                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 451                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 452                 /* mid mh */
 453                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 454                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 455                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 456                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 457                 /* high mh */
 458                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 459                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 460                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 461                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 462         } else {
 463                 if (rdev->pm.num_power_states < 4) {
 464                         /* default */
 465                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 466                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 467                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 468                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 469                         /* low sh */
 470                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 471                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 472                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 473                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 474                         /* mid sh */
 475                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 476                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 477                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 478                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 479                         /* high sh */
 480                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 481                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 482                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 483                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 484                         /* low mh */
 485                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 486                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 487                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 488                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 489                         /* low mh */
 490                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 491                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 492                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 493                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 494                         /* high mh */
 495                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 496                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 497                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 498                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 499                 } else {
 500                         /* default */
 501                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 502                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 503                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 504                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 505                         /* low sh */
 506                         if (rdev->flags & RADEON_IS_MOBILITY)
 507                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 508                         else
 509                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 510                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 511                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 512                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 513                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 514                         /* mid sh */
 515                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 516                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 517                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 518                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 519                         /* high sh */
 520                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 521                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 522                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 523                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 524                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 525                         /* low mh */
 526                         if (rdev->flags & RADEON_IS_MOBILITY)
 527                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 528                         else
 529                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 530                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 531                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 532                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 533                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 534                         /* mid mh */
 535                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 536                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 537                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 538                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 539                         /* high mh */
 540                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 541                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 542                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 543                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 544                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 545                 }
 546         }
 547 }
 548
 549 void r600_pm_misc(struct radeon_device *rdev)
 550 {
 551         int req_ps_idx = rdev->pm.requested_power_state_index;
 552         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 553         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 554         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 555
 556         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 557                 /* 0xff01 is a flag rather then an actual voltage */
 558                 if (voltage->voltage == 0xff01)
 559                         return;
 560                 if (voltage->voltage != rdev->pm.current_vddc) {
 561                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 562                         rdev->pm.current_vddc = voltage->voltage;
 563                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 564                 }
 565         }
 566 }
 567
 568 bool r600_gui_idle(struct radeon_device *rdev)
 569 {
 570         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 571                 return false;
 572         else
 573                 return true;
 574 }
 575
 576 /* hpd for digital panel detect/disconnect */
 577 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 578 {
 579         bool connected = false;
 580
 581         if (ASIC_IS_DCE3(rdev)) {
 582                 switch (hpd) {
 583                 case RADEON_HPD_1:
 584                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 585                                 connected = true;
 586                         break;
 587                 case RADEON_HPD_2:
 588                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 589                                 connected = true;
 590                         break;
 591                 case RADEON_HPD_3:
 592                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 593                                 connected = true;
 594                         break;
 595                 case RADEON_HPD_4:
 596                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 597                                 connected = true;
 598                         break;
 599                         /* DCE 3.2 */
 600                 case RADEON_HPD_5:
 601                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 602                                 connected = true;
 603                         break;
 604                 case RADEON_HPD_6:
 605                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 606                                 connected = true;
 607                         break;
 608                 default:
 609                         break;
 610                 }
 611         } else {
 612                 switch (hpd) {
 613                 case RADEON_HPD_1:
 614                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 615                                 connected = true;
 616                         break;
 617                 case RADEON_HPD_2:
 618                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 619                                 connected = true;
 620                         break;
 621                 case RADEON_HPD_3:
 622                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 623                                 connected = true;
 624                         break;
 625                 default:
 626                         break;
 627                 }
 628         }
 629         return connected;
 630 }
 631
 632 void r600_hpd_set_polarity(struct radeon_device *rdev,
 633                            enum radeon_hpd_id hpd)
 634 {
 635         u32 tmp;
 636         bool connected = r600_hpd_sense(rdev, hpd);
 637
 638         if (ASIC_IS_DCE3(rdev)) {
 639                 switch (hpd) {
 640                 case RADEON_HPD_1:
 641                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 642                         if (connected)
 643                                 tmp &= ~DC_HPDx_INT_POLARITY;
 644                         else
 645                                 tmp |= DC_HPDx_INT_POLARITY;
 646                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 647                         break;
 648                 case RADEON_HPD_2:
 649                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 650                         if (connected)
 651                                 tmp &= ~DC_HPDx_INT_POLARITY;
 652                         else
 653                                 tmp |= DC_HPDx_INT_POLARITY;
 654                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 655                         break;
 656                 case RADEON_HPD_3:
 657                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 658                         if (connected)
 659                                 tmp &= ~DC_HPDx_INT_POLARITY;
 660                         else
 661                                 tmp |= DC_HPDx_INT_POLARITY;
 662                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 663                         break;
 664                 case RADEON_HPD_4:
 665                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 666                         if (connected)
 667                                 tmp &= ~DC_HPDx_INT_POLARITY;
 668                         else
 669                                 tmp |= DC_HPDx_INT_POLARITY;
 670                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 671                         break;
 672                 case RADEON_HPD_5:
 673                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 674                         if (connected)
 675                                 tmp &= ~DC_HPDx_INT_POLARITY;
 676                         else
 677                                 tmp |= DC_HPDx_INT_POLARITY;
 678                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 679                         break;
 680                         /* DCE 3.2 */
 681                 case RADEON_HPD_6:
 682                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 683                         if (connected)
 684                                 tmp &= ~DC_HPDx_INT_POLARITY;
 685                         else
 686                                 tmp |= DC_HPDx_INT_POLARITY;
 687                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 688                         break;
 689                 default:
 690                         break;
 691                 }
 692         } else {
 693                 switch (hpd) {
 694                 case RADEON_HPD_1:
 695                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 696                         if (connected)
 697                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 698                         else
 699                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 700                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 701                         break;
 702                 case RADEON_HPD_2:
 703                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 704                         if (connected)
 705                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 706                         else
 707                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 708                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 709                         break;
 710                 case RADEON_HPD_3:
 711                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 712                         if (connected)
 713                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 714                         else
 715                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 716                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 717                         break;
 718                 default:
 719                         break;
 720                 }
 721         }
 722 }
 723
 724 void r600_hpd_init(struct radeon_device *rdev)
 725 {
 726         struct drm_device *dev = rdev->ddev;
 727         struct drm_connector *connector;
 728         unsigned enable = 0;
 729
 730         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 731                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 732
 733                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 734                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 735                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 736                          * aux dp channel on imac and help (but not completely fix)
 737                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 738                          */
 739                         continue;
 740                 }
 741                 if (ASIC_IS_DCE3(rdev)) {
 742                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 743                         if (ASIC_IS_DCE32(rdev))
 744                                 tmp |= DC_HPDx_EN;
 745
 746                         switch (radeon_connector->hpd.hpd) {
 747                         case RADEON_HPD_1:
 748                                 WREG32(DC_HPD1_CONTROL, tmp);
 749                                 break;
 750                         case RADEON_HPD_2:
 751                                 WREG32(DC_HPD2_CONTROL, tmp);
 752                                 break;
 753                         case RADEON_HPD_3:
 754                                 WREG32(DC_HPD3_CONTROL, tmp);
 755                                 break;
 756                         case RADEON_HPD_4:
 757                                 WREG32(DC_HPD4_CONTROL, tmp);
 758                                 break;
 759                                 /* DCE 3.2 */
 760                         case RADEON_HPD_5:
 761                                 WREG32(DC_HPD5_CONTROL, tmp);
 762                                 break;
 763                         case RADEON_HPD_6:
 764                                 WREG32(DC_HPD6_CONTROL, tmp);
 765                                 break;
 766                         default:
 767                                 break;
 768                         }
 769                 } else {
 770                         switch (radeon_connector->hpd.hpd) {
 771                         case RADEON_HPD_1:
 772                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 773                                 break;
 774                         case RADEON_HPD_2:
 775                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 776                                 break;
 777                         case RADEON_HPD_3:
 778                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 779                                 break;
 780                         default:
 781                                 break;
 782                         }
 783                 }
 784                 enable |= 1 << radeon_connector->hpd.hpd;
 785                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 786         }
 787         radeon_irq_kms_enable_hpd(rdev, enable);
 788 }
 789
 790 void r600_hpd_fini(struct radeon_device *rdev)
 791 {
 792         struct drm_device *dev = rdev->ddev;
 793         struct drm_connector *connector;
 794         unsigned disable = 0;
 795
 796         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 797                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 798                 if (ASIC_IS_DCE3(rdev)) {
 799                         switch (radeon_connector->hpd.hpd) {
 800                         case RADEON_HPD_1:
 801                                 WREG32(DC_HPD1_CONTROL, 0);
 802                                 break;
 803                         case RADEON_HPD_2:
 804                                 WREG32(DC_HPD2_CONTROL, 0);
 805                                 break;
 806                         case RADEON_HPD_3:
 807                                 WREG32(DC_HPD3_CONTROL, 0);
 808                                 break;
 809                         case RADEON_HPD_4:
 810                                 WREG32(DC_HPD4_CONTROL, 0);
 811                                 break;
 812                                 /* DCE 3.2 */
 813                         case RADEON_HPD_5:
 814                                 WREG32(DC_HPD5_CONTROL, 0);
 815                                 break;
 816                         case RADEON_HPD_6:
 817                                 WREG32(DC_HPD6_CONTROL, 0);
 818                                 break;
 819                         default:
 820                                 break;
 821                         }
 822                 } else {
 823                         switch (radeon_connector->hpd.hpd) {
 824                         case RADEON_HPD_1:
 825                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 826                                 break;
 827                         case RADEON_HPD_2:
 828                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 829                                 break;
 830                         case RADEON_HPD_3:
 831                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 832                                 break;
 833                         default:
 834                                 break;
 835                         }
 836                 }
 837                 disable |= 1 << radeon_connector->hpd.hpd;
 838         }
 839         radeon_irq_kms_disable_hpd(rdev, disable);
 840 }
 841
 842 /*
 843  * R600 PCIE GART
 844  */
 845 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 846 {
 847         unsigned i;
 848         u32 tmp;
 849
 850         /* flush hdp cache so updates hit vram */
 851         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 852             !(rdev->flags & RADEON_IS_AGP)) {
 853                 void __iomem *ptr = (void *)rdev->gart.ptr;
 854                 u32 tmp;
 855
 856                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 857                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 858                  * This seems to cause problems on some AGP cards. Just use the old
 859                  * method for them.
 860                  */
 861                 WREG32(HDP_DEBUG1, 0);
 862                 tmp = readl((void __iomem *)ptr);
 863         } else
 864                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 865
 866         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 867         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 868         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 869         for (i = 0; i < rdev->usec_timeout; i++) {
 870                 /* read MC_STATUS */
 871                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 872                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 873                 if (tmp == 2) {
 874                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 875                         return;
 876                 }
 877                 if (tmp) {
 878                         return;
 879                 }
 880                 udelay(1);
 881         }
 882 }
 883
 884 int r600_pcie_gart_init(struct radeon_device *rdev)
 885 {
 886         int r;
 887
 888         if (rdev->gart.robj) {
 889                 WARN(1, "R600 PCIE GART already initialized\n");
 890                 return 0;
 891         }
 892         /* Initialize common gart structure */
 893         r = radeon_gart_init(rdev);
 894         if (r)
 895                 return r;
 896         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 897         return radeon_gart_table_vram_alloc(rdev);
 898 }
 899
 900 static int r600_pcie_gart_enable(struct radeon_device *rdev)
 901 {
 902         u32 tmp;
 903         int r, i;
 904
 905         if (rdev->gart.robj == NULL) {
 906                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 907                 return -EINVAL;
 908         }
 909         r = radeon_gart_table_vram_pin(rdev);
 910         if (r)
 911                 return r;
 912         radeon_gart_restore(rdev);
 913
 914         /* Setup L2 cache */
 915         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 916                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 917                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 918         WREG32(VM_L2_CNTL2, 0);
 919         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 920         /* Setup TLB control */
 921         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 922                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 923                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 924                 ENABLE_WAIT_L2_QUERY;
 925         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 926         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 927         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 928         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 929         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 930         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 931         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 932         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 933         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 934         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 935         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 936         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 937         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 938         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 939         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 940         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 941         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 942         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 943                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 944         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 945                         (u32)(rdev->dummy_page.addr >> 12));
 946         for (i = 1; i < 7; i++)
 947                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 948
 949         r600_pcie_gart_tlb_flush(rdev);
 950         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 951                  (unsigned)(rdev->mc.gtt_size >> 20),
 952                  (unsigned long long)rdev->gart.table_addr);
 953         rdev->gart.ready = true;
 954         return 0;
 955 }
 956
 957 static void r600_pcie_gart_disable(struct radeon_device *rdev)
 958 {
 959         u32 tmp;
 960         int i;
 961
 962         /* Disable all tables */
 963         for (i = 0; i < 7; i++)
 964                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 965
 966         /* Disable L2 cache */
 967         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 968                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 969         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 970         /* Setup L1 TLB control */
 971         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 972                 ENABLE_WAIT_L2_QUERY;
 973         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 974         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 975         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 976         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 977         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 978         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 979         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 980         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 981         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 982         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 983         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 984         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 985         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 986         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 987         radeon_gart_table_vram_unpin(rdev);
 988 }
 989
 990 static void r600_pcie_gart_fini(struct radeon_device *rdev)
 991 {
 992         radeon_gart_fini(rdev);
 993         r600_pcie_gart_disable(rdev);
 994         radeon_gart_table_vram_free(rdev);
 995 }
 996
 997 static void r600_agp_enable(struct radeon_device *rdev)
 998 {
 999         u32 tmp;
1000         int i;
1001
1002         /* Setup L2 cache */
1003         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1004                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1005                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1006         WREG32(VM_L2_CNTL2, 0);
1007         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1008         /* Setup TLB control */
1009         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1010                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1011                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1012                 ENABLE_WAIT_L2_QUERY;
1013         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1014         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1015         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1016         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1017         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1018         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1019         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1020         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1021         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1022         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1023         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1024         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1025         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1026         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1027         for (i = 0; i < 7; i++)
1028                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1029 }
1030
1031 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1032 {
1033         unsigned i;
1034         u32 tmp;
1035
1036         for (i = 0; i < rdev->usec_timeout; i++) {
1037                 /* read MC_STATUS */
1038                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1039                 if (!tmp)
1040                         return 0;
1041                 udelay(1);
1042         }
1043         return -1;
1044 }
1045
1046 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1047 {
1048         uint32_t r;
1049
1050         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1051         r = RREG32(R_0028FC_MC_DATA);
1052         WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1053         return r;
1054 }
1055
1056 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1057 {
1058         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1059                 S_0028F8_MC_IND_WR_EN(1));
1060         WREG32(R_0028FC_MC_DATA, v);
1061         WREG32(R_0028F8_MC_INDEX, 0x7F);
1062 }
1063
1064 static void r600_mc_program(struct radeon_device *rdev)
1065 {
1066         struct rv515_mc_save save;
1067         u32 tmp;
1068         int i, j;
1069
1070         /* Initialize HDP */
1071         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1072                 WREG32((0x2c14 + j), 0x00000000);
1073                 WREG32((0x2c18 + j), 0x00000000);
1074                 WREG32((0x2c1c + j), 0x00000000);
1075                 WREG32((0x2c20 + j), 0x00000000);
1076                 WREG32((0x2c24 + j), 0x00000000);
1077         }
1078         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1079
1080         rv515_mc_stop(rdev, &save);
1081         if (r600_mc_wait_for_idle(rdev)) {
1082                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1083         }
1084         /* Lockout access through VGA aperture (doesn't exist before R600) */
1085         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1086         /* Update configuration */
1087         if (rdev->flags & RADEON_IS_AGP) {
1088                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1089                         /* VRAM before AGP */
1090                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1091                                 rdev->mc.vram_start >> 12);
1092                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1093                                 rdev->mc.gtt_end >> 12);
1094                 } else {
1095                         /* VRAM after AGP */
1096                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1097                                 rdev->mc.gtt_start >> 12);
1098                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1099                                 rdev->mc.vram_end >> 12);
1100                 }
1101         } else {
1102                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1103                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1104         }
1105         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1106         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1107         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1108         WREG32(MC_VM_FB_LOCATION, tmp);
1109         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1110         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1111         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1112         if (rdev->flags & RADEON_IS_AGP) {
1113                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1114                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1115                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1116         } else {
1117                 WREG32(MC_VM_AGP_BASE, 0);
1118                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1119                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1120         }
1121         if (r600_mc_wait_for_idle(rdev)) {
1122                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1123         }
1124         rv515_mc_resume(rdev, &save);
1125         /* we need to own VRAM, so turn off the VGA renderer here
1126          * to stop it overwriting our objects */
1127         rv515_vga_render_disable(rdev);
1128 }
1129
1130 /**
1131  * r600_vram_gtt_location - try to find VRAM & GTT location
1132  * @rdev: radeon device structure holding all necessary informations
1133  * @mc: memory controller structure holding memory informations
1134  *
1135  * Function will place try to place VRAM at same place as in CPU (PCI)
1136  * address space as some GPU seems to have issue when we reprogram at
1137  * different address space.
1138  *
1139  * If there is not enough space to fit the unvisible VRAM after the
1140  * aperture then we limit the VRAM size to the aperture.
1141  *
1142  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1143  * them to be in one from GPU point of view so that we can program GPU to
1144  * catch access outside them (weird GPU policy see ??).
1145  *
1146  * This function will never fails, worst case are limiting VRAM or GTT.
1147  *
1148  * Note: GTT start, end, size should be initialized before calling this
1149  * function on AGP platform.
1150  */
1151 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1152 {
1153         u64 size_bf, size_af;
1154
1155         if (mc->mc_vram_size > 0xE0000000) {
1156                 /* leave room for at least 512M GTT */
1157                 dev_warn(rdev->dev, "limiting VRAM\n");
1158                 mc->real_vram_size = 0xE0000000;
1159                 mc->mc_vram_size = 0xE0000000;
1160         }
1161         if (rdev->flags & RADEON_IS_AGP) {
1162                 size_bf = mc->gtt_start;
1163                 size_af = mc->mc_mask - mc->gtt_end;
1164                 if (size_bf > size_af) {
1165                         if (mc->mc_vram_size > size_bf) {
1166                                 dev_warn(rdev->dev, "limiting VRAM\n");
1167                                 mc->real_vram_size = size_bf;
1168                                 mc->mc_vram_size = size_bf;
1169                         }
1170                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1171                 } else {
1172                         if (mc->mc_vram_size > size_af) {
1173                                 dev_warn(rdev->dev, "limiting VRAM\n");
1174                                 mc->real_vram_size = size_af;
1175                                 mc->mc_vram_size = size_af;
1176                         }
1177                         mc->vram_start = mc->gtt_end + 1;
1178                 }
1179                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1180                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1181                                 mc->mc_vram_size >> 20, mc->vram_start,
1182                                 mc->vram_end, mc->real_vram_size >> 20);
1183         } else {
1184                 u64 base = 0;
1185                 if (rdev->flags & RADEON_IS_IGP) {
1186                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1187                         base <<= 24;
1188                 }
1189                 radeon_vram_location(rdev, &rdev->mc, base);
1190                 rdev->mc.gtt_base_align = 0;
1191                 radeon_gtt_location(rdev, mc);
1192         }
1193 }
1194
1195 static int r600_mc_init(struct radeon_device *rdev)
1196 {
1197         u32 tmp;
1198         int chansize, numchan;
1199         uint32_t h_addr, l_addr;
1200         unsigned long long k8_addr;
1201
1202         /* Get VRAM informations */
1203         rdev->mc.vram_is_ddr = true;
1204         tmp = RREG32(RAMCFG);
1205         if (tmp & CHANSIZE_OVERRIDE) {
1206                 chansize = 16;
1207         } else if (tmp & CHANSIZE_MASK) {
1208                 chansize = 64;
1209         } else {
1210                 chansize = 32;
1211         }
1212         tmp = RREG32(CHMAP);
1213         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1214         case 0:
1215         default:
1216                 numchan = 1;
1217                 break;
1218         case 1:
1219                 numchan = 2;
1220                 break;
1221         case 2:
1222                 numchan = 4;
1223                 break;
1224         case 3:
1225                 numchan = 8;
1226                 break;
1227         }
1228         rdev->mc.vram_width = numchan * chansize;
1229         /* Could aper size report 0 ? */
1230         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1231         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1232         /* Setup GPU memory space */
1233         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1234         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1235         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1236         r600_vram_gtt_location(rdev, &rdev->mc);
1237
1238         if (rdev->flags & RADEON_IS_IGP) {
1239                 rs690_pm_info(rdev);
1240                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1241
1242                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1243                         /* Use K8 direct mapping for fast fb access. */
1244                         rdev->fastfb_working = false;
1245                         h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1246                         l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1247                         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1248 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1249                         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1250 #endif
1251                         {
1252                                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1253                                 * memory is present.
1254                                 */
1255                                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1256                                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1257                                                 (unsigned long long)rdev->mc.aper_base, k8_addr);
1258                                         rdev->mc.aper_base = (resource_size_t)k8_addr;
1259                                         rdev->fastfb_working = true;
1260                                 }
1261                         }
1262                 }
1263         }
1264
1265         radeon_update_bandwidth_info(rdev);
1266         return 0;
1267 }
1268
1269 int r600_vram_scratch_init(struct radeon_device *rdev)
1270 {
1271         int r;
1272
1273         if (rdev->vram_scratch.robj == NULL) {
1274                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1275                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1276                                      NULL, &rdev->vram_scratch.robj);
1277                 if (r) {
1278                         return r;
1279                 }
1280         }
1281
1282         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1283         if (unlikely(r != 0))
1284                 return r;
1285         r = radeon_bo_pin(rdev->vram_scratch.robj,
1286                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1287         if (r) {
1288                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1289                 return r;
1290         }
1291         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1292                                 (void **)&rdev->vram_scratch.ptr);
1293         if (r)
1294                 radeon_bo_unpin(rdev->vram_scratch.robj);
1295         radeon_bo_unreserve(rdev->vram_scratch.robj);
1296
1297         return r;
1298 }
1299
1300 void r600_vram_scratch_fini(struct radeon_device *rdev)
1301 {
1302         int r;
1303
1304         if (rdev->vram_scratch.robj == NULL) {
1305                 return;
1306         }
1307         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1308         if (likely(r == 0)) {
1309                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1310                 radeon_bo_unpin(rdev->vram_scratch.robj);
1311                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1312         }
1313         radeon_bo_unref(&rdev->vram_scratch.robj);
1314 }
1315
1316 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1317 {
1318         u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1319
1320         if (hung)
1321                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1322         else
1323                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1324
1325         WREG32(R600_BIOS_3_SCRATCH, tmp);
1326 }
1327
1328 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1329 {
1330         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1331                  RREG32(R_008010_GRBM_STATUS));
1332         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1333                  RREG32(R_008014_GRBM_STATUS2));
1334         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1335                  RREG32(R_000E50_SRBM_STATUS));
1336         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1337                  RREG32(CP_STALLED_STAT1));
1338         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1339                  RREG32(CP_STALLED_STAT2));
1340         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1341                  RREG32(CP_BUSY_STAT));
1342         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1343                  RREG32(CP_STAT));
1344         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1345                 RREG32(DMA_STATUS_REG));
1346 }
1347
1348 static bool r600_is_display_hung(struct radeon_device *rdev)
1349 {
1350         u32 crtc_hung = 0;
1351         u32 crtc_status[2];
1352         u32 i, j, tmp;
1353
1354         for (i = 0; i < rdev->num_crtc; i++) {
1355                 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1356                         crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1357                         crtc_hung |= (1 << i);
1358                 }
1359         }
1360
1361         for (j = 0; j < 10; j++) {
1362                 for (i = 0; i < rdev->num_crtc; i++) {
1363                         if (crtc_hung & (1 << i)) {
1364                                 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1365                                 if (tmp != crtc_status[i])
1366                                         crtc_hung &= ~(1 << i);
1367                         }
1368                 }
1369                 if (crtc_hung == 0)
1370                         return false;
1371                 udelay(100);
1372         }
1373
1374         return true;
1375 }
1376
1377 static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1378 {
1379         u32 reset_mask = 0;
1380         u32 tmp;
1381
1382         /* GRBM_STATUS */
1383         tmp = RREG32(R_008010_GRBM_STATUS);
1384         if (rdev->family >= CHIP_RV770) {
1385                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1386                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1387                     G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1388                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1389                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1390                         reset_mask |= RADEON_RESET_GFX;
1391         } else {
1392                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1393                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1394                     G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1395                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1396                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1397                         reset_mask |= RADEON_RESET_GFX;
1398         }
1399
1400         if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1401             G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1402                 reset_mask |= RADEON_RESET_CP;
1403
1404         if (G_008010_GRBM_EE_BUSY(tmp))
1405                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1406
1407         /* DMA_STATUS_REG */
1408         tmp = RREG32(DMA_STATUS_REG);
1409         if (!(tmp & DMA_IDLE))
1410                 reset_mask |= RADEON_RESET_DMA;
1411
1412         /* SRBM_STATUS */
1413         tmp = RREG32(R_000E50_SRBM_STATUS);
1414         if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1415                 reset_mask |= RADEON_RESET_RLC;
1416
1417         if (G_000E50_IH_BUSY(tmp))
1418                 reset_mask |= RADEON_RESET_IH;
1419
1420         if (G_000E50_SEM_BUSY(tmp))
1421                 reset_mask |= RADEON_RESET_SEM;
1422
1423         if (G_000E50_GRBM_RQ_PENDING(tmp))
1424                 reset_mask |= RADEON_RESET_GRBM;
1425
1426         if (G_000E50_VMC_BUSY(tmp))
1427                 reset_mask |= RADEON_RESET_VMC;
1428
1429         if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1430             G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1431             G_000E50_MCDW_BUSY(tmp))
1432                 reset_mask |= RADEON_RESET_MC;
1433
1434         if (r600_is_display_hung(rdev))
1435                 reset_mask |= RADEON_RESET_DISPLAY;
1436
1437         /* Skip MC reset as it's mostly likely not hung, just busy */
1438         if (reset_mask & RADEON_RESET_MC) {
1439                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1440                 reset_mask &= ~RADEON_RESET_MC;
1441         }
1442
1443         return reset_mask;
1444 }
1445
1446 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1447 {
1448         struct rv515_mc_save save;
1449         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1450         u32 tmp;
1451
1452         if (reset_mask == 0)
1453                 return;
1454
1455         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1456
1457         r600_print_gpu_status_regs(rdev);
1458
1459         /* Disable CP parsing/prefetching */
1460         if (rdev->family >= CHIP_RV770)
1461                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1462         else
1463                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1464
1465         /* disable the RLC */
1466         WREG32(RLC_CNTL, 0);
1467
1468         if (reset_mask & RADEON_RESET_DMA) {
1469                 /* Disable DMA */
1470                 tmp = RREG32(DMA_RB_CNTL);
1471                 tmp &= ~DMA_RB_ENABLE;
1472                 WREG32(DMA_RB_CNTL, tmp);
1473         }
1474
1475         mdelay(50);
1476
1477         rv515_mc_stop(rdev, &save);
1478         if (r600_mc_wait_for_idle(rdev)) {
1479                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1480         }
1481
1482         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1483                 if (rdev->family >= CHIP_RV770)
1484                         grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1485                                 S_008020_SOFT_RESET_CB(1) |
1486                                 S_008020_SOFT_RESET_PA(1) |
1487                                 S_008020_SOFT_RESET_SC(1) |
1488                                 S_008020_SOFT_RESET_SPI(1) |
1489                                 S_008020_SOFT_RESET_SX(1) |
1490                                 S_008020_SOFT_RESET_SH(1) |
1491                                 S_008020_SOFT_RESET_TC(1) |
1492                                 S_008020_SOFT_RESET_TA(1) |
1493                                 S_008020_SOFT_RESET_VC(1) |
1494                                 S_008020_SOFT_RESET_VGT(1);
1495                 else
1496                         grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1497                                 S_008020_SOFT_RESET_DB(1) |
1498                                 S_008020_SOFT_RESET_CB(1) |
1499                                 S_008020_SOFT_RESET_PA(1) |
1500                                 S_008020_SOFT_RESET_SC(1) |
1501                                 S_008020_SOFT_RESET_SMX(1) |
1502                                 S_008020_SOFT_RESET_SPI(1) |
1503                                 S_008020_SOFT_RESET_SX(1) |
1504                                 S_008020_SOFT_RESET_SH(1) |
1505                                 S_008020_SOFT_RESET_TC(1) |
1506                                 S_008020_SOFT_RESET_TA(1) |
1507                                 S_008020_SOFT_RESET_VC(1) |
1508                                 S_008020_SOFT_RESET_VGT(1);
1509         }
1510
1511         if (reset_mask & RADEON_RESET_CP) {
1512                 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1513                         S_008020_SOFT_RESET_VGT(1);
1514
1515                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1516         }
1517
1518         if (reset_mask & RADEON_RESET_DMA) {
1519                 if (rdev->family >= CHIP_RV770)
1520                         srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1521                 else
1522                         srbm_soft_reset |= SOFT_RESET_DMA;
1523         }
1524
1525         if (reset_mask & RADEON_RESET_RLC)
1526                 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1527
1528         if (reset_mask & RADEON_RESET_SEM)
1529                 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1530
1531         if (reset_mask & RADEON_RESET_IH)
1532                 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1533
1534         if (reset_mask & RADEON_RESET_GRBM)
1535                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1536
1537         if (!(rdev->flags & RADEON_IS_IGP)) {
1538                 if (reset_mask & RADEON_RESET_MC)
1539                         srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1540         }
1541
1542         if (reset_mask & RADEON_RESET_VMC)
1543                 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1544
1545         if (grbm_soft_reset) {
1546                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1547                 tmp |= grbm_soft_reset;
1548                 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1549                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1550                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1551
1552                 udelay(50);
1553
1554                 tmp &= ~grbm_soft_reset;
1555                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1556                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1557         }
1558
1559         if (srbm_soft_reset) {
1560                 tmp = RREG32(SRBM_SOFT_RESET);
1561                 tmp |= srbm_soft_reset;
1562                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1563                 WREG32(SRBM_SOFT_RESET, tmp);
1564                 tmp = RREG32(SRBM_SOFT_RESET);
1565
1566                 udelay(50);
1567
1568                 tmp &= ~srbm_soft_reset;
1569                 WREG32(SRBM_SOFT_RESET, tmp);
1570                 tmp = RREG32(SRBM_SOFT_RESET);
1571         }
1572
1573         /* Wait a little for things to settle down */
1574         mdelay(1);
1575
1576         rv515_mc_resume(rdev, &save);
1577         udelay(50);
1578
1579         r600_print_gpu_status_regs(rdev);
1580 }
1581
1582 int r600_asic_reset(struct radeon_device *rdev)
1583 {
1584         u32 reset_mask;
1585
1586         reset_mask = r600_gpu_check_soft_reset(rdev);
1587
1588         if (reset_mask)
1589                 r600_set_bios_scratch_engine_hung(rdev, true);
1590
1591         r600_gpu_soft_reset(rdev, reset_mask);
1592
1593         reset_mask = r600_gpu_check_soft_reset(rdev);
1594
1595         if (!reset_mask)
1596                 r600_set_bios_scratch_engine_hung(rdev, false);
1597
1598         return 0;
1599 }
1600
1601 /**
1602  * r600_gfx_is_lockup - Check if the GFX engine is locked up
1603  *
1604  * @rdev: radeon_device pointer
1605  * @ring: radeon_ring structure holding ring information
1606  *
1607  * Check if the GFX engine is locked up.
1608  * Returns true if the engine appears to be locked up, false if not.
1609  */
1610 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1611 {
1612         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1613
1614         if (!(reset_mask & (RADEON_RESET_GFX |
1615                             RADEON_RESET_COMPUTE |
1616                             RADEON_RESET_CP))) {
1617                 radeon_ring_lockup_update(ring);
1618                 return false;
1619         }
1620         /* force CP activities */
1621         radeon_ring_force_activity(rdev, ring);
1622         return radeon_ring_test_lockup(rdev, ring);
1623 }
1624
1625 /**
1626  * r600_dma_is_lockup - Check if the DMA engine is locked up
1627  *
1628  * @rdev: radeon_device pointer
1629  * @ring: radeon_ring structure holding ring information
1630  *
1631  * Check if the async DMA engine is locked up.
1632  * Returns true if the engine appears to be locked up, false if not.
1633  */
1634 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1635 {
1636         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1637
1638         if (!(reset_mask & RADEON_RESET_DMA)) {
1639                 radeon_ring_lockup_update(ring);
1640                 return false;
1641         }
1642         /* force ring activities */
1643         radeon_ring_force_activity(rdev, ring);
1644         return radeon_ring_test_lockup(rdev, ring);
1645 }
1646
1647 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1648                               u32 tiling_pipe_num,
1649                               u32 max_rb_num,
1650                               u32 total_max_rb_num,
1651                               u32 disabled_rb_mask)
1652 {
1653         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1654         u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1655         u32 data = 0, mask = 1 << (max_rb_num - 1);
1656         unsigned i, j;
1657
1658         /* mask out the RBs that don't exist on that asic */
1659         tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1660         /* make sure at least one RB is available */
1661         if ((tmp & 0xff) != 0xff)
1662                 disabled_rb_mask = tmp;
1663
1664         rendering_pipe_num = 1 << tiling_pipe_num;
1665         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1666         BUG_ON(rendering_pipe_num < req_rb_num);
1667
1668         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1669         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1670
1671         if (rdev->family <= CHIP_RV740) {
1672                 /* r6xx/r7xx */
1673                 rb_num_width = 2;
1674         } else {
1675                 /* eg+ */
1676                 rb_num_width = 4;
1677         }
1678
1679         for (i = 0; i < max_rb_num; i++) {
1680                 if (!(mask & disabled_rb_mask)) {
1681                         for (j = 0; j < pipe_rb_ratio; j++) {
1682                                 data <<= rb_num_width;
1683                                 data |= max_rb_num - i - 1;
1684                         }
1685                         if (pipe_rb_remain) {
1686                                 data <<= rb_num_width;
1687                                 data |= max_rb_num - i - 1;
1688                                 pipe_rb_remain--;
1689                         }
1690                 }
1691                 mask >>= 1;
1692         }
1693
1694         return data;
1695 }
1696
1697 int r600_count_pipe_bits(uint32_t val)
1698 {
1699         return hweight32(val);
1700 }
1701
1702 static void r600_gpu_init(struct radeon_device *rdev)
1703 {
1704         u32 tiling_config;
1705         u32 ramcfg;
1706         u32 cc_rb_backend_disable;
1707         u32 cc_gc_shader_pipe_config;
1708         u32 tmp;
1709         int i, j;
1710         u32 sq_config;
1711         u32 sq_gpr_resource_mgmt_1 = 0;
1712         u32 sq_gpr_resource_mgmt_2 = 0;
1713         u32 sq_thread_resource_mgmt = 0;
1714         u32 sq_stack_resource_mgmt_1 = 0;
1715         u32 sq_stack_resource_mgmt_2 = 0;
1716         u32 disabled_rb_mask;
1717
1718         rdev->config.r600.tiling_group_size = 256;
1719         switch (rdev->family) {
1720         case CHIP_R600:
1721                 rdev->config.r600.max_pipes = 4;
1722                 rdev->config.r600.max_tile_pipes = 8;
1723                 rdev->config.r600.max_simds = 4;
1724                 rdev->config.r600.max_backends = 4;
1725                 rdev->config.r600.max_gprs = 256;
1726                 rdev->config.r600.max_threads = 192;
1727                 rdev->config.r600.max_stack_entries = 256;
1728                 rdev->config.r600.max_hw_contexts = 8;
1729                 rdev->config.r600.max_gs_threads = 16;
1730                 rdev->config.r600.sx_max_export_size = 128;
1731                 rdev->config.r600.sx_max_export_pos_size = 16;
1732                 rdev->config.r600.sx_max_export_smx_size = 128;
1733                 rdev->config.r600.sq_num_cf_insts = 2;
1734                 break;
1735         case CHIP_RV630:
1736         case CHIP_RV635:
1737                 rdev->config.r600.max_pipes = 2;
1738                 rdev->config.r600.max_tile_pipes = 2;
1739                 rdev->config.r600.max_simds = 3;
1740                 rdev->config.r600.max_backends = 1;
1741                 rdev->config.r600.max_gprs = 128;
1742                 rdev->config.r600.max_threads = 192;
1743                 rdev->config.r600.max_stack_entries = 128;
1744                 rdev->config.r600.max_hw_contexts = 8;
1745                 rdev->config.r600.max_gs_threads = 4;
1746                 rdev->config.r600.sx_max_export_size = 128;
1747                 rdev->config.r600.sx_max_export_pos_size = 16;
1748                 rdev->config.r600.sx_max_export_smx_size = 128;
1749                 rdev->config.r600.sq_num_cf_insts = 2;
1750                 break;
1751         case CHIP_RV610:
1752         case CHIP_RV620:
1753         case CHIP_RS780:
1754         case CHIP_RS880:
1755                 rdev->config.r600.max_pipes = 1;
1756                 rdev->config.r600.max_tile_pipes = 1;
1757                 rdev->config.r600.max_simds = 2;
1758                 rdev->config.r600.max_backends = 1;
1759                 rdev->config.r600.max_gprs = 128;
1760                 rdev->config.r600.max_threads = 192;
1761                 rdev->config.r600.max_stack_entries = 128;
1762                 rdev->config.r600.max_hw_contexts = 4;
1763                 rdev->config.r600.max_gs_threads = 4;
1764                 rdev->config.r600.sx_max_export_size = 128;
1765                 rdev->config.r600.sx_max_export_pos_size = 16;
1766                 rdev->config.r600.sx_max_export_smx_size = 128;
1767                 rdev->config.r600.sq_num_cf_insts = 1;
1768                 break;
1769         case CHIP_RV670:
1770                 rdev->config.r600.max_pipes = 4;
1771                 rdev->config.r600.max_tile_pipes = 4;
1772                 rdev->config.r600.max_simds = 4;
1773                 rdev->config.r600.max_backends = 4;
1774                 rdev->config.r600.max_gprs = 192;
1775                 rdev->config.r600.max_threads = 192;
1776                 rdev->config.r600.max_stack_entries = 256;
1777                 rdev->config.r600.max_hw_contexts = 8;
1778                 rdev->config.r600.max_gs_threads = 16;
1779                 rdev->config.r600.sx_max_export_size = 128;
1780                 rdev->config.r600.sx_max_export_pos_size = 16;
1781                 rdev->config.r600.sx_max_export_smx_size = 128;
1782                 rdev->config.r600.sq_num_cf_insts = 2;
1783                 break;
1784         default:
1785                 break;
1786         }
1787
1788         /* Initialize HDP */
1789         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1790                 WREG32((0x2c14 + j), 0x00000000);
1791                 WREG32((0x2c18 + j), 0x00000000);
1792                 WREG32((0x2c1c + j), 0x00000000);
1793                 WREG32((0x2c20 + j), 0x00000000);
1794                 WREG32((0x2c24 + j), 0x00000000);
1795         }
1796
1797         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1798
1799         /* Setup tiling */
1800         tiling_config = 0;
1801         ramcfg = RREG32(RAMCFG);
1802         switch (rdev->config.r600.max_tile_pipes) {
1803         case 1:
1804                 tiling_config |= PIPE_TILING(0);
1805                 break;
1806         case 2:
1807                 tiling_config |= PIPE_TILING(1);
1808                 break;
1809         case 4:
1810                 tiling_config |= PIPE_TILING(2);
1811                 break;
1812         case 8:
1813                 tiling_config |= PIPE_TILING(3);
1814                 break;
1815         default:
1816                 break;
1817         }
1818         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1819         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1820         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1821         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1822
1823         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1824         if (tmp > 3) {
1825                 tiling_config |= ROW_TILING(3);
1826                 tiling_config |= SAMPLE_SPLIT(3);
1827         } else {
1828                 tiling_config |= ROW_TILING(tmp);
1829                 tiling_config |= SAMPLE_SPLIT(tmp);
1830         }
1831         tiling_config |= BANK_SWAPS(1);
1832
1833         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1834         tmp = R6XX_MAX_BACKENDS -
1835                 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1836         if (tmp < rdev->config.r600.max_backends) {
1837                 rdev->config.r600.max_backends = tmp;
1838         }
1839
1840         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1841         tmp = R6XX_MAX_PIPES -
1842                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1843         if (tmp < rdev->config.r600.max_pipes) {
1844                 rdev->config.r600.max_pipes = tmp;
1845         }
1846         tmp = R6XX_MAX_SIMDS -
1847                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1848         if (tmp < rdev->config.r600.max_simds) {
1849                 rdev->config.r600.max_simds = tmp;
1850         }
1851
1852         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1853         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1854         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1855                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
1856         tiling_config |= tmp << 16;
1857         rdev->config.r600.backend_map = tmp;
1858
1859         rdev->config.r600.tile_config = tiling_config;
1860         WREG32(GB_TILING_CONFIG, tiling_config);
1861         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1862         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1863         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1864
1865         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1866         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1867         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1868
1869         /* Setup some CP states */
1870         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1871         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1872
1873         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1874                              SYNC_WALKER | SYNC_ALIGNER));
1875         /* Setup various GPU states */
1876         if (rdev->family == CHIP_RV670)
1877                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1878
1879         tmp = RREG32(SX_DEBUG_1);
1880         tmp |= SMX_EVENT_RELEASE;
1881         if ((rdev->family > CHIP_R600))
1882                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1883         WREG32(SX_DEBUG_1, tmp);
1884
1885         if (((rdev->family) == CHIP_R600) ||
1886             ((rdev->family) == CHIP_RV630) ||
1887             ((rdev->family) == CHIP_RV610) ||
1888             ((rdev->family) == CHIP_RV620) ||
1889             ((rdev->family) == CHIP_RS780) ||
1890             ((rdev->family) == CHIP_RS880)) {
1891                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1892         } else {
1893                 WREG32(DB_DEBUG, 0);
1894         }
1895         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1896                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1897
1898         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1899         WREG32(VGT_NUM_INSTANCES, 0);
1900
1901         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1902         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1903
1904         tmp = RREG32(SQ_MS_FIFO_SIZES);
1905         if (((rdev->family) == CHIP_RV610) ||
1906             ((rdev->family) == CHIP_RV620) ||
1907             ((rdev->family) == CHIP_RS780) ||
1908             ((rdev->family) == CHIP_RS880)) {
1909                 tmp = (CACHE_FIFO_SIZE(0xa) |
1910                        FETCH_FIFO_HIWATER(0xa) |
1911                        DONE_FIFO_HIWATER(0xe0) |
1912                        ALU_UPDATE_FIFO_HIWATER(0x8));
1913         } else if (((rdev->family) == CHIP_R600) ||
1914                    ((rdev->family) == CHIP_RV630)) {
1915                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1916                 tmp |= DONE_FIFO_HIWATER(0x4);
1917         }
1918         WREG32(SQ_MS_FIFO_SIZES, tmp);
1919
1920         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1921          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1922          */
1923         sq_config = RREG32(SQ_CONFIG);
1924         sq_config &= ~(PS_PRIO(3) |
1925                        VS_PRIO(3) |
1926                        GS_PRIO(3) |
1927                        ES_PRIO(3));
1928         sq_config |= (DX9_CONSTS |
1929                       VC_ENABLE |
1930                       PS_PRIO(0) |
1931                       VS_PRIO(1) |
1932                       GS_PRIO(2) |
1933                       ES_PRIO(3));
1934
1935         if ((rdev->family) == CHIP_R600) {
1936                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1937                                           NUM_VS_GPRS(124) |
1938                                           NUM_CLAUSE_TEMP_GPRS(4));
1939                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1940                                           NUM_ES_GPRS(0));
1941                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1942                                            NUM_VS_THREADS(48) |
1943                                            NUM_GS_THREADS(4) |
1944                                            NUM_ES_THREADS(4));
1945                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1946                                             NUM_VS_STACK_ENTRIES(128));
1947                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1948                                             NUM_ES_STACK_ENTRIES(0));
1949         } else if (((rdev->family) == CHIP_RV610) ||
1950                    ((rdev->family) == CHIP_RV620) ||
1951                    ((rdev->family) == CHIP_RS780) ||
1952                    ((rdev->family) == CHIP_RS880)) {
1953                 /* no vertex cache */
1954                 sq_config &= ~VC_ENABLE;
1955
1956                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1957                                           NUM_VS_GPRS(44) |
1958                                           NUM_CLAUSE_TEMP_GPRS(2));
1959                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1960                                           NUM_ES_GPRS(17));
1961                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1962                                            NUM_VS_THREADS(78) |
1963                                            NUM_GS_THREADS(4) |
1964                                            NUM_ES_THREADS(31));
1965                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1966                                             NUM_VS_STACK_ENTRIES(40));
1967                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1968                                             NUM_ES_STACK_ENTRIES(16));
1969         } else if (((rdev->family) == CHIP_RV630) ||
1970                    ((rdev->family) == CHIP_RV635)) {
1971                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1972                                           NUM_VS_GPRS(44) |
1973                                           NUM_CLAUSE_TEMP_GPRS(2));
1974                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1975                                           NUM_ES_GPRS(18));
1976                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1977                                            NUM_VS_THREADS(78) |
1978                                            NUM_GS_THREADS(4) |
1979                                            NUM_ES_THREADS(31));
1980                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1981                                             NUM_VS_STACK_ENTRIES(40));
1982                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1983                                             NUM_ES_STACK_ENTRIES(16));
1984         } else if ((rdev->family) == CHIP_RV670) {
1985                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1986                                           NUM_VS_GPRS(44) |
1987                                           NUM_CLAUSE_TEMP_GPRS(2));
1988                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1989                                           NUM_ES_GPRS(17));
1990                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1991                                            NUM_VS_THREADS(78) |
1992                                            NUM_GS_THREADS(4) |
1993                                            NUM_ES_THREADS(31));
1994                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1995                                             NUM_VS_STACK_ENTRIES(64));
1996                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1997                                             NUM_ES_STACK_ENTRIES(64));
1998         }
1999
2000         WREG32(SQ_CONFIG, sq_config);
2001         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
2002         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
2003         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2004         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2005         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2006
2007         if (((rdev->family) == CHIP_RV610) ||
2008             ((rdev->family) == CHIP_RV620) ||
2009             ((rdev->family) == CHIP_RS780) ||
2010             ((rdev->family) == CHIP_RS880)) {
2011                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2012         } else {
2013                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2014         }
2015
2016         /* More default values. 2D/3D driver should adjust as needed */
2017         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2018                                          S1_X(0x4) | S1_Y(0xc)));
2019         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2020                                          S1_X(0x2) | S1_Y(0x2) |
2021                                          S2_X(0xa) | S2_Y(0x6) |
2022                                          S3_X(0x6) | S3_Y(0xa)));
2023         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2024                                              S1_X(0x4) | S1_Y(0xc) |
2025                                              S2_X(0x1) | S2_Y(0x6) |
2026                                              S3_X(0xa) | S3_Y(0xe)));
2027         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2028                                              S5_X(0x0) | S5_Y(0x0) |
2029                                              S6_X(0xb) | S6_Y(0x4) |
2030                                              S7_X(0x7) | S7_Y(0x8)));
2031
2032         WREG32(VGT_STRMOUT_EN, 0);
2033         tmp = rdev->config.r600.max_pipes * 16;
2034         switch (rdev->family) {
2035         case CHIP_RV610:
2036         case CHIP_RV620:
2037         case CHIP_RS780:
2038         case CHIP_RS880:
2039                 tmp += 32;
2040                 break;
2041         case CHIP_RV670:
2042                 tmp += 128;
2043                 break;
2044         default:
2045                 break;
2046         }
2047         if (tmp > 256) {
2048                 tmp = 256;
2049         }
2050         WREG32(VGT_ES_PER_GS, 128);
2051         WREG32(VGT_GS_PER_ES, tmp);
2052         WREG32(VGT_GS_PER_VS, 2);
2053         WREG32(VGT_GS_VERTEX_REUSE, 16);
2054
2055         /* more default values. 2D/3D driver should adjust as needed */
2056         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2057         WREG32(VGT_STRMOUT_EN, 0);
2058         WREG32(SX_MISC, 0);
2059         WREG32(PA_SC_MODE_CNTL, 0);
2060         WREG32(PA_SC_AA_CONFIG, 0);
2061         WREG32(PA_SC_LINE_STIPPLE, 0);
2062         WREG32(SPI_INPUT_Z, 0);
2063         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2064         WREG32(CB_COLOR7_FRAG, 0);
2065
2066         /* Clear render buffer base addresses */
2067         WREG32(CB_COLOR0_BASE, 0);
2068         WREG32(CB_COLOR1_BASE, 0);
2069         WREG32(CB_COLOR2_BASE, 0);
2070         WREG32(CB_COLOR3_BASE, 0);
2071         WREG32(CB_COLOR4_BASE, 0);
2072         WREG32(CB_COLOR5_BASE, 0);
2073         WREG32(CB_COLOR6_BASE, 0);
2074         WREG32(CB_COLOR7_BASE, 0);
2075         WREG32(CB_COLOR7_FRAG, 0);
2076
2077         switch (rdev->family) {
2078         case CHIP_RV610:
2079         case CHIP_RV620:
2080         case CHIP_RS780:
2081         case CHIP_RS880:
2082                 tmp = TC_L2_SIZE(8);
2083                 break;
2084         case CHIP_RV630:
2085         case CHIP_RV635:
2086                 tmp = TC_L2_SIZE(4);
2087                 break;
2088         case CHIP_R600:
2089                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2090                 break;
2091         default:
2092                 tmp = TC_L2_SIZE(0);
2093                 break;
2094         }
2095         WREG32(TC_CNTL, tmp);
2096
2097         tmp = RREG32(HDP_HOST_PATH_CNTL);
2098         WREG32(HDP_HOST_PATH_CNTL, tmp);
2099
2100         tmp = RREG32(ARB_POP);
2101         tmp |= ENABLE_TC128;
2102         WREG32(ARB_POP, tmp);
2103
2104         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2105         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2106                                NUM_CLIP_SEQ(3)));
2107         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2108         WREG32(VC_ENHANCE, 0);
2109 }
2110
2111
2112 /*
2113  * Indirect registers accessor
2114  */
2115 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2116 {
2117         u32 r;
2118
2119         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2120         (void)RREG32(PCIE_PORT_INDEX);
2121         r = RREG32(PCIE_PORT_DATA);
2122         return r;
2123 }
2124
2125 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2126 {
2127         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2128         (void)RREG32(PCIE_PORT_INDEX);
2129         WREG32(PCIE_PORT_DATA, (v));
2130         (void)RREG32(PCIE_PORT_DATA);
2131 }
2132
2133 /*
2134  * CP & Ring
2135  */
2136 void r600_cp_stop(struct radeon_device *rdev)
2137 {
2138         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2139         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2140         WREG32(SCRATCH_UMSK, 0);
2141         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2142 }
2143
2144 int r600_init_microcode(struct radeon_device *rdev)
2145 {
2146         const char *chip_name;
2147         const char *rlc_chip_name;
2148         const char *smc_chip_name = "RV770";
2149         size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2150         char fw_name[30];
2151         int err;
2152
2153         DRM_DEBUG("\n");
2154
2155         switch (rdev->family) {
2156         case CHIP_R600:
2157                 chip_name = "R600";
2158                 rlc_chip_name = "R600";
2159                 break;
2160         case CHIP_RV610:
2161                 chip_name = "RV610";
2162                 rlc_chip_name = "R600";
2163                 break;
2164         case CHIP_RV630:
2165                 chip_name = "RV630";
2166                 rlc_chip_name = "R600";
2167                 break;
2168         case CHIP_RV620:
2169                 chip_name = "RV620";
2170                 rlc_chip_name = "R600";
2171                 break;
2172         case CHIP_RV635:
2173                 chip_name = "RV635";
2174                 rlc_chip_name = "R600";
2175                 break;
2176         case CHIP_RV670:
2177                 chip_name = "RV670";
2178                 rlc_chip_name = "R600";
2179                 break;
2180         case CHIP_RS780:
2181         case CHIP_RS880:
2182                 chip_name = "RS780";
2183                 rlc_chip_name = "R600";
2184                 break;
2185         case CHIP_RV770:
2186                 chip_name = "RV770";
2187                 rlc_chip_name = "R700";
2188                 smc_chip_name = "RV770";
2189                 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
2190                 break;
2191         case CHIP_RV730:
2192                 chip_name = "RV730";
2193                 rlc_chip_name = "R700";
2194                 smc_chip_name = "RV730";
2195                 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
2196                 break;
2197         case CHIP_RV710:
2198                 chip_name = "RV710";
2199                 rlc_chip_name = "R700";
2200                 smc_chip_name = "RV710";
2201                 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2202                 break;
2203         case CHIP_RV740:
2204                 chip_name = "RV730";
2205                 rlc_chip_name = "R700";
2206                 smc_chip_name = "RV740";
2207                 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
2208                 break;
2209         case CHIP_CEDAR:
2210                 chip_name = "CEDAR";
2211                 rlc_chip_name = "CEDAR";
2212                 smc_chip_name = "CEDAR";
2213                 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
2214                 break;
2215         case CHIP_REDWOOD:
2216                 chip_name = "REDWOOD";
2217                 rlc_chip_name = "REDWOOD";
2218                 smc_chip_name = "REDWOOD";
2219                 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
2220                 break;
2221         case CHIP_JUNIPER:
2222                 chip_name = "JUNIPER";
2223                 rlc_chip_name = "JUNIPER";
2224                 smc_chip_name = "JUNIPER";
2225                 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
2226                 break;
2227         case CHIP_CYPRESS:
2228         case CHIP_HEMLOCK:
2229                 chip_name = "CYPRESS";
2230                 rlc_chip_name = "CYPRESS";
2231                 smc_chip_name = "CYPRESS";
2232                 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
2233                 break;
2234         case CHIP_PALM:
2235                 chip_name = "PALM";
2236                 rlc_chip_name = "SUMO";
2237                 break;
2238         case CHIP_SUMO:
2239                 chip_name = "SUMO";
2240                 rlc_chip_name = "SUMO";
2241                 break;
2242         case CHIP_SUMO2:
2243                 chip_name = "SUMO2";
2244                 rlc_chip_name = "SUMO";
2245                 break;
2246         default: BUG();
2247         }
2248
2249         if (rdev->family >= CHIP_CEDAR) {
2250                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2251                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2252                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2253         } else if (rdev->family >= CHIP_RV770) {
2254                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2255                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2256                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2257         } else {
2258                 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2259                 me_req_size = R600_PM4_UCODE_SIZE * 12;
2260                 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
2261         }
2262
2263         DRM_INFO("Loading %s Microcode\n", chip_name);
2264
2265         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2266         err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2267         if (err)
2268                 goto out;
2269         if (rdev->pfp_fw->size != pfp_req_size) {
2270                 printk(KERN_ERR
2271                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2272                        rdev->pfp_fw->size, fw_name);
2273                 err = -EINVAL;
2274                 goto out;
2275         }
2276
2277         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2278         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2279         if (err)
2280                 goto out;
2281         if (rdev->me_fw->size != me_req_size) {
2282                 printk(KERN_ERR
2283                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2284                        rdev->me_fw->size, fw_name);
2285                 err = -EINVAL;
2286         }
2287
2288         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2289         err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2290         if (err)
2291                 goto out;
2292         if (rdev->rlc_fw->size != rlc_req_size) {
2293                 printk(KERN_ERR
2294                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2295                        rdev->rlc_fw->size, fw_name);
2296                 err = -EINVAL;
2297         }
2298
2299         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2300                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name);
2301                 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2302                 if (err) {
2303                         printk(KERN_ERR
2304                                "smc: error loading firmware \"%s\"\n",
2305                                fw_name);
2306                         release_firmware(rdev->smc_fw);
2307                         rdev->smc_fw = NULL;
2308                 } else if (rdev->smc_fw->size != smc_req_size) {
2309                         printk(KERN_ERR
2310                                "smc: Bogus length %zu in firmware \"%s\"\n",
2311                                rdev->smc_fw->size, fw_name);
2312                         err = -EINVAL;
2313                 }
2314         }
2315
2316 out:
2317         if (err) {
2318                 if (err != -EINVAL)
2319                         printk(KERN_ERR
2320                                "r600_cp: Failed to load firmware \"%s\"\n",
2321                                fw_name);
2322                 release_firmware(rdev->pfp_fw);
2323                 rdev->pfp_fw = NULL;
2324                 release_firmware(rdev->me_fw);
2325                 rdev->me_fw = NULL;
2326                 release_firmware(rdev->rlc_fw);
2327                 rdev->rlc_fw = NULL;
2328                 release_firmware(rdev->smc_fw);
2329                 rdev->smc_fw = NULL;
2330         }
2331         return err;
2332 }
2333
2334 static int r600_cp_load_microcode(struct radeon_device *rdev)
2335 {
2336         const __be32 *fw_data;
2337         int i;
2338
2339         if (!rdev->me_fw || !rdev->pfp_fw)
2340                 return -EINVAL;
2341
2342         r600_cp_stop(rdev);
2343
2344         WREG32(CP_RB_CNTL,
2345 #ifdef __BIG_ENDIAN
2346                BUF_SWAP_32BIT |
2347 #endif
2348                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2349
2350         /* Reset cp */
2351         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2352         RREG32(GRBM_SOFT_RESET);
2353         mdelay(15);
2354         WREG32(GRBM_SOFT_RESET, 0);
2355
2356         WREG32(CP_ME_RAM_WADDR, 0);
2357
2358         fw_data = (const __be32 *)rdev->me_fw->data;
2359         WREG32(CP_ME_RAM_WADDR, 0);
2360         for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
2361                 WREG32(CP_ME_RAM_DATA,
2362                        be32_to_cpup(fw_data++));
2363
2364         fw_data = (const __be32 *)rdev->pfp_fw->data;
2365         WREG32(CP_PFP_UCODE_ADDR, 0);
2366         for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
2367                 WREG32(CP_PFP_UCODE_DATA,
2368                        be32_to_cpup(fw_data++));
2369
2370         WREG32(CP_PFP_UCODE_ADDR, 0);
2371         WREG32(CP_ME_RAM_WADDR, 0);
2372         WREG32(CP_ME_RAM_RADDR, 0);
2373         return 0;
2374 }
2375
2376 int r600_cp_start(struct radeon_device *rdev)
2377 {
2378         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2379         int r;
2380         uint32_t cp_me;
2381
2382         r = radeon_ring_lock(rdev, ring, 7);
2383         if (r) {
2384                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2385                 return r;
2386         }
2387         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2388         radeon_ring_write(ring, 0x1);
2389         if (rdev->family >= CHIP_RV770) {
2390                 radeon_ring_write(ring, 0x0);
2391                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2392         } else {
2393                 radeon_ring_write(ring, 0x3);
2394                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2395         }
2396         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2397         radeon_ring_write(ring, 0);
2398         radeon_ring_write(ring, 0);
2399         radeon_ring_unlock_commit(rdev, ring);
2400
2401         cp_me = 0xff;
2402         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2403         return 0;
2404 }
2405
2406 int r600_cp_resume(struct radeon_device *rdev)
2407 {
2408         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2409         u32 tmp;
2410         u32 rb_bufsz;
2411         int r;
2412
2413         /* Reset cp */
2414         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2415         RREG32(GRBM_SOFT_RESET);
2416         mdelay(15);
2417         WREG32(GRBM_SOFT_RESET, 0);
2418
2419         /* Set ring buffer size */
2420         rb_bufsz = drm_order(ring->ring_size / 8);
2421         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2422 #ifdef __BIG_ENDIAN
2423         tmp |= BUF_SWAP_32BIT;
2424 #endif
2425         WREG32(CP_RB_CNTL, tmp);
2426         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2427
2428         /* Set the write pointer delay */
2429         WREG32(CP_RB_WPTR_DELAY, 0);
2430
2431         /* Initialize the ring buffer's read and write pointers */
2432         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2433         WREG32(CP_RB_RPTR_WR, 0);
2434         ring->wptr = 0;
2435         WREG32(CP_RB_WPTR, ring->wptr);
2436
2437         /* set the wb address whether it's enabled or not */
2438         WREG32(CP_RB_RPTR_ADDR,
2439                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2440         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2441         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2442
2443         if (rdev->wb.enabled)
2444                 WREG32(SCRATCH_UMSK, 0xff);
2445         else {
2446                 tmp |= RB_NO_UPDATE;
2447                 WREG32(SCRATCH_UMSK, 0);
2448         }
2449
2450         mdelay(1);
2451         WREG32(CP_RB_CNTL, tmp);
2452
2453         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2454         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2455
2456         ring->rptr = RREG32(CP_RB_RPTR);
2457
2458         r600_cp_start(rdev);
2459         ring->ready = true;
2460         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2461         if (r) {
2462                 ring->ready = false;
2463                 return r;
2464         }
2465         return 0;
2466 }
2467
2468 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2469 {
2470         u32 rb_bufsz;
2471         int r;
2472
2473         /* Align ring size */
2474         rb_bufsz = drm_order(ring_size / 8);
2475         ring_size = (1 << (rb_bufsz + 1)) * 4;
2476         ring->ring_size = ring_size;
2477         ring->align_mask = 16 - 1;
2478
2479         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2480                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2481                 if (r) {
2482                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2483                         ring->rptr_save_reg = 0;
2484                 }
2485         }
2486 }
2487
2488 void r600_cp_fini(struct radeon_device *rdev)
2489 {
2490         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2491         r600_cp_stop(rdev);
2492         radeon_ring_fini(rdev, ring);
2493         radeon_scratch_free(rdev, ring->rptr_save_reg);
2494 }
2495
2496 /*
2497  * DMA
2498  * Starting with R600, the GPU has an asynchronous
2499  * DMA engine.  The programming model is very similar
2500  * to the 3D engine (ring buffer, IBs, etc.), but the
2501  * DMA controller has it's own packet format that is
2502  * different form the PM4 format used by the 3D engine.
2503  * It supports copying data, writing embedded data,
2504  * solid fills, and a number of other things.  It also
2505  * has support for tiling/detiling of buffers.
2506  */
2507 /**
2508  * r600_dma_stop - stop the async dma engine
2509  *
2510  * @rdev: radeon_device pointer
2511  *
2512  * Stop the async dma engine (r6xx-evergreen).
2513  */
2514 void r600_dma_stop(struct radeon_device *rdev)
2515 {
2516         u32 rb_cntl = RREG32(DMA_RB_CNTL);
2517
2518         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2519
2520         rb_cntl &= ~DMA_RB_ENABLE;
2521         WREG32(DMA_RB_CNTL, rb_cntl);
2522
2523         rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2524 }
2525
2526 /**
2527  * r600_dma_resume - setup and start the async dma engine
2528  *
2529  * @rdev: radeon_device pointer
2530  *
2531  * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2532  * Returns 0 for success, error for failure.
2533  */
2534 int r600_dma_resume(struct radeon_device *rdev)
2535 {
2536         struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2537         u32 rb_cntl, dma_cntl, ib_cntl;
2538         u32 rb_bufsz;
2539         int r;
2540
2541         /* Reset dma */
2542         if (rdev->family >= CHIP_RV770)
2543                 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2544         else
2545                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2546         RREG32(SRBM_SOFT_RESET);
2547         udelay(50);
2548         WREG32(SRBM_SOFT_RESET, 0);
2549
2550         WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2551         WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2552
2553         /* Set ring buffer size in dwords */
2554         rb_bufsz = drm_order(ring->ring_size / 4);
2555         rb_cntl = rb_bufsz << 1;
2556 #ifdef __BIG_ENDIAN
2557         rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2558 #endif
2559         WREG32(DMA_RB_CNTL, rb_cntl);
2560
2561         /* Initialize the ring buffer's read and write pointers */
2562         WREG32(DMA_RB_RPTR, 0);
2563         WREG32(DMA_RB_WPTR, 0);
2564
2565         /* set the wb address whether it's enabled or not */
2566         WREG32(DMA_RB_RPTR_ADDR_HI,
2567                upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2568         WREG32(DMA_RB_RPTR_ADDR_LO,
2569                ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2570
2571         if (rdev->wb.enabled)
2572                 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2573
2574         WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2575
2576         /* enable DMA IBs */
2577         ib_cntl = DMA_IB_ENABLE;
2578 #ifdef __BIG_ENDIAN
2579         ib_cntl |= DMA_IB_SWAP_ENABLE;
2580 #endif
2581         WREG32(DMA_IB_CNTL, ib_cntl);
2582
2583         dma_cntl = RREG32(DMA_CNTL);
2584         dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2585         WREG32(DMA_CNTL, dma_cntl);
2586
2587         if (rdev->family >= CHIP_RV770)
2588                 WREG32(DMA_MODE, 1);
2589
2590         ring->wptr = 0;
2591         WREG32(DMA_RB_WPTR, ring->wptr << 2);
2592
2593         ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2594
2595         WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2596
2597         ring->ready = true;
2598
2599         r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2600         if (r) {
2601                 ring->ready = false;
2602                 return r;
2603         }
2604
2605         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2606
2607         return 0;
2608 }
2609
2610 /**
2611  * r600_dma_fini - tear down the async dma engine
2612  *
2613  * @rdev: radeon_device pointer
2614  *
2615  * Stop the async dma engine and free the ring (r6xx-evergreen).
2616  */
2617 void r600_dma_fini(struct radeon_device *rdev)
2618 {
2619         r600_dma_stop(rdev);
2620         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2621 }
2622
2623 /*
2624  * UVD
2625  */
2626 uint32_t r600_uvd_get_rptr(struct radeon_device *rdev,
2627                            struct radeon_ring *ring)
2628 {
2629         return RREG32(UVD_RBC_RB_RPTR);
2630 }
2631
2632 uint32_t r600_uvd_get_wptr(struct radeon_device *rdev,
2633                            struct radeon_ring *ring)
2634 {
2635         return RREG32(UVD_RBC_RB_WPTR);
2636 }
2637
2638 void r600_uvd_set_wptr(struct radeon_device *rdev,
2639                        struct radeon_ring *ring)
2640 {
2641         WREG32(UVD_RBC_RB_WPTR, ring->wptr);
2642 }
2643
2644 static int r600_uvd_rbc_start(struct radeon_device *rdev, bool ring_test)
2645 {
2646         struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2647         uint32_t rb_bufsz, tmp;
2648         int r;
2649
2650         /* force RBC into idle state */
2651         WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2652
2653         /* Set the write pointer delay */
2654         WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
2655
2656         /* programm the 4GB memory segment for rptr and ring buffer */
2657         WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
2658                                    (0x7 << 16) | (0x1 << 31));
2659
2660         /* Initialize the ring buffer's read and write pointers */
2661         WREG32(UVD_RBC_RB_RPTR, 0x0);
2662
2663         ring->wptr = ring->rptr = RREG32(UVD_RBC_RB_RPTR);
2664         WREG32(UVD_RBC_RB_WPTR, ring->wptr);
2665
2666         /* set the ring address */
2667         WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
2668
2669         /* Set ring buffer size */
2670         rb_bufsz = drm_order(ring->ring_size);
2671         rb_bufsz = (0x1 << 8) | rb_bufsz;
2672         WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
2673
2674         if (ring_test) {
2675                 ring->ready = true;
2676                 r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);
2677                 if (r) {
2678                         ring->ready = false;
2679                         return r;
2680                 }
2681
2682                 r = radeon_ring_lock(rdev, ring, 10);
2683                 if (r) {
2684                         DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
2685                         return r;
2686                 }
2687
2688                 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
2689                 radeon_ring_write(ring, tmp);
2690                 radeon_ring_write(ring, 0xFFFFF);
2691
2692                 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
2693                 radeon_ring_write(ring, tmp);
2694                 radeon_ring_write(ring, 0xFFFFF);
2695
2696                 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
2697                 radeon_ring_write(ring, tmp);
2698                 radeon_ring_write(ring, 0xFFFFF);
2699
2700                 /* Clear timeout status bits */
2701                 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));
2702                 radeon_ring_write(ring, 0x8);
2703
2704                 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
2705                 radeon_ring_write(ring, 3);
2706
2707                 radeon_ring_unlock_commit(rdev, ring);
2708         }
2709
2710         return 0;
2711 }
2712
2713 void r600_do_uvd_stop(struct radeon_device *rdev)
2714 {
2715         /* force RBC into idle state */
2716         WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2717
2718         /* Stall UMC and register bus before resetting VCPU */
2719         WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
2720         WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
2721         mdelay(1);
2722
2723         /* put VCPU into reset */
2724         WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
2725         mdelay(5);
2726
2727         /* disable VCPU clock */
2728         WREG32(UVD_VCPU_CNTL, 0x0);
2729
2730         /* Unstall UMC and register bus */
2731         WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
2732         WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
2733 }
2734
2735 void r600_uvd_stop(struct radeon_device *rdev)
2736 {
2737         struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2738
2739         r600_do_uvd_stop(rdev);
2740         ring->ready = false;
2741 }
2742
2743 int r600_uvd_init(struct radeon_device *rdev, bool ring_test)
2744 {
2745         int i, j, r;
2746         /* disable byte swapping */
2747         u32 lmi_swap_cntl = 0;
2748         u32 mp_swap_cntl = 0;
2749
2750         /* raise clocks while booting up the VCPU */
2751         radeon_set_uvd_clocks(rdev, 53300, 40000);
2752
2753         /* disable clock gating */
2754         WREG32(UVD_CGC_GATE, 0);
2755
2756         /* disable interupt */
2757         WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
2758
2759         /* Stall UMC and register bus before resetting VCPU */
2760         WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
2761         WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
2762         mdelay(1);
2763
2764         /* put LMI, VCPU, RBC etc... into reset */
2765         WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
2766                LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET |
2767                CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET);
2768         mdelay(5);
2769
2770         /* take UVD block out of reset */
2771         WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
2772         mdelay(5);
2773
2774         /* initialize UVD memory controller */
2775         WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
2776                              (1 << 21) | (1 << 9) | (1 << 20));
2777
2778 #ifdef __BIG_ENDIAN
2779         /* swap (8 in 32) RB and IB */
2780         lmi_swap_cntl = 0xa;
2781         mp_swap_cntl = 0;
2782 #endif
2783         WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);
2784         WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);
2785
2786         WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
2787         WREG32(UVD_MPC_SET_MUXA1, 0x0);
2788         WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);
2789         WREG32(UVD_MPC_SET_MUXB1, 0x0);
2790         WREG32(UVD_MPC_SET_ALU, 0);
2791         WREG32(UVD_MPC_SET_MUX, 0x88);
2792
2793         /* take all subblocks out of reset, except VCPU */
2794         WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
2795         mdelay(5);
2796
2797         /* enable VCPU clock */
2798         WREG32(UVD_VCPU_CNTL,  1 << 9);
2799
2800         /* enable UMC */
2801         WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
2802
2803         /* boot up the VCPU */
2804         WREG32(UVD_SOFT_RESET, 0);
2805         mdelay(10);
2806
2807         WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
2808
2809         for (i = 0; i < 10; ++i) {
2810                 uint32_t status;
2811                 for (j = 0; j < 100; ++j) {
2812                         status = RREG32(UVD_STATUS);
2813                         if (status & 2)
2814                                 break;
2815                         mdelay(10);
2816                 }
2817                 r = 0;
2818                 if (status & 2)
2819                         break;
2820
2821                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
2822                 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
2823                 mdelay(10);
2824                 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
2825                 mdelay(10);
2826                 r = -1;
2827         }
2828
2829         if (r) {
2830                 DRM_ERROR("UVD not responding, giving up!!!\n");
2831                 goto done;
2832         }
2833
2834         /* enable interupt */
2835         WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
2836
2837         r = r600_uvd_rbc_start(rdev, ring_test);
2838         if (!r)
2839                 DRM_INFO("UVD initialized successfully.\n");
2840
2841 done:
2842         /* lower clocks again */
2843         radeon_set_uvd_clocks(rdev, 0, 0);
2844
2845         return r;
2846 }
2847
2848 /*
2849  * GPU scratch registers helpers function.
2850  */
2851 void r600_scratch_init(struct radeon_device *rdev)
2852 {
2853         int i;
2854
2855         rdev->scratch.num_reg = 7;
2856         rdev->scratch.reg_base = SCRATCH_REG0;
2857         for (i = 0; i < rdev->scratch.num_reg; i++) {
2858                 rdev->scratch.free[i] = true;
2859                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2860         }
2861 }
2862
2863 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2864 {
2865         uint32_t scratch;
2866         uint32_t tmp = 0;
2867         unsigned i;
2868         int r;
2869
2870         r = radeon_scratch_get(rdev, &scratch);
2871         if (r) {
2872                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2873                 return r;
2874         }
2875         WREG32(scratch, 0xCAFEDEAD);
2876         r = radeon_ring_lock(rdev, ring, 3);
2877         if (r) {
2878                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2879                 radeon_scratch_free(rdev, scratch);
2880                 return r;
2881         }
2882         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2883         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2884         radeon_ring_write(ring, 0xDEADBEEF);
2885         radeon_ring_unlock_commit(rdev, ring);
2886         for (i = 0; i < rdev->usec_timeout; i++) {
2887                 tmp = RREG32(scratch);
2888                 if (tmp == 0xDEADBEEF)
2889                         break;
2890                 DRM_UDELAY(1);
2891         }
2892         if (i < rdev->usec_timeout) {
2893                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2894         } else {
2895                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2896                           ring->idx, scratch, tmp);
2897                 r = -EINVAL;
2898         }
2899         radeon_scratch_free(rdev, scratch);
2900         return r;
2901 }
2902
2903 /**
2904  * r600_dma_ring_test - simple async dma engine test
2905  *
2906  * @rdev: radeon_device pointer
2907  * @ring: radeon_ring structure holding ring information
2908  *
2909  * Test the DMA engine by writing using it to write an
2910  * value to memory. (r6xx-SI).
2911  * Returns 0 for success, error for failure.
2912  */
2913 int r600_dma_ring_test(struct radeon_device *rdev,
2914                        struct radeon_ring *ring)
2915 {
2916         unsigned i;
2917         int r;
2918         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2919         u32 tmp;
2920
2921         if (!ptr) {
2922                 DRM_ERROR("invalid vram scratch pointer\n");
2923                 return -EINVAL;
2924         }
2925
2926         tmp = 0xCAFEDEAD;
2927         writel(tmp, ptr);
2928
2929         r = radeon_ring_lock(rdev, ring, 4);
2930         if (r) {
2931                 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2932                 return r;
2933         }
2934         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2935         radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2936         radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2937         radeon_ring_write(ring, 0xDEADBEEF);
2938         radeon_ring_unlock_commit(rdev, ring);
2939
2940         for (i = 0; i < rdev->usec_timeout; i++) {
2941                 tmp = readl(ptr);
2942                 if (tmp == 0xDEADBEEF)
2943                         break;
2944                 DRM_UDELAY(1);
2945         }
2946
2947         if (i < rdev->usec_timeout) {
2948                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2949         } else {
2950                 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2951                           ring->idx, tmp);
2952                 r = -EINVAL;
2953         }
2954         return r;
2955 }
2956
2957 int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2958 {
2959         uint32_t tmp = 0;
2960         unsigned i;
2961         int r;
2962
2963         WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);
2964         r = radeon_ring_lock(rdev, ring, 3);
2965         if (r) {
2966                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
2967                           ring->idx, r);
2968                 return r;
2969         }
2970         radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
2971         radeon_ring_write(ring, 0xDEADBEEF);
2972         radeon_ring_unlock_commit(rdev, ring);
2973         for (i = 0; i < rdev->usec_timeout; i++) {
2974                 tmp = RREG32(UVD_CONTEXT_ID);
2975                 if (tmp == 0xDEADBEEF)
2976                         break;
2977                 DRM_UDELAY(1);
2978         }
2979
2980         if (i < rdev->usec_timeout) {
2981                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
2982                          ring->idx, i);
2983         } else {
2984                 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2985                           ring->idx, tmp);
2986                 r = -EINVAL;
2987         }
2988         return r;
2989 }
2990
2991 /*
2992  * CP fences/semaphores
2993  */
2994
2995 void r600_fence_ring_emit(struct radeon_device *rdev,
2996                           struct radeon_fence *fence)
2997 {
2998         struct radeon_ring *ring = &rdev->ring[fence->ring];
2999
3000         if (rdev->wb.use_event) {
3001                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3002                 /* flush read cache over gart */
3003                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3004                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
3005                                         PACKET3_VC_ACTION_ENA |
3006                                         PACKET3_SH_ACTION_ENA);
3007                 radeon_ring_write(ring, 0xFFFFFFFF);
3008                 radeon_ring_write(ring, 0);
3009                 radeon_ring_write(ring, 10); /* poll interval */
3010                 /* EVENT_WRITE_EOP - flush caches, send int */
3011                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3012                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
3013                 radeon_ring_write(ring, addr & 0xffffffff);
3014                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3015                 radeon_ring_write(ring, fence->seq);
3016                 radeon_ring_write(ring, 0);
3017         } else {
3018                 /* flush read cache over gart */
3019                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3020                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
3021                                         PACKET3_VC_ACTION_ENA |
3022                                         PACKET3_SH_ACTION_ENA);
3023                 radeon_ring_write(ring, 0xFFFFFFFF);
3024                 radeon_ring_write(ring, 0);
3025                 radeon_ring_write(ring, 10); /* poll interval */
3026                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
3027                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
3028                 /* wait for 3D idle clean */
3029                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3030                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3031                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
3032                 /* Emit fence sequence & fire IRQ */
3033                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3034                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3035                 radeon_ring_write(ring, fence->seq);
3036                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
3037                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
3038                 radeon_ring_write(ring, RB_INT_STAT);
3039         }
3040 }
3041
3042 void r600_uvd_fence_emit(struct radeon_device *rdev,
3043                          struct radeon_fence *fence)
3044 {
3045         struct radeon_ring *ring = &rdev->ring[fence->ring];
3046         uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
3047
3048         radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
3049         radeon_ring_write(ring, fence->seq);
3050         radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
3051         radeon_ring_write(ring, addr & 0xffffffff);
3052         radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
3053         radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
3054         radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
3055         radeon_ring_write(ring, 0);
3056
3057         radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
3058         radeon_ring_write(ring, 0);
3059         radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
3060         radeon_ring_write(ring, 0);
3061         radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
3062         radeon_ring_write(ring, 2);
3063         return;
3064 }
3065
3066 void r600_semaphore_ring_emit(struct radeon_device *rdev,
3067                               struct radeon_ring *ring,
3068                               struct radeon_semaphore *semaphore,
3069                               bool emit_wait)
3070 {
3071         uint64_t addr = semaphore->gpu_addr;
3072         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3073
3074         if (rdev->family < CHIP_CAYMAN)
3075                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
3076
3077         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3078         radeon_ring_write(ring, addr & 0xffffffff);
3079         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
3080 }
3081
3082 /*
3083  * DMA fences/semaphores
3084  */
3085
3086 /**
3087  * r600_dma_fence_ring_emit - emit a fence on the DMA ring
3088  *
3089  * @rdev: radeon_device pointer
3090  * @fence: radeon fence object
3091  *
3092  * Add a DMA fence packet to the ring to write
3093  * the fence seq number and DMA trap packet to generate
3094  * an interrupt if needed (r6xx-r7xx).
3095  */
3096 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
3097                               struct radeon_fence *fence)
3098 {
3099         struct radeon_ring *ring = &rdev->ring[fence->ring];
3100         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3101
3102         /* write the fence */
3103         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
3104         radeon_ring_write(ring, addr & 0xfffffffc);
3105         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3106         radeon_ring_write(ring, lower_32_bits(fence->seq));
3107         /* generate an interrupt */
3108         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
3109 }
3110
3111 /**
3112  * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
3113  *
3114  * @rdev: radeon_device pointer
3115  * @ring: radeon_ring structure holding ring information
3116  * @semaphore: radeon semaphore object
3117  * @emit_wait: wait or signal semaphore
3118  *
3119  * Add a DMA semaphore packet to the ring wait on or signal
3120  * other rings (r6xx-SI).
3121  */
3122 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
3123                                   struct radeon_ring *ring,
3124                                   struct radeon_semaphore *semaphore,
3125                                   bool emit_wait)
3126 {
3127         u64 addr = semaphore->gpu_addr;
3128         u32 s = emit_wait ? 0 : 1;
3129
3130         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
3131         radeon_ring_write(ring, addr & 0xfffffffc);
3132         radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
3133 }
3134
3135 void r600_uvd_semaphore_emit(struct radeon_device *rdev,
3136                              struct radeon_ring *ring,
3137                              struct radeon_semaphore *semaphore,
3138                              bool emit_wait)
3139 {
3140         uint64_t addr = semaphore->gpu_addr;
3141
3142         radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
3143         radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
3144
3145         radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
3146         radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
3147
3148         radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
3149         radeon_ring_write(ring, emit_wait ? 1 : 0);
3150 }
3151
3152 /**
3153  * r600_copy_cpdma - copy pages using the CP DMA engine
3154  *
3155  * @rdev: radeon_device pointer
3156  * @src_offset: src GPU address
3157  * @dst_offset: dst GPU address
3158  * @num_gpu_pages: number of GPU pages to xfer
3159  * @fence: radeon fence object
3160  *
3161  * Copy GPU paging using the CP DMA engine (r6xx+).
3162  * Used by the radeon ttm implementation to move pages if
3163  * registered as the asic copy callback.
3164  */
3165 int r600_copy_cpdma(struct radeon_device *rdev,
3166                     uint64_t src_offset, uint64_t dst_offset,
3167                     unsigned num_gpu_pages,
3168                     struct radeon_fence **fence)
3169 {
3170         struct radeon_semaphore *sem = NULL;
3171         int ring_index = rdev->asic->copy.blit_ring_index;
3172         struct radeon_ring *ring = &rdev->ring[ring_index];
3173         u32 size_in_bytes, cur_size_in_bytes, tmp;
3174         int i, num_loops;
3175         int r = 0;
3176
3177         r = radeon_semaphore_create(rdev, &sem);
3178         if (r) {
3179                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3180                 return r;
3181         }
3182
3183         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3184         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
3185         r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
3186         if (r) {
3187                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3188                 radeon_semaphore_free(rdev, &sem, NULL);
3189                 return r;
3190         }
3191
3192         if (radeon_fence_need_sync(*fence, ring->idx)) {
3193                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3194                                             ring->idx);
3195                 radeon_fence_note_sync(*fence, ring->idx);
3196         } else {
3197                 radeon_semaphore_free(rdev, &sem, NULL);
3198         }
3199
3200         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3201         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3202         radeon_ring_write(ring, WAIT_3D_IDLE_bit);
3203         for (i = 0; i < num_loops; i++) {
3204                 cur_size_in_bytes = size_in_bytes;
3205                 if (cur_size_in_bytes > 0x1fffff)
3206                         cur_size_in_bytes = 0x1fffff;
3207                 size_in_bytes -= cur_size_in_bytes;
3208                 tmp = upper_32_bits(src_offset) & 0xff;
3209                 if (size_in_bytes == 0)
3210                         tmp |= PACKET3_CP_DMA_CP_SYNC;
3211                 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
3212                 radeon_ring_write(ring, src_offset & 0xffffffff);
3213                 radeon_ring_write(ring, tmp);
3214                 radeon_ring_write(ring, dst_offset & 0xffffffff);
3215                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3216                 radeon_ring_write(ring, cur_size_in_bytes);
3217                 src_offset += cur_size_in_bytes;
3218                 dst_offset += cur_size_in_bytes;
3219         }
3220         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3221         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3222         radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
3223
3224         r = radeon_fence_emit(rdev, fence, ring->idx);
3225         if (r) {
3226                 radeon_ring_unlock_undo(rdev, ring);
3227                 return r;
3228         }
3229
3230         radeon_ring_unlock_commit(rdev, ring);
3231         radeon_semaphore_free(rdev, &sem, *fence);
3232
3233         return r;
3234 }
3235
3236 /**
3237  * r600_copy_dma - copy pages using the DMA engine
3238  *
3239  * @rdev: radeon_device pointer
3240  * @src_offset: src GPU address
3241  * @dst_offset: dst GPU address
3242  * @num_gpu_pages: number of GPU pages to xfer
3243  * @fence: radeon fence object
3244  *
3245  * Copy GPU paging using the DMA engine (r6xx).
3246  * Used by the radeon ttm implementation to move pages if
3247  * registered as the asic copy callback.
3248  */
3249 int r600_copy_dma(struct radeon_device *rdev,
3250                   uint64_t src_offset, uint64_t dst_offset,
3251                   unsigned num_gpu_pages,
3252                   struct radeon_fence **fence)
3253 {
3254         struct radeon_semaphore *sem = NULL;
3255         int ring_index = rdev->asic->copy.dma_ring_index;
3256         struct radeon_ring *ring = &rdev->ring[ring_index];
3257         u32 size_in_dw, cur_size_in_dw;
3258         int i, num_loops;
3259         int r = 0;
3260
3261         r = radeon_semaphore_create(rdev, &sem);
3262         if (r) {
3263                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3264                 return r;
3265         }
3266
3267         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
3268         num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
3269         r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
3270         if (r) {
3271                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3272                 radeon_semaphore_free(rdev, &sem, NULL);
3273                 return r;
3274         }
3275
3276         if (radeon_fence_need_sync(*fence, ring->idx)) {
3277                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3278                                             ring->idx);
3279                 radeon_fence_note_sync(*fence, ring->idx);
3280         } else {
3281                 radeon_semaphore_free(rdev, &sem, NULL);
3282         }
3283
3284         for (i = 0; i < num_loops; i++) {
3285                 cur_size_in_dw = size_in_dw;
3286                 if (cur_size_in_dw > 0xFFFE)
3287                         cur_size_in_dw = 0xFFFE;
3288                 size_in_dw -= cur_size_in_dw;
3289                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
3290                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3291                 radeon_ring_write(ring, src_offset & 0xfffffffc);
3292                 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
3293                                          (upper_32_bits(src_offset) & 0xff)));
3294                 src_offset += cur_size_in_dw * 4;
3295                 dst_offset += cur_size_in_dw * 4;
3296         }
3297
3298         r = radeon_fence_emit(rdev, fence, ring->idx);
3299         if (r) {
3300                 radeon_ring_unlock_undo(rdev, ring);
3301                 return r;
3302         }
3303
3304         radeon_ring_unlock_commit(rdev, ring);
3305         radeon_semaphore_free(rdev, &sem, *fence);
3306
3307         return r;
3308 }
3309
3310 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3311                          uint32_t tiling_flags, uint32_t pitch,
3312                          uint32_t offset, uint32_t obj_size)
3313 {
3314         /* FIXME: implement */
3315         return 0;
3316 }
3317
3318 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3319 {
3320         /* FIXME: implement */
3321 }
3322
3323 static int r600_startup(struct radeon_device *rdev)
3324 {
3325         struct radeon_ring *ring;
3326         int r;
3327
3328         /* enable pcie gen2 link */
3329         r600_pcie_gen2_enable(rdev);
3330
3331         r600_mc_program(rdev);
3332
3333         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3334                 r = r600_init_microcode(rdev);
3335                 if (r) {
3336                         DRM_ERROR("Failed to load firmware!\n");
3337                         return r;
3338                 }
3339         }
3340
3341         r = r600_vram_scratch_init(rdev);
3342         if (r)
3343                 return r;
3344
3345         if (rdev->flags & RADEON_IS_AGP) {
3346                 r600_agp_enable(rdev);
3347         } else {
3348                 r = r600_pcie_gart_enable(rdev);
3349                 if (r)
3350                         return r;
3351         }
3352         r600_gpu_init(rdev);
3353
3354         /* allocate wb buffer */
3355         r = radeon_wb_init(rdev);
3356         if (r)
3357                 return r;
3358
3359         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3360         if (r) {
3361                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3362                 return r;
3363         }
3364
3365         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3366         if (r) {
3367                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3368                 return r;
3369         }
3370
3371         /* Enable IRQ */
3372         if (!rdev->irq.installed) {
3373                 r = radeon_irq_kms_init(rdev);
3374                 if (r)
3375                         return r;
3376         }
3377
3378         r = r600_irq_init(rdev);
3379         if (r) {
3380                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3381                 radeon_irq_kms_fini(rdev);
3382                 return r;
3383         }
3384         r600_irq_set(rdev);
3385
3386         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3387         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3388                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3389                              0, 0xfffff, RADEON_CP_PACKET2);
3390         if (r)
3391                 return r;
3392
3393         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3394         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3395                              DMA_RB_RPTR, DMA_RB_WPTR,
3396                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3397         if (r)
3398                 return r;
3399
3400         r = r600_cp_load_microcode(rdev);
3401         if (r)
3402                 return r;
3403         r = r600_cp_resume(rdev);
3404         if (r)
3405                 return r;
3406
3407         r = r600_dma_resume(rdev);
3408         if (r)
3409                 return r;
3410
3411         r = radeon_ib_pool_init(rdev);
3412         if (r) {
3413                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3414                 return r;
3415         }
3416
3417         r = r600_audio_init(rdev);
3418         if (r) {
3419                 DRM_ERROR("radeon: audio init failed\n");
3420                 return r;
3421         }
3422
3423         return 0;
3424 }
3425
3426 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3427 {
3428         uint32_t temp;
3429
3430         temp = RREG32(CONFIG_CNTL);
3431         if (state == false) {
3432                 temp &= ~(1<<0);
3433                 temp |= (1<<1);
3434         } else {
3435                 temp &= ~(1<<1);
3436         }
3437         WREG32(CONFIG_CNTL, temp);
3438 }
3439
3440 int r600_resume(struct radeon_device *rdev)
3441 {
3442         int r;
3443
3444         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3445          * posting will perform necessary task to bring back GPU into good
3446          * shape.
3447          */
3448         /* post card */
3449         atom_asic_init(rdev->mode_info.atom_context);
3450
3451         rdev->accel_working = true;
3452         r = r600_startup(rdev);
3453         if (r) {
3454                 DRM_ERROR("r600 startup failed on resume\n");
3455                 rdev->accel_working = false;
3456                 return r;
3457         }
3458
3459         return r;
3460 }
3461
3462 int r600_suspend(struct radeon_device *rdev)
3463 {
3464         r600_audio_fini(rdev);
3465         r600_cp_stop(rdev);
3466         r600_dma_stop(rdev);
3467         r600_irq_suspend(rdev);
3468         radeon_wb_disable(rdev);
3469         r600_pcie_gart_disable(rdev);
3470
3471         return 0;
3472 }
3473
3474 /* Plan is to move initialization in that function and use
3475  * helper function so that radeon_device_init pretty much
3476  * do nothing more than calling asic specific function. This
3477  * should also allow to remove a bunch of callback function
3478  * like vram_info.
3479  */
3480 int r600_init(struct radeon_device *rdev)
3481 {
3482         int r;
3483
3484         if (r600_debugfs_mc_info_init(rdev)) {
3485                 DRM_ERROR("Failed to register debugfs file for mc !\n");
3486         }
3487         /* Read BIOS */
3488         if (!radeon_get_bios(rdev)) {
3489                 if (ASIC_IS_AVIVO(rdev))
3490                         return -EINVAL;
3491         }
3492         /* Must be an ATOMBIOS */
3493         if (!rdev->is_atom_bios) {
3494                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3495                 return -EINVAL;
3496         }
3497         r = radeon_atombios_init(rdev);
3498         if (r)
3499                 return r;
3500         /* Post card if necessary */
3501         if (!radeon_card_posted(rdev)) {
3502                 if (!rdev->bios) {
3503                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3504                         return -EINVAL;
3505                 }
3506                 DRM_INFO("GPU not posted. posting now...\n");
3507                 atom_asic_init(rdev->mode_info.atom_context);
3508         }
3509         /* Initialize scratch registers */
3510         r600_scratch_init(rdev);
3511         /* Initialize surface registers */
3512         radeon_surface_init(rdev);
3513         /* Initialize clocks */
3514         radeon_get_clock_info(rdev->ddev);
3515         /* Fence driver */
3516         r = radeon_fence_driver_init(rdev);
3517         if (r)
3518                 return r;
3519         if (rdev->flags & RADEON_IS_AGP) {
3520                 r = radeon_agp_init(rdev);
3521                 if (r)
3522                         radeon_agp_disable(rdev);
3523         }
3524         r = r600_mc_init(rdev);
3525         if (r)
3526                 return r;
3527         /* Memory manager */
3528         r = radeon_bo_init(rdev);
3529         if (r)
3530                 return r;
3531
3532         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3533         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3534
3535         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3536         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3537
3538         rdev->ih.ring_obj = NULL;
3539         r600_ih_ring_init(rdev, 64 * 1024);
3540
3541         r = r600_pcie_gart_init(rdev);
3542         if (r)
3543                 return r;
3544
3545         rdev->accel_working = true;
3546         r = r600_startup(rdev);
3547         if (r) {
3548                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3549                 r600_cp_fini(rdev);
3550                 r600_dma_fini(rdev);
3551                 r600_irq_fini(rdev);
3552                 radeon_wb_fini(rdev);
3553                 radeon_ib_pool_fini(rdev);
3554                 radeon_irq_kms_fini(rdev);
3555                 r600_pcie_gart_fini(rdev);
3556                 rdev->accel_working = false;
3557         }
3558
3559         return 0;
3560 }
3561
3562 void r600_fini(struct radeon_device *rdev)
3563 {
3564         r600_audio_fini(rdev);
3565         r600_cp_fini(rdev);
3566         r600_dma_fini(rdev);
3567         r600_irq_fini(rdev);
3568         radeon_wb_fini(rdev);
3569         radeon_ib_pool_fini(rdev);
3570         radeon_irq_kms_fini(rdev);
3571         r600_pcie_gart_fini(rdev);
3572         r600_vram_scratch_fini(rdev);
3573         radeon_agp_fini(rdev);
3574         radeon_gem_fini(rdev);
3575         radeon_fence_driver_fini(rdev);
3576         radeon_bo_fini(rdev);
3577         radeon_atombios_fini(rdev);
3578         kfree(rdev->bios);
3579         rdev->bios = NULL;
3580 }
3581
3582
3583 /*
3584  * CS stuff
3585  */
3586 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3587 {
3588         struct radeon_ring *ring = &rdev->ring[ib->ring];
3589         u32 next_rptr;
3590
3591         if (ring->rptr_save_reg) {
3592                 next_rptr = ring->wptr + 3 + 4;
3593                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3594                 radeon_ring_write(ring, ((ring->rptr_save_reg -
3595                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3596                 radeon_ring_write(ring, next_rptr);
3597         } else if (rdev->wb.enabled) {
3598                 next_rptr = ring->wptr + 5 + 4;
3599                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3600                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3601                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3602                 radeon_ring_write(ring, next_rptr);
3603                 radeon_ring_write(ring, 0);
3604         }
3605
3606         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3607         radeon_ring_write(ring,
3608 #ifdef __BIG_ENDIAN
3609                           (2 << 0) |
3610 #endif
3611                           (ib->gpu_addr & 0xFFFFFFFC));
3612         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3613         radeon_ring_write(ring, ib->length_dw);
3614 }
3615
3616 void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3617 {
3618         struct radeon_ring *ring = &rdev->ring[ib->ring];
3619
3620         radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));
3621         radeon_ring_write(ring, ib->gpu_addr);
3622         radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));
3623         radeon_ring_write(ring, ib->length_dw);
3624 }
3625
3626 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3627 {
3628         struct radeon_ib ib;
3629         uint32_t scratch;
3630         uint32_t tmp = 0;
3631         unsigned i;
3632         int r;
3633
3634         r = radeon_scratch_get(rdev, &scratch);
3635         if (r) {
3636                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3637                 return r;
3638         }
3639         WREG32(scratch, 0xCAFEDEAD);
3640         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3641         if (r) {
3642                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3643                 goto free_scratch;
3644         }
3645         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3646         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3647         ib.ptr[2] = 0xDEADBEEF;
3648         ib.length_dw = 3;
3649         r = radeon_ib_schedule(rdev, &ib, NULL);
3650         if (r) {
3651                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3652                 goto free_ib;
3653         }
3654         r = radeon_fence_wait(ib.fence, false);
3655         if (r) {
3656                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3657                 goto free_ib;
3658         }
3659         for (i = 0; i < rdev->usec_timeout; i++) {
3660                 tmp = RREG32(scratch);
3661                 if (tmp == 0xDEADBEEF)
3662                         break;
3663                 DRM_UDELAY(1);
3664         }
3665         if (i < rdev->usec_timeout) {
3666                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3667         } else {
3668                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3669                           scratch, tmp);
3670                 r = -EINVAL;
3671         }
3672 free_ib:
3673         radeon_ib_free(rdev, &ib);
3674 free_scratch:
3675         radeon_scratch_free(rdev, scratch);
3676         return r;
3677 }
3678
3679 /**
3680  * r600_dma_ib_test - test an IB on the DMA engine
3681  *
3682  * @rdev: radeon_device pointer
3683  * @ring: radeon_ring structure holding ring information
3684  *
3685  * Test a simple IB in the DMA ring (r6xx-SI).
3686  * Returns 0 on success, error on failure.
3687  */
3688 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3689 {
3690         struct radeon_ib ib;
3691         unsigned i;
3692         int r;
3693         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3694         u32 tmp = 0;
3695
3696         if (!ptr) {
3697                 DRM_ERROR("invalid vram scratch pointer\n");
3698                 return -EINVAL;
3699         }
3700
3701         tmp = 0xCAFEDEAD;
3702         writel(tmp, ptr);
3703
3704         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3705         if (r) {
3706                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3707                 return r;
3708         }
3709
3710         ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3711         ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3712         ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3713         ib.ptr[3] = 0xDEADBEEF;
3714         ib.length_dw = 4;
3715
3716         r = radeon_ib_schedule(rdev, &ib, NULL);
3717         if (r) {
3718                 radeon_ib_free(rdev, &ib);
3719                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3720                 return r;
3721         }
3722         r = radeon_fence_wait(ib.fence, false);
3723         if (r) {
3724                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3725                 return r;
3726         }
3727         for (i = 0; i < rdev->usec_timeout; i++) {
3728                 tmp = readl(ptr);
3729                 if (tmp == 0xDEADBEEF)
3730                         break;
3731                 DRM_UDELAY(1);
3732         }
3733         if (i < rdev->usec_timeout) {
3734                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3735         } else {
3736                 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3737                 r = -EINVAL;
3738         }
3739         radeon_ib_free(rdev, &ib);
3740         return r;
3741 }
3742
3743 int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3744 {
3745         struct radeon_fence *fence = NULL;
3746         int r;
3747
3748         r = radeon_set_uvd_clocks(rdev, 53300, 40000);
3749         if (r) {
3750                 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
3751                 return r;
3752         }
3753
3754         r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
3755         if (r) {
3756                 DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
3757                 goto error;
3758         }
3759
3760         r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);
3761         if (r) {
3762                 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
3763                 goto error;
3764         }
3765
3766         r = radeon_fence_wait(fence, false);
3767         if (r) {
3768                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3769                 goto error;
3770         }
3771         DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
3772 error:
3773         radeon_fence_unref(&fence);
3774         radeon_set_uvd_clocks(rdev, 0, 0);
3775         return r;
3776 }
3777
3778 /**
3779  * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3780  *
3781  * @rdev: radeon_device pointer
3782  * @ib: IB object to schedule
3783  *
3784  * Schedule an IB in the DMA ring (r6xx-r7xx).
3785  */
3786 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3787 {
3788         struct radeon_ring *ring = &rdev->ring[ib->ring];
3789
3790         if (rdev->wb.enabled) {
3791                 u32 next_rptr = ring->wptr + 4;
3792                 while ((next_rptr & 7) != 5)
3793                         next_rptr++;
3794                 next_rptr += 3;
3795                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3796                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3797                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3798                 radeon_ring_write(ring, next_rptr);
3799         }
3800
3801         /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3802          * Pad as necessary with NOPs.
3803          */
3804         while ((ring->wptr & 7) != 5)
3805                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3806         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3807         radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3808         radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3809
3810 }
3811
3812 /*
3813  * Interrupts
3814  *
3815  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3816  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3817  * writing to the ring and the GPU consuming, the GPU writes to the ring
3818  * and host consumes.  As the host irq handler processes interrupts, it
3819  * increments the rptr.  When the rptr catches up with the wptr, all the
3820  * current interrupts have been processed.
3821  */
3822
3823 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3824 {
3825         u32 rb_bufsz;
3826
3827         /* Align ring size */
3828         rb_bufsz = drm_order(ring_size / 4);
3829         ring_size = (1 << rb_bufsz) * 4;
3830         rdev->ih.ring_size = ring_size;
3831         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3832         rdev->ih.rptr = 0;
3833 }
3834
3835 int r600_ih_ring_alloc(struct radeon_device *rdev)
3836 {
3837         int r;
3838
3839         /* Allocate ring buffer */
3840         if (rdev->ih.ring_obj == NULL) {
3841                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3842                                      PAGE_SIZE, true,
3843                                      RADEON_GEM_DOMAIN_GTT,
3844                                      NULL, &rdev->ih.ring_obj);
3845                 if (r) {
3846                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3847                         return r;
3848                 }
3849                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3850                 if (unlikely(r != 0))
3851                         return r;
3852                 r = radeon_bo_pin(rdev->ih.ring_obj,
3853                                   RADEON_GEM_DOMAIN_GTT,
3854                                   &rdev->ih.gpu_addr);
3855                 if (r) {
3856                         radeon_bo_unreserve(rdev->ih.ring_obj);
3857                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3858                         return r;
3859                 }
3860                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3861                                    (void **)&rdev->ih.ring);
3862                 radeon_bo_unreserve(rdev->ih.ring_obj);
3863                 if (r) {
3864                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3865                         return r;
3866                 }
3867         }
3868         return 0;
3869 }
3870
3871 void r600_ih_ring_fini(struct radeon_device *rdev)
3872 {
3873         int r;
3874         if (rdev->ih.ring_obj) {
3875                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3876                 if (likely(r == 0)) {
3877                         radeon_bo_kunmap(rdev->ih.ring_obj);
3878                         radeon_bo_unpin(rdev->ih.ring_obj);
3879                         radeon_bo_unreserve(rdev->ih.ring_obj);
3880                 }
3881                 radeon_bo_unref(&rdev->ih.ring_obj);
3882                 rdev->ih.ring = NULL;
3883                 rdev->ih.ring_obj = NULL;
3884         }
3885 }
3886
3887 void r600_rlc_stop(struct radeon_device *rdev)
3888 {
3889
3890         if ((rdev->family >= CHIP_RV770) &&
3891             (rdev->family <= CHIP_RV740)) {
3892                 /* r7xx asics need to soft reset RLC before halting */
3893                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3894                 RREG32(SRBM_SOFT_RESET);
3895                 mdelay(15);
3896                 WREG32(SRBM_SOFT_RESET, 0);
3897                 RREG32(SRBM_SOFT_RESET);
3898         }
3899
3900         WREG32(RLC_CNTL, 0);
3901 }
3902
3903 static void r600_rlc_start(struct radeon_device *rdev)
3904 {
3905         WREG32(RLC_CNTL, RLC_ENABLE);
3906 }
3907
3908 static int r600_rlc_resume(struct radeon_device *rdev)
3909 {
3910         u32 i;
3911         const __be32 *fw_data;
3912
3913         if (!rdev->rlc_fw)
3914                 return -EINVAL;
3915
3916         r600_rlc_stop(rdev);
3917
3918         WREG32(RLC_HB_CNTL, 0);
3919
3920         WREG32(RLC_HB_BASE, 0);
3921         WREG32(RLC_HB_RPTR, 0);
3922         WREG32(RLC_HB_WPTR, 0);
3923         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3924         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3925         WREG32(RLC_MC_CNTL, 0);
3926         WREG32(RLC_UCODE_CNTL, 0);
3927
3928         fw_data = (const __be32 *)rdev->rlc_fw->data;
3929         if (rdev->family >= CHIP_RV770) {
3930                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3931                         WREG32(RLC_UCODE_ADDR, i);
3932                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3933                 }
3934         } else {
3935                 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
3936                         WREG32(RLC_UCODE_ADDR, i);
3937                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3938                 }
3939         }
3940         WREG32(RLC_UCODE_ADDR, 0);
3941
3942         r600_rlc_start(rdev);
3943
3944         return 0;
3945 }
3946
3947 static void r600_enable_interrupts(struct radeon_device *rdev)
3948 {
3949         u32 ih_cntl = RREG32(IH_CNTL);
3950         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3951
3952         ih_cntl |= ENABLE_INTR;
3953         ih_rb_cntl |= IH_RB_ENABLE;
3954         WREG32(IH_CNTL, ih_cntl);
3955         WREG32(IH_RB_CNTL, ih_rb_cntl);
3956         rdev->ih.enabled = true;
3957 }
3958
3959 void r600_disable_interrupts(struct radeon_device *rdev)
3960 {
3961         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3962         u32 ih_cntl = RREG32(IH_CNTL);
3963
3964         ih_rb_cntl &= ~IH_RB_ENABLE;
3965         ih_cntl &= ~ENABLE_INTR;
3966         WREG32(IH_RB_CNTL, ih_rb_cntl);
3967         WREG32(IH_CNTL, ih_cntl);
3968         /* set rptr, wptr to 0 */
3969         WREG32(IH_RB_RPTR, 0);
3970         WREG32(IH_RB_WPTR, 0);
3971         rdev->ih.enabled = false;
3972         rdev->ih.rptr = 0;
3973 }
3974
3975 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3976 {
3977         u32 tmp;
3978
3979         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3980         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3981         WREG32(DMA_CNTL, tmp);
3982         WREG32(GRBM_INT_CNTL, 0);
3983         WREG32(DxMODE_INT_MASK, 0);
3984         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3985         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3986         if (ASIC_IS_DCE3(rdev)) {
3987                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3988                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3989                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3990                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3991                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3992                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3993                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3994                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3995                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3996                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3997                 if (ASIC_IS_DCE32(rdev)) {
3998                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3999                         WREG32(DC_HPD5_INT_CONTROL, tmp);
4000                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4001                         WREG32(DC_HPD6_INT_CONTROL, tmp);
4002                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4003                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
4004                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4005                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
4006                 } else {
4007                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4008                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4009                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4010                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
4011                 }
4012         } else {
4013                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
4014                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
4015                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
4016                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
4017                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
4018                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
4019                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
4020                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
4021                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4022                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4023                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4024                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
4025         }
4026 }
4027
4028 int r600_irq_init(struct radeon_device *rdev)
4029 {
4030         int ret = 0;
4031         int rb_bufsz;
4032         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
4033
4034         /* allocate ring */
4035         ret = r600_ih_ring_alloc(rdev);
4036         if (ret)
4037                 return ret;
4038
4039         /* disable irqs */
4040         r600_disable_interrupts(rdev);
4041
4042         /* init rlc */
4043         if (rdev->family >= CHIP_CEDAR)
4044                 ret = evergreen_rlc_resume(rdev);
4045         else
4046                 ret = r600_rlc_resume(rdev);
4047         if (ret) {
4048                 r600_ih_ring_fini(rdev);
4049                 return ret;
4050         }
4051
4052         /* setup interrupt control */
4053         /* set dummy read address to ring address */
4054         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
4055         interrupt_cntl = RREG32(INTERRUPT_CNTL);
4056         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
4057          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
4058          */
4059         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
4060         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
4061         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
4062         WREG32(INTERRUPT_CNTL, interrupt_cntl);
4063
4064         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
4065         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
4066
4067         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
4068                       IH_WPTR_OVERFLOW_CLEAR |
4069                       (rb_bufsz << 1));
4070
4071         if (rdev->wb.enabled)
4072                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
4073
4074         /* set the writeback address whether it's enabled or not */
4075         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
4076         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
4077
4078         WREG32(IH_RB_CNTL, ih_rb_cntl);
4079
4080         /* set rptr, wptr to 0 */
4081         WREG32(IH_RB_RPTR, 0);
4082         WREG32(IH_RB_WPTR, 0);
4083
4084         /* Default settings for IH_CNTL (disabled at first) */
4085         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
4086         /* RPTR_REARM only works if msi's are enabled */
4087         if (rdev->msi_enabled)
4088                 ih_cntl |= RPTR_REARM;
4089         WREG32(IH_CNTL, ih_cntl);
4090
4091         /* force the active interrupt state to all disabled */
4092         if (rdev->family >= CHIP_CEDAR)
4093                 evergreen_disable_interrupt_state(rdev);
4094         else
4095                 r600_disable_interrupt_state(rdev);
4096
4097         /* at this point everything should be setup correctly to enable master */
4098         pci_set_master(rdev->pdev);
4099
4100         /* enable irqs */
4101         r600_enable_interrupts(rdev);
4102
4103         return ret;
4104 }
4105
4106 void r600_irq_suspend(struct radeon_device *rdev)
4107 {
4108         r600_irq_disable(rdev);
4109         r600_rlc_stop(rdev);
4110 }
4111
4112 void r600_irq_fini(struct radeon_device *rdev)
4113 {
4114         r600_irq_suspend(rdev);
4115         r600_ih_ring_fini(rdev);
4116 }
4117
4118 int r600_irq_set(struct radeon_device *rdev)
4119 {
4120         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
4121         u32 mode_int = 0;
4122         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
4123         u32 grbm_int_cntl = 0;
4124         u32 hdmi0, hdmi1;
4125         u32 d1grph = 0, d2grph = 0;
4126         u32 dma_cntl;
4127         u32 thermal_int = 0;
4128
4129         if (!rdev->irq.installed) {
4130                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
4131                 return -EINVAL;
4132         }
4133         /* don't enable anything if the ih is disabled */
4134         if (!rdev->ih.enabled) {
4135                 r600_disable_interrupts(rdev);
4136                 /* force the active interrupt state to all disabled */
4137                 r600_disable_interrupt_state(rdev);
4138                 return 0;
4139         }
4140
4141         if (ASIC_IS_DCE3(rdev)) {
4142                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
4143                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
4144                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
4145                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
4146                 if (ASIC_IS_DCE32(rdev)) {
4147                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
4148                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
4149                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4150                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4151                 } else {
4152                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4153                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4154                 }
4155         } else {
4156                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
4157                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
4158                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
4159                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4160                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
4161         }
4162
4163         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
4164
4165         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
4166                 thermal_int = RREG32(CG_THERMAL_INT) &
4167                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
4168         } else if (rdev->family >= CHIP_RV770) {
4169                 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
4170                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
4171         }
4172         if (rdev->irq.dpm_thermal) {
4173                 DRM_DEBUG("dpm thermal\n");
4174                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
4175         }
4176
4177         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
4178                 DRM_DEBUG("r600_irq_set: sw int\n");
4179                 cp_int_cntl |= RB_INT_ENABLE;
4180                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
4181         }
4182
4183         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
4184                 DRM_DEBUG("r600_irq_set: sw int dma\n");
4185                 dma_cntl |= TRAP_ENABLE;
4186         }
4187
4188         if (rdev->irq.crtc_vblank_int[0] ||
4189             atomic_read(&rdev->irq.pflip[0])) {
4190                 DRM_DEBUG("r600_irq_set: vblank 0\n");
4191                 mode_int |= D1MODE_VBLANK_INT_MASK;
4192         }
4193         if (rdev->irq.crtc_vblank_int[1] ||
4194             atomic_read(&rdev->irq.pflip[1])) {
4195                 DRM_DEBUG("r600_irq_set: vblank 1\n");
4196                 mode_int |= D2MODE_VBLANK_INT_MASK;
4197         }
4198         if (rdev->irq.hpd[0]) {
4199                 DRM_DEBUG("r600_irq_set: hpd 1\n");
4200                 hpd1 |= DC_HPDx_INT_EN;
4201         }
4202         if (rdev->irq.hpd[1]) {
4203                 DRM_DEBUG("r600_irq_set: hpd 2\n");
4204                 hpd2 |= DC_HPDx_INT_EN;
4205         }
4206         if (rdev->irq.hpd[2]) {
4207                 DRM_DEBUG("r600_irq_set: hpd 3\n");
4208                 hpd3 |= DC_HPDx_INT_EN;
4209         }
4210         if (rdev->irq.hpd[3]) {
4211                 DRM_DEBUG("r600_irq_set: hpd 4\n");
4212                 hpd4 |= DC_HPDx_INT_EN;
4213         }
4214         if (rdev->irq.hpd[4]) {
4215                 DRM_DEBUG("r600_irq_set: hpd 5\n");
4216                 hpd5 |= DC_HPDx_INT_EN;
4217         }
4218         if (rdev->irq.hpd[5]) {
4219                 DRM_DEBUG("r600_irq_set: hpd 6\n");
4220                 hpd6 |= DC_HPDx_INT_EN;
4221         }
4222         if (rdev->irq.afmt[0]) {
4223                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
4224                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
4225         }
4226         if (rdev->irq.afmt[1]) {
4227                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
4228                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
4229         }
4230
4231         WREG32(CP_INT_CNTL, cp_int_cntl);
4232         WREG32(DMA_CNTL, dma_cntl);
4233         WREG32(DxMODE_INT_MASK, mode_int);
4234         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
4235         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
4236         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
4237         if (ASIC_IS_DCE3(rdev)) {
4238                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
4239                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
4240                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
4241                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
4242                 if (ASIC_IS_DCE32(rdev)) {
4243                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
4244                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
4245                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
4246                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
4247                 } else {
4248                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
4249                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
4250                 }
4251         } else {
4252                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
4253                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
4254                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
4255                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
4256                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
4257         }
4258         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
4259                 WREG32(CG_THERMAL_INT, thermal_int);
4260         } else if (rdev->family >= CHIP_RV770) {
4261                 WREG32(RV770_CG_THERMAL_INT, thermal_int);
4262         }
4263
4264         return 0;
4265 }
4266
4267 static void r600_irq_ack(struct radeon_device *rdev)
4268 {
4269         u32 tmp;
4270
4271         if (ASIC_IS_DCE3(rdev)) {
4272                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
4273                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
4274                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
4275                 if (ASIC_IS_DCE32(rdev)) {
4276                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
4277                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
4278                 } else {
4279                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
4280                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
4281                 }
4282         } else {
4283                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
4284                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
4285                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
4286                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
4287                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
4288         }
4289         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
4290         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
4291
4292         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
4293                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
4294         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
4295                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
4296         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
4297                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
4298         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
4299                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
4300         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
4301                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
4302         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
4303                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
4304         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
4305                 if (ASIC_IS_DCE3(rdev)) {
4306                         tmp = RREG32(DC_HPD1_INT_CONTROL);
4307                         tmp |= DC_HPDx_INT_ACK;
4308                         WREG32(DC_HPD1_INT_CONTROL, tmp);
4309                 } else {
4310                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
4311                         tmp |= DC_HPDx_INT_ACK;
4312                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
4313                 }
4314         }
4315         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4316                 if (ASIC_IS_DCE3(rdev)) {
4317                         tmp = RREG32(DC_HPD2_INT_CONTROL);
4318                         tmp |= DC_HPDx_INT_ACK;
4319                         WREG32(DC_HPD2_INT_CONTROL, tmp);
4320                 } else {
4321                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
4322                         tmp |= DC_HPDx_INT_ACK;
4323                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
4324                 }
4325         }
4326         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
4327                 if (ASIC_IS_DCE3(rdev)) {
4328                         tmp = RREG32(DC_HPD3_INT_CONTROL);
4329                         tmp |= DC_HPDx_INT_ACK;
4330                         WREG32(DC_HPD3_INT_CONTROL, tmp);
4331                 } else {
4332                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
4333                         tmp |= DC_HPDx_INT_ACK;
4334                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
4335                 }
4336         }
4337         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
4338                 tmp = RREG32(DC_HPD4_INT_CONTROL);
4339                 tmp |= DC_HPDx_INT_ACK;
4340                 WREG32(DC_HPD4_INT_CONTROL, tmp);
4341         }
4342         if (ASIC_IS_DCE32(rdev)) {
4343                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4344                         tmp = RREG32(DC_HPD5_INT_CONTROL);
4345                         tmp |= DC_HPDx_INT_ACK;
4346                         WREG32(DC_HPD5_INT_CONTROL, tmp);
4347                 }
4348                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4349                         tmp = RREG32(DC_HPD5_INT_CONTROL);
4350                         tmp |= DC_HPDx_INT_ACK;
4351                         WREG32(DC_HPD6_INT_CONTROL, tmp);
4352                 }
4353                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
4354                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
4355                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4356                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
4357                 }
4358                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
4359                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
4360                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4361                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
4362                 }
4363         } else {
4364                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4365                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
4366                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4367                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4368                 }
4369                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4370                         if (ASIC_IS_DCE3(rdev)) {
4371                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
4372                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4373                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
4374                         } else {
4375                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
4376                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4377                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
4378                         }
4379                 }
4380         }
4381 }
4382
4383 void r600_irq_disable(struct radeon_device *rdev)
4384 {
4385         r600_disable_interrupts(rdev);
4386         /* Wait and acknowledge irq */
4387         mdelay(1);
4388         r600_irq_ack(rdev);
4389         r600_disable_interrupt_state(rdev);
4390 }
4391
4392 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
4393 {
4394         u32 wptr, tmp;
4395
4396         if (rdev->wb.enabled)
4397                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4398         else
4399                 wptr = RREG32(IH_RB_WPTR);
4400
4401         if (wptr & RB_OVERFLOW) {
4402                 /* When a ring buffer overflow happen start parsing interrupt
4403                  * from the last not overwritten vector (wptr + 16). Hopefully
4404                  * this should allow us to catchup.
4405                  */
4406                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
4407                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
4408                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4409                 tmp = RREG32(IH_RB_CNTL);
4410                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4411                 WREG32(IH_RB_CNTL, tmp);
4412         }
4413         return (wptr & rdev->ih.ptr_mask);
4414 }
4415
4416 /*        r600 IV Ring
4417  * Each IV ring entry is 128 bits:
4418  * [7:0]    - interrupt source id
4419  * [31:8]   - reserved
4420  * [59:32]  - interrupt source data
4421  * [127:60]  - reserved
4422  *
4423  * The basic interrupt vector entries
4424  * are decoded as follows:
4425  * src_id  src_data  description
4426  *      1         0  D1 Vblank
4427  *      1         1  D1 Vline
4428  *      5         0  D2 Vblank
4429  *      5         1  D2 Vline
4430  *     19         0  FP Hot plug detection A
4431  *     19         1  FP Hot plug detection B
4432  *     19         2  DAC A auto-detection
4433  *     19         3  DAC B auto-detection
4434  *     21         4  HDMI block A
4435  *     21         5  HDMI block B
4436  *    176         -  CP_INT RB
4437  *    177         -  CP_INT IB1
4438  *    178         -  CP_INT IB2
4439  *    181         -  EOP Interrupt
4440  *    233         -  GUI Idle
4441  *
4442  * Note, these are based on r600 and may need to be
4443  * adjusted or added to on newer asics
4444  */
4445
4446 int r600_irq_process(struct radeon_device *rdev)
4447 {
4448         u32 wptr;
4449         u32 rptr;
4450         u32 src_id, src_data;
4451         u32 ring_index;
4452         bool queue_hotplug = false;
4453         bool queue_hdmi = false;
4454         bool queue_thermal = false;
4455
4456         if (!rdev->ih.enabled || rdev->shutdown)
4457                 return IRQ_NONE;
4458
4459         /* No MSIs, need a dummy read to flush PCI DMAs */
4460         if (!rdev->msi_enabled)
4461                 RREG32(IH_RB_WPTR);
4462
4463         wptr = r600_get_ih_wptr(rdev);
4464
4465 restart_ih:
4466         /* is somebody else already processing irqs? */
4467         if (atomic_xchg(&rdev->ih.lock, 1))
4468                 return IRQ_NONE;
4469
4470         rptr = rdev->ih.rptr;
4471         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4472
4473         /* Order reading of wptr vs. reading of IH ring data */
4474         rmb();
4475
4476         /* display interrupts */
4477         r600_irq_ack(rdev);
4478
4479         while (rptr != wptr) {
4480                 /* wptr/rptr are in bytes! */
4481                 ring_index = rptr / 4;
4482                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4483                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4484
4485                 switch (src_id) {
4486                 case 1: /* D1 vblank/vline */
4487                         switch (src_data) {
4488                         case 0: /* D1 vblank */
4489                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
4490                                         if (rdev->irq.crtc_vblank_int[0]) {
4491                                                 drm_handle_vblank(rdev->ddev, 0);
4492                                                 rdev->pm.vblank_sync = true;
4493                                                 wake_up(&rdev->irq.vblank_queue);
4494                                         }
4495                                         if (atomic_read(&rdev->irq.pflip[0]))
4496                                                 radeon_crtc_handle_flip(rdev, 0);
4497                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4498                                         DRM_DEBUG("IH: D1 vblank\n");
4499                                 }
4500                                 break;
4501                         case 1: /* D1 vline */
4502                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
4503                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4504                                         DRM_DEBUG("IH: D1 vline\n");
4505                                 }
4506                                 break;
4507                         default:
4508                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4509                                 break;
4510                         }
4511                         break;
4512                 case 5: /* D2 vblank/vline */
4513                         switch (src_data) {
4514                         case 0: /* D2 vblank */
4515                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
4516                                         if (rdev->irq.crtc_vblank_int[1]) {
4517                                                 drm_handle_vblank(rdev->ddev, 1);
4518                                                 rdev->pm.vblank_sync = true;
4519                                                 wake_up(&rdev->irq.vblank_queue);
4520                                         }
4521                                         if (atomic_read(&rdev->irq.pflip[1]))
4522                                                 radeon_crtc_handle_flip(rdev, 1);
4523                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4524                                         DRM_DEBUG("IH: D2 vblank\n");
4525                                 }
4526                                 break;
4527                         case 1: /* D1 vline */
4528                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
4529                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4530                                         DRM_DEBUG("IH: D2 vline\n");
4531                                 }
4532                                 break;
4533                         default:
4534                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4535                                 break;
4536                         }
4537                         break;
4538                 case 19: /* HPD/DAC hotplug */
4539                         switch (src_data) {
4540                         case 0:
4541                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
4542                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4543                                         queue_hotplug = true;
4544                                         DRM_DEBUG("IH: HPD1\n");
4545                                 }
4546                                 break;
4547                         case 1:
4548                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4549                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4550                                         queue_hotplug = true;
4551                                         DRM_DEBUG("IH: HPD2\n");
4552                                 }
4553                                 break;
4554                         case 4:
4555                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
4556                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4557                                         queue_hotplug = true;
4558                                         DRM_DEBUG("IH: HPD3\n");
4559                                 }
4560                                 break;
4561                         case 5:
4562                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
4563                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4564                                         queue_hotplug = true;
4565                                         DRM_DEBUG("IH: HPD4\n");
4566                                 }
4567                                 break;
4568                         case 10:
4569                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4570                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4571                                         queue_hotplug = true;
4572                                         DRM_DEBUG("IH: HPD5\n");
4573                                 }
4574                                 break;
4575                         case 12:
4576                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4577                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4578                                         queue_hotplug = true;
4579                                         DRM_DEBUG("IH: HPD6\n");
4580                                 }
4581                                 break;
4582                         default:
4583                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4584                                 break;
4585                         }
4586                         break;
4587                 case 21: /* hdmi */
4588                         switch (src_data) {
4589                         case 4:
4590                                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4591                                         rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4592                                         queue_hdmi = true;
4593                                         DRM_DEBUG("IH: HDMI0\n");
4594                                 }
4595                                 break;
4596                         case 5:
4597                                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4598                                         rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4599                                         queue_hdmi = true;
4600                                         DRM_DEBUG("IH: HDMI1\n");
4601                                 }
4602                                 break;
4603                         default:
4604                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4605                                 break;
4606                         }
4607                         break;
4608                 case 176: /* CP_INT in ring buffer */
4609                 case 177: /* CP_INT in IB1 */
4610                 case 178: /* CP_INT in IB2 */
4611                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4612                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4613                         break;
4614                 case 181: /* CP EOP event */
4615                         DRM_DEBUG("IH: CP EOP\n");
4616                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4617                         break;
4618                 case 224: /* DMA trap event */
4619                         DRM_DEBUG("IH: DMA trap\n");
4620                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4621                         break;
4622                 case 230: /* thermal low to high */
4623                         DRM_DEBUG("IH: thermal low to high\n");
4624                         rdev->pm.dpm.thermal.high_to_low = false;
4625                         queue_thermal = true;
4626                         break;
4627                 case 231: /* thermal high to low */
4628                         DRM_DEBUG("IH: thermal high to low\n");
4629                         rdev->pm.dpm.thermal.high_to_low = true;
4630                         queue_thermal = true;
4631                         break;
4632                 case 233: /* GUI IDLE */
4633                         DRM_DEBUG("IH: GUI idle\n");
4634                         break;
4635                 default:
4636                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4637                         break;
4638                 }
4639
4640                 /* wptr/rptr are in bytes! */
4641                 rptr += 16;
4642                 rptr &= rdev->ih.ptr_mask;
4643         }
4644         if (queue_hotplug)
4645                 schedule_work(&rdev->hotplug_work);
4646         if (queue_hdmi)
4647                 schedule_work(&rdev->audio_work);
4648         if (queue_thermal && rdev->pm.dpm_enabled)
4649                 schedule_work(&rdev->pm.dpm.thermal.work);
4650         rdev->ih.rptr = rptr;
4651         WREG32(IH_RB_RPTR, rdev->ih.rptr);
4652         atomic_set(&rdev->ih.lock, 0);
4653
4654         /* make sure wptr hasn't changed while processing */
4655         wptr = r600_get_ih_wptr(rdev);
4656         if (wptr != rptr)
4657                 goto restart_ih;
4658
4659         return IRQ_HANDLED;
4660 }
4661
4662 /*
4663  * Debugfs info
4664  */
4665 #if defined(CONFIG_DEBUG_FS)
4666
4667 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4668 {
4669         struct drm_info_node *node = (struct drm_info_node *) m->private;
4670         struct drm_device *dev = node->minor->dev;
4671         struct radeon_device *rdev = dev->dev_private;
4672
4673         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4674         DREG32_SYS(m, rdev, VM_L2_STATUS);
4675         return 0;
4676 }
4677
4678 static struct drm_info_list r600_mc_info_list[] = {
4679         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4680 };
4681 #endif
4682
4683 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4684 {
4685 #if defined(CONFIG_DEBUG_FS)
4686         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4687 #else
4688         return 0;
4689 #endif
4690 }
4691
4692 /**
4693  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4694  * rdev: radeon device structure
4695  * bo: buffer object struct which userspace is waiting for idle
4696  *
4697  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4698  * through ring buffer, this leads to corruption in rendering, see
4699  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4700  * directly perform HDP flush by writing register through MMIO.
4701  */
4702 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4703 {
4704         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4705          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4706          * This seems to cause problems on some AGP cards. Just use the old
4707          * method for them.
4708          */
4709         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4710             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4711                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4712                 u32 tmp;
4713
4714                 WREG32(HDP_DEBUG1, 0);
4715                 tmp = readl((void __iomem *)ptr);
4716         } else
4717                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4718 }
4719
4720 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4721 {
4722         u32 link_width_cntl, mask;
4723
4724         if (rdev->flags & RADEON_IS_IGP)
4725                 return;
4726
4727         if (!(rdev->flags & RADEON_IS_PCIE))
4728                 return;
4729
4730         /* x2 cards have a special sequence */
4731         if (ASIC_IS_X2(rdev))
4732                 return;
4733
4734         radeon_gui_idle(rdev);
4735
4736         switch (lanes) {
4737         case 0:
4738                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4739                 break;
4740         case 1:
4741                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4742                 break;
4743         case 2:
4744                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4745                 break;
4746         case 4:
4747                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4748                 break;
4749         case 8:
4750                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4751                 break;
4752         case 12:
4753                 /* not actually supported */
4754                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4755                 break;
4756         case 16:
4757                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4758                 break;
4759         default:
4760                 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4761                 return;
4762         }
4763
4764         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4765         link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4766         link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4767         link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4768                             R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4769
4770         WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4771 }
4772
4773 int r600_get_pcie_lanes(struct radeon_device *rdev)
4774 {
4775         u32 link_width_cntl;
4776
4777         if (rdev->flags & RADEON_IS_IGP)
4778                 return 0;
4779
4780         if (!(rdev->flags & RADEON_IS_PCIE))
4781                 return 0;
4782
4783         /* x2 cards have a special sequence */
4784         if (ASIC_IS_X2(rdev))
4785                 return 0;
4786
4787         radeon_gui_idle(rdev);
4788
4789         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4790
4791         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4792         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4793                 return 1;
4794         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4795                 return 2;
4796         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4797                 return 4;
4798         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4799                 return 8;
4800         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4801                 /* not actually supported */
4802                 return 12;
4803         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4804         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4805         default:
4806                 return 16;
4807         }
4808 }
4809
4810 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4811 {
4812         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4813         u16 link_cntl2;
4814
4815         if (radeon_pcie_gen2 == 0)
4816                 return;
4817
4818         if (rdev->flags & RADEON_IS_IGP)
4819                 return;
4820
4821         if (!(rdev->flags & RADEON_IS_PCIE))
4822                 return;
4823
4824         /* x2 cards have a special sequence */
4825         if (ASIC_IS_X2(rdev))
4826                 return;
4827
4828         /* only RV6xx+ chips are supported */
4829         if (rdev->family <= CHIP_R600)
4830                 return;
4831
4832         if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4833                 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4834                 return;
4835
4836         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4837         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4838                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4839                 return;
4840         }
4841
4842         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4843
4844         /* 55 nm r6xx asics */
4845         if ((rdev->family == CHIP_RV670) ||
4846             (rdev->family == CHIP_RV620) ||
4847             (rdev->family == CHIP_RV635)) {
4848                 /* advertise upconfig capability */
4849                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4850                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4851                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4852                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4853                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4854                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4855                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4856                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4857                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4858                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4859                 } else {
4860                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4861                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4862                 }
4863         }
4864
4865         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4866         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4867             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4868
4869                 /* 55 nm r6xx asics */
4870                 if ((rdev->family == CHIP_RV670) ||
4871                     (rdev->family == CHIP_RV620) ||
4872                     (rdev->family == CHIP_RV635)) {
4873                         WREG32(MM_CFGREGS_CNTL, 0x8);
4874                         link_cntl2 = RREG32(0x4088);
4875                         WREG32(MM_CFGREGS_CNTL, 0);
4876                         /* not supported yet */
4877                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4878                                 return;
4879                 }
4880
4881                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4882                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4883                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4884                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4885                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4886                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4887
4888                 tmp = RREG32(0x541c);
4889                 WREG32(0x541c, tmp | 0x8);
4890                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4891                 link_cntl2 = RREG16(0x4088);
4892                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4893                 link_cntl2 |= 0x2;
4894                 WREG16(0x4088, link_cntl2);
4895                 WREG32(MM_CFGREGS_CNTL, 0);
4896
4897                 if ((rdev->family == CHIP_RV670) ||
4898                     (rdev->family == CHIP_RV620) ||
4899                     (rdev->family == CHIP_RV635)) {
4900                         training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4901                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4902                         WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4903                 } else {
4904                         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4905                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4906                         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4907                 }
4908
4909                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4910                 speed_cntl |= LC_GEN2_EN_STRAP;
4911                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4912
4913         } else {
4914                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4915                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4916                 if (1)
4917                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4918                 else
4919                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4920                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4921         }
4922 }
4923
4924 /**
4925  * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4926  *
4927  * @rdev: radeon_device pointer
4928  *
4929  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4930  * Returns the 64 bit clock counter snapshot.
4931  */
4932 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4933 {
4934         uint64_t clock;
4935
4936         mutex_lock(&rdev->gpu_clock_mutex);
4937         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4938         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4939                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4940         mutex_unlock(&rdev->gpu_clock_mutex);
4941         return clock;
4942 }