drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/radeon_drm.h>
  35 #include "radeon.h"
  36 #include "radeon_asic.h"
  37 #include "radeon_mode.h"
  38 #include "r600d.h"
  39 #include "atom.h"
  40 #include "avivod.h"
  41
  42 #define PFP_UCODE_SIZE 576
  43 #define PM4_UCODE_SIZE 1792
  44 #define RLC_UCODE_SIZE 768
  45 #define R700_PFP_UCODE_SIZE 848
  46 #define R700_PM4_UCODE_SIZE 1360
  47 #define R700_RLC_UCODE_SIZE 1024
  48 #define EVERGREEN_PFP_UCODE_SIZE 1120
  49 #define EVERGREEN_PM4_UCODE_SIZE 1376
  50 #define EVERGREEN_RLC_UCODE_SIZE 768
  51 #define CAYMAN_RLC_UCODE_SIZE 1024
  52 #define ARUBA_RLC_UCODE_SIZE 1536
  53
  54 /* Firmware Names */
  55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  56 MODULE_FIRMWARE("radeon/R600_me.bin");
  57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV610_me.bin");
  59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RV630_me.bin");
  61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV620_me.bin");
  63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV635_me.bin");
  65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RV670_me.bin");
  67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  68 MODULE_FIRMWARE("radeon/RS780_me.bin");
  69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  70 MODULE_FIRMWARE("radeon/RV770_me.bin");
  71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  72 MODULE_FIRMWARE("radeon/RV730_me.bin");
  73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  74 MODULE_FIRMWARE("radeon/RV710_me.bin");
  75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  90 MODULE_FIRMWARE("radeon/PALM_me.bin");
  91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  96
  97 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  98
  99 /* r600,rv610,rv630,rv620,rv635,rv670 */
 100 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 101 static void r600_gpu_init(struct radeon_device *rdev);
 102 void r600_fini(struct radeon_device *rdev);
 103 void r600_irq_disable(struct radeon_device *rdev);
 104 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 105
 106 /* get temperature in millidegrees */
 107 int rv6xx_get_temp(struct radeon_device *rdev)
 108 {
 109         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 110                 ASIC_T_SHIFT;
 111         int actual_temp = temp & 0xff;
 112
 113         if (temp & 0x100)
 114                 actual_temp -= 256;
 115
 116         return actual_temp * 1000;
 117 }
 118
 119 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 120 {
 121         int i;
 122
 123         rdev->pm.dynpm_can_upclock = true;
 124         rdev->pm.dynpm_can_downclock = true;
 125
 126         /* power state array is low to high, default is first */
 127         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 128                 int min_power_state_index = 0;
 129
 130                 if (rdev->pm.num_power_states > 2)
 131                         min_power_state_index = 1;
 132
 133                 switch (rdev->pm.dynpm_planned_action) {
 134                 case DYNPM_ACTION_MINIMUM:
 135                         rdev->pm.requested_power_state_index = min_power_state_index;
 136                         rdev->pm.requested_clock_mode_index = 0;
 137                         rdev->pm.dynpm_can_downclock = false;
 138                         break;
 139                 case DYNPM_ACTION_DOWNCLOCK:
 140                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 141                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 142                                 rdev->pm.dynpm_can_downclock = false;
 143                         } else {
 144                                 if (rdev->pm.active_crtc_count > 1) {
 145                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 146                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 147                                                         continue;
 148                                                 else if (i >= rdev->pm.current_power_state_index) {
 149                                                         rdev->pm.requested_power_state_index =
 150                                                                 rdev->pm.current_power_state_index;
 151                                                         break;
 152                                                 } else {
 153                                                         rdev->pm.requested_power_state_index = i;
 154                                                         break;
 155                                                 }
 156                                         }
 157                                 } else {
 158                                         if (rdev->pm.current_power_state_index == 0)
 159                                                 rdev->pm.requested_power_state_index =
 160                                                         rdev->pm.num_power_states - 1;
 161                                         else
 162                                                 rdev->pm.requested_power_state_index =
 163                                                         rdev->pm.current_power_state_index - 1;
 164                                 }
 165                         }
 166                         rdev->pm.requested_clock_mode_index = 0;
 167                         /* don't use the power state if crtcs are active and no display flag is set */
 168                         if ((rdev->pm.active_crtc_count > 0) &&
 169                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 170                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 171                              RADEON_PM_MODE_NO_DISPLAY)) {
 172                                 rdev->pm.requested_power_state_index++;
 173                         }
 174                         break;
 175                 case DYNPM_ACTION_UPCLOCK:
 176                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 177                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 178                                 rdev->pm.dynpm_can_upclock = false;
 179                         } else {
 180                                 if (rdev->pm.active_crtc_count > 1) {
 181                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 182                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 183                                                         continue;
 184                                                 else if (i <= rdev->pm.current_power_state_index) {
 185                                                         rdev->pm.requested_power_state_index =
 186                                                                 rdev->pm.current_power_state_index;
 187                                                         break;
 188                                                 } else {
 189                                                         rdev->pm.requested_power_state_index = i;
 190                                                         break;
 191                                                 }
 192                                         }
 193                                 } else
 194                                         rdev->pm.requested_power_state_index =
 195                                                 rdev->pm.current_power_state_index + 1;
 196                         }
 197                         rdev->pm.requested_clock_mode_index = 0;
 198                         break;
 199                 case DYNPM_ACTION_DEFAULT:
 200                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 201                         rdev->pm.requested_clock_mode_index = 0;
 202                         rdev->pm.dynpm_can_upclock = false;
 203                         break;
 204                 case DYNPM_ACTION_NONE:
 205                 default:
 206                         DRM_ERROR("Requested mode for not defined action\n");
 207                         return;
 208                 }
 209         } else {
 210                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 211                 /* for now just select the first power state and switch between clock modes */
 212                 /* power state array is low to high, default is first (0) */
 213                 if (rdev->pm.active_crtc_count > 1) {
 214                         rdev->pm.requested_power_state_index = -1;
 215                         /* start at 1 as we don't want the default mode */
 216                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 217                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 218                                         continue;
 219                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 220                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 221                                         rdev->pm.requested_power_state_index = i;
 222                                         break;
 223                                 }
 224                         }
 225                         /* if nothing selected, grab the default state. */
 226                         if (rdev->pm.requested_power_state_index == -1)
 227                                 rdev->pm.requested_power_state_index = 0;
 228                 } else
 229                         rdev->pm.requested_power_state_index = 1;
 230
 231                 switch (rdev->pm.dynpm_planned_action) {
 232                 case DYNPM_ACTION_MINIMUM:
 233                         rdev->pm.requested_clock_mode_index = 0;
 234                         rdev->pm.dynpm_can_downclock = false;
 235                         break;
 236                 case DYNPM_ACTION_DOWNCLOCK:
 237                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 238                                 if (rdev->pm.current_clock_mode_index == 0) {
 239                                         rdev->pm.requested_clock_mode_index = 0;
 240                                         rdev->pm.dynpm_can_downclock = false;
 241                                 } else
 242                                         rdev->pm.requested_clock_mode_index =
 243                                                 rdev->pm.current_clock_mode_index - 1;
 244                         } else {
 245                                 rdev->pm.requested_clock_mode_index = 0;
 246                                 rdev->pm.dynpm_can_downclock = false;
 247                         }
 248                         /* don't use the power state if crtcs are active and no display flag is set */
 249                         if ((rdev->pm.active_crtc_count > 0) &&
 250                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 251                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 252                              RADEON_PM_MODE_NO_DISPLAY)) {
 253                                 rdev->pm.requested_clock_mode_index++;
 254                         }
 255                         break;
 256                 case DYNPM_ACTION_UPCLOCK:
 257                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 258                                 if (rdev->pm.current_clock_mode_index ==
 259                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 260                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 261                                         rdev->pm.dynpm_can_upclock = false;
 262                                 } else
 263                                         rdev->pm.requested_clock_mode_index =
 264                                                 rdev->pm.current_clock_mode_index + 1;
 265                         } else {
 266                                 rdev->pm.requested_clock_mode_index =
 267                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 268                                 rdev->pm.dynpm_can_upclock = false;
 269                         }
 270                         break;
 271                 case DYNPM_ACTION_DEFAULT:
 272                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 273                         rdev->pm.requested_clock_mode_index = 0;
 274                         rdev->pm.dynpm_can_upclock = false;
 275                         break;
 276                 case DYNPM_ACTION_NONE:
 277                 default:
 278                         DRM_ERROR("Requested mode for not defined action\n");
 279                         return;
 280                 }
 281         }
 282
 283         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 284                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 285                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 286                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 287                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 288                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 289                   pcie_lanes);
 290 }
 291
 292 void rs780_pm_init_profile(struct radeon_device *rdev)
 293 {
 294         if (rdev->pm.num_power_states == 2) {
 295                 /* default */
 296                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 297                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 298                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 299                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 300                 /* low sh */
 301                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 302                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 303                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 304                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 305                 /* mid sh */
 306                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 307                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 309                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 310                 /* high sh */
 311                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 312                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 313                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 314                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 315                 /* low mh */
 316                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 317                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 319                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 320                 /* mid mh */
 321                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 322                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 325                 /* high mh */
 326                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 327                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 328                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 330         } else if (rdev->pm.num_power_states == 3) {
 331                 /* default */
 332                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 333                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 334                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 336                 /* low sh */
 337                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 338                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 339                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 340                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 341                 /* mid sh */
 342                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 343                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 344                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 345                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 346                 /* high sh */
 347                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 348                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 349                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 350                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 351                 /* low mh */
 352                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 353                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 354                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 355                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 356                 /* mid mh */
 357                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 358                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 359                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 360                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 361                 /* high mh */
 362                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 363                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 364                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 365                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 366         } else {
 367                 /* default */
 368                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 369                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 370                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 371                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 372                 /* low sh */
 373                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 374                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 375                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 376                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 377                 /* mid sh */
 378                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 379                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 380                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 381                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 382                 /* high sh */
 383                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 384                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 385                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 386                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 387                 /* low mh */
 388                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 389                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 391                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 392                 /* mid mh */
 393                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 394                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 395                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 396                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 397                 /* high mh */
 398                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 399                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 400                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 401                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 402         }
 403 }
 404
 405 void r600_pm_init_profile(struct radeon_device *rdev)
 406 {
 407         int idx;
 408
 409         if (rdev->family == CHIP_R600) {
 410                 /* XXX */
 411                 /* default */
 412                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 413                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 414                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 415                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 416                 /* low sh */
 417                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 418                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 419                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 420                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 421                 /* mid sh */
 422                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 423                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 424                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 425                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 426                 /* high sh */
 427                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 428                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 429                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 430                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 431                 /* low mh */
 432                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 433                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 434                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 435                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 436                 /* mid mh */
 437                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 438                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 439                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 440                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 441                 /* high mh */
 442                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 443                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 444                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 445                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 446         } else {
 447                 if (rdev->pm.num_power_states < 4) {
 448                         /* default */
 449                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 450                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 451                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 452                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 453                         /* low sh */
 454                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 455                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 456                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 457                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 458                         /* mid sh */
 459                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 460                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 461                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 462                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 463                         /* high sh */
 464                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 465                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 466                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 467                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 468                         /* low mh */
 469                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 470                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 471                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 472                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 473                         /* low mh */
 474                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 475                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 476                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 477                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 478                         /* high mh */
 479                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 480                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 481                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 482                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 483                 } else {
 484                         /* default */
 485                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 486                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 487                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 488                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 489                         /* low sh */
 490                         if (rdev->flags & RADEON_IS_MOBILITY)
 491                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 492                         else
 493                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 494                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 495                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 496                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 497                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 498                         /* mid sh */
 499                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 500                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 501                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 502                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 503                         /* high sh */
 504                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 505                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 506                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 507                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 508                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 509                         /* low mh */
 510                         if (rdev->flags & RADEON_IS_MOBILITY)
 511                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 512                         else
 513                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 514                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 515                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 516                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 517                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 518                         /* mid mh */
 519                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 520                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 521                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 522                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 523                         /* high mh */
 524                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 525                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 526                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 527                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 528                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 529                 }
 530         }
 531 }
 532
 533 void r600_pm_misc(struct radeon_device *rdev)
 534 {
 535         int req_ps_idx = rdev->pm.requested_power_state_index;
 536         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 537         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 538         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 539
 540         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 541                 /* 0xff01 is a flag rather then an actual voltage */
 542                 if (voltage->voltage == 0xff01)
 543                         return;
 544                 if (voltage->voltage != rdev->pm.current_vddc) {
 545                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 546                         rdev->pm.current_vddc = voltage->voltage;
 547                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 548                 }
 549         }
 550 }
 551
 552 bool r600_gui_idle(struct radeon_device *rdev)
 553 {
 554         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 555                 return false;
 556         else
 557                 return true;
 558 }
 559
 560 /* hpd for digital panel detect/disconnect */
 561 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 562 {
 563         bool connected = false;
 564
 565         if (ASIC_IS_DCE3(rdev)) {
 566                 switch (hpd) {
 567                 case RADEON_HPD_1:
 568                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 569                                 connected = true;
 570                         break;
 571                 case RADEON_HPD_2:
 572                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 573                                 connected = true;
 574                         break;
 575                 case RADEON_HPD_3:
 576                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 577                                 connected = true;
 578                         break;
 579                 case RADEON_HPD_4:
 580                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 581                                 connected = true;
 582                         break;
 583                         /* DCE 3.2 */
 584                 case RADEON_HPD_5:
 585                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 586                                 connected = true;
 587                         break;
 588                 case RADEON_HPD_6:
 589                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 590                                 connected = true;
 591                         break;
 592                 default:
 593                         break;
 594                 }
 595         } else {
 596                 switch (hpd) {
 597                 case RADEON_HPD_1:
 598                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 599                                 connected = true;
 600                         break;
 601                 case RADEON_HPD_2:
 602                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 603                                 connected = true;
 604                         break;
 605                 case RADEON_HPD_3:
 606                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 607                                 connected = true;
 608                         break;
 609                 default:
 610                         break;
 611                 }
 612         }
 613         return connected;
 614 }
 615
 616 void r600_hpd_set_polarity(struct radeon_device *rdev,
 617                            enum radeon_hpd_id hpd)
 618 {
 619         u32 tmp;
 620         bool connected = r600_hpd_sense(rdev, hpd);
 621
 622         if (ASIC_IS_DCE3(rdev)) {
 623                 switch (hpd) {
 624                 case RADEON_HPD_1:
 625                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 626                         if (connected)
 627                                 tmp &= ~DC_HPDx_INT_POLARITY;
 628                         else
 629                                 tmp |= DC_HPDx_INT_POLARITY;
 630                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 631                         break;
 632                 case RADEON_HPD_2:
 633                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 634                         if (connected)
 635                                 tmp &= ~DC_HPDx_INT_POLARITY;
 636                         else
 637                                 tmp |= DC_HPDx_INT_POLARITY;
 638                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 639                         break;
 640                 case RADEON_HPD_3:
 641                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 642                         if (connected)
 643                                 tmp &= ~DC_HPDx_INT_POLARITY;
 644                         else
 645                                 tmp |= DC_HPDx_INT_POLARITY;
 646                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 647                         break;
 648                 case RADEON_HPD_4:
 649                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 650                         if (connected)
 651                                 tmp &= ~DC_HPDx_INT_POLARITY;
 652                         else
 653                                 tmp |= DC_HPDx_INT_POLARITY;
 654                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 655                         break;
 656                 case RADEON_HPD_5:
 657                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 658                         if (connected)
 659                                 tmp &= ~DC_HPDx_INT_POLARITY;
 660                         else
 661                                 tmp |= DC_HPDx_INT_POLARITY;
 662                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 663                         break;
 664                         /* DCE 3.2 */
 665                 case RADEON_HPD_6:
 666                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 667                         if (connected)
 668                                 tmp &= ~DC_HPDx_INT_POLARITY;
 669                         else
 670                                 tmp |= DC_HPDx_INT_POLARITY;
 671                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 672                         break;
 673                 default:
 674                         break;
 675                 }
 676         } else {
 677                 switch (hpd) {
 678                 case RADEON_HPD_1:
 679                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 680                         if (connected)
 681                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 682                         else
 683                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 684                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 685                         break;
 686                 case RADEON_HPD_2:
 687                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 688                         if (connected)
 689                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 690                         else
 691                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 692                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 693                         break;
 694                 case RADEON_HPD_3:
 695                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 696                         if (connected)
 697                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 698                         else
 699                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 700                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 701                         break;
 702                 default:
 703                         break;
 704                 }
 705         }
 706 }
 707
 708 void r600_hpd_init(struct radeon_device *rdev)
 709 {
 710         struct drm_device *dev = rdev->ddev;
 711         struct drm_connector *connector;
 712         unsigned enable = 0;
 713
 714         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 715                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 716
 717                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 718                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 719                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 720                          * aux dp channel on imac and help (but not completely fix)
 721                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 722                          */
 723                         continue;
 724                 }
 725                 if (ASIC_IS_DCE3(rdev)) {
 726                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 727                         if (ASIC_IS_DCE32(rdev))
 728                                 tmp |= DC_HPDx_EN;
 729
 730                         switch (radeon_connector->hpd.hpd) {
 731                         case RADEON_HPD_1:
 732                                 WREG32(DC_HPD1_CONTROL, tmp);
 733                                 break;
 734                         case RADEON_HPD_2:
 735                                 WREG32(DC_HPD2_CONTROL, tmp);
 736                                 break;
 737                         case RADEON_HPD_3:
 738                                 WREG32(DC_HPD3_CONTROL, tmp);
 739                                 break;
 740                         case RADEON_HPD_4:
 741                                 WREG32(DC_HPD4_CONTROL, tmp);
 742                                 break;
 743                                 /* DCE 3.2 */
 744                         case RADEON_HPD_5:
 745                                 WREG32(DC_HPD5_CONTROL, tmp);
 746                                 break;
 747                         case RADEON_HPD_6:
 748                                 WREG32(DC_HPD6_CONTROL, tmp);
 749                                 break;
 750                         default:
 751                                 break;
 752                         }
 753                 } else {
 754                         switch (radeon_connector->hpd.hpd) {
 755                         case RADEON_HPD_1:
 756                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 757                                 break;
 758                         case RADEON_HPD_2:
 759                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 760                                 break;
 761                         case RADEON_HPD_3:
 762                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 763                                 break;
 764                         default:
 765                                 break;
 766                         }
 767                 }
 768                 enable |= 1 << radeon_connector->hpd.hpd;
 769                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 770         }
 771         radeon_irq_kms_enable_hpd(rdev, enable);
 772 }
 773
 774 void r600_hpd_fini(struct radeon_device *rdev)
 775 {
 776         struct drm_device *dev = rdev->ddev;
 777         struct drm_connector *connector;
 778         unsigned disable = 0;
 779
 780         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 781                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 782                 if (ASIC_IS_DCE3(rdev)) {
 783                         switch (radeon_connector->hpd.hpd) {
 784                         case RADEON_HPD_1:
 785                                 WREG32(DC_HPD1_CONTROL, 0);
 786                                 break;
 787                         case RADEON_HPD_2:
 788                                 WREG32(DC_HPD2_CONTROL, 0);
 789                                 break;
 790                         case RADEON_HPD_3:
 791                                 WREG32(DC_HPD3_CONTROL, 0);
 792                                 break;
 793                         case RADEON_HPD_4:
 794                                 WREG32(DC_HPD4_CONTROL, 0);
 795                                 break;
 796                                 /* DCE 3.2 */
 797                         case RADEON_HPD_5:
 798                                 WREG32(DC_HPD5_CONTROL, 0);
 799                                 break;
 800                         case RADEON_HPD_6:
 801                                 WREG32(DC_HPD6_CONTROL, 0);
 802                                 break;
 803                         default:
 804                                 break;
 805                         }
 806                 } else {
 807                         switch (radeon_connector->hpd.hpd) {
 808                         case RADEON_HPD_1:
 809                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 810                                 break;
 811                         case RADEON_HPD_2:
 812                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 813                                 break;
 814                         case RADEON_HPD_3:
 815                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 816                                 break;
 817                         default:
 818                                 break;
 819                         }
 820                 }
 821                 disable |= 1 << radeon_connector->hpd.hpd;
 822         }
 823         radeon_irq_kms_disable_hpd(rdev, disable);
 824 }
 825
 826 /*
 827  * R600 PCIE GART
 828  */
 829 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 830 {
 831         unsigned i;
 832         u32 tmp;
 833
 834         /* flush hdp cache so updates hit vram */
 835         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 836             !(rdev->flags & RADEON_IS_AGP)) {
 837                 void __iomem *ptr = (void *)rdev->gart.ptr;
 838                 u32 tmp;
 839
 840                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 841                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 842                  * This seems to cause problems on some AGP cards. Just use the old
 843                  * method for them.
 844                  */
 845                 WREG32(HDP_DEBUG1, 0);
 846                 tmp = readl((void __iomem *)ptr);
 847         } else
 848                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 849
 850         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 851         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 852         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 853         for (i = 0; i < rdev->usec_timeout; i++) {
 854                 /* read MC_STATUS */
 855                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 856                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 857                 if (tmp == 2) {
 858                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 859                         return;
 860                 }
 861                 if (tmp) {
 862                         return;
 863                 }
 864                 udelay(1);
 865         }
 866 }
 867
 868 int r600_pcie_gart_init(struct radeon_device *rdev)
 869 {
 870         int r;
 871
 872         if (rdev->gart.robj) {
 873                 WARN(1, "R600 PCIE GART already initialized\n");
 874                 return 0;
 875         }
 876         /* Initialize common gart structure */
 877         r = radeon_gart_init(rdev);
 878         if (r)
 879                 return r;
 880         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 881         return radeon_gart_table_vram_alloc(rdev);
 882 }
 883
 884 static int r600_pcie_gart_enable(struct radeon_device *rdev)
 885 {
 886         u32 tmp;
 887         int r, i;
 888
 889         if (rdev->gart.robj == NULL) {
 890                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 891                 return -EINVAL;
 892         }
 893         r = radeon_gart_table_vram_pin(rdev);
 894         if (r)
 895                 return r;
 896         radeon_gart_restore(rdev);
 897
 898         /* Setup L2 cache */
 899         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 900                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 901                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 902         WREG32(VM_L2_CNTL2, 0);
 903         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 904         /* Setup TLB control */
 905         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 906                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 907                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 908                 ENABLE_WAIT_L2_QUERY;
 909         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 910         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 911         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 912         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 913         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 914         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 915         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 916         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 917         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 918         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 919         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 920         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 921         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 922         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 923         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 924         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 925         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 926         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 927                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 928         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 929                         (u32)(rdev->dummy_page.addr >> 12));
 930         for (i = 1; i < 7; i++)
 931                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 932
 933         r600_pcie_gart_tlb_flush(rdev);
 934         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 935                  (unsigned)(rdev->mc.gtt_size >> 20),
 936                  (unsigned long long)rdev->gart.table_addr);
 937         rdev->gart.ready = true;
 938         return 0;
 939 }
 940
 941 static void r600_pcie_gart_disable(struct radeon_device *rdev)
 942 {
 943         u32 tmp;
 944         int i;
 945
 946         /* Disable all tables */
 947         for (i = 0; i < 7; i++)
 948                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 949
 950         /* Disable L2 cache */
 951         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 952                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 953         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 954         /* Setup L1 TLB control */
 955         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 956                 ENABLE_WAIT_L2_QUERY;
 957         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 958         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 959         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 960         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 961         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 962         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 963         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 966         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 967         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 968         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 971         radeon_gart_table_vram_unpin(rdev);
 972 }
 973
 974 static void r600_pcie_gart_fini(struct radeon_device *rdev)
 975 {
 976         radeon_gart_fini(rdev);
 977         r600_pcie_gart_disable(rdev);
 978         radeon_gart_table_vram_free(rdev);
 979 }
 980
 981 static void r600_agp_enable(struct radeon_device *rdev)
 982 {
 983         u32 tmp;
 984         int i;
 985
 986         /* Setup L2 cache */
 987         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 988                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 989                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 990         WREG32(VM_L2_CNTL2, 0);
 991         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 992         /* Setup TLB control */
 993         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 994                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 995                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 996                 ENABLE_WAIT_L2_QUERY;
 997         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 998         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 999         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1000         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1001         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1002         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1003         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1004         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1005         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1006         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1007         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1008         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1010         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1011         for (i = 0; i < 7; i++)
1012                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1013 }
1014
1015 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1016 {
1017         unsigned i;
1018         u32 tmp;
1019
1020         for (i = 0; i < rdev->usec_timeout; i++) {
1021                 /* read MC_STATUS */
1022                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1023                 if (!tmp)
1024                         return 0;
1025                 udelay(1);
1026         }
1027         return -1;
1028 }
1029
1030 static void r600_mc_program(struct radeon_device *rdev)
1031 {
1032         struct rv515_mc_save save;
1033         u32 tmp;
1034         int i, j;
1035
1036         /* Initialize HDP */
1037         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1038                 WREG32((0x2c14 + j), 0x00000000);
1039                 WREG32((0x2c18 + j), 0x00000000);
1040                 WREG32((0x2c1c + j), 0x00000000);
1041                 WREG32((0x2c20 + j), 0x00000000);
1042                 WREG32((0x2c24 + j), 0x00000000);
1043         }
1044         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1045
1046         rv515_mc_stop(rdev, &save);
1047         if (r600_mc_wait_for_idle(rdev)) {
1048                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1049         }
1050         /* Lockout access through VGA aperture (doesn't exist before R600) */
1051         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1052         /* Update configuration */
1053         if (rdev->flags & RADEON_IS_AGP) {
1054                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1055                         /* VRAM before AGP */
1056                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1057                                 rdev->mc.vram_start >> 12);
1058                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1059                                 rdev->mc.gtt_end >> 12);
1060                 } else {
1061                         /* VRAM after AGP */
1062                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1063                                 rdev->mc.gtt_start >> 12);
1064                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1065                                 rdev->mc.vram_end >> 12);
1066                 }
1067         } else {
1068                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1069                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1070         }
1071         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1072         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1073         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1074         WREG32(MC_VM_FB_LOCATION, tmp);
1075         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1076         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1077         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1078         if (rdev->flags & RADEON_IS_AGP) {
1079                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1080                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1081                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1082         } else {
1083                 WREG32(MC_VM_AGP_BASE, 0);
1084                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1085                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1086         }
1087         if (r600_mc_wait_for_idle(rdev)) {
1088                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1089         }
1090         rv515_mc_resume(rdev, &save);
1091         /* we need to own VRAM, so turn off the VGA renderer here
1092          * to stop it overwriting our objects */
1093         rv515_vga_render_disable(rdev);
1094 }
1095
1096 /**
1097  * r600_vram_gtt_location - try to find VRAM & GTT location
1098  * @rdev: radeon device structure holding all necessary informations
1099  * @mc: memory controller structure holding memory informations
1100  *
1101  * Function will place try to place VRAM at same place as in CPU (PCI)
1102  * address space as some GPU seems to have issue when we reprogram at
1103  * different address space.
1104  *
1105  * If there is not enough space to fit the unvisible VRAM after the
1106  * aperture then we limit the VRAM size to the aperture.
1107  *
1108  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1109  * them to be in one from GPU point of view so that we can program GPU to
1110  * catch access outside them (weird GPU policy see ??).
1111  *
1112  * This function will never fails, worst case are limiting VRAM or GTT.
1113  *
1114  * Note: GTT start, end, size should be initialized before calling this
1115  * function on AGP platform.
1116  */
1117 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1118 {
1119         u64 size_bf, size_af;
1120
1121         if (mc->mc_vram_size > 0xE0000000) {
1122                 /* leave room for at least 512M GTT */
1123                 dev_warn(rdev->dev, "limiting VRAM\n");
1124                 mc->real_vram_size = 0xE0000000;
1125                 mc->mc_vram_size = 0xE0000000;
1126         }
1127         if (rdev->flags & RADEON_IS_AGP) {
1128                 size_bf = mc->gtt_start;
1129                 size_af = 0xFFFFFFFF - mc->gtt_end;
1130                 if (size_bf > size_af) {
1131                         if (mc->mc_vram_size > size_bf) {
1132                                 dev_warn(rdev->dev, "limiting VRAM\n");
1133                                 mc->real_vram_size = size_bf;
1134                                 mc->mc_vram_size = size_bf;
1135                         }
1136                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1137                 } else {
1138                         if (mc->mc_vram_size > size_af) {
1139                                 dev_warn(rdev->dev, "limiting VRAM\n");
1140                                 mc->real_vram_size = size_af;
1141                                 mc->mc_vram_size = size_af;
1142                         }
1143                         mc->vram_start = mc->gtt_end + 1;
1144                 }
1145                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1146                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1147                                 mc->mc_vram_size >> 20, mc->vram_start,
1148                                 mc->vram_end, mc->real_vram_size >> 20);
1149         } else {
1150                 u64 base = 0;
1151                 if (rdev->flags & RADEON_IS_IGP) {
1152                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1153                         base <<= 24;
1154                 }
1155                 radeon_vram_location(rdev, &rdev->mc, base);
1156                 rdev->mc.gtt_base_align = 0;
1157                 radeon_gtt_location(rdev, mc);
1158         }
1159 }
1160
1161 static int r600_mc_init(struct radeon_device *rdev)
1162 {
1163         u32 tmp;
1164         int chansize, numchan;
1165
1166         /* Get VRAM informations */
1167         rdev->mc.vram_is_ddr = true;
1168         tmp = RREG32(RAMCFG);
1169         if (tmp & CHANSIZE_OVERRIDE) {
1170                 chansize = 16;
1171         } else if (tmp & CHANSIZE_MASK) {
1172                 chansize = 64;
1173         } else {
1174                 chansize = 32;
1175         }
1176         tmp = RREG32(CHMAP);
1177         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1178         case 0:
1179         default:
1180                 numchan = 1;
1181                 break;
1182         case 1:
1183                 numchan = 2;
1184                 break;
1185         case 2:
1186                 numchan = 4;
1187                 break;
1188         case 3:
1189                 numchan = 8;
1190                 break;
1191         }
1192         rdev->mc.vram_width = numchan * chansize;
1193         /* Could aper size report 0 ? */
1194         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1195         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1196         /* Setup GPU memory space */
1197         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1198         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1199         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1200         r600_vram_gtt_location(rdev, &rdev->mc);
1201
1202         if (rdev->flags & RADEON_IS_IGP) {
1203                 rs690_pm_info(rdev);
1204                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1205         }
1206         radeon_update_bandwidth_info(rdev);
1207         return 0;
1208 }
1209
1210 int r600_vram_scratch_init(struct radeon_device *rdev)
1211 {
1212         int r;
1213
1214         if (rdev->vram_scratch.robj == NULL) {
1215                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1216                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1217                                      NULL, &rdev->vram_scratch.robj);
1218                 if (r) {
1219                         return r;
1220                 }
1221         }
1222
1223         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1224         if (unlikely(r != 0))
1225                 return r;
1226         r = radeon_bo_pin(rdev->vram_scratch.robj,
1227                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1228         if (r) {
1229                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1230                 return r;
1231         }
1232         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1233                                 (void **)&rdev->vram_scratch.ptr);
1234         if (r)
1235                 radeon_bo_unpin(rdev->vram_scratch.robj);
1236         radeon_bo_unreserve(rdev->vram_scratch.robj);
1237
1238         return r;
1239 }
1240
1241 void r600_vram_scratch_fini(struct radeon_device *rdev)
1242 {
1243         int r;
1244
1245         if (rdev->vram_scratch.robj == NULL) {
1246                 return;
1247         }
1248         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1249         if (likely(r == 0)) {
1250                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1251                 radeon_bo_unpin(rdev->vram_scratch.robj);
1252                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1253         }
1254         radeon_bo_unref(&rdev->vram_scratch.robj);
1255 }
1256
1257 /* We doesn't check that the GPU really needs a reset we simply do the
1258  * reset, it's up to the caller to determine if the GPU needs one. We
1259  * might add an helper function to check that.
1260  */
1261 static int r600_gpu_soft_reset(struct radeon_device *rdev)
1262 {
1263         struct rv515_mc_save save;
1264         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1265                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1266                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1267                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1268                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1269                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1270                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1271                                 S_008010_GUI_ACTIVE(1);
1272         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1273                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1274                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1275                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1276                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1277                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1278                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1279                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1280         u32 tmp;
1281
1282         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1283                 return 0;
1284
1285         dev_info(rdev->dev, "GPU softreset \n");
1286         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1287                 RREG32(R_008010_GRBM_STATUS));
1288         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1289                 RREG32(R_008014_GRBM_STATUS2));
1290         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1291                 RREG32(R_000E50_SRBM_STATUS));
1292         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1293                 RREG32(CP_STALLED_STAT1));
1294         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1295                 RREG32(CP_STALLED_STAT2));
1296         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1297                 RREG32(CP_BUSY_STAT));
1298         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1299                 RREG32(CP_STAT));
1300         rv515_mc_stop(rdev, &save);
1301         if (r600_mc_wait_for_idle(rdev)) {
1302                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1303         }
1304         /* Disable CP parsing/prefetching */
1305         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1306         /* Check if any of the rendering block is busy and reset it */
1307         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1308             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1309                 tmp = S_008020_SOFT_RESET_CR(1) |
1310                         S_008020_SOFT_RESET_DB(1) |
1311                         S_008020_SOFT_RESET_CB(1) |
1312                         S_008020_SOFT_RESET_PA(1) |
1313                         S_008020_SOFT_RESET_SC(1) |
1314                         S_008020_SOFT_RESET_SMX(1) |
1315                         S_008020_SOFT_RESET_SPI(1) |
1316                         S_008020_SOFT_RESET_SX(1) |
1317                         S_008020_SOFT_RESET_SH(1) |
1318                         S_008020_SOFT_RESET_TC(1) |
1319                         S_008020_SOFT_RESET_TA(1) |
1320                         S_008020_SOFT_RESET_VC(1) |
1321                         S_008020_SOFT_RESET_VGT(1);
1322                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1323                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1324                 RREG32(R_008020_GRBM_SOFT_RESET);
1325                 mdelay(15);
1326                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1327         }
1328         /* Reset CP (we always reset CP) */
1329         tmp = S_008020_SOFT_RESET_CP(1);
1330         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1331         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1332         RREG32(R_008020_GRBM_SOFT_RESET);
1333         mdelay(15);
1334         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1335         /* Wait a little for things to settle down */
1336         mdelay(1);
1337         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1338                 RREG32(R_008010_GRBM_STATUS));
1339         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1340                 RREG32(R_008014_GRBM_STATUS2));
1341         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1342                 RREG32(R_000E50_SRBM_STATUS));
1343         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1344                 RREG32(CP_STALLED_STAT1));
1345         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1346                 RREG32(CP_STALLED_STAT2));
1347         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1348                 RREG32(CP_BUSY_STAT));
1349         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1350                 RREG32(CP_STAT));
1351         rv515_mc_resume(rdev, &save);
1352         return 0;
1353 }
1354
1355 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1356 {
1357         u32 srbm_status;
1358         u32 grbm_status;
1359         u32 grbm_status2;
1360
1361         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1362         grbm_status = RREG32(R_008010_GRBM_STATUS);
1363         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1364         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1365                 radeon_ring_lockup_update(ring);
1366                 return false;
1367         }
1368         /* force CP activities */
1369         radeon_ring_force_activity(rdev, ring);
1370         return radeon_ring_test_lockup(rdev, ring);
1371 }
1372
1373 /**
1374  * r600_dma_is_lockup - Check if the DMA engine is locked up
1375  *
1376  * @rdev: radeon_device pointer
1377  * @ring: radeon_ring structure holding ring information
1378  *
1379  * Check if the async DMA engine is locked up (r6xx-evergreen).
1380  * Returns true if the engine appears to be locked up, false if not.
1381  */
1382 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1383 {
1384         u32 dma_status_reg;
1385
1386         dma_status_reg = RREG32(DMA_STATUS_REG);
1387         if (dma_status_reg & DMA_IDLE) {
1388                 radeon_ring_lockup_update(ring);
1389                 return false;
1390         }
1391         /* force ring activities */
1392         radeon_ring_force_activity(rdev, ring);
1393         return radeon_ring_test_lockup(rdev, ring);
1394 }
1395
1396 int r600_asic_reset(struct radeon_device *rdev)
1397 {
1398         return r600_gpu_soft_reset(rdev);
1399 }
1400
1401 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1402                               u32 tiling_pipe_num,
1403                               u32 max_rb_num,
1404                               u32 total_max_rb_num,
1405                               u32 disabled_rb_mask)
1406 {
1407         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1408         u32 pipe_rb_ratio, pipe_rb_remain;
1409         u32 data = 0, mask = 1 << (max_rb_num - 1);
1410         unsigned i, j;
1411
1412         /* mask out the RBs that don't exist on that asic */
1413         disabled_rb_mask |= (0xff << max_rb_num) & 0xff;
1414
1415         rendering_pipe_num = 1 << tiling_pipe_num;
1416         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1417         BUG_ON(rendering_pipe_num < req_rb_num);
1418
1419         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1420         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1421
1422         if (rdev->family <= CHIP_RV740) {
1423                 /* r6xx/r7xx */
1424                 rb_num_width = 2;
1425         } else {
1426                 /* eg+ */
1427                 rb_num_width = 4;
1428         }
1429
1430         for (i = 0; i < max_rb_num; i++) {
1431                 if (!(mask & disabled_rb_mask)) {
1432                         for (j = 0; j < pipe_rb_ratio; j++) {
1433                                 data <<= rb_num_width;
1434                                 data |= max_rb_num - i - 1;
1435                         }
1436                         if (pipe_rb_remain) {
1437                                 data <<= rb_num_width;
1438                                 data |= max_rb_num - i - 1;
1439                                 pipe_rb_remain--;
1440                         }
1441                 }
1442                 mask >>= 1;
1443         }
1444
1445         return data;
1446 }
1447
1448 int r600_count_pipe_bits(uint32_t val)
1449 {
1450         int i, ret = 0;
1451
1452         for (i = 0; i < 32; i++) {
1453                 ret += val & 1;
1454                 val >>= 1;
1455         }
1456         return ret;
1457 }
1458
1459 static void r600_gpu_init(struct radeon_device *rdev)
1460 {
1461         u32 tiling_config;
1462         u32 ramcfg;
1463         u32 cc_rb_backend_disable;
1464         u32 cc_gc_shader_pipe_config;
1465         u32 tmp;
1466         int i, j;
1467         u32 sq_config;
1468         u32 sq_gpr_resource_mgmt_1 = 0;
1469         u32 sq_gpr_resource_mgmt_2 = 0;
1470         u32 sq_thread_resource_mgmt = 0;
1471         u32 sq_stack_resource_mgmt_1 = 0;
1472         u32 sq_stack_resource_mgmt_2 = 0;
1473         u32 disabled_rb_mask;
1474
1475         rdev->config.r600.tiling_group_size = 256;
1476         switch (rdev->family) {
1477         case CHIP_R600:
1478                 rdev->config.r600.max_pipes = 4;
1479                 rdev->config.r600.max_tile_pipes = 8;
1480                 rdev->config.r600.max_simds = 4;
1481                 rdev->config.r600.max_backends = 4;
1482                 rdev->config.r600.max_gprs = 256;
1483                 rdev->config.r600.max_threads = 192;
1484                 rdev->config.r600.max_stack_entries = 256;
1485                 rdev->config.r600.max_hw_contexts = 8;
1486                 rdev->config.r600.max_gs_threads = 16;
1487                 rdev->config.r600.sx_max_export_size = 128;
1488                 rdev->config.r600.sx_max_export_pos_size = 16;
1489                 rdev->config.r600.sx_max_export_smx_size = 128;
1490                 rdev->config.r600.sq_num_cf_insts = 2;
1491                 break;
1492         case CHIP_RV630:
1493         case CHIP_RV635:
1494                 rdev->config.r600.max_pipes = 2;
1495                 rdev->config.r600.max_tile_pipes = 2;
1496                 rdev->config.r600.max_simds = 3;
1497                 rdev->config.r600.max_backends = 1;
1498                 rdev->config.r600.max_gprs = 128;
1499                 rdev->config.r600.max_threads = 192;
1500                 rdev->config.r600.max_stack_entries = 128;
1501                 rdev->config.r600.max_hw_contexts = 8;
1502                 rdev->config.r600.max_gs_threads = 4;
1503                 rdev->config.r600.sx_max_export_size = 128;
1504                 rdev->config.r600.sx_max_export_pos_size = 16;
1505                 rdev->config.r600.sx_max_export_smx_size = 128;
1506                 rdev->config.r600.sq_num_cf_insts = 2;
1507                 break;
1508         case CHIP_RV610:
1509         case CHIP_RV620:
1510         case CHIP_RS780:
1511         case CHIP_RS880:
1512                 rdev->config.r600.max_pipes = 1;
1513                 rdev->config.r600.max_tile_pipes = 1;
1514                 rdev->config.r600.max_simds = 2;
1515                 rdev->config.r600.max_backends = 1;
1516                 rdev->config.r600.max_gprs = 128;
1517                 rdev->config.r600.max_threads = 192;
1518                 rdev->config.r600.max_stack_entries = 128;
1519                 rdev->config.r600.max_hw_contexts = 4;
1520                 rdev->config.r600.max_gs_threads = 4;
1521                 rdev->config.r600.sx_max_export_size = 128;
1522                 rdev->config.r600.sx_max_export_pos_size = 16;
1523                 rdev->config.r600.sx_max_export_smx_size = 128;
1524                 rdev->config.r600.sq_num_cf_insts = 1;
1525                 break;
1526         case CHIP_RV670:
1527                 rdev->config.r600.max_pipes = 4;
1528                 rdev->config.r600.max_tile_pipes = 4;
1529                 rdev->config.r600.max_simds = 4;
1530                 rdev->config.r600.max_backends = 4;
1531                 rdev->config.r600.max_gprs = 192;
1532                 rdev->config.r600.max_threads = 192;
1533                 rdev->config.r600.max_stack_entries = 256;
1534                 rdev->config.r600.max_hw_contexts = 8;
1535                 rdev->config.r600.max_gs_threads = 16;
1536                 rdev->config.r600.sx_max_export_size = 128;
1537                 rdev->config.r600.sx_max_export_pos_size = 16;
1538                 rdev->config.r600.sx_max_export_smx_size = 128;
1539                 rdev->config.r600.sq_num_cf_insts = 2;
1540                 break;
1541         default:
1542                 break;
1543         }
1544
1545         /* Initialize HDP */
1546         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1547                 WREG32((0x2c14 + j), 0x00000000);
1548                 WREG32((0x2c18 + j), 0x00000000);
1549                 WREG32((0x2c1c + j), 0x00000000);
1550                 WREG32((0x2c20 + j), 0x00000000);
1551                 WREG32((0x2c24 + j), 0x00000000);
1552         }
1553
1554         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1555
1556         /* Setup tiling */
1557         tiling_config = 0;
1558         ramcfg = RREG32(RAMCFG);
1559         switch (rdev->config.r600.max_tile_pipes) {
1560         case 1:
1561                 tiling_config |= PIPE_TILING(0);
1562                 break;
1563         case 2:
1564                 tiling_config |= PIPE_TILING(1);
1565                 break;
1566         case 4:
1567                 tiling_config |= PIPE_TILING(2);
1568                 break;
1569         case 8:
1570                 tiling_config |= PIPE_TILING(3);
1571                 break;
1572         default:
1573                 break;
1574         }
1575         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1576         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1577         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1578         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1579
1580         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1581         if (tmp > 3) {
1582                 tiling_config |= ROW_TILING(3);
1583                 tiling_config |= SAMPLE_SPLIT(3);
1584         } else {
1585                 tiling_config |= ROW_TILING(tmp);
1586                 tiling_config |= SAMPLE_SPLIT(tmp);
1587         }
1588         tiling_config |= BANK_SWAPS(1);
1589
1590         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1591         tmp = R6XX_MAX_BACKENDS -
1592                 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1593         if (tmp < rdev->config.r600.max_backends) {
1594                 rdev->config.r600.max_backends = tmp;
1595         }
1596
1597         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1598         tmp = R6XX_MAX_PIPES -
1599                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1600         if (tmp < rdev->config.r600.max_pipes) {
1601                 rdev->config.r600.max_pipes = tmp;
1602         }
1603         tmp = R6XX_MAX_SIMDS -
1604                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1605         if (tmp < rdev->config.r600.max_simds) {
1606                 rdev->config.r600.max_simds = tmp;
1607         }
1608
1609         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1610         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1611         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1612                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
1613         tiling_config |= tmp << 16;
1614         rdev->config.r600.backend_map = tmp;
1615
1616         rdev->config.r600.tile_config = tiling_config;
1617         WREG32(GB_TILING_CONFIG, tiling_config);
1618         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1619         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1620         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1621
1622         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1623         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1624         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1625
1626         /* Setup some CP states */
1627         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1628         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1629
1630         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1631                              SYNC_WALKER | SYNC_ALIGNER));
1632         /* Setup various GPU states */
1633         if (rdev->family == CHIP_RV670)
1634                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1635
1636         tmp = RREG32(SX_DEBUG_1);
1637         tmp |= SMX_EVENT_RELEASE;
1638         if ((rdev->family > CHIP_R600))
1639                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1640         WREG32(SX_DEBUG_1, tmp);
1641
1642         if (((rdev->family) == CHIP_R600) ||
1643             ((rdev->family) == CHIP_RV630) ||
1644             ((rdev->family) == CHIP_RV610) ||
1645             ((rdev->family) == CHIP_RV620) ||
1646             ((rdev->family) == CHIP_RS780) ||
1647             ((rdev->family) == CHIP_RS880)) {
1648                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1649         } else {
1650                 WREG32(DB_DEBUG, 0);
1651         }
1652         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1653                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1654
1655         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1656         WREG32(VGT_NUM_INSTANCES, 0);
1657
1658         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1659         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1660
1661         tmp = RREG32(SQ_MS_FIFO_SIZES);
1662         if (((rdev->family) == CHIP_RV610) ||
1663             ((rdev->family) == CHIP_RV620) ||
1664             ((rdev->family) == CHIP_RS780) ||
1665             ((rdev->family) == CHIP_RS880)) {
1666                 tmp = (CACHE_FIFO_SIZE(0xa) |
1667                        FETCH_FIFO_HIWATER(0xa) |
1668                        DONE_FIFO_HIWATER(0xe0) |
1669                        ALU_UPDATE_FIFO_HIWATER(0x8));
1670         } else if (((rdev->family) == CHIP_R600) ||
1671                    ((rdev->family) == CHIP_RV630)) {
1672                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1673                 tmp |= DONE_FIFO_HIWATER(0x4);
1674         }
1675         WREG32(SQ_MS_FIFO_SIZES, tmp);
1676
1677         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1678          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1679          */
1680         sq_config = RREG32(SQ_CONFIG);
1681         sq_config &= ~(PS_PRIO(3) |
1682                        VS_PRIO(3) |
1683                        GS_PRIO(3) |
1684                        ES_PRIO(3));
1685         sq_config |= (DX9_CONSTS |
1686                       VC_ENABLE |
1687                       PS_PRIO(0) |
1688                       VS_PRIO(1) |
1689                       GS_PRIO(2) |
1690                       ES_PRIO(3));
1691
1692         if ((rdev->family) == CHIP_R600) {
1693                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1694                                           NUM_VS_GPRS(124) |
1695                                           NUM_CLAUSE_TEMP_GPRS(4));
1696                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1697                                           NUM_ES_GPRS(0));
1698                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1699                                            NUM_VS_THREADS(48) |
1700                                            NUM_GS_THREADS(4) |
1701                                            NUM_ES_THREADS(4));
1702                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1703                                             NUM_VS_STACK_ENTRIES(128));
1704                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1705                                             NUM_ES_STACK_ENTRIES(0));
1706         } else if (((rdev->family) == CHIP_RV610) ||
1707                    ((rdev->family) == CHIP_RV620) ||
1708                    ((rdev->family) == CHIP_RS780) ||
1709                    ((rdev->family) == CHIP_RS880)) {
1710                 /* no vertex cache */
1711                 sq_config &= ~VC_ENABLE;
1712
1713                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1714                                           NUM_VS_GPRS(44) |
1715                                           NUM_CLAUSE_TEMP_GPRS(2));
1716                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1717                                           NUM_ES_GPRS(17));
1718                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1719                                            NUM_VS_THREADS(78) |
1720                                            NUM_GS_THREADS(4) |
1721                                            NUM_ES_THREADS(31));
1722                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1723                                             NUM_VS_STACK_ENTRIES(40));
1724                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1725                                             NUM_ES_STACK_ENTRIES(16));
1726         } else if (((rdev->family) == CHIP_RV630) ||
1727                    ((rdev->family) == CHIP_RV635)) {
1728                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1729                                           NUM_VS_GPRS(44) |
1730                                           NUM_CLAUSE_TEMP_GPRS(2));
1731                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1732                                           NUM_ES_GPRS(18));
1733                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1734                                            NUM_VS_THREADS(78) |
1735                                            NUM_GS_THREADS(4) |
1736                                            NUM_ES_THREADS(31));
1737                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1738                                             NUM_VS_STACK_ENTRIES(40));
1739                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1740                                             NUM_ES_STACK_ENTRIES(16));
1741         } else if ((rdev->family) == CHIP_RV670) {
1742                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1743                                           NUM_VS_GPRS(44) |
1744                                           NUM_CLAUSE_TEMP_GPRS(2));
1745                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1746                                           NUM_ES_GPRS(17));
1747                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1748                                            NUM_VS_THREADS(78) |
1749                                            NUM_GS_THREADS(4) |
1750                                            NUM_ES_THREADS(31));
1751                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1752                                             NUM_VS_STACK_ENTRIES(64));
1753                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1754                                             NUM_ES_STACK_ENTRIES(64));
1755         }
1756
1757         WREG32(SQ_CONFIG, sq_config);
1758         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1759         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1760         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1761         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1762         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1763
1764         if (((rdev->family) == CHIP_RV610) ||
1765             ((rdev->family) == CHIP_RV620) ||
1766             ((rdev->family) == CHIP_RS780) ||
1767             ((rdev->family) == CHIP_RS880)) {
1768                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1769         } else {
1770                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1771         }
1772
1773         /* More default values. 2D/3D driver should adjust as needed */
1774         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1775                                          S1_X(0x4) | S1_Y(0xc)));
1776         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1777                                          S1_X(0x2) | S1_Y(0x2) |
1778                                          S2_X(0xa) | S2_Y(0x6) |
1779                                          S3_X(0x6) | S3_Y(0xa)));
1780         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1781                                              S1_X(0x4) | S1_Y(0xc) |
1782                                              S2_X(0x1) | S2_Y(0x6) |
1783                                              S3_X(0xa) | S3_Y(0xe)));
1784         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1785                                              S5_X(0x0) | S5_Y(0x0) |
1786                                              S6_X(0xb) | S6_Y(0x4) |
1787                                              S7_X(0x7) | S7_Y(0x8)));
1788
1789         WREG32(VGT_STRMOUT_EN, 0);
1790         tmp = rdev->config.r600.max_pipes * 16;
1791         switch (rdev->family) {
1792         case CHIP_RV610:
1793         case CHIP_RV620:
1794         case CHIP_RS780:
1795         case CHIP_RS880:
1796                 tmp += 32;
1797                 break;
1798         case CHIP_RV670:
1799                 tmp += 128;
1800                 break;
1801         default:
1802                 break;
1803         }
1804         if (tmp > 256) {
1805                 tmp = 256;
1806         }
1807         WREG32(VGT_ES_PER_GS, 128);
1808         WREG32(VGT_GS_PER_ES, tmp);
1809         WREG32(VGT_GS_PER_VS, 2);
1810         WREG32(VGT_GS_VERTEX_REUSE, 16);
1811
1812         /* more default values. 2D/3D driver should adjust as needed */
1813         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1814         WREG32(VGT_STRMOUT_EN, 0);
1815         WREG32(SX_MISC, 0);
1816         WREG32(PA_SC_MODE_CNTL, 0);
1817         WREG32(PA_SC_AA_CONFIG, 0);
1818         WREG32(PA_SC_LINE_STIPPLE, 0);
1819         WREG32(SPI_INPUT_Z, 0);
1820         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1821         WREG32(CB_COLOR7_FRAG, 0);
1822
1823         /* Clear render buffer base addresses */
1824         WREG32(CB_COLOR0_BASE, 0);
1825         WREG32(CB_COLOR1_BASE, 0);
1826         WREG32(CB_COLOR2_BASE, 0);
1827         WREG32(CB_COLOR3_BASE, 0);
1828         WREG32(CB_COLOR4_BASE, 0);
1829         WREG32(CB_COLOR5_BASE, 0);
1830         WREG32(CB_COLOR6_BASE, 0);
1831         WREG32(CB_COLOR7_BASE, 0);
1832         WREG32(CB_COLOR7_FRAG, 0);
1833
1834         switch (rdev->family) {
1835         case CHIP_RV610:
1836         case CHIP_RV620:
1837         case CHIP_RS780:
1838         case CHIP_RS880:
1839                 tmp = TC_L2_SIZE(8);
1840                 break;
1841         case CHIP_RV630:
1842         case CHIP_RV635:
1843                 tmp = TC_L2_SIZE(4);
1844                 break;
1845         case CHIP_R600:
1846                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1847                 break;
1848         default:
1849                 tmp = TC_L2_SIZE(0);
1850                 break;
1851         }
1852         WREG32(TC_CNTL, tmp);
1853
1854         tmp = RREG32(HDP_HOST_PATH_CNTL);
1855         WREG32(HDP_HOST_PATH_CNTL, tmp);
1856
1857         tmp = RREG32(ARB_POP);
1858         tmp |= ENABLE_TC128;
1859         WREG32(ARB_POP, tmp);
1860
1861         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1862         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1863                                NUM_CLIP_SEQ(3)));
1864         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1865         WREG32(VC_ENHANCE, 0);
1866 }
1867
1868
1869 /*
1870  * Indirect registers accessor
1871  */
1872 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1873 {
1874         u32 r;
1875
1876         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1877         (void)RREG32(PCIE_PORT_INDEX);
1878         r = RREG32(PCIE_PORT_DATA);
1879         return r;
1880 }
1881
1882 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1883 {
1884         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1885         (void)RREG32(PCIE_PORT_INDEX);
1886         WREG32(PCIE_PORT_DATA, (v));
1887         (void)RREG32(PCIE_PORT_DATA);
1888 }
1889
1890 /*
1891  * CP & Ring
1892  */
1893 void r600_cp_stop(struct radeon_device *rdev)
1894 {
1895         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1896         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1897         WREG32(SCRATCH_UMSK, 0);
1898         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1899 }
1900
1901 int r600_init_microcode(struct radeon_device *rdev)
1902 {
1903         struct platform_device *pdev;
1904         const char *chip_name;
1905         const char *rlc_chip_name;
1906         size_t pfp_req_size, me_req_size, rlc_req_size;
1907         char fw_name[30];
1908         int err;
1909
1910         DRM_DEBUG("\n");
1911
1912         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1913         err = IS_ERR(pdev);
1914         if (err) {
1915                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1916                 return -EINVAL;
1917         }
1918
1919         switch (rdev->family) {
1920         case CHIP_R600:
1921                 chip_name = "R600";
1922                 rlc_chip_name = "R600";
1923                 break;
1924         case CHIP_RV610:
1925                 chip_name = "RV610";
1926                 rlc_chip_name = "R600";
1927                 break;
1928         case CHIP_RV630:
1929                 chip_name = "RV630";
1930                 rlc_chip_name = "R600";
1931                 break;
1932         case CHIP_RV620:
1933                 chip_name = "RV620";
1934                 rlc_chip_name = "R600";
1935                 break;
1936         case CHIP_RV635:
1937                 chip_name = "RV635";
1938                 rlc_chip_name = "R600";
1939                 break;
1940         case CHIP_RV670:
1941                 chip_name = "RV670";
1942                 rlc_chip_name = "R600";
1943                 break;
1944         case CHIP_RS780:
1945         case CHIP_RS880:
1946                 chip_name = "RS780";
1947                 rlc_chip_name = "R600";
1948                 break;
1949         case CHIP_RV770:
1950                 chip_name = "RV770";
1951                 rlc_chip_name = "R700";
1952                 break;
1953         case CHIP_RV730:
1954         case CHIP_RV740:
1955                 chip_name = "RV730";
1956                 rlc_chip_name = "R700";
1957                 break;
1958         case CHIP_RV710:
1959                 chip_name = "RV710";
1960                 rlc_chip_name = "R700";
1961                 break;
1962         case CHIP_CEDAR:
1963                 chip_name = "CEDAR";
1964                 rlc_chip_name = "CEDAR";
1965                 break;
1966         case CHIP_REDWOOD:
1967                 chip_name = "REDWOOD";
1968                 rlc_chip_name = "REDWOOD";
1969                 break;
1970         case CHIP_JUNIPER:
1971                 chip_name = "JUNIPER";
1972                 rlc_chip_name = "JUNIPER";
1973                 break;
1974         case CHIP_CYPRESS:
1975         case CHIP_HEMLOCK:
1976                 chip_name = "CYPRESS";
1977                 rlc_chip_name = "CYPRESS";
1978                 break;
1979         case CHIP_PALM:
1980                 chip_name = "PALM";
1981                 rlc_chip_name = "SUMO";
1982                 break;
1983         case CHIP_SUMO:
1984                 chip_name = "SUMO";
1985                 rlc_chip_name = "SUMO";
1986                 break;
1987         case CHIP_SUMO2:
1988                 chip_name = "SUMO2";
1989                 rlc_chip_name = "SUMO";
1990                 break;
1991         default: BUG();
1992         }
1993
1994         if (rdev->family >= CHIP_CEDAR) {
1995                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1996                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1997                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1998         } else if (rdev->family >= CHIP_RV770) {
1999                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2000                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2001                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2002         } else {
2003                 pfp_req_size = PFP_UCODE_SIZE * 4;
2004                 me_req_size = PM4_UCODE_SIZE * 12;
2005                 rlc_req_size = RLC_UCODE_SIZE * 4;
2006         }
2007
2008         DRM_INFO("Loading %s Microcode\n", chip_name);
2009
2010         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2011         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2012         if (err)
2013                 goto out;
2014         if (rdev->pfp_fw->size != pfp_req_size) {
2015                 printk(KERN_ERR
2016                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2017                        rdev->pfp_fw->size, fw_name);
2018                 err = -EINVAL;
2019                 goto out;
2020         }
2021
2022         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2023         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2024         if (err)
2025                 goto out;
2026         if (rdev->me_fw->size != me_req_size) {
2027                 printk(KERN_ERR
2028                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2029                        rdev->me_fw->size, fw_name);
2030                 err = -EINVAL;
2031         }
2032
2033         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2034         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2035         if (err)
2036                 goto out;
2037         if (rdev->rlc_fw->size != rlc_req_size) {
2038                 printk(KERN_ERR
2039                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2040                        rdev->rlc_fw->size, fw_name);
2041                 err = -EINVAL;
2042         }
2043
2044 out:
2045         platform_device_unregister(pdev);
2046
2047         if (err) {
2048                 if (err != -EINVAL)
2049                         printk(KERN_ERR
2050                                "r600_cp: Failed to load firmware \"%s\"\n",
2051                                fw_name);
2052                 release_firmware(rdev->pfp_fw);
2053                 rdev->pfp_fw = NULL;
2054                 release_firmware(rdev->me_fw);
2055                 rdev->me_fw = NULL;
2056                 release_firmware(rdev->rlc_fw);
2057                 rdev->rlc_fw = NULL;
2058         }
2059         return err;
2060 }
2061
2062 static int r600_cp_load_microcode(struct radeon_device *rdev)
2063 {
2064         const __be32 *fw_data;
2065         int i;
2066
2067         if (!rdev->me_fw || !rdev->pfp_fw)
2068                 return -EINVAL;
2069
2070         r600_cp_stop(rdev);
2071
2072         WREG32(CP_RB_CNTL,
2073 #ifdef __BIG_ENDIAN
2074                BUF_SWAP_32BIT |
2075 #endif
2076                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2077
2078         /* Reset cp */
2079         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2080         RREG32(GRBM_SOFT_RESET);
2081         mdelay(15);
2082         WREG32(GRBM_SOFT_RESET, 0);
2083
2084         WREG32(CP_ME_RAM_WADDR, 0);
2085
2086         fw_data = (const __be32 *)rdev->me_fw->data;
2087         WREG32(CP_ME_RAM_WADDR, 0);
2088         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2089                 WREG32(CP_ME_RAM_DATA,
2090                        be32_to_cpup(fw_data++));
2091
2092         fw_data = (const __be32 *)rdev->pfp_fw->data;
2093         WREG32(CP_PFP_UCODE_ADDR, 0);
2094         for (i = 0; i < PFP_UCODE_SIZE; i++)
2095                 WREG32(CP_PFP_UCODE_DATA,
2096                        be32_to_cpup(fw_data++));
2097
2098         WREG32(CP_PFP_UCODE_ADDR, 0);
2099         WREG32(CP_ME_RAM_WADDR, 0);
2100         WREG32(CP_ME_RAM_RADDR, 0);
2101         return 0;
2102 }
2103
2104 int r600_cp_start(struct radeon_device *rdev)
2105 {
2106         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2107         int r;
2108         uint32_t cp_me;
2109
2110         r = radeon_ring_lock(rdev, ring, 7);
2111         if (r) {
2112                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2113                 return r;
2114         }
2115         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2116         radeon_ring_write(ring, 0x1);
2117         if (rdev->family >= CHIP_RV770) {
2118                 radeon_ring_write(ring, 0x0);
2119                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2120         } else {
2121                 radeon_ring_write(ring, 0x3);
2122                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2123         }
2124         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2125         radeon_ring_write(ring, 0);
2126         radeon_ring_write(ring, 0);
2127         radeon_ring_unlock_commit(rdev, ring);
2128
2129         cp_me = 0xff;
2130         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2131         return 0;
2132 }
2133
2134 int r600_cp_resume(struct radeon_device *rdev)
2135 {
2136         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2137         u32 tmp;
2138         u32 rb_bufsz;
2139         int r;
2140
2141         /* Reset cp */
2142         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2143         RREG32(GRBM_SOFT_RESET);
2144         mdelay(15);
2145         WREG32(GRBM_SOFT_RESET, 0);
2146
2147         /* Set ring buffer size */
2148         rb_bufsz = drm_order(ring->ring_size / 8);
2149         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2150 #ifdef __BIG_ENDIAN
2151         tmp |= BUF_SWAP_32BIT;
2152 #endif
2153         WREG32(CP_RB_CNTL, tmp);
2154         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2155
2156         /* Set the write pointer delay */
2157         WREG32(CP_RB_WPTR_DELAY, 0);
2158
2159         /* Initialize the ring buffer's read and write pointers */
2160         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2161         WREG32(CP_RB_RPTR_WR, 0);
2162         ring->wptr = 0;
2163         WREG32(CP_RB_WPTR, ring->wptr);
2164
2165         /* set the wb address whether it's enabled or not */
2166         WREG32(CP_RB_RPTR_ADDR,
2167                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2168         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2169         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2170
2171         if (rdev->wb.enabled)
2172                 WREG32(SCRATCH_UMSK, 0xff);
2173         else {
2174                 tmp |= RB_NO_UPDATE;
2175                 WREG32(SCRATCH_UMSK, 0);
2176         }
2177
2178         mdelay(1);
2179         WREG32(CP_RB_CNTL, tmp);
2180
2181         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2182         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2183
2184         ring->rptr = RREG32(CP_RB_RPTR);
2185
2186         r600_cp_start(rdev);
2187         ring->ready = true;
2188         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2189         if (r) {
2190                 ring->ready = false;
2191                 return r;
2192         }
2193         return 0;
2194 }
2195
2196 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2197 {
2198         u32 rb_bufsz;
2199         int r;
2200
2201         /* Align ring size */
2202         rb_bufsz = drm_order(ring_size / 8);
2203         ring_size = (1 << (rb_bufsz + 1)) * 4;
2204         ring->ring_size = ring_size;
2205         ring->align_mask = 16 - 1;
2206
2207         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2208                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2209                 if (r) {
2210                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2211                         ring->rptr_save_reg = 0;
2212                 }
2213         }
2214 }
2215
2216 void r600_cp_fini(struct radeon_device *rdev)
2217 {
2218         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2219         r600_cp_stop(rdev);
2220         radeon_ring_fini(rdev, ring);
2221         radeon_scratch_free(rdev, ring->rptr_save_reg);
2222 }
2223
2224 /*
2225  * DMA
2226  * Starting with R600, the GPU has an asynchronous
2227  * DMA engine.  The programming model is very similar
2228  * to the 3D engine (ring buffer, IBs, etc.), but the
2229  * DMA controller has it's own packet format that is
2230  * different form the PM4 format used by the 3D engine.
2231  * It supports copying data, writing embedded data,
2232  * solid fills, and a number of other things.  It also
2233  * has support for tiling/detiling of buffers.
2234  */
2235 /**
2236  * r600_dma_stop - stop the async dma engine
2237  *
2238  * @rdev: radeon_device pointer
2239  *
2240  * Stop the async dma engine (r6xx-evergreen).
2241  */
2242 void r600_dma_stop(struct radeon_device *rdev)
2243 {
2244         u32 rb_cntl = RREG32(DMA_RB_CNTL);
2245
2246         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2247
2248         rb_cntl &= ~DMA_RB_ENABLE;
2249         WREG32(DMA_RB_CNTL, rb_cntl);
2250
2251         rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2252 }
2253
2254 /**
2255  * r600_dma_resume - setup and start the async dma engine
2256  *
2257  * @rdev: radeon_device pointer
2258  *
2259  * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2260  * Returns 0 for success, error for failure.
2261  */
2262 int r600_dma_resume(struct radeon_device *rdev)
2263 {
2264         struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2265         u32 rb_cntl, dma_cntl;
2266         u32 rb_bufsz;
2267         int r;
2268
2269         /* Reset dma */
2270         if (rdev->family >= CHIP_RV770)
2271                 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2272         else
2273                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2274         RREG32(SRBM_SOFT_RESET);
2275         udelay(50);
2276         WREG32(SRBM_SOFT_RESET, 0);
2277
2278         WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2279         WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2280
2281         /* Set ring buffer size in dwords */
2282         rb_bufsz = drm_order(ring->ring_size / 4);
2283         rb_cntl = rb_bufsz << 1;
2284 #ifdef __BIG_ENDIAN
2285         rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2286 #endif
2287         WREG32(DMA_RB_CNTL, rb_cntl);
2288
2289         /* Initialize the ring buffer's read and write pointers */
2290         WREG32(DMA_RB_RPTR, 0);
2291         WREG32(DMA_RB_WPTR, 0);
2292
2293         /* set the wb address whether it's enabled or not */
2294         WREG32(DMA_RB_RPTR_ADDR_HI,
2295                upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2296         WREG32(DMA_RB_RPTR_ADDR_LO,
2297                ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2298
2299         if (rdev->wb.enabled)
2300                 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2301
2302         WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2303
2304         /* enable DMA IBs */
2305         WREG32(DMA_IB_CNTL, DMA_IB_ENABLE);
2306
2307         dma_cntl = RREG32(DMA_CNTL);
2308         dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2309         WREG32(DMA_CNTL, dma_cntl);
2310
2311         if (rdev->family >= CHIP_RV770)
2312                 WREG32(DMA_MODE, 1);
2313
2314         ring->wptr = 0;
2315         WREG32(DMA_RB_WPTR, ring->wptr << 2);
2316
2317         ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2318
2319         WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2320
2321         ring->ready = true;
2322
2323         r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2324         if (r) {
2325                 ring->ready = false;
2326                 return r;
2327         }
2328
2329         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2330
2331         return 0;
2332 }
2333
2334 /**
2335  * r600_dma_fini - tear down the async dma engine
2336  *
2337  * @rdev: radeon_device pointer
2338  *
2339  * Stop the async dma engine and free the ring (r6xx-evergreen).
2340  */
2341 void r600_dma_fini(struct radeon_device *rdev)
2342 {
2343         r600_dma_stop(rdev);
2344         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2345 }
2346
2347 /*
2348  * GPU scratch registers helpers function.
2349  */
2350 void r600_scratch_init(struct radeon_device *rdev)
2351 {
2352         int i;
2353
2354         rdev->scratch.num_reg = 7;
2355         rdev->scratch.reg_base = SCRATCH_REG0;
2356         for (i = 0; i < rdev->scratch.num_reg; i++) {
2357                 rdev->scratch.free[i] = true;
2358                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2359         }
2360 }
2361
2362 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2363 {
2364         uint32_t scratch;
2365         uint32_t tmp = 0;
2366         unsigned i;
2367         int r;
2368
2369         r = radeon_scratch_get(rdev, &scratch);
2370         if (r) {
2371                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2372                 return r;
2373         }
2374         WREG32(scratch, 0xCAFEDEAD);
2375         r = radeon_ring_lock(rdev, ring, 3);
2376         if (r) {
2377                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2378                 radeon_scratch_free(rdev, scratch);
2379                 return r;
2380         }
2381         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2382         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2383         radeon_ring_write(ring, 0xDEADBEEF);
2384         radeon_ring_unlock_commit(rdev, ring);
2385         for (i = 0; i < rdev->usec_timeout; i++) {
2386                 tmp = RREG32(scratch);
2387                 if (tmp == 0xDEADBEEF)
2388                         break;
2389                 DRM_UDELAY(1);
2390         }
2391         if (i < rdev->usec_timeout) {
2392                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2393         } else {
2394                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2395                           ring->idx, scratch, tmp);
2396                 r = -EINVAL;
2397         }
2398         radeon_scratch_free(rdev, scratch);
2399         return r;
2400 }
2401
2402 /**
2403  * r600_dma_ring_test - simple async dma engine test
2404  *
2405  * @rdev: radeon_device pointer
2406  * @ring: radeon_ring structure holding ring information
2407  *
2408  * Test the DMA engine by writing using it to write an
2409  * value to memory. (r6xx-SI).
2410  * Returns 0 for success, error for failure.
2411  */
2412 int r600_dma_ring_test(struct radeon_device *rdev,
2413                        struct radeon_ring *ring)
2414 {
2415         unsigned i;
2416         int r;
2417         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2418         u32 tmp;
2419
2420         if (!ptr) {
2421                 DRM_ERROR("invalid vram scratch pointer\n");
2422                 return -EINVAL;
2423         }
2424
2425         tmp = 0xCAFEDEAD;
2426         writel(tmp, ptr);
2427
2428         r = radeon_ring_lock(rdev, ring, 4);
2429         if (r) {
2430                 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2431                 return r;
2432         }
2433         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2434         radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2435         radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2436         radeon_ring_write(ring, 0xDEADBEEF);
2437         radeon_ring_unlock_commit(rdev, ring);
2438
2439         for (i = 0; i < rdev->usec_timeout; i++) {
2440                 tmp = readl(ptr);
2441                 if (tmp == 0xDEADBEEF)
2442                         break;
2443                 DRM_UDELAY(1);
2444         }
2445
2446         if (i < rdev->usec_timeout) {
2447                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2448         } else {
2449                 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2450                           ring->idx, tmp);
2451                 r = -EINVAL;
2452         }
2453         return r;
2454 }
2455
2456 /*
2457  * CP fences/semaphores
2458  */
2459
2460 void r600_fence_ring_emit(struct radeon_device *rdev,
2461                           struct radeon_fence *fence)
2462 {
2463         struct radeon_ring *ring = &rdev->ring[fence->ring];
2464
2465         if (rdev->wb.use_event) {
2466                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2467                 /* flush read cache over gart */
2468                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2469                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2470                                         PACKET3_VC_ACTION_ENA |
2471                                         PACKET3_SH_ACTION_ENA);
2472                 radeon_ring_write(ring, 0xFFFFFFFF);
2473                 radeon_ring_write(ring, 0);
2474                 radeon_ring_write(ring, 10); /* poll interval */
2475                 /* EVENT_WRITE_EOP - flush caches, send int */
2476                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2477                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2478                 radeon_ring_write(ring, addr & 0xffffffff);
2479                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2480                 radeon_ring_write(ring, fence->seq);
2481                 radeon_ring_write(ring, 0);
2482         } else {
2483                 /* flush read cache over gart */
2484                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2485                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2486                                         PACKET3_VC_ACTION_ENA |
2487                                         PACKET3_SH_ACTION_ENA);
2488                 radeon_ring_write(ring, 0xFFFFFFFF);
2489                 radeon_ring_write(ring, 0);
2490                 radeon_ring_write(ring, 10); /* poll interval */
2491                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2492                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2493                 /* wait for 3D idle clean */
2494                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2495                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2496                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2497                 /* Emit fence sequence & fire IRQ */
2498                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2499                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2500                 radeon_ring_write(ring, fence->seq);
2501                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2502                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2503                 radeon_ring_write(ring, RB_INT_STAT);
2504         }
2505 }
2506
2507 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2508                               struct radeon_ring *ring,
2509                               struct radeon_semaphore *semaphore,
2510                               bool emit_wait)
2511 {
2512         uint64_t addr = semaphore->gpu_addr;
2513         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2514
2515         if (rdev->family < CHIP_CAYMAN)
2516                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2517
2518         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2519         radeon_ring_write(ring, addr & 0xffffffff);
2520         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2521 }
2522
2523 /*
2524  * DMA fences/semaphores
2525  */
2526
2527 /**
2528  * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2529  *
2530  * @rdev: radeon_device pointer
2531  * @fence: radeon fence object
2532  *
2533  * Add a DMA fence packet to the ring to write
2534  * the fence seq number and DMA trap packet to generate
2535  * an interrupt if needed (r6xx-r7xx).
2536  */
2537 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
2538                               struct radeon_fence *fence)
2539 {
2540         struct radeon_ring *ring = &rdev->ring[fence->ring];
2541         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2542         /* write the fence */
2543         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
2544         radeon_ring_write(ring, addr & 0xfffffffc);
2545         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
2546         radeon_ring_write(ring, fence->seq);
2547         /* generate an interrupt */
2548         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
2549 }
2550
2551 /**
2552  * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
2553  *
2554  * @rdev: radeon_device pointer
2555  * @ring: radeon_ring structure holding ring information
2556  * @semaphore: radeon semaphore object
2557  * @emit_wait: wait or signal semaphore
2558  *
2559  * Add a DMA semaphore packet to the ring wait on or signal
2560  * other rings (r6xx-SI).
2561  */
2562 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2563                                   struct radeon_ring *ring,
2564                                   struct radeon_semaphore *semaphore,
2565                                   bool emit_wait)
2566 {
2567         u64 addr = semaphore->gpu_addr;
2568         u32 s = emit_wait ? 0 : 1;
2569
2570         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
2571         radeon_ring_write(ring, addr & 0xfffffffc);
2572         radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2573 }
2574
2575 int r600_copy_blit(struct radeon_device *rdev,
2576                    uint64_t src_offset,
2577                    uint64_t dst_offset,
2578                    unsigned num_gpu_pages,
2579                    struct radeon_fence **fence)
2580 {
2581         struct radeon_semaphore *sem = NULL;
2582         struct radeon_sa_bo *vb = NULL;
2583         int r;
2584
2585         r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
2586         if (r) {
2587                 return r;
2588         }
2589         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
2590         r600_blit_done_copy(rdev, fence, vb, sem);
2591         return 0;
2592 }
2593
2594 /**
2595  * r600_copy_dma - copy pages using the DMA engine
2596  *
2597  * @rdev: radeon_device pointer
2598  * @src_offset: src GPU address
2599  * @dst_offset: dst GPU address
2600  * @num_gpu_pages: number of GPU pages to xfer
2601  * @fence: radeon fence object
2602  *
2603  * Copy GPU paging using the DMA engine (r6xx-r7xx).
2604  * Used by the radeon ttm implementation to move pages if
2605  * registered as the asic copy callback.
2606  */
2607 int r600_copy_dma(struct radeon_device *rdev,
2608                   uint64_t src_offset, uint64_t dst_offset,
2609                   unsigned num_gpu_pages,
2610                   struct radeon_fence **fence)
2611 {
2612         struct radeon_semaphore *sem = NULL;
2613         int ring_index = rdev->asic->copy.dma_ring_index;
2614         struct radeon_ring *ring = &rdev->ring[ring_index];
2615         u32 size_in_dw, cur_size_in_dw;
2616         int i, num_loops;
2617         int r = 0;
2618
2619         r = radeon_semaphore_create(rdev, &sem);
2620         if (r) {
2621                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2622                 return r;
2623         }
2624
2625         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
2626         num_loops = DIV_ROUND_UP(size_in_dw, 0xffff);
2627         r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
2628         if (r) {
2629                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2630                 radeon_semaphore_free(rdev, &sem, NULL);
2631                 return r;
2632         }
2633
2634         if (radeon_fence_need_sync(*fence, ring->idx)) {
2635                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2636                                             ring->idx);
2637                 radeon_fence_note_sync(*fence, ring->idx);
2638         } else {
2639                 radeon_semaphore_free(rdev, &sem, NULL);
2640         }
2641
2642         for (i = 0; i < num_loops; i++) {
2643                 cur_size_in_dw = size_in_dw;
2644                 if (cur_size_in_dw > 0xFFFF)
2645                         cur_size_in_dw = 0xFFFF;
2646                 size_in_dw -= cur_size_in_dw;
2647                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2648                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2649                 radeon_ring_write(ring, src_offset & 0xfffffffc);
2650                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2651                 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
2652                 src_offset += cur_size_in_dw * 4;
2653                 dst_offset += cur_size_in_dw * 4;
2654         }
2655
2656         r = radeon_fence_emit(rdev, fence, ring->idx);
2657         if (r) {
2658                 radeon_ring_unlock_undo(rdev, ring);
2659                 return r;
2660         }
2661
2662         radeon_ring_unlock_commit(rdev, ring);
2663         radeon_semaphore_free(rdev, &sem, *fence);
2664
2665         return r;
2666 }
2667
2668 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2669                          uint32_t tiling_flags, uint32_t pitch,
2670                          uint32_t offset, uint32_t obj_size)
2671 {
2672         /* FIXME: implement */
2673         return 0;
2674 }
2675
2676 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2677 {
2678         /* FIXME: implement */
2679 }
2680
2681 static int r600_startup(struct radeon_device *rdev)
2682 {
2683         struct radeon_ring *ring;
2684         int r;
2685
2686         /* enable pcie gen2 link */
2687         r600_pcie_gen2_enable(rdev);
2688
2689         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2690                 r = r600_init_microcode(rdev);
2691                 if (r) {
2692                         DRM_ERROR("Failed to load firmware!\n");
2693                         return r;
2694                 }
2695         }
2696
2697         r = r600_vram_scratch_init(rdev);
2698         if (r)
2699                 return r;
2700
2701         r600_mc_program(rdev);
2702         if (rdev->flags & RADEON_IS_AGP) {
2703                 r600_agp_enable(rdev);
2704         } else {
2705                 r = r600_pcie_gart_enable(rdev);
2706                 if (r)
2707                         return r;
2708         }
2709         r600_gpu_init(rdev);
2710         r = r600_blit_init(rdev);
2711         if (r) {
2712                 r600_blit_fini(rdev);
2713                 rdev->asic->copy.copy = NULL;
2714                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2715         }
2716
2717         /* allocate wb buffer */
2718         r = radeon_wb_init(rdev);
2719         if (r)
2720                 return r;
2721
2722         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2723         if (r) {
2724                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2725                 return r;
2726         }
2727
2728         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2729         if (r) {
2730                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2731                 return r;
2732         }
2733
2734         /* Enable IRQ */
2735         r = r600_irq_init(rdev);
2736         if (r) {
2737                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2738                 radeon_irq_kms_fini(rdev);
2739                 return r;
2740         }
2741         r600_irq_set(rdev);
2742
2743         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2744         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2745                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2746                              0, 0xfffff, RADEON_CP_PACKET2);
2747         if (r)
2748                 return r;
2749
2750         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2751         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2752                              DMA_RB_RPTR, DMA_RB_WPTR,
2753                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2754         if (r)
2755                 return r;
2756
2757         r = r600_cp_load_microcode(rdev);
2758         if (r)
2759                 return r;
2760         r = r600_cp_resume(rdev);
2761         if (r)
2762                 return r;
2763
2764         r = r600_dma_resume(rdev);
2765         if (r)
2766                 return r;
2767
2768         r = radeon_ib_pool_init(rdev);
2769         if (r) {
2770                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2771                 return r;
2772         }
2773
2774         r = r600_audio_init(rdev);
2775         if (r) {
2776                 DRM_ERROR("radeon: audio init failed\n");
2777                 return r;
2778         }
2779
2780         return 0;
2781 }
2782
2783 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2784 {
2785         uint32_t temp;
2786
2787         temp = RREG32(CONFIG_CNTL);
2788         if (state == false) {
2789                 temp &= ~(1<<0);
2790                 temp |= (1<<1);
2791         } else {
2792                 temp &= ~(1<<1);
2793         }
2794         WREG32(CONFIG_CNTL, temp);
2795 }
2796
2797 int r600_resume(struct radeon_device *rdev)
2798 {
2799         int r;
2800
2801         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2802          * posting will perform necessary task to bring back GPU into good
2803          * shape.
2804          */
2805         /* post card */
2806         atom_asic_init(rdev->mode_info.atom_context);
2807
2808         rdev->accel_working = true;
2809         r = r600_startup(rdev);
2810         if (r) {
2811                 DRM_ERROR("r600 startup failed on resume\n");
2812                 rdev->accel_working = false;
2813                 return r;
2814         }
2815
2816         return r;
2817 }
2818
2819 int r600_suspend(struct radeon_device *rdev)
2820 {
2821         r600_audio_fini(rdev);
2822         r600_cp_stop(rdev);
2823         r600_dma_stop(rdev);
2824         r600_irq_suspend(rdev);
2825         radeon_wb_disable(rdev);
2826         r600_pcie_gart_disable(rdev);
2827
2828         return 0;
2829 }
2830
2831 /* Plan is to move initialization in that function and use
2832  * helper function so that radeon_device_init pretty much
2833  * do nothing more than calling asic specific function. This
2834  * should also allow to remove a bunch of callback function
2835  * like vram_info.
2836  */
2837 int r600_init(struct radeon_device *rdev)
2838 {
2839         int r;
2840
2841         if (r600_debugfs_mc_info_init(rdev)) {
2842                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2843         }
2844         /* Read BIOS */
2845         if (!radeon_get_bios(rdev)) {
2846                 if (ASIC_IS_AVIVO(rdev))
2847                         return -EINVAL;
2848         }
2849         /* Must be an ATOMBIOS */
2850         if (!rdev->is_atom_bios) {
2851                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2852                 return -EINVAL;
2853         }
2854         r = radeon_atombios_init(rdev);
2855         if (r)
2856                 return r;
2857         /* Post card if necessary */
2858         if (!radeon_card_posted(rdev)) {
2859                 if (!rdev->bios) {
2860                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2861                         return -EINVAL;
2862                 }
2863                 DRM_INFO("GPU not posted. posting now...\n");
2864                 atom_asic_init(rdev->mode_info.atom_context);
2865         }
2866         /* Initialize scratch registers */
2867         r600_scratch_init(rdev);
2868         /* Initialize surface registers */
2869         radeon_surface_init(rdev);
2870         /* Initialize clocks */
2871         radeon_get_clock_info(rdev->ddev);
2872         /* Fence driver */
2873         r = radeon_fence_driver_init(rdev);
2874         if (r)
2875                 return r;
2876         if (rdev->flags & RADEON_IS_AGP) {
2877                 r = radeon_agp_init(rdev);
2878                 if (r)
2879                         radeon_agp_disable(rdev);
2880         }
2881         r = r600_mc_init(rdev);
2882         if (r)
2883                 return r;
2884         /* Memory manager */
2885         r = radeon_bo_init(rdev);
2886         if (r)
2887                 return r;
2888
2889         r = radeon_irq_kms_init(rdev);
2890         if (r)
2891                 return r;
2892
2893         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2894         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2895
2896         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2897         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2898
2899         rdev->ih.ring_obj = NULL;
2900         r600_ih_ring_init(rdev, 64 * 1024);
2901
2902         r = r600_pcie_gart_init(rdev);
2903         if (r)
2904                 return r;
2905
2906         rdev->accel_working = true;
2907         r = r600_startup(rdev);
2908         if (r) {
2909                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2910                 r600_cp_fini(rdev);
2911                 r600_dma_fini(rdev);
2912                 r600_irq_fini(rdev);
2913                 radeon_wb_fini(rdev);
2914                 radeon_ib_pool_fini(rdev);
2915                 radeon_irq_kms_fini(rdev);
2916                 r600_pcie_gart_fini(rdev);
2917                 rdev->accel_working = false;
2918         }
2919
2920         return 0;
2921 }
2922
2923 void r600_fini(struct radeon_device *rdev)
2924 {
2925         r600_audio_fini(rdev);
2926         r600_blit_fini(rdev);
2927         r600_cp_fini(rdev);
2928         r600_dma_fini(rdev);
2929         r600_irq_fini(rdev);
2930         radeon_wb_fini(rdev);
2931         radeon_ib_pool_fini(rdev);
2932         radeon_irq_kms_fini(rdev);
2933         r600_pcie_gart_fini(rdev);
2934         r600_vram_scratch_fini(rdev);
2935         radeon_agp_fini(rdev);
2936         radeon_gem_fini(rdev);
2937         radeon_fence_driver_fini(rdev);
2938         radeon_bo_fini(rdev);
2939         radeon_atombios_fini(rdev);
2940         kfree(rdev->bios);
2941         rdev->bios = NULL;
2942 }
2943
2944
2945 /*
2946  * CS stuff
2947  */
2948 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2949 {
2950         struct radeon_ring *ring = &rdev->ring[ib->ring];
2951         u32 next_rptr;
2952
2953         if (ring->rptr_save_reg) {
2954                 next_rptr = ring->wptr + 3 + 4;
2955                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2956                 radeon_ring_write(ring, ((ring->rptr_save_reg -
2957                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2958                 radeon_ring_write(ring, next_rptr);
2959         } else if (rdev->wb.enabled) {
2960                 next_rptr = ring->wptr + 5 + 4;
2961                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
2962                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2963                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
2964                 radeon_ring_write(ring, next_rptr);
2965                 radeon_ring_write(ring, 0);
2966         }
2967
2968         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2969         radeon_ring_write(ring,
2970 #ifdef __BIG_ENDIAN
2971                           (2 << 0) |
2972 #endif
2973                           (ib->gpu_addr & 0xFFFFFFFC));
2974         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2975         radeon_ring_write(ring, ib->length_dw);
2976 }
2977
2978 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
2979 {
2980         struct radeon_ib ib;
2981         uint32_t scratch;
2982         uint32_t tmp = 0;
2983         unsigned i;
2984         int r;
2985
2986         r = radeon_scratch_get(rdev, &scratch);
2987         if (r) {
2988                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2989                 return r;
2990         }
2991         WREG32(scratch, 0xCAFEDEAD);
2992         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
2993         if (r) {
2994                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2995                 goto free_scratch;
2996         }
2997         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2998         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2999         ib.ptr[2] = 0xDEADBEEF;
3000         ib.length_dw = 3;
3001         r = radeon_ib_schedule(rdev, &ib, NULL);
3002         if (r) {
3003                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3004                 goto free_ib;
3005         }
3006         r = radeon_fence_wait(ib.fence, false);
3007         if (r) {
3008                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3009                 goto free_ib;
3010         }
3011         for (i = 0; i < rdev->usec_timeout; i++) {
3012                 tmp = RREG32(scratch);
3013                 if (tmp == 0xDEADBEEF)
3014                         break;
3015                 DRM_UDELAY(1);
3016         }
3017         if (i < rdev->usec_timeout) {
3018                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3019         } else {
3020                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3021                           scratch, tmp);
3022                 r = -EINVAL;
3023         }
3024 free_ib:
3025         radeon_ib_free(rdev, &ib);
3026 free_scratch:
3027         radeon_scratch_free(rdev, scratch);
3028         return r;
3029 }
3030
3031 /**
3032  * r600_dma_ib_test - test an IB on the DMA engine
3033  *
3034  * @rdev: radeon_device pointer
3035  * @ring: radeon_ring structure holding ring information
3036  *
3037  * Test a simple IB in the DMA ring (r6xx-SI).
3038  * Returns 0 on success, error on failure.
3039  */
3040 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3041 {
3042         struct radeon_ib ib;
3043         unsigned i;
3044         int r;
3045         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3046         u32 tmp = 0;
3047
3048         if (!ptr) {
3049                 DRM_ERROR("invalid vram scratch pointer\n");
3050                 return -EINVAL;
3051         }
3052
3053         tmp = 0xCAFEDEAD;
3054         writel(tmp, ptr);
3055
3056         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3057         if (r) {
3058                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3059                 return r;
3060         }
3061
3062         ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3063         ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3064         ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3065         ib.ptr[3] = 0xDEADBEEF;
3066         ib.length_dw = 4;
3067
3068         r = radeon_ib_schedule(rdev, &ib, NULL);
3069         if (r) {
3070                 radeon_ib_free(rdev, &ib);
3071                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3072                 return r;
3073         }
3074         r = radeon_fence_wait(ib.fence, false);
3075         if (r) {
3076                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3077                 return r;
3078         }
3079         for (i = 0; i < rdev->usec_timeout; i++) {
3080                 tmp = readl(ptr);
3081                 if (tmp == 0xDEADBEEF)
3082                         break;
3083                 DRM_UDELAY(1);
3084         }
3085         if (i < rdev->usec_timeout) {
3086                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3087         } else {
3088                 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3089                 r = -EINVAL;
3090         }
3091         radeon_ib_free(rdev, &ib);
3092         return r;
3093 }
3094
3095 /**
3096  * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3097  *
3098  * @rdev: radeon_device pointer
3099  * @ib: IB object to schedule
3100  *
3101  * Schedule an IB in the DMA ring (r6xx-r7xx).
3102  */
3103 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3104 {
3105         struct radeon_ring *ring = &rdev->ring[ib->ring];
3106
3107         if (rdev->wb.enabled) {
3108                 u32 next_rptr = ring->wptr + 4;
3109                 while ((next_rptr & 7) != 5)
3110                         next_rptr++;
3111                 next_rptr += 3;
3112                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3113                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3114                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3115                 radeon_ring_write(ring, next_rptr);
3116         }
3117
3118         /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3119          * Pad as necessary with NOPs.
3120          */
3121         while ((ring->wptr & 7) != 5)
3122                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3123         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3124         radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3125         radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3126
3127 }
3128
3129 /*
3130  * Interrupts
3131  *
3132  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3133  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3134  * writing to the ring and the GPU consuming, the GPU writes to the ring
3135  * and host consumes.  As the host irq handler processes interrupts, it
3136  * increments the rptr.  When the rptr catches up with the wptr, all the
3137  * current interrupts have been processed.
3138  */
3139
3140 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3141 {
3142         u32 rb_bufsz;
3143
3144         /* Align ring size */
3145         rb_bufsz = drm_order(ring_size / 4);
3146         ring_size = (1 << rb_bufsz) * 4;
3147         rdev->ih.ring_size = ring_size;
3148         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3149         rdev->ih.rptr = 0;
3150 }
3151
3152 int r600_ih_ring_alloc(struct radeon_device *rdev)
3153 {
3154         int r;
3155
3156         /* Allocate ring buffer */
3157         if (rdev->ih.ring_obj == NULL) {
3158                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3159                                      PAGE_SIZE, true,
3160                                      RADEON_GEM_DOMAIN_GTT,
3161                                      NULL, &rdev->ih.ring_obj);
3162                 if (r) {
3163                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3164                         return r;
3165                 }
3166                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3167                 if (unlikely(r != 0))
3168                         return r;
3169                 r = radeon_bo_pin(rdev->ih.ring_obj,
3170                                   RADEON_GEM_DOMAIN_GTT,
3171                                   &rdev->ih.gpu_addr);
3172                 if (r) {
3173                         radeon_bo_unreserve(rdev->ih.ring_obj);
3174                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3175                         return r;
3176                 }
3177                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3178                                    (void **)&rdev->ih.ring);
3179                 radeon_bo_unreserve(rdev->ih.ring_obj);
3180                 if (r) {
3181                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3182                         return r;
3183                 }
3184         }
3185         return 0;
3186 }
3187
3188 void r600_ih_ring_fini(struct radeon_device *rdev)
3189 {
3190         int r;
3191         if (rdev->ih.ring_obj) {
3192                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3193                 if (likely(r == 0)) {
3194                         radeon_bo_kunmap(rdev->ih.ring_obj);
3195                         radeon_bo_unpin(rdev->ih.ring_obj);
3196                         radeon_bo_unreserve(rdev->ih.ring_obj);
3197                 }
3198                 radeon_bo_unref(&rdev->ih.ring_obj);
3199                 rdev->ih.ring = NULL;
3200                 rdev->ih.ring_obj = NULL;
3201         }
3202 }
3203
3204 void r600_rlc_stop(struct radeon_device *rdev)
3205 {
3206
3207         if ((rdev->family >= CHIP_RV770) &&
3208             (rdev->family <= CHIP_RV740)) {
3209                 /* r7xx asics need to soft reset RLC before halting */
3210                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3211                 RREG32(SRBM_SOFT_RESET);
3212                 mdelay(15);
3213                 WREG32(SRBM_SOFT_RESET, 0);
3214                 RREG32(SRBM_SOFT_RESET);
3215         }
3216
3217         WREG32(RLC_CNTL, 0);
3218 }
3219
3220 static void r600_rlc_start(struct radeon_device *rdev)
3221 {
3222         WREG32(RLC_CNTL, RLC_ENABLE);
3223 }
3224
3225 static int r600_rlc_init(struct radeon_device *rdev)
3226 {
3227         u32 i;
3228         const __be32 *fw_data;
3229
3230         if (!rdev->rlc_fw)
3231                 return -EINVAL;
3232
3233         r600_rlc_stop(rdev);
3234
3235         WREG32(RLC_HB_CNTL, 0);
3236
3237         if (rdev->family == CHIP_ARUBA) {
3238                 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3239                 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3240         }
3241         if (rdev->family <= CHIP_CAYMAN) {
3242                 WREG32(RLC_HB_BASE, 0);
3243                 WREG32(RLC_HB_RPTR, 0);
3244                 WREG32(RLC_HB_WPTR, 0);
3245         }
3246         if (rdev->family <= CHIP_CAICOS) {
3247                 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3248                 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3249         }
3250         WREG32(RLC_MC_CNTL, 0);
3251         WREG32(RLC_UCODE_CNTL, 0);
3252
3253         fw_data = (const __be32 *)rdev->rlc_fw->data;
3254         if (rdev->family >= CHIP_ARUBA) {
3255                 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3256                         WREG32(RLC_UCODE_ADDR, i);
3257                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3258                 }
3259         } else if (rdev->family >= CHIP_CAYMAN) {
3260                 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3261                         WREG32(RLC_UCODE_ADDR, i);
3262                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3263                 }
3264         } else if (rdev->family >= CHIP_CEDAR) {
3265                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3266                         WREG32(RLC_UCODE_ADDR, i);
3267                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3268                 }
3269         } else if (rdev->family >= CHIP_RV770) {
3270                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3271                         WREG32(RLC_UCODE_ADDR, i);
3272                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3273                 }
3274         } else {
3275                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
3276                         WREG32(RLC_UCODE_ADDR, i);
3277                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3278                 }
3279         }
3280         WREG32(RLC_UCODE_ADDR, 0);
3281
3282         r600_rlc_start(rdev);
3283
3284         return 0;
3285 }
3286
3287 static void r600_enable_interrupts(struct radeon_device *rdev)
3288 {
3289         u32 ih_cntl = RREG32(IH_CNTL);
3290         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3291
3292         ih_cntl |= ENABLE_INTR;
3293         ih_rb_cntl |= IH_RB_ENABLE;
3294         WREG32(IH_CNTL, ih_cntl);
3295         WREG32(IH_RB_CNTL, ih_rb_cntl);
3296         rdev->ih.enabled = true;
3297 }
3298
3299 void r600_disable_interrupts(struct radeon_device *rdev)
3300 {
3301         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3302         u32 ih_cntl = RREG32(IH_CNTL);
3303
3304         ih_rb_cntl &= ~IH_RB_ENABLE;
3305         ih_cntl &= ~ENABLE_INTR;
3306         WREG32(IH_RB_CNTL, ih_rb_cntl);
3307         WREG32(IH_CNTL, ih_cntl);
3308         /* set rptr, wptr to 0 */
3309         WREG32(IH_RB_RPTR, 0);
3310         WREG32(IH_RB_WPTR, 0);
3311         rdev->ih.enabled = false;
3312         rdev->ih.rptr = 0;
3313 }
3314
3315 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3316 {
3317         u32 tmp;
3318
3319         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3320         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3321         WREG32(DMA_CNTL, tmp);
3322         WREG32(GRBM_INT_CNTL, 0);
3323         WREG32(DxMODE_INT_MASK, 0);
3324         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3325         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3326         if (ASIC_IS_DCE3(rdev)) {
3327                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3328                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3329                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3330                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3331                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3332                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3333                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3334                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3335                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3336                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3337                 if (ASIC_IS_DCE32(rdev)) {
3338                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3339                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3340                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3341                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3342                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3343                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3344                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3345                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3346                 } else {
3347                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3348                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3349                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3350                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3351                 }
3352         } else {
3353                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3354                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3355                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3356                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3357                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3358                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3359                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3360                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3361                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3362                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3363                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3364                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3365         }
3366 }
3367
3368 int r600_irq_init(struct radeon_device *rdev)
3369 {
3370         int ret = 0;
3371         int rb_bufsz;
3372         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3373
3374         /* allocate ring */
3375         ret = r600_ih_ring_alloc(rdev);
3376         if (ret)
3377                 return ret;
3378
3379         /* disable irqs */
3380         r600_disable_interrupts(rdev);
3381
3382         /* init rlc */
3383         ret = r600_rlc_init(rdev);
3384         if (ret) {
3385                 r600_ih_ring_fini(rdev);
3386                 return ret;
3387         }
3388
3389         /* setup interrupt control */
3390         /* set dummy read address to ring address */
3391         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3392         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3393         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3394          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3395          */
3396         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3397         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3398         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3399         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3400
3401         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3402         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3403
3404         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3405                       IH_WPTR_OVERFLOW_CLEAR |
3406                       (rb_bufsz << 1));
3407
3408         if (rdev->wb.enabled)
3409                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3410
3411         /* set the writeback address whether it's enabled or not */
3412         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3413         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3414
3415         WREG32(IH_RB_CNTL, ih_rb_cntl);
3416
3417         /* set rptr, wptr to 0 */
3418         WREG32(IH_RB_RPTR, 0);
3419         WREG32(IH_RB_WPTR, 0);
3420
3421         /* Default settings for IH_CNTL (disabled at first) */
3422         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3423         /* RPTR_REARM only works if msi's are enabled */
3424         if (rdev->msi_enabled)
3425                 ih_cntl |= RPTR_REARM;
3426         WREG32(IH_CNTL, ih_cntl);
3427
3428         /* force the active interrupt state to all disabled */
3429         if (rdev->family >= CHIP_CEDAR)
3430                 evergreen_disable_interrupt_state(rdev);
3431         else
3432                 r600_disable_interrupt_state(rdev);
3433
3434         /* at this point everything should be setup correctly to enable master */
3435         pci_set_master(rdev->pdev);
3436
3437         /* enable irqs */
3438         r600_enable_interrupts(rdev);
3439
3440         return ret;
3441 }
3442
3443 void r600_irq_suspend(struct radeon_device *rdev)
3444 {
3445         r600_irq_disable(rdev);
3446         r600_rlc_stop(rdev);
3447 }
3448
3449 void r600_irq_fini(struct radeon_device *rdev)
3450 {
3451         r600_irq_suspend(rdev);
3452         r600_ih_ring_fini(rdev);
3453 }
3454
3455 int r600_irq_set(struct radeon_device *rdev)
3456 {
3457         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3458         u32 mode_int = 0;
3459         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3460         u32 grbm_int_cntl = 0;
3461         u32 hdmi0, hdmi1;
3462         u32 d1grph = 0, d2grph = 0;
3463         u32 dma_cntl;
3464
3465         if (!rdev->irq.installed) {
3466                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3467                 return -EINVAL;
3468         }
3469         /* don't enable anything if the ih is disabled */
3470         if (!rdev->ih.enabled) {
3471                 r600_disable_interrupts(rdev);
3472                 /* force the active interrupt state to all disabled */
3473                 r600_disable_interrupt_state(rdev);
3474                 return 0;
3475         }
3476
3477         if (ASIC_IS_DCE3(rdev)) {
3478                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3479                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3480                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3481                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3482                 if (ASIC_IS_DCE32(rdev)) {
3483                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3484                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3485                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3486                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3487                 } else {
3488                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3489                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3490                 }
3491         } else {
3492                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3493                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3494                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3495                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3496                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3497         }
3498         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3499
3500         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3501                 DRM_DEBUG("r600_irq_set: sw int\n");
3502                 cp_int_cntl |= RB_INT_ENABLE;
3503                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3504         }
3505
3506         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3507                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3508                 dma_cntl |= TRAP_ENABLE;
3509         }
3510
3511         if (rdev->irq.crtc_vblank_int[0] ||
3512             atomic_read(&rdev->irq.pflip[0])) {
3513                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3514                 mode_int |= D1MODE_VBLANK_INT_MASK;
3515         }
3516         if (rdev->irq.crtc_vblank_int[1] ||
3517             atomic_read(&rdev->irq.pflip[1])) {
3518                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3519                 mode_int |= D2MODE_VBLANK_INT_MASK;
3520         }
3521         if (rdev->irq.hpd[0]) {
3522                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3523                 hpd1 |= DC_HPDx_INT_EN;
3524         }
3525         if (rdev->irq.hpd[1]) {
3526                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3527                 hpd2 |= DC_HPDx_INT_EN;
3528         }
3529         if (rdev->irq.hpd[2]) {
3530                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3531                 hpd3 |= DC_HPDx_INT_EN;
3532         }
3533         if (rdev->irq.hpd[3]) {
3534                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3535                 hpd4 |= DC_HPDx_INT_EN;
3536         }
3537         if (rdev->irq.hpd[4]) {
3538                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3539                 hpd5 |= DC_HPDx_INT_EN;
3540         }
3541         if (rdev->irq.hpd[5]) {
3542                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3543                 hpd6 |= DC_HPDx_INT_EN;
3544         }
3545         if (rdev->irq.afmt[0]) {
3546                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3547                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3548         }
3549         if (rdev->irq.afmt[1]) {
3550                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3551                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3552         }
3553
3554         WREG32(CP_INT_CNTL, cp_int_cntl);
3555         WREG32(DMA_CNTL, dma_cntl);
3556         WREG32(DxMODE_INT_MASK, mode_int);
3557         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3558         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3559         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3560         if (ASIC_IS_DCE3(rdev)) {
3561                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3562                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3563                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3564                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3565                 if (ASIC_IS_DCE32(rdev)) {
3566                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3567                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3568                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3569                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3570                 } else {
3571                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3572                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3573                 }
3574         } else {
3575                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3576                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3577                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3578                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3579                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3580         }
3581
3582         return 0;
3583 }
3584
3585 static void r600_irq_ack(struct radeon_device *rdev)
3586 {
3587         u32 tmp;
3588
3589         if (ASIC_IS_DCE3(rdev)) {
3590                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3591                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3592                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3593                 if (ASIC_IS_DCE32(rdev)) {
3594                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3595                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3596                 } else {
3597                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3598                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3599                 }
3600         } else {
3601                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3602                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3603                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3604                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3605                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3606         }
3607         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3608         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3609
3610         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3611                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3612         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3613                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3614         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3615                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3616         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3617                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3618         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3619                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3620         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3621                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3622         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3623                 if (ASIC_IS_DCE3(rdev)) {
3624                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3625                         tmp |= DC_HPDx_INT_ACK;
3626                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3627                 } else {
3628                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3629                         tmp |= DC_HPDx_INT_ACK;
3630                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3631                 }
3632         }
3633         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3634                 if (ASIC_IS_DCE3(rdev)) {
3635                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3636                         tmp |= DC_HPDx_INT_ACK;
3637                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3638                 } else {
3639                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3640                         tmp |= DC_HPDx_INT_ACK;
3641                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3642                 }
3643         }
3644         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3645                 if (ASIC_IS_DCE3(rdev)) {
3646                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3647                         tmp |= DC_HPDx_INT_ACK;
3648                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3649                 } else {
3650                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3651                         tmp |= DC_HPDx_INT_ACK;
3652                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3653                 }
3654         }
3655         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3656                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3657                 tmp |= DC_HPDx_INT_ACK;
3658                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3659         }
3660         if (ASIC_IS_DCE32(rdev)) {
3661                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3662                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3663                         tmp |= DC_HPDx_INT_ACK;
3664                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3665                 }
3666                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3667                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3668                         tmp |= DC_HPDx_INT_ACK;
3669                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3670                 }
3671                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3672                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3673                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3674                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3675                 }
3676                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3677                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3678                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3679                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3680                 }
3681         } else {
3682                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3683                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3684                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3685                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3686                 }
3687                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3688                         if (ASIC_IS_DCE3(rdev)) {
3689                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3690                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3691                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3692                         } else {
3693                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3694                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3695                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3696                         }
3697                 }
3698         }
3699 }
3700
3701 void r600_irq_disable(struct radeon_device *rdev)
3702 {
3703         r600_disable_interrupts(rdev);
3704         /* Wait and acknowledge irq */
3705         mdelay(1);
3706         r600_irq_ack(rdev);
3707         r600_disable_interrupt_state(rdev);
3708 }
3709
3710 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3711 {
3712         u32 wptr, tmp;
3713
3714         if (rdev->wb.enabled)
3715                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3716         else
3717                 wptr = RREG32(IH_RB_WPTR);
3718
3719         if (wptr & RB_OVERFLOW) {
3720                 /* When a ring buffer overflow happen start parsing interrupt
3721                  * from the last not overwritten vector (wptr + 16). Hopefully
3722                  * this should allow us to catchup.
3723                  */
3724                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3725                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3726                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3727                 tmp = RREG32(IH_RB_CNTL);
3728                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3729                 WREG32(IH_RB_CNTL, tmp);
3730         }
3731         return (wptr & rdev->ih.ptr_mask);
3732 }
3733
3734 /*        r600 IV Ring
3735  * Each IV ring entry is 128 bits:
3736  * [7:0]    - interrupt source id
3737  * [31:8]   - reserved
3738  * [59:32]  - interrupt source data
3739  * [127:60]  - reserved
3740  *
3741  * The basic interrupt vector entries
3742  * are decoded as follows:
3743  * src_id  src_data  description
3744  *      1         0  D1 Vblank
3745  *      1         1  D1 Vline
3746  *      5         0  D2 Vblank
3747  *      5         1  D2 Vline
3748  *     19         0  FP Hot plug detection A
3749  *     19         1  FP Hot plug detection B
3750  *     19         2  DAC A auto-detection
3751  *     19         3  DAC B auto-detection
3752  *     21         4  HDMI block A
3753  *     21         5  HDMI block B
3754  *    176         -  CP_INT RB
3755  *    177         -  CP_INT IB1
3756  *    178         -  CP_INT IB2
3757  *    181         -  EOP Interrupt
3758  *    233         -  GUI Idle
3759  *
3760  * Note, these are based on r600 and may need to be
3761  * adjusted or added to on newer asics
3762  */
3763
3764 int r600_irq_process(struct radeon_device *rdev)
3765 {
3766         u32 wptr;
3767         u32 rptr;
3768         u32 src_id, src_data;
3769         u32 ring_index;
3770         bool queue_hotplug = false;
3771         bool queue_hdmi = false;
3772
3773         if (!rdev->ih.enabled || rdev->shutdown)
3774                 return IRQ_NONE;
3775
3776         /* No MSIs, need a dummy read to flush PCI DMAs */
3777         if (!rdev->msi_enabled)
3778                 RREG32(IH_RB_WPTR);
3779
3780         wptr = r600_get_ih_wptr(rdev);
3781
3782 restart_ih:
3783         /* is somebody else already processing irqs? */
3784         if (atomic_xchg(&rdev->ih.lock, 1))
3785                 return IRQ_NONE;
3786
3787         rptr = rdev->ih.rptr;
3788         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3789
3790         /* Order reading of wptr vs. reading of IH ring data */
3791         rmb();
3792
3793         /* display interrupts */
3794         r600_irq_ack(rdev);
3795
3796         while (rptr != wptr) {
3797                 /* wptr/rptr are in bytes! */
3798                 ring_index = rptr / 4;
3799                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3800                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3801
3802                 switch (src_id) {
3803                 case 1: /* D1 vblank/vline */
3804                         switch (src_data) {
3805                         case 0: /* D1 vblank */
3806                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3807                                         if (rdev->irq.crtc_vblank_int[0]) {
3808                                                 drm_handle_vblank(rdev->ddev, 0);
3809                                                 rdev->pm.vblank_sync = true;
3810                                                 wake_up(&rdev->irq.vblank_queue);
3811                                         }
3812                                         if (atomic_read(&rdev->irq.pflip[0]))
3813                                                 radeon_crtc_handle_flip(rdev, 0);
3814                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3815                                         DRM_DEBUG("IH: D1 vblank\n");
3816                                 }
3817                                 break;
3818                         case 1: /* D1 vline */
3819                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3820                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3821                                         DRM_DEBUG("IH: D1 vline\n");
3822                                 }
3823                                 break;
3824                         default:
3825                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3826                                 break;
3827                         }
3828                         break;
3829                 case 5: /* D2 vblank/vline */
3830                         switch (src_data) {
3831                         case 0: /* D2 vblank */
3832                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3833                                         if (rdev->irq.crtc_vblank_int[1]) {
3834                                                 drm_handle_vblank(rdev->ddev, 1);
3835                                                 rdev->pm.vblank_sync = true;
3836                                                 wake_up(&rdev->irq.vblank_queue);
3837                                         }
3838                                         if (atomic_read(&rdev->irq.pflip[1]))
3839                                                 radeon_crtc_handle_flip(rdev, 1);
3840                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3841                                         DRM_DEBUG("IH: D2 vblank\n");
3842                                 }
3843                                 break;
3844                         case 1: /* D1 vline */
3845                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3846                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3847                                         DRM_DEBUG("IH: D2 vline\n");
3848                                 }
3849                                 break;
3850                         default:
3851                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3852                                 break;
3853                         }
3854                         break;
3855                 case 19: /* HPD/DAC hotplug */
3856                         switch (src_data) {
3857                         case 0:
3858                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3859                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3860                                         queue_hotplug = true;
3861                                         DRM_DEBUG("IH: HPD1\n");
3862                                 }
3863                                 break;
3864                         case 1:
3865                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3866                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3867                                         queue_hotplug = true;
3868                                         DRM_DEBUG("IH: HPD2\n");
3869                                 }
3870                                 break;
3871                         case 4:
3872                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3873                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3874                                         queue_hotplug = true;
3875                                         DRM_DEBUG("IH: HPD3\n");
3876                                 }
3877                                 break;
3878                         case 5:
3879                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3880                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3881                                         queue_hotplug = true;
3882                                         DRM_DEBUG("IH: HPD4\n");
3883                                 }
3884                                 break;
3885                         case 10:
3886                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3887                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3888                                         queue_hotplug = true;
3889                                         DRM_DEBUG("IH: HPD5\n");
3890                                 }
3891                                 break;
3892                         case 12:
3893                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3894                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3895                                         queue_hotplug = true;
3896                                         DRM_DEBUG("IH: HPD6\n");
3897                                 }
3898                                 break;
3899                         default:
3900                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3901                                 break;
3902                         }
3903                         break;
3904                 case 21: /* hdmi */
3905                         switch (src_data) {
3906                         case 4:
3907                                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3908                                         rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3909                                         queue_hdmi = true;
3910                                         DRM_DEBUG("IH: HDMI0\n");
3911                                 }
3912                                 break;
3913                         case 5:
3914                                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3915                                         rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3916                                         queue_hdmi = true;
3917                                         DRM_DEBUG("IH: HDMI1\n");
3918                                 }
3919                                 break;
3920                         default:
3921                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3922                                 break;
3923                         }
3924                         break;
3925                 case 176: /* CP_INT in ring buffer */
3926                 case 177: /* CP_INT in IB1 */
3927                 case 178: /* CP_INT in IB2 */
3928                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3929                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3930                         break;
3931                 case 181: /* CP EOP event */
3932                         DRM_DEBUG("IH: CP EOP\n");
3933                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3934                         break;
3935                 case 224: /* DMA trap event */
3936                         DRM_DEBUG("IH: DMA trap\n");
3937                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3938                         break;
3939                 case 233: /* GUI IDLE */
3940                         DRM_DEBUG("IH: GUI idle\n");
3941                         break;
3942                 default:
3943                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3944                         break;
3945                 }
3946
3947                 /* wptr/rptr are in bytes! */
3948                 rptr += 16;
3949                 rptr &= rdev->ih.ptr_mask;
3950         }
3951         if (queue_hotplug)
3952                 schedule_work(&rdev->hotplug_work);
3953         if (queue_hdmi)
3954                 schedule_work(&rdev->audio_work);
3955         rdev->ih.rptr = rptr;
3956         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3957         atomic_set(&rdev->ih.lock, 0);
3958
3959         /* make sure wptr hasn't changed while processing */
3960         wptr = r600_get_ih_wptr(rdev);
3961         if (wptr != rptr)
3962                 goto restart_ih;
3963
3964         return IRQ_HANDLED;
3965 }
3966
3967 /*
3968  * Debugfs info
3969  */
3970 #if defined(CONFIG_DEBUG_FS)
3971
3972 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3973 {
3974         struct drm_info_node *node = (struct drm_info_node *) m->private;
3975         struct drm_device *dev = node->minor->dev;
3976         struct radeon_device *rdev = dev->dev_private;
3977
3978         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3979         DREG32_SYS(m, rdev, VM_L2_STATUS);
3980         return 0;
3981 }
3982
3983 static struct drm_info_list r600_mc_info_list[] = {
3984         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3985 };
3986 #endif
3987
3988 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3989 {
3990 #if defined(CONFIG_DEBUG_FS)
3991         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3992 #else
3993         return 0;
3994 #endif
3995 }
3996
3997 /**
3998  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3999  * rdev: radeon device structure
4000  * bo: buffer object struct which userspace is waiting for idle
4001  *
4002  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4003  * through ring buffer, this leads to corruption in rendering, see
4004  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4005  * directly perform HDP flush by writing register through MMIO.
4006  */
4007 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4008 {
4009         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4010          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4011          * This seems to cause problems on some AGP cards. Just use the old
4012          * method for them.
4013          */
4014         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4015             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4016                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4017                 u32 tmp;
4018
4019                 WREG32(HDP_DEBUG1, 0);
4020                 tmp = readl((void __iomem *)ptr);
4021         } else
4022                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4023 }
4024
4025 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4026 {
4027         u32 link_width_cntl, mask, target_reg;
4028
4029         if (rdev->flags & RADEON_IS_IGP)
4030                 return;
4031
4032         if (!(rdev->flags & RADEON_IS_PCIE))
4033                 return;
4034
4035         /* x2 cards have a special sequence */
4036         if (ASIC_IS_X2(rdev))
4037                 return;
4038
4039         /* FIXME wait for idle */
4040
4041         switch (lanes) {
4042         case 0:
4043                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4044                 break;
4045         case 1:
4046                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4047                 break;
4048         case 2:
4049                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4050                 break;
4051         case 4:
4052                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4053                 break;
4054         case 8:
4055                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4056                 break;
4057         case 12:
4058                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4059                 break;
4060         case 16:
4061         default:
4062                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4063                 break;
4064         }
4065
4066         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4067
4068         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4069             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4070                 return;
4071
4072         if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4073                 return;
4074
4075         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
4076                              RADEON_PCIE_LC_RECONFIG_NOW |
4077                              R600_PCIE_LC_RENEGOTIATE_EN |
4078                              R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4079         link_width_cntl |= mask;
4080
4081         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4082
4083         /* some northbridges can renegotiate the link rather than requiring
4084          * a complete re-config.
4085          * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4086          */
4087         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4088                 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4089         else
4090                 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4091
4092         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4093                                                        RADEON_PCIE_LC_RECONFIG_NOW));
4094
4095         if (rdev->family >= CHIP_RV770)
4096                 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4097         else
4098                 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4099
4100         /* wait for lane set to complete */
4101         link_width_cntl = RREG32(target_reg);
4102         while (link_width_cntl == 0xffffffff)
4103                 link_width_cntl = RREG32(target_reg);
4104
4105 }
4106
4107 int r600_get_pcie_lanes(struct radeon_device *rdev)
4108 {
4109         u32 link_width_cntl;
4110
4111         if (rdev->flags & RADEON_IS_IGP)
4112                 return 0;
4113
4114         if (!(rdev->flags & RADEON_IS_PCIE))
4115                 return 0;
4116
4117         /* x2 cards have a special sequence */
4118         if (ASIC_IS_X2(rdev))
4119                 return 0;
4120
4121         /* FIXME wait for idle */
4122
4123         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4124
4125         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4126         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4127                 return 0;
4128         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4129                 return 1;
4130         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4131                 return 2;
4132         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4133                 return 4;
4134         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4135                 return 8;
4136         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4137         default:
4138                 return 16;
4139         }
4140 }
4141
4142 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4143 {
4144         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4145         u16 link_cntl2;
4146         u32 mask;
4147         int ret;
4148
4149         if (radeon_pcie_gen2 == 0)
4150                 return;
4151
4152         if (rdev->flags & RADEON_IS_IGP)
4153                 return;
4154
4155         if (!(rdev->flags & RADEON_IS_PCIE))
4156                 return;
4157
4158         /* x2 cards have a special sequence */
4159         if (ASIC_IS_X2(rdev))
4160                 return;
4161
4162         /* only RV6xx+ chips are supported */
4163         if (rdev->family <= CHIP_R600)
4164                 return;
4165
4166         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
4167         if (ret != 0)
4168                 return;
4169
4170         if (!(mask & DRM_PCIE_SPEED_50))
4171                 return;
4172
4173         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4174         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4175                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4176                 return;
4177         }
4178
4179         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4180
4181         /* 55 nm r6xx asics */
4182         if ((rdev->family == CHIP_RV670) ||
4183             (rdev->family == CHIP_RV620) ||
4184             (rdev->family == CHIP_RV635)) {
4185                 /* advertise upconfig capability */
4186                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4187                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4188                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4189                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4190                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4191                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4192                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4193                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4194                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4195                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4196                 } else {
4197                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4198                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4199                 }
4200         }
4201
4202         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4203         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4204             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4205
4206                 /* 55 nm r6xx asics */
4207                 if ((rdev->family == CHIP_RV670) ||
4208                     (rdev->family == CHIP_RV620) ||
4209                     (rdev->family == CHIP_RV635)) {
4210                         WREG32(MM_CFGREGS_CNTL, 0x8);
4211                         link_cntl2 = RREG32(0x4088);
4212                         WREG32(MM_CFGREGS_CNTL, 0);
4213                         /* not supported yet */
4214                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4215                                 return;
4216                 }
4217
4218                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4219                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4220                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4221                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4222                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4223                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4224
4225                 tmp = RREG32(0x541c);
4226                 WREG32(0x541c, tmp | 0x8);
4227                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4228                 link_cntl2 = RREG16(0x4088);
4229                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4230                 link_cntl2 |= 0x2;
4231                 WREG16(0x4088, link_cntl2);
4232                 WREG32(MM_CFGREGS_CNTL, 0);
4233
4234                 if ((rdev->family == CHIP_RV670) ||
4235                     (rdev->family == CHIP_RV620) ||
4236                     (rdev->family == CHIP_RV635)) {
4237                         training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
4238                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4239                         WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
4240                 } else {
4241                         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4242                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4243                         WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4244                 }
4245
4246                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4247                 speed_cntl |= LC_GEN2_EN_STRAP;
4248                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4249
4250         } else {
4251                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4252                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4253                 if (1)
4254                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4255                 else
4256                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4257                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4258         }
4259 }
4260
4261 /**
4262  * r600_get_gpu_clock - return GPU clock counter snapshot
4263  *
4264  * @rdev: radeon_device pointer
4265  *
4266  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4267  * Returns the 64 bit clock counter snapshot.
4268  */
4269 uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
4270 {
4271         uint64_t clock;
4272
4273         mutex_lock(&rdev->gpu_clock_mutex);
4274         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4275         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4276                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4277         mutex_unlock(&rdev->gpu_clock_mutex);
4278         return clock;
4279 }