drivers/gpu/drm/radeon/r600_blit_kms.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  * Copyright 2009 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include "drmP.h"
  27 #include "drm.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30
  31 #include "r600d.h"
  32 #include "r600_blit_shaders.h"
  33
  34 #define DI_PT_RECTLIST        0x11
  35 #define DI_INDEX_SIZE_16_BIT  0x0
  36 #define DI_SRC_SEL_AUTO_INDEX 0x2
  37
  38 #define FMT_8                 0x1
  39 #define FMT_5_6_5             0x8
  40 #define FMT_8_8_8_8           0x1a
  41 #define COLOR_8               0x1
  42 #define COLOR_5_6_5           0x8
  43 #define COLOR_8_8_8_8         0x1a
  44
  45 #define RECT_UNIT_H           32
  46 #define RECT_UNIT_W           (RADEON_GPU_PAGE_SIZE / 4 / RECT_UNIT_H)
  47 #define MAX_RECT_DIM          8192
  48
  49 /* emits 21 on rv770+, 23 on r600 */
  50 static void
  51 set_render_target(struct radeon_device *rdev, int format,
  52                   int w, int h, u64 gpu_addr)
  53 {
  54         u32 cb_color_info;
  55         int pitch, slice;
  56
  57         h = ALIGN(h, 8);
  58         if (h < 8)
  59                 h = 8;
  60
  61         cb_color_info = CB_FORMAT(format) |
  62                 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
  63                 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
  64         pitch = (w / 8) - 1;
  65         slice = ((w * h) / 64) - 1;
  66
  67         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  68         radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  69         radeon_ring_write(rdev, gpu_addr >> 8);
  70
  71         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
  72                 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
  73                 radeon_ring_write(rdev, 2 << 0);
  74         }
  75
  76         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  77         radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  78         radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
  79
  80         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  81         radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  82         radeon_ring_write(rdev, 0);
  83
  84         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  85         radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  86         radeon_ring_write(rdev, cb_color_info);
  87
  88         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  89         radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  90         radeon_ring_write(rdev, 0);
  91
  92         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  93         radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  94         radeon_ring_write(rdev, 0);
  95
  96         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  97         radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  98         radeon_ring_write(rdev, 0);
  99 }
 100
 101 /* emits 5dw */
 102 static void
 103 cp_set_surface_sync(struct radeon_device *rdev,
 104                     u32 sync_type, u32 size,
 105                     u64 mc_addr)
 106 {
 107         u32 cp_coher_size;
 108
 109         if (size == 0xffffffff)
 110                 cp_coher_size = 0xffffffff;
 111         else
 112                 cp_coher_size = ((size + 255) >> 8);
 113
 114         radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
 115         radeon_ring_write(rdev, sync_type);
 116         radeon_ring_write(rdev, cp_coher_size);
 117         radeon_ring_write(rdev, mc_addr >> 8);
 118         radeon_ring_write(rdev, 10); /* poll interval */
 119 }
 120
 121 /* emits 21dw + 1 surface sync = 26dw */
 122 static void
 123 set_shaders(struct radeon_device *rdev)
 124 {
 125         u64 gpu_addr;
 126         u32 sq_pgm_resources;
 127
 128         /* setup shader regs */
 129         sq_pgm_resources = (1 << 0);
 130
 131         /* VS */
 132         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 133         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 134         radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 135         radeon_ring_write(rdev, gpu_addr >> 8);
 136
 137         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 138         radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 139         radeon_ring_write(rdev, sq_pgm_resources);
 140
 141         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 142         radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 143         radeon_ring_write(rdev, 0);
 144
 145         /* PS */
 146         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 147         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 148         radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 149         radeon_ring_write(rdev, gpu_addr >> 8);
 150
 151         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 152         radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 153         radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
 154
 155         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 156         radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 157         radeon_ring_write(rdev, 2);
 158
 159         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 160         radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 161         radeon_ring_write(rdev, 0);
 162
 163         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 164         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 165 }
 166
 167 /* emits 9 + 1 sync (5) = 14*/
 168 static void
 169 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 170 {
 171         u32 sq_vtx_constant_word2;
 172
 173         sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
 174                 SQ_VTXC_STRIDE(16);
 175 #ifdef __BIG_ENDIAN
 176         sq_vtx_constant_word2 |=  SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
 177 #endif
 178
 179         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
 180         radeon_ring_write(rdev, 0x460);
 181         radeon_ring_write(rdev, gpu_addr & 0xffffffff);
 182         radeon_ring_write(rdev, 48 - 1);
 183         radeon_ring_write(rdev, sq_vtx_constant_word2);
 184         radeon_ring_write(rdev, 1 << 0);
 185         radeon_ring_write(rdev, 0);
 186         radeon_ring_write(rdev, 0);
 187         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
 188
 189         if ((rdev->family == CHIP_RV610) ||
 190             (rdev->family == CHIP_RV620) ||
 191             (rdev->family == CHIP_RS780) ||
 192             (rdev->family == CHIP_RS880) ||
 193             (rdev->family == CHIP_RV710))
 194                 cp_set_surface_sync(rdev,
 195                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 196         else
 197                 cp_set_surface_sync(rdev,
 198                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 199 }
 200
 201 /* emits 9 */
 202 static void
 203 set_tex_resource(struct radeon_device *rdev,
 204                  int format, int w, int h, int pitch,
 205                  u64 gpu_addr)
 206 {
 207         uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 208
 209         if (h < 1)
 210                 h = 1;
 211
 212         sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
 213                 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
 214         sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
 215                 S_038000_TEX_WIDTH(w - 1);
 216
 217         sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
 218         sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
 219
 220         sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
 221                 S_038010_DST_SEL_X(SQ_SEL_X) |
 222                 S_038010_DST_SEL_Y(SQ_SEL_Y) |
 223                 S_038010_DST_SEL_Z(SQ_SEL_Z) |
 224                 S_038010_DST_SEL_W(SQ_SEL_W);
 225
 226         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
 227         radeon_ring_write(rdev, 0);
 228         radeon_ring_write(rdev, sq_tex_resource_word0);
 229         radeon_ring_write(rdev, sq_tex_resource_word1);
 230         radeon_ring_write(rdev, gpu_addr >> 8);
 231         radeon_ring_write(rdev, gpu_addr >> 8);
 232         radeon_ring_write(rdev, sq_tex_resource_word4);
 233         radeon_ring_write(rdev, 0);
 234         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
 235 }
 236
 237 /* emits 12 */
 238 static void
 239 set_scissors(struct radeon_device *rdev, int x1, int y1,
 240              int x2, int y2)
 241 {
 242         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 243         radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 244         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
 245         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 246
 247         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 248         radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 249         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 250         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 251
 252         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 253         radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 254         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 255         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 256 }
 257
 258 /* emits 10 */
 259 static void
 260 draw_auto(struct radeon_device *rdev)
 261 {
 262         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 263         radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 264         radeon_ring_write(rdev, DI_PT_RECTLIST);
 265
 266         radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
 267         radeon_ring_write(rdev,
 268 #ifdef __BIG_ENDIAN
 269                           (2 << 2) |
 270 #endif
 271                           DI_INDEX_SIZE_16_BIT);
 272
 273         radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
 274         radeon_ring_write(rdev, 1);
 275
 276         radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 277         radeon_ring_write(rdev, 3);
 278         radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 279
 280 }
 281
 282 /* emits 14 */
 283 static void
 284 set_default_state(struct radeon_device *rdev)
 285 {
 286         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
 287         u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
 288         int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
 289         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 290         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 291         u64 gpu_addr;
 292         int dwords;
 293
 294         switch (rdev->family) {
 295         case CHIP_R600:
 296                 num_ps_gprs = 192;
 297                 num_vs_gprs = 56;
 298                 num_temp_gprs = 4;
 299                 num_gs_gprs = 0;
 300                 num_es_gprs = 0;
 301                 num_ps_threads = 136;
 302                 num_vs_threads = 48;
 303                 num_gs_threads = 4;
 304                 num_es_threads = 4;
 305                 num_ps_stack_entries = 128;
 306                 num_vs_stack_entries = 128;
 307                 num_gs_stack_entries = 0;
 308                 num_es_stack_entries = 0;
 309                 break;
 310         case CHIP_RV630:
 311         case CHIP_RV635:
 312                 num_ps_gprs = 84;
 313                 num_vs_gprs = 36;
 314                 num_temp_gprs = 4;
 315                 num_gs_gprs = 0;
 316                 num_es_gprs = 0;
 317                 num_ps_threads = 144;
 318                 num_vs_threads = 40;
 319                 num_gs_threads = 4;
 320                 num_es_threads = 4;
 321                 num_ps_stack_entries = 40;
 322                 num_vs_stack_entries = 40;
 323                 num_gs_stack_entries = 32;
 324                 num_es_stack_entries = 16;
 325                 break;
 326         case CHIP_RV610:
 327         case CHIP_RV620:
 328         case CHIP_RS780:
 329         case CHIP_RS880:
 330         default:
 331                 num_ps_gprs = 84;
 332                 num_vs_gprs = 36;
 333                 num_temp_gprs = 4;
 334                 num_gs_gprs = 0;
 335                 num_es_gprs = 0;
 336                 num_ps_threads = 136;
 337                 num_vs_threads = 48;
 338                 num_gs_threads = 4;
 339                 num_es_threads = 4;
 340                 num_ps_stack_entries = 40;
 341                 num_vs_stack_entries = 40;
 342                 num_gs_stack_entries = 32;
 343                 num_es_stack_entries = 16;
 344                 break;
 345         case CHIP_RV670:
 346                 num_ps_gprs = 144;
 347                 num_vs_gprs = 40;
 348                 num_temp_gprs = 4;
 349                 num_gs_gprs = 0;
 350                 num_es_gprs = 0;
 351                 num_ps_threads = 136;
 352                 num_vs_threads = 48;
 353                 num_gs_threads = 4;
 354                 num_es_threads = 4;
 355                 num_ps_stack_entries = 40;
 356                 num_vs_stack_entries = 40;
 357                 num_gs_stack_entries = 32;
 358                 num_es_stack_entries = 16;
 359                 break;
 360         case CHIP_RV770:
 361                 num_ps_gprs = 192;
 362                 num_vs_gprs = 56;
 363                 num_temp_gprs = 4;
 364                 num_gs_gprs = 0;
 365                 num_es_gprs = 0;
 366                 num_ps_threads = 188;
 367                 num_vs_threads = 60;
 368                 num_gs_threads = 0;
 369                 num_es_threads = 0;
 370                 num_ps_stack_entries = 256;
 371                 num_vs_stack_entries = 256;
 372                 num_gs_stack_entries = 0;
 373                 num_es_stack_entries = 0;
 374                 break;
 375         case CHIP_RV730:
 376         case CHIP_RV740:
 377                 num_ps_gprs = 84;
 378                 num_vs_gprs = 36;
 379                 num_temp_gprs = 4;
 380                 num_gs_gprs = 0;
 381                 num_es_gprs = 0;
 382                 num_ps_threads = 188;
 383                 num_vs_threads = 60;
 384                 num_gs_threads = 0;
 385                 num_es_threads = 0;
 386                 num_ps_stack_entries = 128;
 387                 num_vs_stack_entries = 128;
 388                 num_gs_stack_entries = 0;
 389                 num_es_stack_entries = 0;
 390                 break;
 391         case CHIP_RV710:
 392                 num_ps_gprs = 192;
 393                 num_vs_gprs = 56;
 394                 num_temp_gprs = 4;
 395                 num_gs_gprs = 0;
 396                 num_es_gprs = 0;
 397                 num_ps_threads = 144;
 398                 num_vs_threads = 48;
 399                 num_gs_threads = 0;
 400                 num_es_threads = 0;
 401                 num_ps_stack_entries = 128;
 402                 num_vs_stack_entries = 128;
 403                 num_gs_stack_entries = 0;
 404                 num_es_stack_entries = 0;
 405                 break;
 406         }
 407
 408         if ((rdev->family == CHIP_RV610) ||
 409             (rdev->family == CHIP_RV620) ||
 410             (rdev->family == CHIP_RS780) ||
 411             (rdev->family == CHIP_RS880) ||
 412             (rdev->family == CHIP_RV710))
 413                 sq_config = 0;
 414         else
 415                 sq_config = VC_ENABLE;
 416
 417         sq_config |= (DX9_CONSTS |
 418                       ALU_INST_PREFER_VECTOR |
 419                       PS_PRIO(0) |
 420                       VS_PRIO(1) |
 421                       GS_PRIO(2) |
 422                       ES_PRIO(3));
 423
 424         sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 425                                   NUM_VS_GPRS(num_vs_gprs) |
 426                                   NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 427         sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 428                                   NUM_ES_GPRS(num_es_gprs));
 429         sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 430                                    NUM_VS_THREADS(num_vs_threads) |
 431                                    NUM_GS_THREADS(num_gs_threads) |
 432                                    NUM_ES_THREADS(num_es_threads));
 433         sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 434                                     NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 435         sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 436                                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 437
 438         /* emit an IB pointing at default state */
 439         dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
 440         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
 441         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 442         radeon_ring_write(rdev,
 443 #ifdef __BIG_ENDIAN
 444                           (2 << 0) |
 445 #endif
 446                           (gpu_addr & 0xFFFFFFFC));
 447         radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
 448         radeon_ring_write(rdev, dwords);
 449
 450         /* SQ config */
 451         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
 452         radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 453         radeon_ring_write(rdev, sq_config);
 454         radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
 455         radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
 456         radeon_ring_write(rdev, sq_thread_resource_mgmt);
 457         radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
 458         radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
 459 }
 460
 461 static uint32_t i2f(uint32_t input)
 462 {
 463         u32 result, i, exponent, fraction;
 464
 465         if ((input & 0x3fff) == 0)
 466                 result = 0; /* 0 is a special case */
 467         else {
 468                 exponent = 140; /* exponent biased by 127; */
 469                 fraction = (input & 0x3fff) << 10; /* cheat and only
 470                                                       handle numbers below 2^^15 */
 471                 for (i = 0; i < 14; i++) {
 472                         if (fraction & 0x800000)
 473                                 break;
 474                         else {
 475                                 fraction = fraction << 1; /* keep
 476                                                              shifting left until top bit = 1 */
 477                                 exponent = exponent - 1;
 478                         }
 479                 }
 480                 result = exponent << 23 | (fraction & 0x7fffff); /* mask
 481                                                                     off top bit; assumed 1 */
 482         }
 483         return result;
 484 }
 485
 486 int r600_blit_init(struct radeon_device *rdev)
 487 {
 488         u32 obj_size;
 489         int i, r, dwords;
 490         void *ptr;
 491         u32 packet2s[16];
 492         int num_packet2s = 0;
 493
 494         /* pin copy shader into vram if already initialized */
 495         if (rdev->r600_blit.shader_obj)
 496                 goto done;
 497
 498         mutex_init(&rdev->r600_blit.mutex);
 499         rdev->r600_blit.state_offset = 0;
 500
 501         if (rdev->family >= CHIP_RV770)
 502                 rdev->r600_blit.state_len = r7xx_default_size;
 503         else
 504                 rdev->r600_blit.state_len = r6xx_default_size;
 505
 506         dwords = rdev->r600_blit.state_len;
 507         while (dwords & 0xf) {
 508                 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
 509                 dwords++;
 510         }
 511
 512         obj_size = dwords * 4;
 513         obj_size = ALIGN(obj_size, 256);
 514
 515         rdev->r600_blit.vs_offset = obj_size;
 516         obj_size += r6xx_vs_size * 4;
 517         obj_size = ALIGN(obj_size, 256);
 518
 519         rdev->r600_blit.ps_offset = obj_size;
 520         obj_size += r6xx_ps_size * 4;
 521         obj_size = ALIGN(obj_size, 256);
 522
 523         r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 524                                 &rdev->r600_blit.shader_obj);
 525         if (r) {
 526                 DRM_ERROR("r600 failed to allocate shader\n");
 527                 return r;
 528         }
 529
 530         DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
 531                   obj_size,
 532                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 533
 534         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 535         if (unlikely(r != 0))
 536                 return r;
 537         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 538         if (r) {
 539                 DRM_ERROR("failed to map blit object %d\n", r);
 540                 return r;
 541         }
 542         if (rdev->family >= CHIP_RV770)
 543                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 544                             r7xx_default_state, rdev->r600_blit.state_len * 4);
 545         else
 546                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 547                             r6xx_default_state, rdev->r600_blit.state_len * 4);
 548         if (num_packet2s)
 549                 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 550                             packet2s, num_packet2s * 4);
 551         for (i = 0; i < r6xx_vs_size; i++)
 552                 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
 553         for (i = 0; i < r6xx_ps_size; i++)
 554                 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
 555         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 556         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 557
 558 done:
 559         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 560         if (unlikely(r != 0))
 561                 return r;
 562         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 563                           &rdev->r600_blit.shader_gpu_addr);
 564         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 565         if (r) {
 566                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 567                 return r;
 568         }
 569         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 570         return 0;
 571 }
 572
 573 void r600_blit_fini(struct radeon_device *rdev)
 574 {
 575         int r;
 576
 577         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 578         if (rdev->r600_blit.shader_obj == NULL)
 579                 return;
 580         /* If we can't reserve the bo, unref should be enough to destroy
 581          * it when it becomes idle.
 582          */
 583         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 584         if (!r) {
 585                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
 586                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 587         }
 588         radeon_bo_unref(&rdev->r600_blit.shader_obj);
 589 }
 590
 591 static int r600_vb_ib_get(struct radeon_device *rdev)
 592 {
 593         int r;
 594         r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
 595         if (r) {
 596                 DRM_ERROR("failed to get IB for vertex buffer\n");
 597                 return r;
 598         }
 599
 600         rdev->r600_blit.vb_total = 64*1024;
 601         rdev->r600_blit.vb_used = 0;
 602         return 0;
 603 }
 604
 605 static void r600_vb_ib_put(struct radeon_device *rdev)
 606 {
 607         radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
 608         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
 609 }
 610
 611 /* FIXME: the function is very similar to evergreen_blit_create_rect, except
 612    that it different predefined constants; consider commonizing */
 613 static unsigned r600_blit_create_rect(unsigned num_pages, int *width, int *height)
 614 {
 615         unsigned max_pages;
 616         unsigned pages = num_pages;
 617         int w, h;
 618
 619         if (num_pages == 0) {
 620                 /* not supposed to be called with no pages, but just in case */
 621                 h = 0;
 622                 w = 0;
 623                 pages = 0;
 624                 WARN_ON(1);
 625         } else {
 626                 int rect_order = 2;
 627                 h = RECT_UNIT_H;
 628                 while (num_pages / rect_order) {
 629                         h *= 2;
 630                         rect_order *= 4;
 631                         if (h >= MAX_RECT_DIM) {
 632                                 h = MAX_RECT_DIM;
 633                                 break;
 634                         }
 635                 }
 636                 max_pages = (MAX_RECT_DIM * h) / (RECT_UNIT_W * RECT_UNIT_H);
 637                 if (pages > max_pages)
 638                         pages = max_pages;
 639                 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
 640                 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
 641                 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
 642                 BUG_ON(pages == 0);
 643         }
 644
 645
 646         DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
 647
 648         /* return width and height only of the caller wants it */
 649         if (height)
 650                 *height = h;
 651         if (width)
 652                 *width = w;
 653
 654         return pages;
 655 }
 656
 657
 658 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_pages)
 659 {
 660         int r;
 661         int ring_size;
 662         /* loops of emits 64 + fence emit possible */
 663         int dwords_per_loop = 76, num_loops = 0;
 664
 665         r = r600_vb_ib_get(rdev);
 666         if (r)
 667                 return r;
 668
 669         /* set_render_target emits 2 extra dwords on rv6xx */
 670         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
 671                 dwords_per_loop += 2;
 672
 673         /* num loops */
 674         while (num_pages) {
 675                 num_pages -= r600_blit_create_rect(num_pages, NULL, NULL);
 676                 num_loops++;
 677         }
 678
 679         /* calculate number of loops correctly */
 680         ring_size = num_loops * dwords_per_loop;
 681         /* set default  + shaders */
 682         ring_size += 40; /* shaders + def state */
 683         ring_size += 10; /* fence emit for VB IB */
 684         ring_size += 5; /* done copy */
 685         ring_size += 10; /* fence emit for done copy */
 686         r = radeon_ring_lock(rdev, ring_size);
 687         if (r)
 688                 return r;
 689
 690         set_default_state(rdev); /* 14 */
 691         set_shaders(rdev); /* 26 */
 692         return 0;
 693 }
 694
 695 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
 696 {
 697         int r;
 698
 699         if (rdev->r600_blit.vb_ib)
 700                 r600_vb_ib_put(rdev);
 701
 702         if (fence)
 703                 r = radeon_fence_emit(rdev, fence);
 704
 705         radeon_ring_unlock_commit(rdev);
 706 }
 707
 708 void r600_kms_blit_copy(struct radeon_device *rdev,
 709                         u64 src_gpu_addr, u64 dst_gpu_addr,
 710                         unsigned num_pages)
 711 {
 712         u64 vb_gpu_addr;
 713         u32 *vb;
 714
 715         DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
 716                   num_pages, rdev->r600_blit.vb_used);
 717         vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 718
 719         while (num_pages) {
 720                 int w, h;
 721                 unsigned size_in_bytes;
 722                 unsigned pages_per_loop = r600_blit_create_rect(num_pages, &w, &h);
 723
 724                 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
 725                 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
 726
 727                 if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 728                         WARN_ON(1);
 729                 }
 730
 731                 vb[0] = 0;
 732                 vb[1] = 0;
 733                 vb[2] = 0;
 734                 vb[3] = 0;
 735
 736                 vb[4] = 0;
 737                 vb[5] = i2f(h);
 738                 vb[6] = 0;
 739                 vb[7] = i2f(h);
 740
 741                 vb[8] = i2f(w);
 742                 vb[9] = i2f(h);
 743                 vb[10] = i2f(w);
 744                 vb[11] = i2f(h);
 745
 746                 /* src 9 */
 747                 set_tex_resource(rdev, FMT_8_8_8_8, w, h, w, src_gpu_addr);
 748
 749                 /* 5 */
 750                 cp_set_surface_sync(rdev,
 751                                     PACKET3_TC_ACTION_ENA, size_in_bytes, src_gpu_addr);
 752
 753                 /* dst 23 */
 754                 set_render_target(rdev, COLOR_8_8_8_8, w, h, dst_gpu_addr);
 755
 756                 /* scissors 12  */
 757                 set_scissors(rdev, 0, 0, w, h);
 758
 759                 /* Vertex buffer setup 14 */
 760                 vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 761                 set_vtx_resource(rdev, vb_gpu_addr);
 762
 763                 /* draw 10 */
 764                 draw_auto(rdev);
 765
 766                 /* 5 */
 767                 cp_set_surface_sync(rdev,
 768                                     PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 769                                     size_in_bytes, dst_gpu_addr);
 770
 771                 /* 78 ring dwords per loop */
 772                 vb += 12;
 773                 rdev->r600_blit.vb_used += 4*12;
 774                 src_gpu_addr += size_in_bytes;
 775                 dst_gpu_addr += size_in_bytes;
 776                 num_pages -= pages_per_loop;
 777         }
 778 }