2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
106 #define RADEON_IB_POOL_SIZE 16
107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
108 #define RADEONFB_CONN_LIMIT 4
109 #define RADEON_BIOS_NUM_SCRATCH 8
111 /* max number of rings */
112 #define RADEON_NUM_RINGS 3
114 /* fence seq are set to this number when signaled */
115 #define RADEON_FENCE_SIGNALED_SEQ 0LL
117 /* internal ring indices */
118 /* r1xx+ has gfx CP ring */
119 #define RADEON_RING_TYPE_GFX_INDEX 0
121 /* cayman has 2 compute CP rings */
122 #define CAYMAN_RING_TYPE_CP1_INDEX 1
123 #define CAYMAN_RING_TYPE_CP2_INDEX 2
125 /* hardcode those limit for now */
126 #define RADEON_VA_RESERVED_SIZE (8 << 20)
127 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
130 * Errata workarounds.
132 enum radeon_pll_errata {
133 CHIP_ERRATA_R300_CG = 0x00000001,
134 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
135 CHIP_ERRATA_PLL_DELAY = 0x00000004
139 struct radeon_device;
145 #define ATRM_BIOS_PAGE 4096
147 #if defined(CONFIG_VGA_SWITCHEROO)
148 bool radeon_atrm_supported(struct pci_dev *pdev);
149 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
151 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
156 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
160 bool radeon_get_bios(struct radeon_device *rdev);
165 struct radeon_dummy_page {
169 int radeon_dummy_page_init(struct radeon_device *rdev);
170 void radeon_dummy_page_fini(struct radeon_device *rdev);
176 struct radeon_clock {
177 struct radeon_pll p1pll;
178 struct radeon_pll p2pll;
179 struct radeon_pll dcpll;
180 struct radeon_pll spll;
181 struct radeon_pll mpll;
183 uint32_t default_mclk;
184 uint32_t default_sclk;
185 uint32_t default_dispclk;
187 uint32_t max_pixel_clock;
193 int radeon_pm_init(struct radeon_device *rdev);
194 void radeon_pm_fini(struct radeon_device *rdev);
195 void radeon_pm_compute_clocks(struct radeon_device *rdev);
196 void radeon_pm_suspend(struct radeon_device *rdev);
197 void radeon_pm_resume(struct radeon_device *rdev);
198 void radeon_combios_get_power_modes(struct radeon_device *rdev);
199 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
200 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
201 void rs690_pm_info(struct radeon_device *rdev);
202 extern int rv6xx_get_temp(struct radeon_device *rdev);
203 extern int rv770_get_temp(struct radeon_device *rdev);
204 extern int evergreen_get_temp(struct radeon_device *rdev);
205 extern int sumo_get_temp(struct radeon_device *rdev);
206 extern int si_get_temp(struct radeon_device *rdev);
207 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
208 unsigned *bankh, unsigned *mtaspect,
209 unsigned *tile_split);
214 struct radeon_fence_driver {
215 uint32_t scratch_reg;
217 volatile uint32_t *cpu_addr;
218 /* sync_seq is protected by ring emission lock */
219 uint64_t sync_seq[RADEON_NUM_RINGS];
221 unsigned long last_activity;
225 struct radeon_fence {
226 struct radeon_device *rdev;
228 /* protected by radeon_fence.lock */
234 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
235 int radeon_fence_driver_init(struct radeon_device *rdev);
236 void radeon_fence_driver_fini(struct radeon_device *rdev);
237 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
238 void radeon_fence_process(struct radeon_device *rdev, int ring);
239 bool radeon_fence_signaled(struct radeon_fence *fence);
240 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
241 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
242 void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
243 int radeon_fence_wait_any(struct radeon_device *rdev,
244 struct radeon_fence **fences,
246 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
247 void radeon_fence_unref(struct radeon_fence **fence);
248 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
249 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
250 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
251 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
252 struct radeon_fence *b)
262 BUG_ON(a->ring != b->ring);
264 if (a->seq > b->seq) {
274 struct radeon_surface_reg {
275 struct radeon_bo *bo;
278 #define RADEON_GEM_MAX_SURFACES 8
284 struct ttm_bo_global_ref bo_global_ref;
285 struct drm_global_reference mem_global_ref;
286 struct ttm_bo_device bdev;
287 bool mem_global_referenced;
291 /* bo virtual address in a specific vm */
292 struct radeon_bo_va {
293 /* bo list is protected by bo being reserved */
294 struct list_head bo_list;
295 /* vm list is protected by vm mutex */
296 struct list_head vm_list;
297 /* constant after initialization */
298 struct radeon_vm *vm;
299 struct radeon_bo *bo;
307 /* Protected by gem.mutex */
308 struct list_head list;
309 /* Protected by tbo.reserved */
311 struct ttm_placement placement;
312 struct ttm_buffer_object tbo;
313 struct ttm_bo_kmap_obj kmap;
319 /* list of all virtual address to which this bo
323 /* Constant after initialization */
324 struct radeon_device *rdev;
325 struct drm_gem_object gem_base;
327 struct ttm_bo_kmap_obj dma_buf_vmap;
330 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
332 struct radeon_bo_list {
333 struct ttm_validate_buffer tv;
334 struct radeon_bo *bo;
341 /* sub-allocation manager, it has to be protected by another lock.
342 * By conception this is an helper for other part of the driver
343 * like the indirect buffer or semaphore, which both have their
346 * Principe is simple, we keep a list of sub allocation in offset
347 * order (first entry has offset == 0, last entry has the highest
350 * When allocating new object we first check if there is room at
351 * the end total_size - (last_object_offset + last_object_size) >=
352 * alloc_size. If so we allocate new object there.
354 * When there is not enough room at the end, we start waiting for
355 * each sub object until we reach object_offset+object_size >=
356 * alloc_size, this object then become the sub object we return.
358 * Alignment can't be bigger than page size.
360 * Hole are not considered for allocation to keep things simple.
361 * Assumption is that there won't be hole (all object on same
364 struct radeon_sa_manager {
365 wait_queue_head_t wq;
366 struct radeon_bo *bo;
367 struct list_head *hole;
368 struct list_head flist[RADEON_NUM_RINGS];
369 struct list_head olist;
378 /* sub-allocation buffer */
379 struct radeon_sa_bo {
380 struct list_head olist;
381 struct list_head flist;
382 struct radeon_sa_manager *manager;
385 struct radeon_fence *fence;
393 struct list_head objects;
396 int radeon_gem_init(struct radeon_device *rdev);
397 void radeon_gem_fini(struct radeon_device *rdev);
398 int radeon_gem_object_create(struct radeon_device *rdev, int size,
399 int alignment, int initial_domain,
400 bool discardable, bool kernel,
401 struct drm_gem_object **obj);
403 int radeon_mode_dumb_create(struct drm_file *file_priv,
404 struct drm_device *dev,
405 struct drm_mode_create_dumb *args);
406 int radeon_mode_dumb_mmap(struct drm_file *filp,
407 struct drm_device *dev,
408 uint32_t handle, uint64_t *offset_p);
409 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
410 struct drm_device *dev,
416 /* everything here is constant */
417 struct radeon_semaphore {
418 struct radeon_sa_bo *sa_bo;
423 int radeon_semaphore_create(struct radeon_device *rdev,
424 struct radeon_semaphore **semaphore);
425 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
426 struct radeon_semaphore *semaphore);
427 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
428 struct radeon_semaphore *semaphore);
429 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
430 struct radeon_semaphore *semaphore,
431 int signaler, int waiter);
432 void radeon_semaphore_free(struct radeon_device *rdev,
433 struct radeon_semaphore **semaphore,
434 struct radeon_fence *fence);
437 * GART structures, functions & helpers
441 #define RADEON_GPU_PAGE_SIZE 4096
442 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
443 #define RADEON_GPU_PAGE_SHIFT 12
444 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
447 dma_addr_t table_addr;
448 struct radeon_bo *robj;
450 unsigned num_gpu_pages;
451 unsigned num_cpu_pages;
454 dma_addr_t *pages_addr;
458 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
459 void radeon_gart_table_ram_free(struct radeon_device *rdev);
460 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
461 void radeon_gart_table_vram_free(struct radeon_device *rdev);
462 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
463 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
464 int radeon_gart_init(struct radeon_device *rdev);
465 void radeon_gart_fini(struct radeon_device *rdev);
466 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
468 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
469 int pages, struct page **pagelist,
470 dma_addr_t *dma_addr);
471 void radeon_gart_restore(struct radeon_device *rdev);
475 * GPU MC structures, functions & helpers
478 resource_size_t aper_size;
479 resource_size_t aper_base;
480 resource_size_t agp_base;
481 /* for some chips with <= 32MB we need to lie
482 * about vram size near mc fb location */
484 u64 visible_vram_size;
494 bool igp_sideport_enabled;
498 bool radeon_combios_sideport_present(struct radeon_device *rdev);
499 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
502 * GPU scratch registers structures, functions & helpers
504 struct radeon_scratch {
511 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
512 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
519 struct radeon_unpin_work {
520 struct work_struct work;
521 struct radeon_device *rdev;
523 struct radeon_fence *fence;
524 struct drm_pending_vblank_event *event;
525 struct radeon_bo *old_rbo;
529 struct r500_irq_stat_regs {
534 struct r600_irq_stat_regs {
544 struct evergreen_irq_stat_regs {
565 union radeon_irq_stat_regs {
566 struct r500_irq_stat_regs r500;
567 struct r600_irq_stat_regs r600;
568 struct evergreen_irq_stat_regs evergreen;
571 #define RADEON_MAX_HPD_PINS 6
572 #define RADEON_MAX_CRTCS 6
573 #define RADEON_MAX_AFMT_BLOCKS 6
578 atomic_t ring_int[RADEON_NUM_RINGS];
579 bool crtc_vblank_int[RADEON_MAX_CRTCS];
580 atomic_t pflip[RADEON_MAX_CRTCS];
581 wait_queue_head_t vblank_queue;
582 bool hpd[RADEON_MAX_HPD_PINS];
585 wait_queue_head_t idle_queue;
586 bool afmt[RADEON_MAX_AFMT_BLOCKS];
587 union radeon_irq_stat_regs stat_regs;
590 int radeon_irq_kms_init(struct radeon_device *rdev);
591 void radeon_irq_kms_fini(struct radeon_device *rdev);
592 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
593 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
594 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
595 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
596 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
597 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
598 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
599 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
600 int radeon_irq_kms_wait_gui_idle(struct radeon_device *rdev);
607 struct radeon_sa_bo *sa_bo;
612 struct radeon_fence *fence;
615 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
616 struct radeon_semaphore *semaphore;
620 struct radeon_bo *ring_obj;
621 volatile uint32_t *ring;
625 unsigned rptr_save_reg;
630 unsigned ring_free_dw;
632 unsigned long last_activity;
647 struct list_head list;
653 struct radeon_sa_bo *sa_bo;
655 /* last fence for cs using this vm */
656 struct radeon_fence *fence;
659 struct radeon_vm_funcs {
660 int (*init)(struct radeon_device *rdev);
661 void (*fini)(struct radeon_device *rdev);
662 /* cs mutex must be lock for schedule_ib */
663 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
664 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
665 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
666 uint32_t (*page_flags)(struct radeon_device *rdev,
667 struct radeon_vm *vm,
669 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
670 unsigned pfn, uint64_t addr, uint32_t flags);
673 struct radeon_vm_manager {
675 struct list_head lru_vm;
677 struct radeon_sa_manager sa_manager;
679 /* fields constant after init */
680 const struct radeon_vm_funcs *funcs;
681 /* number of VMIDs */
683 /* vram base address for page table entry */
684 u64 vram_base_offset;
690 * file private structure
692 struct radeon_fpriv {
700 struct radeon_bo *ring_obj;
701 volatile uint32_t *ring;
710 struct r600_blit_cp_primitives {
711 void (*set_render_target)(struct radeon_device *rdev, int format,
712 int w, int h, u64 gpu_addr);
713 void (*cp_set_surface_sync)(struct radeon_device *rdev,
714 u32 sync_type, u32 size,
716 void (*set_shaders)(struct radeon_device *rdev);
717 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
718 void (*set_tex_resource)(struct radeon_device *rdev,
719 int format, int w, int h, int pitch,
720 u64 gpu_addr, u32 size);
721 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
723 void (*draw_auto)(struct radeon_device *rdev);
724 void (*set_default_state)(struct radeon_device *rdev);
728 struct radeon_bo *shader_obj;
729 struct r600_blit_cp_primitives primitives;
731 int ring_size_common;
732 int ring_size_per_loop;
734 u32 vs_offset, ps_offset;
743 /* for power gating */
744 struct radeon_bo *save_restore_obj;
745 uint64_t save_restore_gpu_addr;
746 /* for clear state */
747 struct radeon_bo *clear_state_obj;
748 uint64_t clear_state_gpu_addr;
751 int radeon_ib_get(struct radeon_device *rdev, int ring,
752 struct radeon_ib *ib, unsigned size);
753 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
754 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
755 struct radeon_ib *const_ib);
756 int radeon_ib_pool_init(struct radeon_device *rdev);
757 void radeon_ib_pool_fini(struct radeon_device *rdev);
758 int radeon_ib_ring_tests(struct radeon_device *rdev);
759 /* Ring access between begin & end cannot sleep */
760 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
761 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
762 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
763 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
764 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
765 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
766 void radeon_ring_undo(struct radeon_ring *ring);
767 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
768 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
769 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
770 void radeon_ring_lockup_update(struct radeon_ring *ring);
771 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
772 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
774 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
775 unsigned size, uint32_t *data);
776 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
777 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
778 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
779 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
785 struct radeon_cs_reloc {
786 struct drm_gem_object *gobj;
787 struct radeon_bo *robj;
788 struct radeon_bo_list lobj;
793 struct radeon_cs_chunk {
799 void __user *user_ptr;
800 int last_copied_page;
804 struct radeon_cs_parser {
806 struct radeon_device *rdev;
807 struct drm_file *filp;
810 struct radeon_cs_chunk *chunks;
811 uint64_t *chunks_array;
816 struct radeon_cs_reloc *relocs;
817 struct radeon_cs_reloc **relocs_ptr;
818 struct list_head validated;
819 /* indices of various chunks */
821 int chunk_relocs_idx;
823 int chunk_const_ib_idx;
825 struct radeon_ib const_ib;
834 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
835 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
837 struct radeon_cs_packet {
846 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
847 struct radeon_cs_packet *pkt,
848 unsigned idx, unsigned reg);
849 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
850 struct radeon_cs_packet *pkt);
856 int radeon_agp_init(struct radeon_device *rdev);
857 void radeon_agp_resume(struct radeon_device *rdev);
858 void radeon_agp_suspend(struct radeon_device *rdev);
859 void radeon_agp_fini(struct radeon_device *rdev);
866 struct radeon_bo *wb_obj;
867 volatile uint32_t *wb;
873 #define RADEON_WB_SCRATCH_OFFSET 0
874 #define RADEON_WB_CP_RPTR_OFFSET 1024
875 #define RADEON_WB_CP1_RPTR_OFFSET 1280
876 #define RADEON_WB_CP2_RPTR_OFFSET 1536
877 #define R600_WB_IH_WPTR_OFFSET 2048
878 #define R600_WB_EVENT_OFFSET 3072
881 * struct radeon_pm - power management datas
882 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
883 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
884 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
885 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
886 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
887 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
888 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
889 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
890 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
891 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
892 * @needed_bandwidth: current bandwidth needs
894 * It keeps track of various data needed to take powermanagement decision.
895 * Bandwidth need is used to determine minimun clock of the GPU and memory.
896 * Equation between gpu/memory clock and available bandwidth is hw dependent
897 * (type of memory, bus size, efficiency, ...)
900 enum radeon_pm_method {
905 enum radeon_dynpm_state {
906 DYNPM_STATE_DISABLED,
910 DYNPM_STATE_SUSPENDED,
912 enum radeon_dynpm_action {
914 DYNPM_ACTION_MINIMUM,
915 DYNPM_ACTION_DOWNCLOCK,
916 DYNPM_ACTION_UPCLOCK,
920 enum radeon_voltage_type {
927 enum radeon_pm_state_type {
928 POWER_STATE_TYPE_DEFAULT,
929 POWER_STATE_TYPE_POWERSAVE,
930 POWER_STATE_TYPE_BATTERY,
931 POWER_STATE_TYPE_BALANCED,
932 POWER_STATE_TYPE_PERFORMANCE,
935 enum radeon_pm_profile_type {
943 #define PM_PROFILE_DEFAULT_IDX 0
944 #define PM_PROFILE_LOW_SH_IDX 1
945 #define PM_PROFILE_MID_SH_IDX 2
946 #define PM_PROFILE_HIGH_SH_IDX 3
947 #define PM_PROFILE_LOW_MH_IDX 4
948 #define PM_PROFILE_MID_MH_IDX 5
949 #define PM_PROFILE_HIGH_MH_IDX 6
950 #define PM_PROFILE_MAX 7
952 struct radeon_pm_profile {
959 enum radeon_int_thermal_type {
963 THERMAL_TYPE_EVERGREEN,
969 struct radeon_voltage {
970 enum radeon_voltage_type type;
972 struct radeon_gpio_rec gpio;
973 u32 delay; /* delay in usec from voltage drop to sclk change */
974 bool active_high; /* voltage drop is active when bit is high */
976 u8 vddc_id; /* index into vddc voltage table */
977 u8 vddci_id; /* index into vddci voltage table */
981 /* evergreen+ vddci */
985 /* clock mode flags */
986 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
988 struct radeon_pm_clock_info {
994 struct radeon_voltage voltage;
995 /* standardized clock flags */
1000 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1002 struct radeon_power_state {
1003 enum radeon_pm_state_type type;
1004 struct radeon_pm_clock_info *clock_info;
1005 /* number of valid clock modes in this power state */
1006 int num_clock_modes;
1007 struct radeon_pm_clock_info *default_clock_mode;
1008 /* standardized state flags */
1010 u32 misc; /* vbios specific flags */
1011 u32 misc2; /* vbios specific flags */
1012 int pcie_lanes; /* pcie lanes */
1016 * Some modes are overclocked by very low value, accept them
1018 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1022 /* write locked while reprogramming mclk */
1023 struct rw_semaphore mclk_lock;
1025 int active_crtc_count;
1028 fixed20_12 max_bandwidth;
1029 fixed20_12 igp_sideport_mclk;
1030 fixed20_12 igp_system_mclk;
1031 fixed20_12 igp_ht_link_clk;
1032 fixed20_12 igp_ht_link_width;
1033 fixed20_12 k8_bandwidth;
1034 fixed20_12 sideport_bandwidth;
1035 fixed20_12 ht_bandwidth;
1036 fixed20_12 core_bandwidth;
1039 fixed20_12 needed_bandwidth;
1040 struct radeon_power_state *power_state;
1041 /* number of valid power states */
1042 int num_power_states;
1043 int current_power_state_index;
1044 int current_clock_mode_index;
1045 int requested_power_state_index;
1046 int requested_clock_mode_index;
1047 int default_power_state_index;
1056 struct radeon_i2c_chan *i2c_bus;
1057 /* selected pm method */
1058 enum radeon_pm_method pm_method;
1059 /* dynpm power management */
1060 struct delayed_work dynpm_idle_work;
1061 enum radeon_dynpm_state dynpm_state;
1062 enum radeon_dynpm_action dynpm_planned_action;
1063 unsigned long dynpm_action_timeout;
1064 bool dynpm_can_upclock;
1065 bool dynpm_can_downclock;
1066 /* profile-based power management */
1067 enum radeon_pm_profile_type profile;
1069 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1070 /* internal thermal controller on rv6xx+ */
1071 enum radeon_int_thermal_type int_thermal_type;
1072 struct device *int_hwmon_dev;
1075 int radeon_pm_get_type_index(struct radeon_device *rdev,
1076 enum radeon_pm_state_type ps_type,
1082 int bits_per_sample;
1090 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1096 void radeon_test_moves(struct radeon_device *rdev);
1097 void radeon_test_ring_sync(struct radeon_device *rdev,
1098 struct radeon_ring *cpA,
1099 struct radeon_ring *cpB);
1100 void radeon_test_syncing(struct radeon_device *rdev);
1106 struct radeon_debugfs {
1107 struct drm_info_list *files;
1111 int radeon_debugfs_add_files(struct radeon_device *rdev,
1112 struct drm_info_list *files,
1114 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1118 * ASIC specific functions.
1120 struct radeon_asic {
1121 int (*init)(struct radeon_device *rdev);
1122 void (*fini)(struct radeon_device *rdev);
1123 int (*resume)(struct radeon_device *rdev);
1124 int (*suspend)(struct radeon_device *rdev);
1125 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1126 int (*asic_reset)(struct radeon_device *rdev);
1127 /* ioctl hw specific callback. Some hw might want to perform special
1128 * operation on specific ioctl. For instance on wait idle some hw
1129 * might want to perform and HDP flush through MMIO as it seems that
1130 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1133 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1134 /* check if 3D engine is idle */
1135 bool (*gui_idle)(struct radeon_device *rdev);
1136 /* wait for mc_idle */
1137 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1140 void (*tlb_flush)(struct radeon_device *rdev);
1141 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1143 /* ring specific callbacks */
1145 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1146 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1147 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1148 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1149 struct radeon_semaphore *semaphore, bool emit_wait);
1150 int (*cs_parse)(struct radeon_cs_parser *p);
1151 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1152 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1153 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1154 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1155 } ring[RADEON_NUM_RINGS];
1158 int (*set)(struct radeon_device *rdev);
1159 int (*process)(struct radeon_device *rdev);
1163 /* display watermarks */
1164 void (*bandwidth_update)(struct radeon_device *rdev);
1165 /* get frame count */
1166 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1167 /* wait for vblank */
1168 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1170 /* copy functions for bo handling */
1172 int (*blit)(struct radeon_device *rdev,
1173 uint64_t src_offset,
1174 uint64_t dst_offset,
1175 unsigned num_gpu_pages,
1176 struct radeon_fence **fence);
1177 u32 blit_ring_index;
1178 int (*dma)(struct radeon_device *rdev,
1179 uint64_t src_offset,
1180 uint64_t dst_offset,
1181 unsigned num_gpu_pages,
1182 struct radeon_fence **fence);
1184 /* method used for bo copy */
1185 int (*copy)(struct radeon_device *rdev,
1186 uint64_t src_offset,
1187 uint64_t dst_offset,
1188 unsigned num_gpu_pages,
1189 struct radeon_fence **fence);
1190 /* ring used for bo copies */
1191 u32 copy_ring_index;
1195 int (*set_reg)(struct radeon_device *rdev, int reg,
1196 uint32_t tiling_flags, uint32_t pitch,
1197 uint32_t offset, uint32_t obj_size);
1198 void (*clear_reg)(struct radeon_device *rdev, int reg);
1200 /* hotplug detect */
1202 void (*init)(struct radeon_device *rdev);
1203 void (*fini)(struct radeon_device *rdev);
1204 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1205 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1207 /* power management */
1209 void (*misc)(struct radeon_device *rdev);
1210 void (*prepare)(struct radeon_device *rdev);
1211 void (*finish)(struct radeon_device *rdev);
1212 void (*init_profile)(struct radeon_device *rdev);
1213 void (*get_dynpm_state)(struct radeon_device *rdev);
1214 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1215 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1216 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1217 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1218 int (*get_pcie_lanes)(struct radeon_device *rdev);
1219 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1220 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1224 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1225 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1226 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1234 const unsigned *reg_safe_bm;
1235 unsigned reg_safe_bm_size;
1240 const unsigned *reg_safe_bm;
1241 unsigned reg_safe_bm_size;
1248 unsigned max_tile_pipes;
1250 unsigned max_backends;
1252 unsigned max_threads;
1253 unsigned max_stack_entries;
1254 unsigned max_hw_contexts;
1255 unsigned max_gs_threads;
1256 unsigned sx_max_export_size;
1257 unsigned sx_max_export_pos_size;
1258 unsigned sx_max_export_smx_size;
1259 unsigned sq_num_cf_insts;
1260 unsigned tiling_nbanks;
1261 unsigned tiling_npipes;
1262 unsigned tiling_group_size;
1263 unsigned tile_config;
1264 unsigned backend_map;
1269 unsigned max_tile_pipes;
1271 unsigned max_backends;
1273 unsigned max_threads;
1274 unsigned max_stack_entries;
1275 unsigned max_hw_contexts;
1276 unsigned max_gs_threads;
1277 unsigned sx_max_export_size;
1278 unsigned sx_max_export_pos_size;
1279 unsigned sx_max_export_smx_size;
1280 unsigned sq_num_cf_insts;
1281 unsigned sx_num_of_sets;
1282 unsigned sc_prim_fifo_size;
1283 unsigned sc_hiz_tile_fifo_size;
1284 unsigned sc_earlyz_tile_fifo_fize;
1285 unsigned tiling_nbanks;
1286 unsigned tiling_npipes;
1287 unsigned tiling_group_size;
1288 unsigned tile_config;
1289 unsigned backend_map;
1292 struct evergreen_asic {
1295 unsigned max_tile_pipes;
1297 unsigned max_backends;
1299 unsigned max_threads;
1300 unsigned max_stack_entries;
1301 unsigned max_hw_contexts;
1302 unsigned max_gs_threads;
1303 unsigned sx_max_export_size;
1304 unsigned sx_max_export_pos_size;
1305 unsigned sx_max_export_smx_size;
1306 unsigned sq_num_cf_insts;
1307 unsigned sx_num_of_sets;
1308 unsigned sc_prim_fifo_size;
1309 unsigned sc_hiz_tile_fifo_size;
1310 unsigned sc_earlyz_tile_fifo_size;
1311 unsigned tiling_nbanks;
1312 unsigned tiling_npipes;
1313 unsigned tiling_group_size;
1314 unsigned tile_config;
1315 unsigned backend_map;
1318 struct cayman_asic {
1319 unsigned max_shader_engines;
1320 unsigned max_pipes_per_simd;
1321 unsigned max_tile_pipes;
1322 unsigned max_simds_per_se;
1323 unsigned max_backends_per_se;
1324 unsigned max_texture_channel_caches;
1326 unsigned max_threads;
1327 unsigned max_gs_threads;
1328 unsigned max_stack_entries;
1329 unsigned sx_num_of_sets;
1330 unsigned sx_max_export_size;
1331 unsigned sx_max_export_pos_size;
1332 unsigned sx_max_export_smx_size;
1333 unsigned max_hw_contexts;
1334 unsigned sq_num_cf_insts;
1335 unsigned sc_prim_fifo_size;
1336 unsigned sc_hiz_tile_fifo_size;
1337 unsigned sc_earlyz_tile_fifo_size;
1339 unsigned num_shader_engines;
1340 unsigned num_shader_pipes_per_simd;
1341 unsigned num_tile_pipes;
1342 unsigned num_simds_per_se;
1343 unsigned num_backends_per_se;
1344 unsigned backend_disable_mask_per_asic;
1345 unsigned backend_map;
1346 unsigned num_texture_channel_caches;
1347 unsigned mem_max_burst_length_bytes;
1348 unsigned mem_row_size_in_kb;
1349 unsigned shader_engine_tile_size;
1351 unsigned multi_gpu_tile_size;
1353 unsigned tile_config;
1357 unsigned max_shader_engines;
1358 unsigned max_tile_pipes;
1359 unsigned max_cu_per_sh;
1360 unsigned max_sh_per_se;
1361 unsigned max_backends_per_se;
1362 unsigned max_texture_channel_caches;
1364 unsigned max_gs_threads;
1365 unsigned max_hw_contexts;
1366 unsigned sc_prim_fifo_size_frontend;
1367 unsigned sc_prim_fifo_size_backend;
1368 unsigned sc_hiz_tile_fifo_size;
1369 unsigned sc_earlyz_tile_fifo_size;
1371 unsigned num_tile_pipes;
1372 unsigned num_backends_per_se;
1373 unsigned backend_disable_mask_per_asic;
1374 unsigned backend_map;
1375 unsigned num_texture_channel_caches;
1376 unsigned mem_max_burst_length_bytes;
1377 unsigned mem_row_size_in_kb;
1378 unsigned shader_engine_tile_size;
1380 unsigned multi_gpu_tile_size;
1382 unsigned tile_config;
1385 union radeon_asic_config {
1386 struct r300_asic r300;
1387 struct r100_asic r100;
1388 struct r600_asic r600;
1389 struct rv770_asic rv770;
1390 struct evergreen_asic evergreen;
1391 struct cayman_asic cayman;
1396 * asic initizalization from radeon_asic.c
1398 void radeon_agp_disable(struct radeon_device *rdev);
1399 int radeon_asic_init(struct radeon_device *rdev);
1405 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1406 struct drm_file *filp);
1407 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1408 struct drm_file *filp);
1409 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1410 struct drm_file *file_priv);
1411 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1412 struct drm_file *file_priv);
1413 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1414 struct drm_file *file_priv);
1415 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1416 struct drm_file *file_priv);
1417 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1418 struct drm_file *filp);
1419 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1420 struct drm_file *filp);
1421 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1422 struct drm_file *filp);
1423 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1424 struct drm_file *filp);
1425 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1426 struct drm_file *filp);
1427 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1428 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1429 struct drm_file *filp);
1430 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1431 struct drm_file *filp);
1433 /* VRAM scratch page for HDP bug, default vram page */
1434 struct r600_vram_scratch {
1435 struct radeon_bo *robj;
1436 volatile uint32_t *ptr;
1442 * Core structure, functions and helpers.
1444 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1445 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1447 struct radeon_device {
1449 struct drm_device *ddev;
1450 struct pci_dev *pdev;
1451 struct rw_semaphore exclusive_lock;
1453 union radeon_asic_config config;
1454 enum radeon_family family;
1455 unsigned long flags;
1457 enum radeon_pll_errata pll_errata;
1464 uint16_t bios_header_start;
1465 struct radeon_bo *stollen_vga_memory;
1467 resource_size_t rmmio_base;
1468 resource_size_t rmmio_size;
1469 void __iomem *rmmio;
1470 radeon_rreg_t mc_rreg;
1471 radeon_wreg_t mc_wreg;
1472 radeon_rreg_t pll_rreg;
1473 radeon_wreg_t pll_wreg;
1474 uint32_t pcie_reg_mask;
1475 radeon_rreg_t pciep_rreg;
1476 radeon_wreg_t pciep_wreg;
1478 void __iomem *rio_mem;
1479 resource_size_t rio_mem_size;
1480 struct radeon_clock clock;
1481 struct radeon_mc mc;
1482 struct radeon_gart gart;
1483 struct radeon_mode_info mode_info;
1484 struct radeon_scratch scratch;
1485 struct radeon_mman mman;
1486 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1487 wait_queue_head_t fence_queue;
1488 struct mutex ring_lock;
1489 struct radeon_ring ring[RADEON_NUM_RINGS];
1491 struct radeon_sa_manager ring_tmp_bo;
1492 struct radeon_irq irq;
1493 struct radeon_asic *asic;
1494 struct radeon_gem gem;
1495 struct radeon_pm pm;
1496 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1497 struct radeon_wb wb;
1498 struct radeon_dummy_page dummy_page;
1503 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1504 const struct firmware *me_fw; /* all family ME firmware */
1505 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1506 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1507 const struct firmware *mc_fw; /* NI MC firmware */
1508 const struct firmware *ce_fw; /* SI CE firmware */
1509 struct r600_blit r600_blit;
1510 struct r600_vram_scratch vram_scratch;
1511 int msi_enabled; /* msi enabled */
1512 struct r600_ih ih; /* r6/700 interrupt ring */
1514 struct work_struct hotplug_work;
1515 struct work_struct audio_work;
1516 int num_crtc; /* number of crtcs */
1517 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1519 struct r600_audio audio_status; /* audio stuff */
1520 struct notifier_block acpi_nb;
1521 /* only one userspace can use Hyperz features or CMASK at a time */
1522 struct drm_file *hyperz_filp;
1523 struct drm_file *cmask_filp;
1525 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1527 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1528 unsigned debugfs_count;
1529 /* virtual memory */
1530 struct radeon_vm_manager vm_manager;
1533 int radeon_device_init(struct radeon_device *rdev,
1534 struct drm_device *ddev,
1535 struct pci_dev *pdev,
1537 void radeon_device_fini(struct radeon_device *rdev);
1538 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1540 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1541 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1542 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1543 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1548 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1551 * Registers read & write functions.
1553 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1554 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1555 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1556 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1557 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1558 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1559 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1560 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1561 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1562 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1563 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1564 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1565 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1566 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1567 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1568 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1569 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1570 #define WREG32_P(reg, val, mask) \
1572 uint32_t tmp_ = RREG32(reg); \
1574 tmp_ |= ((val) & ~(mask)); \
1575 WREG32(reg, tmp_); \
1577 #define WREG32_PLL_P(reg, val, mask) \
1579 uint32_t tmp_ = RREG32_PLL(reg); \
1581 tmp_ |= ((val) & ~(mask)); \
1582 WREG32_PLL(reg, tmp_); \
1584 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1585 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1586 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1589 * Indirect registers accessor
1591 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1595 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1596 r = RREG32(RADEON_PCIE_DATA);
1600 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1602 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1603 WREG32(RADEON_PCIE_DATA, (v));
1606 void r100_pll_errata_after_index(struct radeon_device *rdev);
1612 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1613 (rdev->pdev->device == 0x5969))
1614 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1615 (rdev->family == CHIP_RV200) || \
1616 (rdev->family == CHIP_RS100) || \
1617 (rdev->family == CHIP_RS200) || \
1618 (rdev->family == CHIP_RV250) || \
1619 (rdev->family == CHIP_RV280) || \
1620 (rdev->family == CHIP_RS300))
1621 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1622 (rdev->family == CHIP_RV350) || \
1623 (rdev->family == CHIP_R350) || \
1624 (rdev->family == CHIP_RV380) || \
1625 (rdev->family == CHIP_R420) || \
1626 (rdev->family == CHIP_R423) || \
1627 (rdev->family == CHIP_RV410) || \
1628 (rdev->family == CHIP_RS400) || \
1629 (rdev->family == CHIP_RS480))
1630 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1631 (rdev->ddev->pdev->device == 0x9443) || \
1632 (rdev->ddev->pdev->device == 0x944B) || \
1633 (rdev->ddev->pdev->device == 0x9506) || \
1634 (rdev->ddev->pdev->device == 0x9509) || \
1635 (rdev->ddev->pdev->device == 0x950F) || \
1636 (rdev->ddev->pdev->device == 0x689C) || \
1637 (rdev->ddev->pdev->device == 0x689D))
1638 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1639 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1640 (rdev->family == CHIP_RS690) || \
1641 (rdev->family == CHIP_RS740) || \
1642 (rdev->family >= CHIP_R600))
1643 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1644 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1645 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1646 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1647 (rdev->flags & RADEON_IS_IGP))
1648 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1649 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1650 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1651 (rdev->flags & RADEON_IS_IGP))
1656 #define RBIOS8(i) (rdev->bios[i])
1657 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1658 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1660 int radeon_combios_init(struct radeon_device *rdev);
1661 void radeon_combios_fini(struct radeon_device *rdev);
1662 int radeon_atombios_init(struct radeon_device *rdev);
1663 void radeon_atombios_fini(struct radeon_device *rdev);
1669 #if DRM_DEBUG_CODE == 0
1670 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1672 ring->ring[ring->wptr++] = v;
1673 ring->wptr &= ring->ptr_mask;
1675 ring->ring_free_dw--;
1678 /* With debugging this is just too big to inline */
1679 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1685 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1686 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1687 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1688 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1689 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1690 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1691 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1692 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1693 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1694 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1695 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1696 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1697 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1698 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1699 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1700 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1701 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1702 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1703 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1704 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1705 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1706 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1707 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1708 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1709 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1710 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1711 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1712 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1713 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1714 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1715 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1716 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1717 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1718 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1719 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1720 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1721 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1722 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1723 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1724 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1725 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1726 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1727 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1728 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1729 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1730 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1731 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1732 #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1733 #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1734 #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1735 #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1737 /* Common functions */
1739 extern int radeon_gpu_reset(struct radeon_device *rdev);
1740 extern void radeon_agp_disable(struct radeon_device *rdev);
1741 extern int radeon_modeset_init(struct radeon_device *rdev);
1742 extern void radeon_modeset_fini(struct radeon_device *rdev);
1743 extern bool radeon_card_posted(struct radeon_device *rdev);
1744 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1745 extern void radeon_update_display_priority(struct radeon_device *rdev);
1746 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1747 extern void radeon_scratch_init(struct radeon_device *rdev);
1748 extern void radeon_wb_fini(struct radeon_device *rdev);
1749 extern int radeon_wb_init(struct radeon_device *rdev);
1750 extern void radeon_wb_disable(struct radeon_device *rdev);
1751 extern void radeon_surface_init(struct radeon_device *rdev);
1752 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1753 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1754 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1755 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1756 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1757 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1758 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1759 extern int radeon_resume_kms(struct drm_device *dev);
1760 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1761 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1766 int radeon_vm_manager_init(struct radeon_device *rdev);
1767 void radeon_vm_manager_fini(struct radeon_device *rdev);
1768 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1769 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1770 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1771 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1772 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1773 struct radeon_vm *vm,
1774 struct radeon_bo *bo,
1775 struct ttm_mem_reg *mem);
1776 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1777 struct radeon_bo *bo);
1778 int radeon_vm_bo_add(struct radeon_device *rdev,
1779 struct radeon_vm *vm,
1780 struct radeon_bo *bo,
1783 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1784 struct radeon_vm *vm,
1785 struct radeon_bo *bo);
1788 void r600_audio_update_hdmi(struct work_struct *work);
1791 * R600 vram scratch functions
1793 int r600_vram_scratch_init(struct radeon_device *rdev);
1794 void r600_vram_scratch_fini(struct radeon_device *rdev);
1797 * r600 cs checking helper
1799 unsigned r600_mip_minify(unsigned size, unsigned level);
1800 bool r600_fmt_is_valid_color(u32 format);
1801 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1802 int r600_fmt_get_blocksize(u32 format);
1803 int r600_fmt_get_nblocksx(u32 format, u32 w);
1804 int r600_fmt_get_nblocksy(u32 format, u32 h);
1807 * r600 functions used by radeon_encoder.c
1809 struct radeon_hdmi_acr {
1823 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1825 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1826 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1827 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1828 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1829 u32 tiling_pipe_num,
1831 u32 total_max_rb_num,
1832 u32 enabled_rb_mask);
1835 * evergreen functions used by radeon_encoder.c
1838 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1840 extern int ni_init_microcode(struct radeon_device *rdev);
1841 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1844 #if defined(CONFIG_ACPI)
1845 extern int radeon_acpi_init(struct radeon_device *rdev);
1847 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1850 #include "radeon_object.h"