2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
69 #include <ttm/ttm_bo_api.h>
70 #include <ttm/ttm_bo_driver.h>
71 #include <ttm/ttm_placement.h>
72 #include <ttm/ttm_module.h>
73 #include <ttm/ttm_execbuf_util.h>
75 #include "radeon_family.h"
76 #include "radeon_mode.h"
77 #include "radeon_reg.h"
82 extern int radeon_no_wb;
83 extern int radeon_modeset;
84 extern int radeon_dynclks;
85 extern int radeon_r4xx_atom;
86 extern int radeon_agpmode;
87 extern int radeon_vram_limit;
88 extern int radeon_gart_size;
89 extern int radeon_benchmarking;
90 extern int radeon_testing;
91 extern int radeon_connector_table;
93 extern int radeon_audio;
94 extern int radeon_disp_priority;
95 extern int radeon_hw_i2c;
96 extern int radeon_pcie_gen2;
97 extern int radeon_msi;
98 extern int radeon_lockup_timeout;
99 extern int radeon_fastfb;
100 extern int radeon_dpm;
101 extern int radeon_aspm;
102 extern int radeon_runtime_pm;
103 extern int radeon_hard_reset;
104 extern int radeon_vm_size;
105 extern int radeon_vm_block_size;
106 extern int radeon_deep_color;
107 extern int radeon_use_pflipirq;
108 extern int radeon_bapm;
109 extern int radeon_backlight;
112 * Copy from radeon_drv.h so we don't have to include both and have conflicting
115 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
116 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
117 /* RADEON_IB_POOL_SIZE must be a power of 2 */
118 #define RADEON_IB_POOL_SIZE 16
119 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
120 #define RADEONFB_CONN_LIMIT 4
121 #define RADEON_BIOS_NUM_SCRATCH 8
123 /* fence seq are set to this number when signaled */
124 #define RADEON_FENCE_SIGNALED_SEQ 0LL
126 /* internal ring indices */
127 /* r1xx+ has gfx CP ring */
128 #define RADEON_RING_TYPE_GFX_INDEX 0
130 /* cayman has 2 compute CP rings */
131 #define CAYMAN_RING_TYPE_CP1_INDEX 1
132 #define CAYMAN_RING_TYPE_CP2_INDEX 2
134 /* R600+ has an async dma ring */
135 #define R600_RING_TYPE_DMA_INDEX 3
136 /* cayman add a second async dma ring */
137 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
140 #define R600_RING_TYPE_UVD_INDEX 5
143 #define TN_RING_TYPE_VCE1_INDEX 6
144 #define TN_RING_TYPE_VCE2_INDEX 7
146 /* max number of rings */
147 #define RADEON_NUM_RINGS 8
149 /* number of hw syncs before falling back on blocking */
150 #define RADEON_NUM_SYNCS 4
152 /* number of hw syncs before falling back on blocking */
153 #define RADEON_NUM_SYNCS 4
155 /* hardcode those limit for now */
156 #define RADEON_VA_IB_OFFSET (1 << 20)
157 #define RADEON_VA_RESERVED_SIZE (8 << 20)
158 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
160 /* hard reset data */
161 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
164 #define RADEON_RESET_GFX (1 << 0)
165 #define RADEON_RESET_COMPUTE (1 << 1)
166 #define RADEON_RESET_DMA (1 << 2)
167 #define RADEON_RESET_CP (1 << 3)
168 #define RADEON_RESET_GRBM (1 << 4)
169 #define RADEON_RESET_DMA1 (1 << 5)
170 #define RADEON_RESET_RLC (1 << 6)
171 #define RADEON_RESET_SEM (1 << 7)
172 #define RADEON_RESET_IH (1 << 8)
173 #define RADEON_RESET_VMC (1 << 9)
174 #define RADEON_RESET_MC (1 << 10)
175 #define RADEON_RESET_DISPLAY (1 << 11)
178 #define RADEON_CG_BLOCK_GFX (1 << 0)
179 #define RADEON_CG_BLOCK_MC (1 << 1)
180 #define RADEON_CG_BLOCK_SDMA (1 << 2)
181 #define RADEON_CG_BLOCK_UVD (1 << 3)
182 #define RADEON_CG_BLOCK_VCE (1 << 4)
183 #define RADEON_CG_BLOCK_HDP (1 << 5)
184 #define RADEON_CG_BLOCK_BIF (1 << 6)
187 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
188 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
189 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
190 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
191 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
192 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
193 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
194 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
195 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
196 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
197 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
198 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
199 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
200 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
201 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
202 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
203 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
206 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
207 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
208 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
209 #define RADEON_PG_SUPPORT_UVD (1 << 3)
210 #define RADEON_PG_SUPPORT_VCE (1 << 4)
211 #define RADEON_PG_SUPPORT_CP (1 << 5)
212 #define RADEON_PG_SUPPORT_GDS (1 << 6)
213 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
214 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
215 #define RADEON_PG_SUPPORT_ACP (1 << 9)
216 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
218 /* max cursor sizes (in pixels) */
219 #define CURSOR_WIDTH 64
220 #define CURSOR_HEIGHT 64
222 #define CIK_CURSOR_WIDTH 128
223 #define CIK_CURSOR_HEIGHT 128
226 * Errata workarounds.
228 enum radeon_pll_errata {
229 CHIP_ERRATA_R300_CG = 0x00000001,
230 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
231 CHIP_ERRATA_PLL_DELAY = 0x00000004
235 struct radeon_device;
241 bool radeon_get_bios(struct radeon_device *rdev);
246 struct radeon_dummy_page {
250 int radeon_dummy_page_init(struct radeon_device *rdev);
251 void radeon_dummy_page_fini(struct radeon_device *rdev);
257 struct radeon_clock {
258 struct radeon_pll p1pll;
259 struct radeon_pll p2pll;
260 struct radeon_pll dcpll;
261 struct radeon_pll spll;
262 struct radeon_pll mpll;
264 uint32_t default_mclk;
265 uint32_t default_sclk;
266 uint32_t default_dispclk;
267 uint32_t current_dispclk;
269 uint32_t max_pixel_clock;
275 int radeon_pm_init(struct radeon_device *rdev);
276 int radeon_pm_late_init(struct radeon_device *rdev);
277 void radeon_pm_fini(struct radeon_device *rdev);
278 void radeon_pm_compute_clocks(struct radeon_device *rdev);
279 void radeon_pm_suspend(struct radeon_device *rdev);
280 void radeon_pm_resume(struct radeon_device *rdev);
281 void radeon_combios_get_power_modes(struct radeon_device *rdev);
282 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
283 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
287 struct atom_clock_dividers *dividers);
288 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
291 struct atom_mpll_param *mpll_param);
292 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
293 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
294 u16 voltage_level, u8 voltage_type,
295 u32 *gpio_value, u32 *gpio_mask);
296 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
297 u32 eng_clock, u32 mem_clock);
298 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
299 u8 voltage_type, u16 *voltage_step);
300 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
301 u16 voltage_id, u16 *voltage);
302 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
305 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
307 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
308 u16 *vddc, u16 *vddci,
309 u16 virtual_voltage_id,
310 u16 vbios_voltage_id);
311 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
312 u16 virtual_voltage_id,
314 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
318 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
319 u8 voltage_type, u16 *min_voltage);
320 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
321 u8 voltage_type, u16 *max_voltage);
322 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
323 u8 voltage_type, u8 voltage_mode,
324 struct atom_voltage_table *voltage_table);
325 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
326 u8 voltage_type, u8 voltage_mode);
327 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
329 u8 *svd_gpio_id, u8 *svc_gpio_id);
330 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
332 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
334 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
336 struct atom_mc_reg_table *reg_table);
337 int radeon_atom_get_memory_info(struct radeon_device *rdev,
338 u8 module_index, struct atom_memory_info *mem_info);
339 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
340 bool gddr5, u8 module_index,
341 struct atom_memory_clock_range_table *mclk_range_table);
342 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
343 u16 voltage_id, u16 *voltage);
344 void rs690_pm_info(struct radeon_device *rdev);
345 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
346 unsigned *bankh, unsigned *mtaspect,
347 unsigned *tile_split);
352 struct radeon_fence_driver {
353 uint32_t scratch_reg;
355 volatile uint32_t *cpu_addr;
356 /* sync_seq is protected by ring emission lock */
357 uint64_t sync_seq[RADEON_NUM_RINGS];
362 struct radeon_fence {
363 struct radeon_device *rdev;
365 /* protected by radeon_fence.lock */
371 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
372 int radeon_fence_driver_init(struct radeon_device *rdev);
373 void radeon_fence_driver_fini(struct radeon_device *rdev);
374 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
375 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
376 void radeon_fence_process(struct radeon_device *rdev, int ring);
377 bool radeon_fence_signaled(struct radeon_fence *fence);
378 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
379 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
380 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
381 int radeon_fence_wait_any(struct radeon_device *rdev,
382 struct radeon_fence **fences,
384 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
385 void radeon_fence_unref(struct radeon_fence **fence);
386 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
387 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
388 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
389 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
390 struct radeon_fence *b)
400 BUG_ON(a->ring != b->ring);
402 if (a->seq > b->seq) {
409 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
410 struct radeon_fence *b)
420 BUG_ON(a->ring != b->ring);
422 return a->seq < b->seq;
428 struct radeon_surface_reg {
429 struct radeon_bo *bo;
432 #define RADEON_GEM_MAX_SURFACES 8
438 struct ttm_bo_global_ref bo_global_ref;
439 struct drm_global_reference mem_global_ref;
440 struct ttm_bo_device bdev;
441 bool mem_global_referenced;
444 #if defined(CONFIG_DEBUG_FS)
450 /* bo virtual address in a specific vm */
451 struct radeon_bo_va {
452 /* protected by bo being reserved */
453 struct list_head bo_list;
458 /* protected by vm mutex */
459 struct interval_tree_node it;
460 struct list_head vm_status;
462 /* constant after initialization */
463 struct radeon_vm *vm;
464 struct radeon_bo *bo;
468 /* Protected by gem.mutex */
469 struct list_head list;
470 /* Protected by tbo.reserved */
473 struct ttm_placement placement;
474 struct ttm_buffer_object tbo;
475 struct ttm_bo_kmap_obj kmap;
482 /* list of all virtual address to which this bo
486 /* Constant after initialization */
487 struct radeon_device *rdev;
488 struct drm_gem_object gem_base;
490 struct ttm_bo_kmap_obj dma_buf_vmap;
493 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
495 int radeon_gem_debugfs_init(struct radeon_device *rdev);
497 /* sub-allocation manager, it has to be protected by another lock.
498 * By conception this is an helper for other part of the driver
499 * like the indirect buffer or semaphore, which both have their
502 * Principe is simple, we keep a list of sub allocation in offset
503 * order (first entry has offset == 0, last entry has the highest
506 * When allocating new object we first check if there is room at
507 * the end total_size - (last_object_offset + last_object_size) >=
508 * alloc_size. If so we allocate new object there.
510 * When there is not enough room at the end, we start waiting for
511 * each sub object until we reach object_offset+object_size >=
512 * alloc_size, this object then become the sub object we return.
514 * Alignment can't be bigger than page size.
516 * Hole are not considered for allocation to keep things simple.
517 * Assumption is that there won't be hole (all object on same
520 struct radeon_sa_manager {
521 wait_queue_head_t wq;
522 struct radeon_bo *bo;
523 struct list_head *hole;
524 struct list_head flist[RADEON_NUM_RINGS];
525 struct list_head olist;
535 /* sub-allocation buffer */
536 struct radeon_sa_bo {
537 struct list_head olist;
538 struct list_head flist;
539 struct radeon_sa_manager *manager;
542 struct radeon_fence *fence;
550 struct list_head objects;
553 int radeon_gem_init(struct radeon_device *rdev);
554 void radeon_gem_fini(struct radeon_device *rdev);
555 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
556 int alignment, int initial_domain,
557 u32 flags, bool kernel,
558 struct drm_gem_object **obj);
560 int radeon_mode_dumb_create(struct drm_file *file_priv,
561 struct drm_device *dev,
562 struct drm_mode_create_dumb *args);
563 int radeon_mode_dumb_mmap(struct drm_file *filp,
564 struct drm_device *dev,
565 uint32_t handle, uint64_t *offset_p);
570 struct radeon_semaphore {
571 struct radeon_sa_bo *sa_bo;
574 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
577 int radeon_semaphore_create(struct radeon_device *rdev,
578 struct radeon_semaphore **semaphore);
579 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
580 struct radeon_semaphore *semaphore);
581 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
582 struct radeon_semaphore *semaphore);
583 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
584 struct radeon_fence *fence);
585 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
586 struct radeon_semaphore *semaphore,
588 void radeon_semaphore_free(struct radeon_device *rdev,
589 struct radeon_semaphore **semaphore,
590 struct radeon_fence *fence);
593 * GART structures, functions & helpers
597 #define RADEON_GPU_PAGE_SIZE 4096
598 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
599 #define RADEON_GPU_PAGE_SHIFT 12
600 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
602 #define RADEON_GART_PAGE_DUMMY 0
603 #define RADEON_GART_PAGE_VALID (1 << 0)
604 #define RADEON_GART_PAGE_READ (1 << 1)
605 #define RADEON_GART_PAGE_WRITE (1 << 2)
606 #define RADEON_GART_PAGE_SNOOP (1 << 3)
609 dma_addr_t table_addr;
610 struct radeon_bo *robj;
612 unsigned num_gpu_pages;
613 unsigned num_cpu_pages;
616 dma_addr_t *pages_addr;
620 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
621 void radeon_gart_table_ram_free(struct radeon_device *rdev);
622 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
623 void radeon_gart_table_vram_free(struct radeon_device *rdev);
624 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
625 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
626 int radeon_gart_init(struct radeon_device *rdev);
627 void radeon_gart_fini(struct radeon_device *rdev);
628 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
630 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
631 int pages, struct page **pagelist,
632 dma_addr_t *dma_addr, uint32_t flags);
636 * GPU MC structures, functions & helpers
639 resource_size_t aper_size;
640 resource_size_t aper_base;
641 resource_size_t agp_base;
642 /* for some chips with <= 32MB we need to lie
643 * about vram size near mc fb location */
645 u64 visible_vram_size;
655 bool igp_sideport_enabled;
660 bool radeon_combios_sideport_present(struct radeon_device *rdev);
661 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
664 * GPU scratch registers structures, functions & helpers
666 struct radeon_scratch {
673 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
674 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
677 * GPU doorbell structures, functions & helpers
679 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
681 struct radeon_doorbell {
683 resource_size_t base;
684 resource_size_t size;
686 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
687 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
690 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
691 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
697 struct radeon_flip_work {
698 struct work_struct flip_work;
699 struct work_struct unpin_work;
700 struct radeon_device *rdev;
703 struct drm_pending_vblank_event *event;
704 struct radeon_bo *old_rbo;
705 struct radeon_fence *fence;
708 struct r500_irq_stat_regs {
713 struct r600_irq_stat_regs {
723 struct evergreen_irq_stat_regs {
744 struct cik_irq_stat_regs {
760 union radeon_irq_stat_regs {
761 struct r500_irq_stat_regs r500;
762 struct r600_irq_stat_regs r600;
763 struct evergreen_irq_stat_regs evergreen;
764 struct cik_irq_stat_regs cik;
770 atomic_t ring_int[RADEON_NUM_RINGS];
771 bool crtc_vblank_int[RADEON_MAX_CRTCS];
772 atomic_t pflip[RADEON_MAX_CRTCS];
773 wait_queue_head_t vblank_queue;
774 bool hpd[RADEON_MAX_HPD_PINS];
775 bool afmt[RADEON_MAX_AFMT_BLOCKS];
776 union radeon_irq_stat_regs stat_regs;
780 int radeon_irq_kms_init(struct radeon_device *rdev);
781 void radeon_irq_kms_fini(struct radeon_device *rdev);
782 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
783 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
784 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
785 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
786 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
787 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
788 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
789 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
796 struct radeon_sa_bo *sa_bo;
801 struct radeon_fence *fence;
802 struct radeon_vm *vm;
804 struct radeon_semaphore *semaphore;
808 struct radeon_bo *ring_obj;
809 volatile uint32_t *ring;
811 unsigned rptr_save_reg;
812 u64 next_rptr_gpu_addr;
813 volatile u32 *next_rptr_cpu_addr;
817 unsigned ring_free_dw;
820 atomic64_t last_activity;
827 u64 last_semaphore_signal_addr;
828 u64 last_semaphore_wait_addr;
833 struct radeon_bo *mqd_obj;
839 struct radeon_bo *hpd_eop_obj;
840 u64 hpd_eop_gpu_addr;
850 /* maximum number of VMIDs */
851 #define RADEON_NUM_VM 16
853 /* number of entries in page table */
854 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
856 /* PTBs (Page Table Blocks) need to be aligned to 32K */
857 #define RADEON_VM_PTB_ALIGN_SIZE 32768
858 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
859 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
861 #define R600_PTE_VALID (1 << 0)
862 #define R600_PTE_SYSTEM (1 << 1)
863 #define R600_PTE_SNOOPED (1 << 2)
864 #define R600_PTE_READABLE (1 << 5)
865 #define R600_PTE_WRITEABLE (1 << 6)
867 /* PTE (Page Table Entry) fragment field for different page sizes */
868 #define R600_PTE_FRAG_4KB (0 << 7)
869 #define R600_PTE_FRAG_64KB (4 << 7)
870 #define R600_PTE_FRAG_256KB (6 << 7)
872 /* flags needed to be set so we can copy directly from the GART table */
873 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
874 R600_PTE_SYSTEM | R600_PTE_VALID )
876 struct radeon_vm_pt {
877 struct radeon_bo *bo;
885 /* BOs moved, but not yet updated in the PT */
886 struct list_head invalidated;
888 /* BOs freed, but not yet updated in the PT */
889 struct list_head freed;
891 /* contains the page directory */
892 struct radeon_bo *page_directory;
893 uint64_t pd_gpu_addr;
894 unsigned max_pde_used;
896 /* array of page tables, one for each page directory entry */
897 struct radeon_vm_pt *page_tables;
899 struct radeon_bo_va *ib_bo_va;
902 /* last fence for cs using this vm */
903 struct radeon_fence *fence;
904 /* last flush or NULL if we still need to flush */
905 struct radeon_fence *last_flush;
906 /* last use of vmid */
907 struct radeon_fence *last_id_use;
910 struct radeon_vm_manager {
911 struct radeon_fence *active[RADEON_NUM_VM];
913 /* number of VMIDs */
915 /* vram base address for page table entry */
916 u64 vram_base_offset;
919 /* for hw to save the PD addr on suspend/resume */
920 uint32_t saved_table_addr[RADEON_NUM_VM];
924 * file private structure
926 struct radeon_fpriv {
934 struct radeon_bo *ring_obj;
935 volatile uint32_t *ring;
947 #include "clearstate_defs.h"
950 /* for power gating */
951 struct radeon_bo *save_restore_obj;
952 uint64_t save_restore_gpu_addr;
953 volatile uint32_t *sr_ptr;
956 /* for clear state */
957 struct radeon_bo *clear_state_obj;
958 uint64_t clear_state_gpu_addr;
959 volatile uint32_t *cs_ptr;
960 const struct cs_section_def *cs_data;
961 u32 clear_state_size;
963 struct radeon_bo *cp_table_obj;
964 uint64_t cp_table_gpu_addr;
965 volatile uint32_t *cp_table_ptr;
969 int radeon_ib_get(struct radeon_device *rdev, int ring,
970 struct radeon_ib *ib, struct radeon_vm *vm,
972 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
973 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
974 struct radeon_ib *const_ib, bool hdp_flush);
975 int radeon_ib_pool_init(struct radeon_device *rdev);
976 void radeon_ib_pool_fini(struct radeon_device *rdev);
977 int radeon_ib_ring_tests(struct radeon_device *rdev);
978 /* Ring access between begin & end cannot sleep */
979 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
980 struct radeon_ring *ring);
981 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
982 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
983 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
984 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
986 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
988 void radeon_ring_undo(struct radeon_ring *ring);
989 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
990 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
991 void radeon_ring_lockup_update(struct radeon_device *rdev,
992 struct radeon_ring *ring);
993 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
994 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
996 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
997 unsigned size, uint32_t *data);
998 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
999 unsigned rptr_offs, u32 nop);
1000 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1003 /* r600 async dma */
1004 void r600_dma_stop(struct radeon_device *rdev);
1005 int r600_dma_resume(struct radeon_device *rdev);
1006 void r600_dma_fini(struct radeon_device *rdev);
1008 void cayman_dma_stop(struct radeon_device *rdev);
1009 int cayman_dma_resume(struct radeon_device *rdev);
1010 void cayman_dma_fini(struct radeon_device *rdev);
1015 struct radeon_cs_reloc {
1016 struct drm_gem_object *gobj;
1017 struct radeon_bo *robj;
1018 struct ttm_validate_buffer tv;
1019 uint64_t gpu_offset;
1020 unsigned prefered_domains;
1021 unsigned allowed_domains;
1022 uint32_t tiling_flags;
1026 struct radeon_cs_chunk {
1030 void __user *user_ptr;
1033 struct radeon_cs_parser {
1035 struct radeon_device *rdev;
1036 struct drm_file *filp;
1039 struct radeon_cs_chunk *chunks;
1040 uint64_t *chunks_array;
1045 struct radeon_cs_reloc *relocs;
1046 struct radeon_cs_reloc **relocs_ptr;
1047 struct radeon_cs_reloc *vm_bos;
1048 struct list_head validated;
1049 unsigned dma_reloc_idx;
1050 /* indices of various chunks */
1052 int chunk_relocs_idx;
1053 int chunk_flags_idx;
1054 int chunk_const_ib_idx;
1055 struct radeon_ib ib;
1056 struct radeon_ib const_ib;
1063 struct ww_acquire_ctx ticket;
1066 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1068 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1071 return ibc->kdata[idx];
1072 return p->ib.ptr[idx];
1076 struct radeon_cs_packet {
1082 unsigned one_reg_wr;
1085 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1086 struct radeon_cs_packet *pkt,
1087 unsigned idx, unsigned reg);
1088 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1089 struct radeon_cs_packet *pkt);
1095 int radeon_agp_init(struct radeon_device *rdev);
1096 void radeon_agp_resume(struct radeon_device *rdev);
1097 void radeon_agp_suspend(struct radeon_device *rdev);
1098 void radeon_agp_fini(struct radeon_device *rdev);
1105 struct radeon_bo *wb_obj;
1106 volatile uint32_t *wb;
1112 #define RADEON_WB_SCRATCH_OFFSET 0
1113 #define RADEON_WB_RING0_NEXT_RPTR 256
1114 #define RADEON_WB_CP_RPTR_OFFSET 1024
1115 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1116 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1117 #define R600_WB_DMA_RPTR_OFFSET 1792
1118 #define R600_WB_IH_WPTR_OFFSET 2048
1119 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1120 #define R600_WB_EVENT_OFFSET 3072
1121 #define CIK_WB_CP1_WPTR_OFFSET 3328
1122 #define CIK_WB_CP2_WPTR_OFFSET 3584
1125 * struct radeon_pm - power management datas
1126 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1127 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1128 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1129 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1130 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1131 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1132 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1133 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1134 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1135 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1136 * @needed_bandwidth: current bandwidth needs
1138 * It keeps track of various data needed to take powermanagement decision.
1139 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1140 * Equation between gpu/memory clock and available bandwidth is hw dependent
1141 * (type of memory, bus size, efficiency, ...)
1144 enum radeon_pm_method {
1150 enum radeon_dynpm_state {
1151 DYNPM_STATE_DISABLED,
1152 DYNPM_STATE_MINIMUM,
1155 DYNPM_STATE_SUSPENDED,
1157 enum radeon_dynpm_action {
1159 DYNPM_ACTION_MINIMUM,
1160 DYNPM_ACTION_DOWNCLOCK,
1161 DYNPM_ACTION_UPCLOCK,
1162 DYNPM_ACTION_DEFAULT
1165 enum radeon_voltage_type {
1172 enum radeon_pm_state_type {
1173 /* not used for dpm */
1174 POWER_STATE_TYPE_DEFAULT,
1175 POWER_STATE_TYPE_POWERSAVE,
1176 /* user selectable states */
1177 POWER_STATE_TYPE_BATTERY,
1178 POWER_STATE_TYPE_BALANCED,
1179 POWER_STATE_TYPE_PERFORMANCE,
1180 /* internal states */
1181 POWER_STATE_TYPE_INTERNAL_UVD,
1182 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1183 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1184 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1185 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1186 POWER_STATE_TYPE_INTERNAL_BOOT,
1187 POWER_STATE_TYPE_INTERNAL_THERMAL,
1188 POWER_STATE_TYPE_INTERNAL_ACPI,
1189 POWER_STATE_TYPE_INTERNAL_ULV,
1190 POWER_STATE_TYPE_INTERNAL_3DPERF,
1193 enum radeon_pm_profile_type {
1201 #define PM_PROFILE_DEFAULT_IDX 0
1202 #define PM_PROFILE_LOW_SH_IDX 1
1203 #define PM_PROFILE_MID_SH_IDX 2
1204 #define PM_PROFILE_HIGH_SH_IDX 3
1205 #define PM_PROFILE_LOW_MH_IDX 4
1206 #define PM_PROFILE_MID_MH_IDX 5
1207 #define PM_PROFILE_HIGH_MH_IDX 6
1208 #define PM_PROFILE_MAX 7
1210 struct radeon_pm_profile {
1211 int dpms_off_ps_idx;
1213 int dpms_off_cm_idx;
1217 enum radeon_int_thermal_type {
1219 THERMAL_TYPE_EXTERNAL,
1220 THERMAL_TYPE_EXTERNAL_GPIO,
1223 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1224 THERMAL_TYPE_EVERGREEN,
1228 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1233 struct radeon_voltage {
1234 enum radeon_voltage_type type;
1236 struct radeon_gpio_rec gpio;
1237 u32 delay; /* delay in usec from voltage drop to sclk change */
1238 bool active_high; /* voltage drop is active when bit is high */
1240 u8 vddc_id; /* index into vddc voltage table */
1241 u8 vddci_id; /* index into vddci voltage table */
1245 /* evergreen+ vddci */
1249 /* clock mode flags */
1250 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1252 struct radeon_pm_clock_info {
1258 struct radeon_voltage voltage;
1259 /* standardized clock flags */
1264 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1266 struct radeon_power_state {
1267 enum radeon_pm_state_type type;
1268 struct radeon_pm_clock_info *clock_info;
1269 /* number of valid clock modes in this power state */
1270 int num_clock_modes;
1271 struct radeon_pm_clock_info *default_clock_mode;
1272 /* standardized state flags */
1274 u32 misc; /* vbios specific flags */
1275 u32 misc2; /* vbios specific flags */
1276 int pcie_lanes; /* pcie lanes */
1280 * Some modes are overclocked by very low value, accept them
1282 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1284 enum radeon_dpm_auto_throttle_src {
1285 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1286 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1289 enum radeon_dpm_event_src {
1290 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1291 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1292 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1293 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1294 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1297 #define RADEON_MAX_VCE_LEVELS 6
1299 enum radeon_vce_level {
1300 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1301 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1302 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1303 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1304 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1305 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1309 u32 caps; /* vbios flags */
1310 u32 class; /* vbios flags */
1311 u32 class2; /* vbios flags */
1319 enum radeon_vce_level vce_level;
1324 struct radeon_dpm_thermal {
1325 /* thermal interrupt work */
1326 struct work_struct work;
1327 /* low temperature threshold */
1329 /* high temperature threshold */
1331 /* was interrupt low to high or high to low */
1335 enum radeon_clk_action
1341 struct radeon_blacklist_clocks
1345 enum radeon_clk_action action;
1348 struct radeon_clock_and_voltage_limits {
1355 struct radeon_clock_array {
1360 struct radeon_clock_voltage_dependency_entry {
1365 struct radeon_clock_voltage_dependency_table {
1367 struct radeon_clock_voltage_dependency_entry *entries;
1370 union radeon_cac_leakage_entry {
1382 struct radeon_cac_leakage_table {
1384 union radeon_cac_leakage_entry *entries;
1387 struct radeon_phase_shedding_limits_entry {
1393 struct radeon_phase_shedding_limits_table {
1395 struct radeon_phase_shedding_limits_entry *entries;
1398 struct radeon_uvd_clock_voltage_dependency_entry {
1404 struct radeon_uvd_clock_voltage_dependency_table {
1406 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1409 struct radeon_vce_clock_voltage_dependency_entry {
1415 struct radeon_vce_clock_voltage_dependency_table {
1417 struct radeon_vce_clock_voltage_dependency_entry *entries;
1420 struct radeon_ppm_table {
1422 u16 cpu_core_number;
1424 u32 small_ac_platform_tdp;
1426 u32 small_ac_platform_tdc;
1433 struct radeon_cac_tdp_table {
1435 u16 configurable_tdp;
1437 u16 battery_power_limit;
1438 u16 small_power_limit;
1439 u16 low_cac_leakage;
1440 u16 high_cac_leakage;
1441 u16 maximum_power_delivery_limit;
1444 struct radeon_dpm_dynamic_state {
1445 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1446 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1447 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1448 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1449 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1450 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1451 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1452 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1453 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1454 struct radeon_clock_array valid_sclk_values;
1455 struct radeon_clock_array valid_mclk_values;
1456 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1457 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1458 u32 mclk_sclk_ratio;
1459 u32 sclk_mclk_delta;
1460 u16 vddc_vddci_delta;
1461 u16 min_vddc_for_pcie_gen2;
1462 struct radeon_cac_leakage_table cac_leakage_table;
1463 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1464 struct radeon_ppm_table *ppm_table;
1465 struct radeon_cac_tdp_table *cac_tdp_table;
1468 struct radeon_dpm_fan {
1478 bool ucode_fan_control;
1481 enum radeon_pcie_gen {
1482 RADEON_PCIE_GEN1 = 0,
1483 RADEON_PCIE_GEN2 = 1,
1484 RADEON_PCIE_GEN3 = 2,
1485 RADEON_PCIE_GEN_INVALID = 0xffff
1488 enum radeon_dpm_forced_level {
1489 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1490 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1491 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1494 struct radeon_vce_state {
1506 struct radeon_ps *ps;
1507 /* number of valid power states */
1509 /* current power state that is active */
1510 struct radeon_ps *current_ps;
1511 /* requested power state */
1512 struct radeon_ps *requested_ps;
1513 /* boot up power state */
1514 struct radeon_ps *boot_ps;
1515 /* default uvd power state */
1516 struct radeon_ps *uvd_ps;
1517 /* vce requirements */
1518 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1519 enum radeon_vce_level vce_level;
1520 enum radeon_pm_state_type state;
1521 enum radeon_pm_state_type user_state;
1523 u32 voltage_response_time;
1524 u32 backbias_response_time;
1526 u32 new_active_crtcs;
1527 int new_active_crtc_count;
1528 u32 current_active_crtcs;
1529 int current_active_crtc_count;
1530 struct radeon_dpm_dynamic_state dyn_state;
1531 struct radeon_dpm_fan fan;
1534 u32 near_tdp_limit_adjusted;
1535 u32 sq_ramping_threshold;
1539 u16 load_line_slope;
1542 /* special states active */
1543 bool thermal_active;
1546 /* thermal handling */
1547 struct radeon_dpm_thermal thermal;
1549 enum radeon_dpm_forced_level forced_level;
1550 /* track UVD streams */
1555 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1556 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1560 /* write locked while reprogramming mclk */
1561 struct rw_semaphore mclk_lock;
1563 int active_crtc_count;
1566 fixed20_12 max_bandwidth;
1567 fixed20_12 igp_sideport_mclk;
1568 fixed20_12 igp_system_mclk;
1569 fixed20_12 igp_ht_link_clk;
1570 fixed20_12 igp_ht_link_width;
1571 fixed20_12 k8_bandwidth;
1572 fixed20_12 sideport_bandwidth;
1573 fixed20_12 ht_bandwidth;
1574 fixed20_12 core_bandwidth;
1577 fixed20_12 needed_bandwidth;
1578 struct radeon_power_state *power_state;
1579 /* number of valid power states */
1580 int num_power_states;
1581 int current_power_state_index;
1582 int current_clock_mode_index;
1583 int requested_power_state_index;
1584 int requested_clock_mode_index;
1585 int default_power_state_index;
1594 struct radeon_i2c_chan *i2c_bus;
1595 /* selected pm method */
1596 enum radeon_pm_method pm_method;
1597 /* dynpm power management */
1598 struct delayed_work dynpm_idle_work;
1599 enum radeon_dynpm_state dynpm_state;
1600 enum radeon_dynpm_action dynpm_planned_action;
1601 unsigned long dynpm_action_timeout;
1602 bool dynpm_can_upclock;
1603 bool dynpm_can_downclock;
1604 /* profile-based power management */
1605 enum radeon_pm_profile_type profile;
1607 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1608 /* internal thermal controller on rv6xx+ */
1609 enum radeon_int_thermal_type int_thermal_type;
1610 struct device *int_hwmon_dev;
1613 struct radeon_dpm dpm;
1616 int radeon_pm_get_type_index(struct radeon_device *rdev,
1617 enum radeon_pm_state_type ps_type,
1622 #define RADEON_MAX_UVD_HANDLES 10
1623 #define RADEON_UVD_STACK_SIZE (1024*1024)
1624 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1627 struct radeon_bo *vcpu_bo;
1631 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1632 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1633 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1634 struct delayed_work idle_work;
1637 int radeon_uvd_init(struct radeon_device *rdev);
1638 void radeon_uvd_fini(struct radeon_device *rdev);
1639 int radeon_uvd_suspend(struct radeon_device *rdev);
1640 int radeon_uvd_resume(struct radeon_device *rdev);
1641 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1642 uint32_t handle, struct radeon_fence **fence);
1643 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1644 uint32_t handle, struct radeon_fence **fence);
1645 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1646 void radeon_uvd_free_handles(struct radeon_device *rdev,
1647 struct drm_file *filp);
1648 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1649 void radeon_uvd_note_usage(struct radeon_device *rdev);
1650 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1651 unsigned vclk, unsigned dclk,
1652 unsigned vco_min, unsigned vco_max,
1653 unsigned fb_factor, unsigned fb_mask,
1654 unsigned pd_min, unsigned pd_max,
1656 unsigned *optimal_fb_div,
1657 unsigned *optimal_vclk_div,
1658 unsigned *optimal_dclk_div);
1659 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1660 unsigned cg_upll_func_cntl);
1665 #define RADEON_MAX_VCE_HANDLES 16
1666 #define RADEON_VCE_STACK_SIZE (1024*1024)
1667 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1670 struct radeon_bo *vcpu_bo;
1672 unsigned fw_version;
1673 unsigned fb_version;
1674 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1675 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1676 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1677 struct delayed_work idle_work;
1680 int radeon_vce_init(struct radeon_device *rdev);
1681 void radeon_vce_fini(struct radeon_device *rdev);
1682 int radeon_vce_suspend(struct radeon_device *rdev);
1683 int radeon_vce_resume(struct radeon_device *rdev);
1684 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1685 uint32_t handle, struct radeon_fence **fence);
1686 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1687 uint32_t handle, struct radeon_fence **fence);
1688 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1689 void radeon_vce_note_usage(struct radeon_device *rdev);
1690 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1691 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1692 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1693 struct radeon_ring *ring,
1694 struct radeon_semaphore *semaphore,
1696 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1697 void radeon_vce_fence_emit(struct radeon_device *rdev,
1698 struct radeon_fence *fence);
1699 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1700 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1702 struct r600_audio_pin {
1705 int bits_per_sample;
1715 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1722 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1728 void radeon_test_moves(struct radeon_device *rdev);
1729 void radeon_test_ring_sync(struct radeon_device *rdev,
1730 struct radeon_ring *cpA,
1731 struct radeon_ring *cpB);
1732 void radeon_test_syncing(struct radeon_device *rdev);
1738 struct radeon_debugfs {
1739 struct drm_info_list *files;
1743 int radeon_debugfs_add_files(struct radeon_device *rdev,
1744 struct drm_info_list *files,
1746 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1749 * ASIC ring specific functions.
1751 struct radeon_asic_ring {
1752 /* ring read/write ptr handling */
1753 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1754 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1755 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1757 /* validating and patching of IBs */
1758 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1759 int (*cs_parse)(struct radeon_cs_parser *p);
1761 /* command emmit functions */
1762 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1763 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1764 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1765 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1766 struct radeon_semaphore *semaphore, bool emit_wait);
1767 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1769 /* testing functions */
1770 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1771 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1772 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1775 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1779 * ASIC specific functions.
1781 struct radeon_asic {
1782 int (*init)(struct radeon_device *rdev);
1783 void (*fini)(struct radeon_device *rdev);
1784 int (*resume)(struct radeon_device *rdev);
1785 int (*suspend)(struct radeon_device *rdev);
1786 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1787 int (*asic_reset)(struct radeon_device *rdev);
1788 /* Flush the HDP cache via MMIO */
1789 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1790 /* check if 3D engine is idle */
1791 bool (*gui_idle)(struct radeon_device *rdev);
1792 /* wait for mc_idle */
1793 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1794 /* get the reference clock */
1795 u32 (*get_xclk)(struct radeon_device *rdev);
1796 /* get the gpu clock counter */
1797 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1800 void (*tlb_flush)(struct radeon_device *rdev);
1801 void (*set_page)(struct radeon_device *rdev, unsigned i,
1802 uint64_t addr, uint32_t flags);
1805 int (*init)(struct radeon_device *rdev);
1806 void (*fini)(struct radeon_device *rdev);
1807 void (*copy_pages)(struct radeon_device *rdev,
1808 struct radeon_ib *ib,
1809 uint64_t pe, uint64_t src,
1811 void (*write_pages)(struct radeon_device *rdev,
1812 struct radeon_ib *ib,
1814 uint64_t addr, unsigned count,
1815 uint32_t incr, uint32_t flags);
1816 void (*set_pages)(struct radeon_device *rdev,
1817 struct radeon_ib *ib,
1819 uint64_t addr, unsigned count,
1820 uint32_t incr, uint32_t flags);
1821 void (*pad_ib)(struct radeon_ib *ib);
1823 /* ring specific callbacks */
1824 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1827 int (*set)(struct radeon_device *rdev);
1828 int (*process)(struct radeon_device *rdev);
1832 /* display watermarks */
1833 void (*bandwidth_update)(struct radeon_device *rdev);
1834 /* get frame count */
1835 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1836 /* wait for vblank */
1837 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1838 /* set backlight level */
1839 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1840 /* get backlight level */
1841 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1842 /* audio callbacks */
1843 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1844 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1846 /* copy functions for bo handling */
1848 int (*blit)(struct radeon_device *rdev,
1849 uint64_t src_offset,
1850 uint64_t dst_offset,
1851 unsigned num_gpu_pages,
1852 struct radeon_fence **fence);
1853 u32 blit_ring_index;
1854 int (*dma)(struct radeon_device *rdev,
1855 uint64_t src_offset,
1856 uint64_t dst_offset,
1857 unsigned num_gpu_pages,
1858 struct radeon_fence **fence);
1860 /* method used for bo copy */
1861 int (*copy)(struct radeon_device *rdev,
1862 uint64_t src_offset,
1863 uint64_t dst_offset,
1864 unsigned num_gpu_pages,
1865 struct radeon_fence **fence);
1866 /* ring used for bo copies */
1867 u32 copy_ring_index;
1871 int (*set_reg)(struct radeon_device *rdev, int reg,
1872 uint32_t tiling_flags, uint32_t pitch,
1873 uint32_t offset, uint32_t obj_size);
1874 void (*clear_reg)(struct radeon_device *rdev, int reg);
1876 /* hotplug detect */
1878 void (*init)(struct radeon_device *rdev);
1879 void (*fini)(struct radeon_device *rdev);
1880 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1881 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1883 /* static power management */
1885 void (*misc)(struct radeon_device *rdev);
1886 void (*prepare)(struct radeon_device *rdev);
1887 void (*finish)(struct radeon_device *rdev);
1888 void (*init_profile)(struct radeon_device *rdev);
1889 void (*get_dynpm_state)(struct radeon_device *rdev);
1890 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1891 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1892 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1893 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1894 int (*get_pcie_lanes)(struct radeon_device *rdev);
1895 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1896 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1897 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1898 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1899 int (*get_temperature)(struct radeon_device *rdev);
1901 /* dynamic power management */
1903 int (*init)(struct radeon_device *rdev);
1904 void (*setup_asic)(struct radeon_device *rdev);
1905 int (*enable)(struct radeon_device *rdev);
1906 int (*late_enable)(struct radeon_device *rdev);
1907 void (*disable)(struct radeon_device *rdev);
1908 int (*pre_set_power_state)(struct radeon_device *rdev);
1909 int (*set_power_state)(struct radeon_device *rdev);
1910 void (*post_set_power_state)(struct radeon_device *rdev);
1911 void (*display_configuration_changed)(struct radeon_device *rdev);
1912 void (*fini)(struct radeon_device *rdev);
1913 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1914 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1915 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1916 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1917 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1918 bool (*vblank_too_short)(struct radeon_device *rdev);
1919 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1920 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1924 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1925 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1933 const unsigned *reg_safe_bm;
1934 unsigned reg_safe_bm_size;
1939 const unsigned *reg_safe_bm;
1940 unsigned reg_safe_bm_size;
1947 unsigned max_tile_pipes;
1949 unsigned max_backends;
1951 unsigned max_threads;
1952 unsigned max_stack_entries;
1953 unsigned max_hw_contexts;
1954 unsigned max_gs_threads;
1955 unsigned sx_max_export_size;
1956 unsigned sx_max_export_pos_size;
1957 unsigned sx_max_export_smx_size;
1958 unsigned sq_num_cf_insts;
1959 unsigned tiling_nbanks;
1960 unsigned tiling_npipes;
1961 unsigned tiling_group_size;
1962 unsigned tile_config;
1963 unsigned backend_map;
1964 unsigned active_simds;
1969 unsigned max_tile_pipes;
1971 unsigned max_backends;
1973 unsigned max_threads;
1974 unsigned max_stack_entries;
1975 unsigned max_hw_contexts;
1976 unsigned max_gs_threads;
1977 unsigned sx_max_export_size;
1978 unsigned sx_max_export_pos_size;
1979 unsigned sx_max_export_smx_size;
1980 unsigned sq_num_cf_insts;
1981 unsigned sx_num_of_sets;
1982 unsigned sc_prim_fifo_size;
1983 unsigned sc_hiz_tile_fifo_size;
1984 unsigned sc_earlyz_tile_fifo_fize;
1985 unsigned tiling_nbanks;
1986 unsigned tiling_npipes;
1987 unsigned tiling_group_size;
1988 unsigned tile_config;
1989 unsigned backend_map;
1990 unsigned active_simds;
1993 struct evergreen_asic {
1996 unsigned max_tile_pipes;
1998 unsigned max_backends;
2000 unsigned max_threads;
2001 unsigned max_stack_entries;
2002 unsigned max_hw_contexts;
2003 unsigned max_gs_threads;
2004 unsigned sx_max_export_size;
2005 unsigned sx_max_export_pos_size;
2006 unsigned sx_max_export_smx_size;
2007 unsigned sq_num_cf_insts;
2008 unsigned sx_num_of_sets;
2009 unsigned sc_prim_fifo_size;
2010 unsigned sc_hiz_tile_fifo_size;
2011 unsigned sc_earlyz_tile_fifo_size;
2012 unsigned tiling_nbanks;
2013 unsigned tiling_npipes;
2014 unsigned tiling_group_size;
2015 unsigned tile_config;
2016 unsigned backend_map;
2017 unsigned active_simds;
2020 struct cayman_asic {
2021 unsigned max_shader_engines;
2022 unsigned max_pipes_per_simd;
2023 unsigned max_tile_pipes;
2024 unsigned max_simds_per_se;
2025 unsigned max_backends_per_se;
2026 unsigned max_texture_channel_caches;
2028 unsigned max_threads;
2029 unsigned max_gs_threads;
2030 unsigned max_stack_entries;
2031 unsigned sx_num_of_sets;
2032 unsigned sx_max_export_size;
2033 unsigned sx_max_export_pos_size;
2034 unsigned sx_max_export_smx_size;
2035 unsigned max_hw_contexts;
2036 unsigned sq_num_cf_insts;
2037 unsigned sc_prim_fifo_size;
2038 unsigned sc_hiz_tile_fifo_size;
2039 unsigned sc_earlyz_tile_fifo_size;
2041 unsigned num_shader_engines;
2042 unsigned num_shader_pipes_per_simd;
2043 unsigned num_tile_pipes;
2044 unsigned num_simds_per_se;
2045 unsigned num_backends_per_se;
2046 unsigned backend_disable_mask_per_asic;
2047 unsigned backend_map;
2048 unsigned num_texture_channel_caches;
2049 unsigned mem_max_burst_length_bytes;
2050 unsigned mem_row_size_in_kb;
2051 unsigned shader_engine_tile_size;
2053 unsigned multi_gpu_tile_size;
2055 unsigned tile_config;
2056 unsigned active_simds;
2060 unsigned max_shader_engines;
2061 unsigned max_tile_pipes;
2062 unsigned max_cu_per_sh;
2063 unsigned max_sh_per_se;
2064 unsigned max_backends_per_se;
2065 unsigned max_texture_channel_caches;
2067 unsigned max_gs_threads;
2068 unsigned max_hw_contexts;
2069 unsigned sc_prim_fifo_size_frontend;
2070 unsigned sc_prim_fifo_size_backend;
2071 unsigned sc_hiz_tile_fifo_size;
2072 unsigned sc_earlyz_tile_fifo_size;
2074 unsigned num_tile_pipes;
2075 unsigned backend_enable_mask;
2076 unsigned backend_disable_mask_per_asic;
2077 unsigned backend_map;
2078 unsigned num_texture_channel_caches;
2079 unsigned mem_max_burst_length_bytes;
2080 unsigned mem_row_size_in_kb;
2081 unsigned shader_engine_tile_size;
2083 unsigned multi_gpu_tile_size;
2085 unsigned tile_config;
2086 uint32_t tile_mode_array[32];
2087 uint32_t active_cus;
2091 unsigned max_shader_engines;
2092 unsigned max_tile_pipes;
2093 unsigned max_cu_per_sh;
2094 unsigned max_sh_per_se;
2095 unsigned max_backends_per_se;
2096 unsigned max_texture_channel_caches;
2098 unsigned max_gs_threads;
2099 unsigned max_hw_contexts;
2100 unsigned sc_prim_fifo_size_frontend;
2101 unsigned sc_prim_fifo_size_backend;
2102 unsigned sc_hiz_tile_fifo_size;
2103 unsigned sc_earlyz_tile_fifo_size;
2105 unsigned num_tile_pipes;
2106 unsigned backend_enable_mask;
2107 unsigned backend_disable_mask_per_asic;
2108 unsigned backend_map;
2109 unsigned num_texture_channel_caches;
2110 unsigned mem_max_burst_length_bytes;
2111 unsigned mem_row_size_in_kb;
2112 unsigned shader_engine_tile_size;
2114 unsigned multi_gpu_tile_size;
2116 unsigned tile_config;
2117 uint32_t tile_mode_array[32];
2118 uint32_t macrotile_mode_array[16];
2119 uint32_t active_cus;
2122 union radeon_asic_config {
2123 struct r300_asic r300;
2124 struct r100_asic r100;
2125 struct r600_asic r600;
2126 struct rv770_asic rv770;
2127 struct evergreen_asic evergreen;
2128 struct cayman_asic cayman;
2130 struct cik_asic cik;
2134 * asic initizalization from radeon_asic.c
2136 void radeon_agp_disable(struct radeon_device *rdev);
2137 int radeon_asic_init(struct radeon_device *rdev);
2143 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2144 struct drm_file *filp);
2145 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2146 struct drm_file *filp);
2147 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2148 struct drm_file *file_priv);
2149 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2150 struct drm_file *file_priv);
2151 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2152 struct drm_file *file_priv);
2153 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2154 struct drm_file *file_priv);
2155 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2156 struct drm_file *filp);
2157 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2158 struct drm_file *filp);
2159 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2160 struct drm_file *filp);
2161 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2162 struct drm_file *filp);
2163 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *filp);
2165 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2166 struct drm_file *filp);
2167 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2168 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2169 struct drm_file *filp);
2170 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2171 struct drm_file *filp);
2173 /* VRAM scratch page for HDP bug, default vram page */
2174 struct r600_vram_scratch {
2175 struct radeon_bo *robj;
2176 volatile uint32_t *ptr;
2183 struct radeon_atif_notification_cfg {
2188 struct radeon_atif_notifications {
2189 bool display_switch;
2190 bool expansion_mode_change;
2192 bool forced_power_state;
2193 bool system_power_state;
2194 bool display_conf_change;
2196 bool brightness_change;
2197 bool dgpu_display_event;
2200 struct radeon_atif_functions {
2202 bool sbios_requests;
2203 bool select_active_disp;
2205 bool get_tv_standard;
2206 bool set_tv_standard;
2207 bool get_panel_expansion_mode;
2208 bool set_panel_expansion_mode;
2209 bool temperature_change;
2210 bool graphics_device_types;
2213 struct radeon_atif {
2214 struct radeon_atif_notifications notifications;
2215 struct radeon_atif_functions functions;
2216 struct radeon_atif_notification_cfg notification_cfg;
2217 struct radeon_encoder *encoder_for_bl;
2220 struct radeon_atcs_functions {
2224 bool pcie_bus_width;
2227 struct radeon_atcs {
2228 struct radeon_atcs_functions functions;
2232 * Core structure, functions and helpers.
2234 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2235 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2237 struct radeon_device {
2239 struct drm_device *ddev;
2240 struct pci_dev *pdev;
2241 struct rw_semaphore exclusive_lock;
2243 union radeon_asic_config config;
2244 enum radeon_family family;
2245 unsigned long flags;
2247 enum radeon_pll_errata pll_errata;
2254 uint16_t bios_header_start;
2255 struct radeon_bo *stollen_vga_memory;
2257 resource_size_t rmmio_base;
2258 resource_size_t rmmio_size;
2259 /* protects concurrent MM_INDEX/DATA based register access */
2260 spinlock_t mmio_idx_lock;
2261 /* protects concurrent SMC based register access */
2262 spinlock_t smc_idx_lock;
2263 /* protects concurrent PLL register access */
2264 spinlock_t pll_idx_lock;
2265 /* protects concurrent MC register access */
2266 spinlock_t mc_idx_lock;
2267 /* protects concurrent PCIE register access */
2268 spinlock_t pcie_idx_lock;
2269 /* protects concurrent PCIE_PORT register access */
2270 spinlock_t pciep_idx_lock;
2271 /* protects concurrent PIF register access */
2272 spinlock_t pif_idx_lock;
2273 /* protects concurrent CG register access */
2274 spinlock_t cg_idx_lock;
2275 /* protects concurrent UVD register access */
2276 spinlock_t uvd_idx_lock;
2277 /* protects concurrent RCU register access */
2278 spinlock_t rcu_idx_lock;
2279 /* protects concurrent DIDT register access */
2280 spinlock_t didt_idx_lock;
2281 /* protects concurrent ENDPOINT (audio) register access */
2282 spinlock_t end_idx_lock;
2283 void __iomem *rmmio;
2284 radeon_rreg_t mc_rreg;
2285 radeon_wreg_t mc_wreg;
2286 radeon_rreg_t pll_rreg;
2287 radeon_wreg_t pll_wreg;
2288 uint32_t pcie_reg_mask;
2289 radeon_rreg_t pciep_rreg;
2290 radeon_wreg_t pciep_wreg;
2292 void __iomem *rio_mem;
2293 resource_size_t rio_mem_size;
2294 struct radeon_clock clock;
2295 struct radeon_mc mc;
2296 struct radeon_gart gart;
2297 struct radeon_mode_info mode_info;
2298 struct radeon_scratch scratch;
2299 struct radeon_doorbell doorbell;
2300 struct radeon_mman mman;
2301 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2302 wait_queue_head_t fence_queue;
2303 struct mutex ring_lock;
2304 struct radeon_ring ring[RADEON_NUM_RINGS];
2306 struct radeon_sa_manager ring_tmp_bo;
2307 struct radeon_irq irq;
2308 struct radeon_asic *asic;
2309 struct radeon_gem gem;
2310 struct radeon_pm pm;
2311 struct radeon_uvd uvd;
2312 struct radeon_vce vce;
2313 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2314 struct radeon_wb wb;
2315 struct radeon_dummy_page dummy_page;
2320 bool fastfb_working; /* IGP feature*/
2322 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2323 const struct firmware *me_fw; /* all family ME firmware */
2324 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2325 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2326 const struct firmware *mc_fw; /* NI MC firmware */
2327 const struct firmware *ce_fw; /* SI CE firmware */
2328 const struct firmware *mec_fw; /* CIK MEC firmware */
2329 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2330 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2331 const struct firmware *smc_fw; /* SMC firmware */
2332 const struct firmware *uvd_fw; /* UVD firmware */
2333 const struct firmware *vce_fw; /* VCE firmware */
2335 struct r600_vram_scratch vram_scratch;
2336 int msi_enabled; /* msi enabled */
2337 struct r600_ih ih; /* r6/700 interrupt ring */
2338 struct radeon_rlc rlc;
2339 struct radeon_mec mec;
2340 struct work_struct hotplug_work;
2341 struct work_struct audio_work;
2342 struct work_struct reset_work;
2343 int num_crtc; /* number of crtcs */
2344 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2346 struct r600_audio audio; /* audio stuff */
2347 struct notifier_block acpi_nb;
2348 /* only one userspace can use Hyperz features or CMASK at a time */
2349 struct drm_file *hyperz_filp;
2350 struct drm_file *cmask_filp;
2352 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2354 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2355 unsigned debugfs_count;
2356 /* virtual memory */
2357 struct radeon_vm_manager vm_manager;
2358 struct mutex gpu_clock_mutex;
2360 atomic64_t vram_usage;
2361 atomic64_t gtt_usage;
2362 atomic64_t num_bytes_moved;
2363 /* ACPI interface */
2364 struct radeon_atif atif;
2365 struct radeon_atcs atcs;
2366 /* srbm instance registers */
2367 struct mutex srbm_mutex;
2368 /* clock, powergating flags */
2372 struct dev_pm_domain vga_pm_domain;
2373 bool have_disp_power_ref;
2376 /* tracking pinned memory */
2381 bool radeon_is_px(struct drm_device *dev);
2382 int radeon_device_init(struct radeon_device *rdev,
2383 struct drm_device *ddev,
2384 struct pci_dev *pdev,
2386 void radeon_device_fini(struct radeon_device *rdev);
2387 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2389 #define RADEON_MIN_MMIO_SIZE 0x10000
2391 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2392 bool always_indirect)
2394 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2395 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2396 return readl(((void __iomem *)rdev->rmmio) + reg);
2398 unsigned long flags;
2401 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2402 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2403 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2404 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2410 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2411 bool always_indirect)
2413 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2414 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2416 unsigned long flags;
2418 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2419 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2420 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2421 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2425 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2426 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2428 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2429 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2434 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2437 * Registers read & write functions.
2439 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2440 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2441 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2442 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2443 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2444 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2445 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2446 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2447 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2448 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2449 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2450 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2451 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2452 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2453 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2454 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2455 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2456 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2457 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2458 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2459 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2460 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2461 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2462 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2463 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2464 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2465 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2466 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2467 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2468 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2469 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2470 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2471 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2472 #define WREG32_P(reg, val, mask) \
2474 uint32_t tmp_ = RREG32(reg); \
2476 tmp_ |= ((val) & ~(mask)); \
2477 WREG32(reg, tmp_); \
2479 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2480 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2481 #define WREG32_PLL_P(reg, val, mask) \
2483 uint32_t tmp_ = RREG32_PLL(reg); \
2485 tmp_ |= ((val) & ~(mask)); \
2486 WREG32_PLL(reg, tmp_); \
2488 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2489 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2490 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2492 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2493 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2496 * Indirect registers accessor
2498 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2500 unsigned long flags;
2503 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2504 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2505 r = RREG32(RADEON_PCIE_DATA);
2506 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2510 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2512 unsigned long flags;
2514 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2515 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2516 WREG32(RADEON_PCIE_DATA, (v));
2517 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2520 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2522 unsigned long flags;
2525 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2526 WREG32(TN_SMC_IND_INDEX_0, (reg));
2527 r = RREG32(TN_SMC_IND_DATA_0);
2528 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2532 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2534 unsigned long flags;
2536 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2537 WREG32(TN_SMC_IND_INDEX_0, (reg));
2538 WREG32(TN_SMC_IND_DATA_0, (v));
2539 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2542 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2544 unsigned long flags;
2547 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2548 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2549 r = RREG32(R600_RCU_DATA);
2550 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2554 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2556 unsigned long flags;
2558 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2559 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2560 WREG32(R600_RCU_DATA, (v));
2561 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2564 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2566 unsigned long flags;
2569 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2570 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2571 r = RREG32(EVERGREEN_CG_IND_DATA);
2572 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2576 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2578 unsigned long flags;
2580 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2581 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2582 WREG32(EVERGREEN_CG_IND_DATA, (v));
2583 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2586 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2588 unsigned long flags;
2591 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2592 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2593 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2594 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2598 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2600 unsigned long flags;
2602 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2603 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2604 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2605 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2608 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2610 unsigned long flags;
2613 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2614 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2615 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2616 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2620 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2622 unsigned long flags;
2624 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2625 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2626 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2627 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2630 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2632 unsigned long flags;
2635 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2636 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2637 r = RREG32(R600_UVD_CTX_DATA);
2638 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2642 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2644 unsigned long flags;
2646 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2647 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2648 WREG32(R600_UVD_CTX_DATA, (v));
2649 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2653 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2655 unsigned long flags;
2658 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2659 WREG32(CIK_DIDT_IND_INDEX, (reg));
2660 r = RREG32(CIK_DIDT_IND_DATA);
2661 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2665 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2667 unsigned long flags;
2669 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2670 WREG32(CIK_DIDT_IND_INDEX, (reg));
2671 WREG32(CIK_DIDT_IND_DATA, (v));
2672 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2675 void r100_pll_errata_after_index(struct radeon_device *rdev);
2681 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2682 (rdev->pdev->device == 0x5969))
2683 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2684 (rdev->family == CHIP_RV200) || \
2685 (rdev->family == CHIP_RS100) || \
2686 (rdev->family == CHIP_RS200) || \
2687 (rdev->family == CHIP_RV250) || \
2688 (rdev->family == CHIP_RV280) || \
2689 (rdev->family == CHIP_RS300))
2690 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2691 (rdev->family == CHIP_RV350) || \
2692 (rdev->family == CHIP_R350) || \
2693 (rdev->family == CHIP_RV380) || \
2694 (rdev->family == CHIP_R420) || \
2695 (rdev->family == CHIP_R423) || \
2696 (rdev->family == CHIP_RV410) || \
2697 (rdev->family == CHIP_RS400) || \
2698 (rdev->family == CHIP_RS480))
2699 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2700 (rdev->ddev->pdev->device == 0x9443) || \
2701 (rdev->ddev->pdev->device == 0x944B) || \
2702 (rdev->ddev->pdev->device == 0x9506) || \
2703 (rdev->ddev->pdev->device == 0x9509) || \
2704 (rdev->ddev->pdev->device == 0x950F) || \
2705 (rdev->ddev->pdev->device == 0x689C) || \
2706 (rdev->ddev->pdev->device == 0x689D))
2707 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2708 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2709 (rdev->family == CHIP_RS690) || \
2710 (rdev->family == CHIP_RS740) || \
2711 (rdev->family >= CHIP_R600))
2712 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2713 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2714 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2715 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2716 (rdev->flags & RADEON_IS_IGP))
2717 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2718 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2719 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2720 (rdev->flags & RADEON_IS_IGP))
2721 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2722 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2723 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2724 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2725 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2726 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2727 (rdev->family == CHIP_MULLINS))
2729 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2730 (rdev->ddev->pdev->device == 0x6850) || \
2731 (rdev->ddev->pdev->device == 0x6858) || \
2732 (rdev->ddev->pdev->device == 0x6859) || \
2733 (rdev->ddev->pdev->device == 0x6840) || \
2734 (rdev->ddev->pdev->device == 0x6841) || \
2735 (rdev->ddev->pdev->device == 0x6842) || \
2736 (rdev->ddev->pdev->device == 0x6843))
2741 #define RBIOS8(i) (rdev->bios[i])
2742 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2743 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2745 int radeon_combios_init(struct radeon_device *rdev);
2746 void radeon_combios_fini(struct radeon_device *rdev);
2747 int radeon_atombios_init(struct radeon_device *rdev);
2748 void radeon_atombios_fini(struct radeon_device *rdev);
2754 #if DRM_DEBUG_CODE == 0
2755 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2757 ring->ring[ring->wptr++] = v;
2758 ring->wptr &= ring->ptr_mask;
2760 ring->ring_free_dw--;
2763 /* With debugging this is just too big to inline */
2764 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2770 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2771 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2772 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2773 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2774 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2775 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2776 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2777 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2778 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2779 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2780 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2781 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2782 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2783 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2784 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2785 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2786 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2787 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2788 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2789 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2790 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2791 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2792 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2793 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2794 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2795 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2796 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2797 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2798 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2799 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2800 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2801 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2802 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2803 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2804 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2805 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2806 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2807 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2808 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2809 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2810 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2811 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2812 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2813 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2814 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2815 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2816 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2817 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2818 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2819 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2820 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2821 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2822 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2823 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2824 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2825 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2826 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2827 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2828 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2829 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2830 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2831 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2832 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2833 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2834 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2835 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2836 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2837 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2838 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2839 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2840 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2841 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2842 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2843 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2844 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2845 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2846 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2847 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2848 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2849 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2850 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2851 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2852 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2853 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2854 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2855 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2856 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2858 /* Common functions */
2860 extern int radeon_gpu_reset(struct radeon_device *rdev);
2861 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2862 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2863 extern void radeon_agp_disable(struct radeon_device *rdev);
2864 extern int radeon_modeset_init(struct radeon_device *rdev);
2865 extern void radeon_modeset_fini(struct radeon_device *rdev);
2866 extern bool radeon_card_posted(struct radeon_device *rdev);
2867 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2868 extern void radeon_update_display_priority(struct radeon_device *rdev);
2869 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2870 extern void radeon_scratch_init(struct radeon_device *rdev);
2871 extern void radeon_wb_fini(struct radeon_device *rdev);
2872 extern int radeon_wb_init(struct radeon_device *rdev);
2873 extern void radeon_wb_disable(struct radeon_device *rdev);
2874 extern void radeon_surface_init(struct radeon_device *rdev);
2875 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2876 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2877 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2878 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2879 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2880 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2881 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2882 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2883 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2884 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2885 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2886 const u32 *registers,
2887 const u32 array_size);
2892 int radeon_vm_manager_init(struct radeon_device *rdev);
2893 void radeon_vm_manager_fini(struct radeon_device *rdev);
2894 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2895 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2896 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2897 struct radeon_vm *vm,
2898 struct list_head *head);
2899 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2900 struct radeon_vm *vm, int ring);
2901 void radeon_vm_flush(struct radeon_device *rdev,
2902 struct radeon_vm *vm,
2904 void radeon_vm_fence(struct radeon_device *rdev,
2905 struct radeon_vm *vm,
2906 struct radeon_fence *fence);
2907 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2908 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2909 struct radeon_vm *vm);
2910 int radeon_vm_clear_freed(struct radeon_device *rdev,
2911 struct radeon_vm *vm);
2912 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2913 struct radeon_vm *vm);
2914 int radeon_vm_bo_update(struct radeon_device *rdev,
2915 struct radeon_bo_va *bo_va,
2916 struct ttm_mem_reg *mem);
2917 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2918 struct radeon_bo *bo);
2919 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2920 struct radeon_bo *bo);
2921 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2922 struct radeon_vm *vm,
2923 struct radeon_bo *bo);
2924 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2925 struct radeon_bo_va *bo_va,
2928 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2929 struct radeon_bo_va *bo_va);
2932 void r600_audio_update_hdmi(struct work_struct *work);
2933 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2934 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2935 void r600_audio_enable(struct radeon_device *rdev,
2936 struct r600_audio_pin *pin,
2938 void dce6_audio_enable(struct radeon_device *rdev,
2939 struct r600_audio_pin *pin,
2943 * R600 vram scratch functions
2945 int r600_vram_scratch_init(struct radeon_device *rdev);
2946 void r600_vram_scratch_fini(struct radeon_device *rdev);
2949 * r600 cs checking helper
2951 unsigned r600_mip_minify(unsigned size, unsigned level);
2952 bool r600_fmt_is_valid_color(u32 format);
2953 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2954 int r600_fmt_get_blocksize(u32 format);
2955 int r600_fmt_get_nblocksx(u32 format, u32 w);
2956 int r600_fmt_get_nblocksy(u32 format, u32 h);
2959 * r600 functions used by radeon_encoder.c
2961 struct radeon_hdmi_acr {
2975 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2977 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2978 u32 tiling_pipe_num,
2980 u32 total_max_rb_num,
2981 u32 enabled_rb_mask);
2984 * evergreen functions used by radeon_encoder.c
2987 extern int ni_init_microcode(struct radeon_device *rdev);
2988 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2991 #if defined(CONFIG_ACPI)
2992 extern int radeon_acpi_init(struct radeon_device *rdev);
2993 extern void radeon_acpi_fini(struct radeon_device *rdev);
2994 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2995 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2996 u8 perf_req, bool advertise);
2997 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2999 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3000 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3003 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3004 struct radeon_cs_packet *pkt,
3006 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3007 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3008 struct radeon_cs_packet *pkt);
3009 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3010 struct radeon_cs_reloc **cs_reloc,
3012 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3013 uint32_t *vline_start_end,
3014 uint32_t *vline_status);
3016 #include "radeon_object.h"