2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
106 #define RADEON_IB_POOL_SIZE 16
107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
108 #define RADEONFB_CONN_LIMIT 4
109 #define RADEON_BIOS_NUM_SCRATCH 8
111 /* max number of rings */
112 #define RADEON_NUM_RINGS 5
114 /* fence seq are set to this number when signaled */
115 #define RADEON_FENCE_SIGNALED_SEQ 0LL
117 /* internal ring indices */
118 /* r1xx+ has gfx CP ring */
119 #define RADEON_RING_TYPE_GFX_INDEX 0
121 /* cayman has 2 compute CP rings */
122 #define CAYMAN_RING_TYPE_CP1_INDEX 1
123 #define CAYMAN_RING_TYPE_CP2_INDEX 2
125 /* R600+ has an async dma ring */
126 #define R600_RING_TYPE_DMA_INDEX 3
127 /* cayman add a second async dma ring */
128 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
130 /* hardcode those limit for now */
131 #define RADEON_VA_IB_OFFSET (1 << 20)
132 #define RADEON_VA_RESERVED_SIZE (8 << 20)
133 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
136 #define RADEON_RESET_GFX (1 << 0)
137 #define RADEON_RESET_COMPUTE (1 << 1)
138 #define RADEON_RESET_DMA (1 << 2)
141 * Errata workarounds.
143 enum radeon_pll_errata {
144 CHIP_ERRATA_R300_CG = 0x00000001,
145 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
146 CHIP_ERRATA_PLL_DELAY = 0x00000004
150 struct radeon_device;
156 bool radeon_get_bios(struct radeon_device *rdev);
161 struct radeon_dummy_page {
165 int radeon_dummy_page_init(struct radeon_device *rdev);
166 void radeon_dummy_page_fini(struct radeon_device *rdev);
172 struct radeon_clock {
173 struct radeon_pll p1pll;
174 struct radeon_pll p2pll;
175 struct radeon_pll dcpll;
176 struct radeon_pll spll;
177 struct radeon_pll mpll;
179 uint32_t default_mclk;
180 uint32_t default_sclk;
181 uint32_t default_dispclk;
183 uint32_t max_pixel_clock;
189 int radeon_pm_init(struct radeon_device *rdev);
190 void radeon_pm_fini(struct radeon_device *rdev);
191 void radeon_pm_compute_clocks(struct radeon_device *rdev);
192 void radeon_pm_suspend(struct radeon_device *rdev);
193 void radeon_pm_resume(struct radeon_device *rdev);
194 void radeon_combios_get_power_modes(struct radeon_device *rdev);
195 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
196 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
197 void rs690_pm_info(struct radeon_device *rdev);
198 extern int rv6xx_get_temp(struct radeon_device *rdev);
199 extern int rv770_get_temp(struct radeon_device *rdev);
200 extern int evergreen_get_temp(struct radeon_device *rdev);
201 extern int sumo_get_temp(struct radeon_device *rdev);
202 extern int si_get_temp(struct radeon_device *rdev);
203 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
204 unsigned *bankh, unsigned *mtaspect,
205 unsigned *tile_split);
210 struct radeon_fence_driver {
211 uint32_t scratch_reg;
213 volatile uint32_t *cpu_addr;
214 /* sync_seq is protected by ring emission lock */
215 uint64_t sync_seq[RADEON_NUM_RINGS];
217 unsigned long last_activity;
221 struct radeon_fence {
222 struct radeon_device *rdev;
224 /* protected by radeon_fence.lock */
230 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
231 int radeon_fence_driver_init(struct radeon_device *rdev);
232 void radeon_fence_driver_fini(struct radeon_device *rdev);
233 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
234 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
235 void radeon_fence_process(struct radeon_device *rdev, int ring);
236 bool radeon_fence_signaled(struct radeon_fence *fence);
237 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
238 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
239 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
240 int radeon_fence_wait_any(struct radeon_device *rdev,
241 struct radeon_fence **fences,
243 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
244 void radeon_fence_unref(struct radeon_fence **fence);
245 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
246 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
247 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
248 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
249 struct radeon_fence *b)
259 BUG_ON(a->ring != b->ring);
261 if (a->seq > b->seq) {
268 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
269 struct radeon_fence *b)
279 BUG_ON(a->ring != b->ring);
281 return a->seq < b->seq;
287 struct radeon_surface_reg {
288 struct radeon_bo *bo;
291 #define RADEON_GEM_MAX_SURFACES 8
297 struct ttm_bo_global_ref bo_global_ref;
298 struct drm_global_reference mem_global_ref;
299 struct ttm_bo_device bdev;
300 bool mem_global_referenced;
304 /* bo virtual address in a specific vm */
305 struct radeon_bo_va {
306 /* protected by bo being reserved */
307 struct list_head bo_list;
314 /* protected by vm mutex */
315 struct list_head vm_list;
317 /* constant after initialization */
318 struct radeon_vm *vm;
319 struct radeon_bo *bo;
323 /* Protected by gem.mutex */
324 struct list_head list;
325 /* Protected by tbo.reserved */
327 u32 busy_placements[3];
328 struct ttm_placement placement;
329 struct ttm_buffer_object tbo;
330 struct ttm_bo_kmap_obj kmap;
336 /* list of all virtual address to which this bo
340 /* Constant after initialization */
341 struct radeon_device *rdev;
342 struct drm_gem_object gem_base;
344 struct ttm_bo_kmap_obj dma_buf_vmap;
347 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
349 struct radeon_bo_list {
350 struct ttm_validate_buffer tv;
351 struct radeon_bo *bo;
358 /* sub-allocation manager, it has to be protected by another lock.
359 * By conception this is an helper for other part of the driver
360 * like the indirect buffer or semaphore, which both have their
363 * Principe is simple, we keep a list of sub allocation in offset
364 * order (first entry has offset == 0, last entry has the highest
367 * When allocating new object we first check if there is room at
368 * the end total_size - (last_object_offset + last_object_size) >=
369 * alloc_size. If so we allocate new object there.
371 * When there is not enough room at the end, we start waiting for
372 * each sub object until we reach object_offset+object_size >=
373 * alloc_size, this object then become the sub object we return.
375 * Alignment can't be bigger than page size.
377 * Hole are not considered for allocation to keep things simple.
378 * Assumption is that there won't be hole (all object on same
381 struct radeon_sa_manager {
382 wait_queue_head_t wq;
383 struct radeon_bo *bo;
384 struct list_head *hole;
385 struct list_head flist[RADEON_NUM_RINGS];
386 struct list_head olist;
395 /* sub-allocation buffer */
396 struct radeon_sa_bo {
397 struct list_head olist;
398 struct list_head flist;
399 struct radeon_sa_manager *manager;
402 struct radeon_fence *fence;
410 struct list_head objects;
413 int radeon_gem_init(struct radeon_device *rdev);
414 void radeon_gem_fini(struct radeon_device *rdev);
415 int radeon_gem_object_create(struct radeon_device *rdev, int size,
416 int alignment, int initial_domain,
417 bool discardable, bool kernel,
418 struct drm_gem_object **obj);
420 int radeon_mode_dumb_create(struct drm_file *file_priv,
421 struct drm_device *dev,
422 struct drm_mode_create_dumb *args);
423 int radeon_mode_dumb_mmap(struct drm_file *filp,
424 struct drm_device *dev,
425 uint32_t handle, uint64_t *offset_p);
426 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
427 struct drm_device *dev,
433 /* everything here is constant */
434 struct radeon_semaphore {
435 struct radeon_sa_bo *sa_bo;
440 int radeon_semaphore_create(struct radeon_device *rdev,
441 struct radeon_semaphore **semaphore);
442 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
443 struct radeon_semaphore *semaphore);
444 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
445 struct radeon_semaphore *semaphore);
446 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
447 struct radeon_semaphore *semaphore,
448 int signaler, int waiter);
449 void radeon_semaphore_free(struct radeon_device *rdev,
450 struct radeon_semaphore **semaphore,
451 struct radeon_fence *fence);
454 * GART structures, functions & helpers
458 #define RADEON_GPU_PAGE_SIZE 4096
459 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
460 #define RADEON_GPU_PAGE_SHIFT 12
461 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
464 dma_addr_t table_addr;
465 struct radeon_bo *robj;
467 unsigned num_gpu_pages;
468 unsigned num_cpu_pages;
471 dma_addr_t *pages_addr;
475 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
476 void radeon_gart_table_ram_free(struct radeon_device *rdev);
477 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
478 void radeon_gart_table_vram_free(struct radeon_device *rdev);
479 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
480 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
481 int radeon_gart_init(struct radeon_device *rdev);
482 void radeon_gart_fini(struct radeon_device *rdev);
483 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
485 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
486 int pages, struct page **pagelist,
487 dma_addr_t *dma_addr);
488 void radeon_gart_restore(struct radeon_device *rdev);
492 * GPU MC structures, functions & helpers
495 resource_size_t aper_size;
496 resource_size_t aper_base;
497 resource_size_t agp_base;
498 /* for some chips with <= 32MB we need to lie
499 * about vram size near mc fb location */
501 u64 visible_vram_size;
511 bool igp_sideport_enabled;
515 bool radeon_combios_sideport_present(struct radeon_device *rdev);
516 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
519 * GPU scratch registers structures, functions & helpers
521 struct radeon_scratch {
528 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
529 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
536 struct radeon_unpin_work {
537 struct work_struct work;
538 struct radeon_device *rdev;
540 struct radeon_fence *fence;
541 struct drm_pending_vblank_event *event;
542 struct radeon_bo *old_rbo;
546 struct r500_irq_stat_regs {
551 struct r600_irq_stat_regs {
561 struct evergreen_irq_stat_regs {
582 union radeon_irq_stat_regs {
583 struct r500_irq_stat_regs r500;
584 struct r600_irq_stat_regs r600;
585 struct evergreen_irq_stat_regs evergreen;
588 #define RADEON_MAX_HPD_PINS 6
589 #define RADEON_MAX_CRTCS 6
590 #define RADEON_MAX_AFMT_BLOCKS 6
595 atomic_t ring_int[RADEON_NUM_RINGS];
596 bool crtc_vblank_int[RADEON_MAX_CRTCS];
597 atomic_t pflip[RADEON_MAX_CRTCS];
598 wait_queue_head_t vblank_queue;
599 bool hpd[RADEON_MAX_HPD_PINS];
600 bool afmt[RADEON_MAX_AFMT_BLOCKS];
601 union radeon_irq_stat_regs stat_regs;
604 int radeon_irq_kms_init(struct radeon_device *rdev);
605 void radeon_irq_kms_fini(struct radeon_device *rdev);
606 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
607 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
608 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
609 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
610 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
611 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
612 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
613 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
620 struct radeon_sa_bo *sa_bo;
625 struct radeon_fence *fence;
626 struct radeon_vm *vm;
628 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
629 struct radeon_semaphore *semaphore;
633 struct radeon_bo *ring_obj;
634 volatile uint32_t *ring;
638 unsigned rptr_save_reg;
639 u64 next_rptr_gpu_addr;
640 volatile u32 *next_rptr_cpu_addr;
645 unsigned ring_free_dw;
647 unsigned long last_activity;
663 /* maximum number of VMIDs */
664 #define RADEON_NUM_VM 16
666 /* defines number of bits in page table versus page directory,
667 * a page is 4KB so we have 12 bits offset, 9 bits in the page
668 * table and the remaining 19 bits are in the page directory */
669 #define RADEON_VM_BLOCK_SIZE 9
671 /* number of entries in page table */
672 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
675 struct list_head list;
679 /* contains the page directory */
680 struct radeon_sa_bo *page_directory;
681 uint64_t pd_gpu_addr;
683 /* array of page tables, one for each page directory entry */
684 struct radeon_sa_bo **page_tables;
687 /* last fence for cs using this vm */
688 struct radeon_fence *fence;
689 /* last flush or NULL if we still need to flush */
690 struct radeon_fence *last_flush;
693 struct radeon_vm_manager {
695 struct list_head lru_vm;
696 struct radeon_fence *active[RADEON_NUM_VM];
697 struct radeon_sa_manager sa_manager;
699 /* number of VMIDs */
701 /* vram base address for page table entry */
702 u64 vram_base_offset;
708 * file private structure
710 struct radeon_fpriv {
718 struct radeon_bo *ring_obj;
719 volatile uint32_t *ring;
728 struct r600_blit_cp_primitives {
729 void (*set_render_target)(struct radeon_device *rdev, int format,
730 int w, int h, u64 gpu_addr);
731 void (*cp_set_surface_sync)(struct radeon_device *rdev,
732 u32 sync_type, u32 size,
734 void (*set_shaders)(struct radeon_device *rdev);
735 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
736 void (*set_tex_resource)(struct radeon_device *rdev,
737 int format, int w, int h, int pitch,
738 u64 gpu_addr, u32 size);
739 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
741 void (*draw_auto)(struct radeon_device *rdev);
742 void (*set_default_state)(struct radeon_device *rdev);
746 struct radeon_bo *shader_obj;
747 struct r600_blit_cp_primitives primitives;
749 int ring_size_common;
750 int ring_size_per_loop;
752 u32 vs_offset, ps_offset;
761 /* for power gating */
762 struct radeon_bo *save_restore_obj;
763 uint64_t save_restore_gpu_addr;
764 /* for clear state */
765 struct radeon_bo *clear_state_obj;
766 uint64_t clear_state_gpu_addr;
769 int radeon_ib_get(struct radeon_device *rdev, int ring,
770 struct radeon_ib *ib, struct radeon_vm *vm,
772 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
773 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
774 struct radeon_ib *const_ib);
775 int radeon_ib_pool_init(struct radeon_device *rdev);
776 void radeon_ib_pool_fini(struct radeon_device *rdev);
777 int radeon_ib_ring_tests(struct radeon_device *rdev);
778 /* Ring access between begin & end cannot sleep */
779 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
780 struct radeon_ring *ring);
781 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
782 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
783 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
784 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
785 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
786 void radeon_ring_undo(struct radeon_ring *ring);
787 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
788 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
789 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
790 void radeon_ring_lockup_update(struct radeon_ring *ring);
791 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
792 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
794 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
795 unsigned size, uint32_t *data);
796 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
797 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
798 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
799 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
803 void r600_dma_stop(struct radeon_device *rdev);
804 int r600_dma_resume(struct radeon_device *rdev);
805 void r600_dma_fini(struct radeon_device *rdev);
807 void cayman_dma_stop(struct radeon_device *rdev);
808 int cayman_dma_resume(struct radeon_device *rdev);
809 void cayman_dma_fini(struct radeon_device *rdev);
814 struct radeon_cs_reloc {
815 struct drm_gem_object *gobj;
816 struct radeon_bo *robj;
817 struct radeon_bo_list lobj;
822 struct radeon_cs_chunk {
828 void __user *user_ptr;
829 int last_copied_page;
833 struct radeon_cs_parser {
835 struct radeon_device *rdev;
836 struct drm_file *filp;
839 struct radeon_cs_chunk *chunks;
840 uint64_t *chunks_array;
845 struct radeon_cs_reloc *relocs;
846 struct radeon_cs_reloc **relocs_ptr;
847 struct list_head validated;
848 unsigned dma_reloc_idx;
849 /* indices of various chunks */
851 int chunk_relocs_idx;
853 int chunk_const_ib_idx;
855 struct radeon_ib const_ib;
864 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
865 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
867 struct radeon_cs_packet {
876 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
877 struct radeon_cs_packet *pkt,
878 unsigned idx, unsigned reg);
879 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
880 struct radeon_cs_packet *pkt);
886 int radeon_agp_init(struct radeon_device *rdev);
887 void radeon_agp_resume(struct radeon_device *rdev);
888 void radeon_agp_suspend(struct radeon_device *rdev);
889 void radeon_agp_fini(struct radeon_device *rdev);
896 struct radeon_bo *wb_obj;
897 volatile uint32_t *wb;
903 #define RADEON_WB_SCRATCH_OFFSET 0
904 #define RADEON_WB_RING0_NEXT_RPTR 256
905 #define RADEON_WB_CP_RPTR_OFFSET 1024
906 #define RADEON_WB_CP1_RPTR_OFFSET 1280
907 #define RADEON_WB_CP2_RPTR_OFFSET 1536
908 #define R600_WB_DMA_RPTR_OFFSET 1792
909 #define R600_WB_IH_WPTR_OFFSET 2048
910 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
911 #define R600_WB_EVENT_OFFSET 3072
914 * struct radeon_pm - power management datas
915 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
916 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
917 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
918 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
919 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
920 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
921 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
922 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
923 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
924 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
925 * @needed_bandwidth: current bandwidth needs
927 * It keeps track of various data needed to take powermanagement decision.
928 * Bandwidth need is used to determine minimun clock of the GPU and memory.
929 * Equation between gpu/memory clock and available bandwidth is hw dependent
930 * (type of memory, bus size, efficiency, ...)
933 enum radeon_pm_method {
938 enum radeon_dynpm_state {
939 DYNPM_STATE_DISABLED,
943 DYNPM_STATE_SUSPENDED,
945 enum radeon_dynpm_action {
947 DYNPM_ACTION_MINIMUM,
948 DYNPM_ACTION_DOWNCLOCK,
949 DYNPM_ACTION_UPCLOCK,
953 enum radeon_voltage_type {
960 enum radeon_pm_state_type {
961 POWER_STATE_TYPE_DEFAULT,
962 POWER_STATE_TYPE_POWERSAVE,
963 POWER_STATE_TYPE_BATTERY,
964 POWER_STATE_TYPE_BALANCED,
965 POWER_STATE_TYPE_PERFORMANCE,
968 enum radeon_pm_profile_type {
976 #define PM_PROFILE_DEFAULT_IDX 0
977 #define PM_PROFILE_LOW_SH_IDX 1
978 #define PM_PROFILE_MID_SH_IDX 2
979 #define PM_PROFILE_HIGH_SH_IDX 3
980 #define PM_PROFILE_LOW_MH_IDX 4
981 #define PM_PROFILE_MID_MH_IDX 5
982 #define PM_PROFILE_HIGH_MH_IDX 6
983 #define PM_PROFILE_MAX 7
985 struct radeon_pm_profile {
992 enum radeon_int_thermal_type {
996 THERMAL_TYPE_EVERGREEN,
1002 struct radeon_voltage {
1003 enum radeon_voltage_type type;
1005 struct radeon_gpio_rec gpio;
1006 u32 delay; /* delay in usec from voltage drop to sclk change */
1007 bool active_high; /* voltage drop is active when bit is high */
1009 u8 vddc_id; /* index into vddc voltage table */
1010 u8 vddci_id; /* index into vddci voltage table */
1014 /* evergreen+ vddci */
1018 /* clock mode flags */
1019 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1021 struct radeon_pm_clock_info {
1027 struct radeon_voltage voltage;
1028 /* standardized clock flags */
1033 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1035 struct radeon_power_state {
1036 enum radeon_pm_state_type type;
1037 struct radeon_pm_clock_info *clock_info;
1038 /* number of valid clock modes in this power state */
1039 int num_clock_modes;
1040 struct radeon_pm_clock_info *default_clock_mode;
1041 /* standardized state flags */
1043 u32 misc; /* vbios specific flags */
1044 u32 misc2; /* vbios specific flags */
1045 int pcie_lanes; /* pcie lanes */
1049 * Some modes are overclocked by very low value, accept them
1051 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1055 /* write locked while reprogramming mclk */
1056 struct rw_semaphore mclk_lock;
1058 int active_crtc_count;
1061 fixed20_12 max_bandwidth;
1062 fixed20_12 igp_sideport_mclk;
1063 fixed20_12 igp_system_mclk;
1064 fixed20_12 igp_ht_link_clk;
1065 fixed20_12 igp_ht_link_width;
1066 fixed20_12 k8_bandwidth;
1067 fixed20_12 sideport_bandwidth;
1068 fixed20_12 ht_bandwidth;
1069 fixed20_12 core_bandwidth;
1072 fixed20_12 needed_bandwidth;
1073 struct radeon_power_state *power_state;
1074 /* number of valid power states */
1075 int num_power_states;
1076 int current_power_state_index;
1077 int current_clock_mode_index;
1078 int requested_power_state_index;
1079 int requested_clock_mode_index;
1080 int default_power_state_index;
1089 struct radeon_i2c_chan *i2c_bus;
1090 /* selected pm method */
1091 enum radeon_pm_method pm_method;
1092 /* dynpm power management */
1093 struct delayed_work dynpm_idle_work;
1094 enum radeon_dynpm_state dynpm_state;
1095 enum radeon_dynpm_action dynpm_planned_action;
1096 unsigned long dynpm_action_timeout;
1097 bool dynpm_can_upclock;
1098 bool dynpm_can_downclock;
1099 /* profile-based power management */
1100 enum radeon_pm_profile_type profile;
1102 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1103 /* internal thermal controller on rv6xx+ */
1104 enum radeon_int_thermal_type int_thermal_type;
1105 struct device *int_hwmon_dev;
1108 int radeon_pm_get_type_index(struct radeon_device *rdev,
1109 enum radeon_pm_state_type ps_type,
1115 int bits_per_sample;
1123 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1129 void radeon_test_moves(struct radeon_device *rdev);
1130 void radeon_test_ring_sync(struct radeon_device *rdev,
1131 struct radeon_ring *cpA,
1132 struct radeon_ring *cpB);
1133 void radeon_test_syncing(struct radeon_device *rdev);
1139 struct radeon_debugfs {
1140 struct drm_info_list *files;
1144 int radeon_debugfs_add_files(struct radeon_device *rdev,
1145 struct drm_info_list *files,
1147 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1151 * ASIC specific functions.
1153 struct radeon_asic {
1154 int (*init)(struct radeon_device *rdev);
1155 void (*fini)(struct radeon_device *rdev);
1156 int (*resume)(struct radeon_device *rdev);
1157 int (*suspend)(struct radeon_device *rdev);
1158 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1159 int (*asic_reset)(struct radeon_device *rdev);
1160 /* ioctl hw specific callback. Some hw might want to perform special
1161 * operation on specific ioctl. For instance on wait idle some hw
1162 * might want to perform and HDP flush through MMIO as it seems that
1163 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1166 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1167 /* check if 3D engine is idle */
1168 bool (*gui_idle)(struct radeon_device *rdev);
1169 /* wait for mc_idle */
1170 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1173 void (*tlb_flush)(struct radeon_device *rdev);
1174 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1177 int (*init)(struct radeon_device *rdev);
1178 void (*fini)(struct radeon_device *rdev);
1181 void (*set_page)(struct radeon_device *rdev, uint64_t pe,
1182 uint64_t addr, unsigned count,
1183 uint32_t incr, uint32_t flags);
1185 /* ring specific callbacks */
1187 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1188 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1189 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1190 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1191 struct radeon_semaphore *semaphore, bool emit_wait);
1192 int (*cs_parse)(struct radeon_cs_parser *p);
1193 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1194 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1195 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1196 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1197 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1198 } ring[RADEON_NUM_RINGS];
1201 int (*set)(struct radeon_device *rdev);
1202 int (*process)(struct radeon_device *rdev);
1206 /* display watermarks */
1207 void (*bandwidth_update)(struct radeon_device *rdev);
1208 /* get frame count */
1209 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1210 /* wait for vblank */
1211 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1212 /* set backlight level */
1213 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1214 /* get backlight level */
1215 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1217 /* copy functions for bo handling */
1219 int (*blit)(struct radeon_device *rdev,
1220 uint64_t src_offset,
1221 uint64_t dst_offset,
1222 unsigned num_gpu_pages,
1223 struct radeon_fence **fence);
1224 u32 blit_ring_index;
1225 int (*dma)(struct radeon_device *rdev,
1226 uint64_t src_offset,
1227 uint64_t dst_offset,
1228 unsigned num_gpu_pages,
1229 struct radeon_fence **fence);
1231 /* method used for bo copy */
1232 int (*copy)(struct radeon_device *rdev,
1233 uint64_t src_offset,
1234 uint64_t dst_offset,
1235 unsigned num_gpu_pages,
1236 struct radeon_fence **fence);
1237 /* ring used for bo copies */
1238 u32 copy_ring_index;
1242 int (*set_reg)(struct radeon_device *rdev, int reg,
1243 uint32_t tiling_flags, uint32_t pitch,
1244 uint32_t offset, uint32_t obj_size);
1245 void (*clear_reg)(struct radeon_device *rdev, int reg);
1247 /* hotplug detect */
1249 void (*init)(struct radeon_device *rdev);
1250 void (*fini)(struct radeon_device *rdev);
1251 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1252 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1254 /* power management */
1256 void (*misc)(struct radeon_device *rdev);
1257 void (*prepare)(struct radeon_device *rdev);
1258 void (*finish)(struct radeon_device *rdev);
1259 void (*init_profile)(struct radeon_device *rdev);
1260 void (*get_dynpm_state)(struct radeon_device *rdev);
1261 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1262 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1263 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1264 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1265 int (*get_pcie_lanes)(struct radeon_device *rdev);
1266 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1267 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1271 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1272 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1273 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1281 const unsigned *reg_safe_bm;
1282 unsigned reg_safe_bm_size;
1287 const unsigned *reg_safe_bm;
1288 unsigned reg_safe_bm_size;
1295 unsigned max_tile_pipes;
1297 unsigned max_backends;
1299 unsigned max_threads;
1300 unsigned max_stack_entries;
1301 unsigned max_hw_contexts;
1302 unsigned max_gs_threads;
1303 unsigned sx_max_export_size;
1304 unsigned sx_max_export_pos_size;
1305 unsigned sx_max_export_smx_size;
1306 unsigned sq_num_cf_insts;
1307 unsigned tiling_nbanks;
1308 unsigned tiling_npipes;
1309 unsigned tiling_group_size;
1310 unsigned tile_config;
1311 unsigned backend_map;
1316 unsigned max_tile_pipes;
1318 unsigned max_backends;
1320 unsigned max_threads;
1321 unsigned max_stack_entries;
1322 unsigned max_hw_contexts;
1323 unsigned max_gs_threads;
1324 unsigned sx_max_export_size;
1325 unsigned sx_max_export_pos_size;
1326 unsigned sx_max_export_smx_size;
1327 unsigned sq_num_cf_insts;
1328 unsigned sx_num_of_sets;
1329 unsigned sc_prim_fifo_size;
1330 unsigned sc_hiz_tile_fifo_size;
1331 unsigned sc_earlyz_tile_fifo_fize;
1332 unsigned tiling_nbanks;
1333 unsigned tiling_npipes;
1334 unsigned tiling_group_size;
1335 unsigned tile_config;
1336 unsigned backend_map;
1339 struct evergreen_asic {
1342 unsigned max_tile_pipes;
1344 unsigned max_backends;
1346 unsigned max_threads;
1347 unsigned max_stack_entries;
1348 unsigned max_hw_contexts;
1349 unsigned max_gs_threads;
1350 unsigned sx_max_export_size;
1351 unsigned sx_max_export_pos_size;
1352 unsigned sx_max_export_smx_size;
1353 unsigned sq_num_cf_insts;
1354 unsigned sx_num_of_sets;
1355 unsigned sc_prim_fifo_size;
1356 unsigned sc_hiz_tile_fifo_size;
1357 unsigned sc_earlyz_tile_fifo_size;
1358 unsigned tiling_nbanks;
1359 unsigned tiling_npipes;
1360 unsigned tiling_group_size;
1361 unsigned tile_config;
1362 unsigned backend_map;
1365 struct cayman_asic {
1366 unsigned max_shader_engines;
1367 unsigned max_pipes_per_simd;
1368 unsigned max_tile_pipes;
1369 unsigned max_simds_per_se;
1370 unsigned max_backends_per_se;
1371 unsigned max_texture_channel_caches;
1373 unsigned max_threads;
1374 unsigned max_gs_threads;
1375 unsigned max_stack_entries;
1376 unsigned sx_num_of_sets;
1377 unsigned sx_max_export_size;
1378 unsigned sx_max_export_pos_size;
1379 unsigned sx_max_export_smx_size;
1380 unsigned max_hw_contexts;
1381 unsigned sq_num_cf_insts;
1382 unsigned sc_prim_fifo_size;
1383 unsigned sc_hiz_tile_fifo_size;
1384 unsigned sc_earlyz_tile_fifo_size;
1386 unsigned num_shader_engines;
1387 unsigned num_shader_pipes_per_simd;
1388 unsigned num_tile_pipes;
1389 unsigned num_simds_per_se;
1390 unsigned num_backends_per_se;
1391 unsigned backend_disable_mask_per_asic;
1392 unsigned backend_map;
1393 unsigned num_texture_channel_caches;
1394 unsigned mem_max_burst_length_bytes;
1395 unsigned mem_row_size_in_kb;
1396 unsigned shader_engine_tile_size;
1398 unsigned multi_gpu_tile_size;
1400 unsigned tile_config;
1404 unsigned max_shader_engines;
1405 unsigned max_tile_pipes;
1406 unsigned max_cu_per_sh;
1407 unsigned max_sh_per_se;
1408 unsigned max_backends_per_se;
1409 unsigned max_texture_channel_caches;
1411 unsigned max_gs_threads;
1412 unsigned max_hw_contexts;
1413 unsigned sc_prim_fifo_size_frontend;
1414 unsigned sc_prim_fifo_size_backend;
1415 unsigned sc_hiz_tile_fifo_size;
1416 unsigned sc_earlyz_tile_fifo_size;
1418 unsigned num_tile_pipes;
1419 unsigned num_backends_per_se;
1420 unsigned backend_disable_mask_per_asic;
1421 unsigned backend_map;
1422 unsigned num_texture_channel_caches;
1423 unsigned mem_max_burst_length_bytes;
1424 unsigned mem_row_size_in_kb;
1425 unsigned shader_engine_tile_size;
1427 unsigned multi_gpu_tile_size;
1429 unsigned tile_config;
1432 union radeon_asic_config {
1433 struct r300_asic r300;
1434 struct r100_asic r100;
1435 struct r600_asic r600;
1436 struct rv770_asic rv770;
1437 struct evergreen_asic evergreen;
1438 struct cayman_asic cayman;
1443 * asic initizalization from radeon_asic.c
1445 void radeon_agp_disable(struct radeon_device *rdev);
1446 int radeon_asic_init(struct radeon_device *rdev);
1452 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1453 struct drm_file *filp);
1454 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1455 struct drm_file *filp);
1456 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1457 struct drm_file *file_priv);
1458 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1459 struct drm_file *file_priv);
1460 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1461 struct drm_file *file_priv);
1462 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1463 struct drm_file *file_priv);
1464 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1465 struct drm_file *filp);
1466 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1467 struct drm_file *filp);
1468 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1469 struct drm_file *filp);
1470 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1471 struct drm_file *filp);
1472 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1473 struct drm_file *filp);
1474 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1475 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1476 struct drm_file *filp);
1477 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1478 struct drm_file *filp);
1480 /* VRAM scratch page for HDP bug, default vram page */
1481 struct r600_vram_scratch {
1482 struct radeon_bo *robj;
1483 volatile uint32_t *ptr;
1490 struct radeon_atif_notification_cfg {
1495 struct radeon_atif_notifications {
1496 bool display_switch;
1497 bool expansion_mode_change;
1499 bool forced_power_state;
1500 bool system_power_state;
1501 bool display_conf_change;
1503 bool brightness_change;
1504 bool dgpu_display_event;
1507 struct radeon_atif_functions {
1509 bool sbios_requests;
1510 bool select_active_disp;
1512 bool get_tv_standard;
1513 bool set_tv_standard;
1514 bool get_panel_expansion_mode;
1515 bool set_panel_expansion_mode;
1516 bool temperature_change;
1517 bool graphics_device_types;
1520 struct radeon_atif {
1521 struct radeon_atif_notifications notifications;
1522 struct radeon_atif_functions functions;
1523 struct radeon_atif_notification_cfg notification_cfg;
1524 struct radeon_encoder *encoder_for_bl;
1527 struct radeon_atcs_functions {
1531 bool pcie_bus_width;
1534 struct radeon_atcs {
1535 struct radeon_atcs_functions functions;
1539 * Core structure, functions and helpers.
1541 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1542 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1544 struct radeon_device {
1546 struct drm_device *ddev;
1547 struct pci_dev *pdev;
1548 struct rw_semaphore exclusive_lock;
1550 union radeon_asic_config config;
1551 enum radeon_family family;
1552 unsigned long flags;
1554 enum radeon_pll_errata pll_errata;
1561 uint16_t bios_header_start;
1562 struct radeon_bo *stollen_vga_memory;
1564 resource_size_t rmmio_base;
1565 resource_size_t rmmio_size;
1566 /* protects concurrent MM_INDEX/DATA based register access */
1567 spinlock_t mmio_idx_lock;
1568 void __iomem *rmmio;
1569 radeon_rreg_t mc_rreg;
1570 radeon_wreg_t mc_wreg;
1571 radeon_rreg_t pll_rreg;
1572 radeon_wreg_t pll_wreg;
1573 uint32_t pcie_reg_mask;
1574 radeon_rreg_t pciep_rreg;
1575 radeon_wreg_t pciep_wreg;
1577 void __iomem *rio_mem;
1578 resource_size_t rio_mem_size;
1579 struct radeon_clock clock;
1580 struct radeon_mc mc;
1581 struct radeon_gart gart;
1582 struct radeon_mode_info mode_info;
1583 struct radeon_scratch scratch;
1584 struct radeon_mman mman;
1585 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1586 wait_queue_head_t fence_queue;
1587 struct mutex ring_lock;
1588 struct radeon_ring ring[RADEON_NUM_RINGS];
1590 struct radeon_sa_manager ring_tmp_bo;
1591 struct radeon_irq irq;
1592 struct radeon_asic *asic;
1593 struct radeon_gem gem;
1594 struct radeon_pm pm;
1595 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1596 struct radeon_wb wb;
1597 struct radeon_dummy_page dummy_page;
1602 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1603 const struct firmware *me_fw; /* all family ME firmware */
1604 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1605 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1606 const struct firmware *mc_fw; /* NI MC firmware */
1607 const struct firmware *ce_fw; /* SI CE firmware */
1608 struct r600_blit r600_blit;
1609 struct r600_vram_scratch vram_scratch;
1610 int msi_enabled; /* msi enabled */
1611 struct r600_ih ih; /* r6/700 interrupt ring */
1613 struct work_struct hotplug_work;
1614 struct work_struct audio_work;
1615 int num_crtc; /* number of crtcs */
1616 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1618 struct r600_audio audio_status; /* audio stuff */
1619 struct notifier_block acpi_nb;
1620 /* only one userspace can use Hyperz features or CMASK at a time */
1621 struct drm_file *hyperz_filp;
1622 struct drm_file *cmask_filp;
1624 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1626 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1627 unsigned debugfs_count;
1628 /* virtual memory */
1629 struct radeon_vm_manager vm_manager;
1630 struct mutex gpu_clock_mutex;
1631 /* ACPI interface */
1632 struct radeon_atif atif;
1633 struct radeon_atcs atcs;
1636 int radeon_device_init(struct radeon_device *rdev,
1637 struct drm_device *ddev,
1638 struct pci_dev *pdev,
1640 void radeon_device_fini(struct radeon_device *rdev);
1641 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1643 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
1644 bool always_indirect);
1645 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
1646 bool always_indirect);
1647 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1648 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1653 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1656 * Registers read & write functions.
1658 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1659 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1660 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1661 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1662 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
1663 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
1664 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
1665 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
1666 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1667 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1668 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1669 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1670 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1671 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1672 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1673 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1674 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1675 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1676 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1677 #define WREG32_P(reg, val, mask) \
1679 uint32_t tmp_ = RREG32(reg); \
1681 tmp_ |= ((val) & ~(mask)); \
1682 WREG32(reg, tmp_); \
1684 #define WREG32_PLL_P(reg, val, mask) \
1686 uint32_t tmp_ = RREG32_PLL(reg); \
1688 tmp_ |= ((val) & ~(mask)); \
1689 WREG32_PLL(reg, tmp_); \
1691 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1692 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1693 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1696 * Indirect registers accessor
1698 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1702 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1703 r = RREG32(RADEON_PCIE_DATA);
1707 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1709 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1710 WREG32(RADEON_PCIE_DATA, (v));
1713 void r100_pll_errata_after_index(struct radeon_device *rdev);
1719 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1720 (rdev->pdev->device == 0x5969))
1721 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1722 (rdev->family == CHIP_RV200) || \
1723 (rdev->family == CHIP_RS100) || \
1724 (rdev->family == CHIP_RS200) || \
1725 (rdev->family == CHIP_RV250) || \
1726 (rdev->family == CHIP_RV280) || \
1727 (rdev->family == CHIP_RS300))
1728 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1729 (rdev->family == CHIP_RV350) || \
1730 (rdev->family == CHIP_R350) || \
1731 (rdev->family == CHIP_RV380) || \
1732 (rdev->family == CHIP_R420) || \
1733 (rdev->family == CHIP_R423) || \
1734 (rdev->family == CHIP_RV410) || \
1735 (rdev->family == CHIP_RS400) || \
1736 (rdev->family == CHIP_RS480))
1737 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1738 (rdev->ddev->pdev->device == 0x9443) || \
1739 (rdev->ddev->pdev->device == 0x944B) || \
1740 (rdev->ddev->pdev->device == 0x9506) || \
1741 (rdev->ddev->pdev->device == 0x9509) || \
1742 (rdev->ddev->pdev->device == 0x950F) || \
1743 (rdev->ddev->pdev->device == 0x689C) || \
1744 (rdev->ddev->pdev->device == 0x689D))
1745 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1746 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1747 (rdev->family == CHIP_RS690) || \
1748 (rdev->family == CHIP_RS740) || \
1749 (rdev->family >= CHIP_R600))
1750 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1751 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1752 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1753 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1754 (rdev->flags & RADEON_IS_IGP))
1755 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1756 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1757 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1758 (rdev->flags & RADEON_IS_IGP))
1763 #define RBIOS8(i) (rdev->bios[i])
1764 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1765 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1767 int radeon_combios_init(struct radeon_device *rdev);
1768 void radeon_combios_fini(struct radeon_device *rdev);
1769 int radeon_atombios_init(struct radeon_device *rdev);
1770 void radeon_atombios_fini(struct radeon_device *rdev);
1776 #if DRM_DEBUG_CODE == 0
1777 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1779 ring->ring[ring->wptr++] = v;
1780 ring->wptr &= ring->ptr_mask;
1782 ring->ring_free_dw--;
1785 /* With debugging this is just too big to inline */
1786 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1792 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1793 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1794 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1795 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1796 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1797 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1798 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1799 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1800 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1801 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
1802 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1803 #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags)))
1804 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1805 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1806 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1807 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1808 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1809 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1810 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
1811 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1812 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1813 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1814 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1815 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1816 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1817 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1818 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1819 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1820 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1821 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1822 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1823 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1824 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1825 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1826 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1827 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1828 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1829 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1830 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1831 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1832 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1833 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1834 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1835 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1836 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1837 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1838 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1839 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1840 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1841 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1842 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1843 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1844 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1845 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1846 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1847 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1848 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1850 /* Common functions */
1852 extern int radeon_gpu_reset(struct radeon_device *rdev);
1853 extern void radeon_agp_disable(struct radeon_device *rdev);
1854 extern int radeon_modeset_init(struct radeon_device *rdev);
1855 extern void radeon_modeset_fini(struct radeon_device *rdev);
1856 extern bool radeon_card_posted(struct radeon_device *rdev);
1857 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1858 extern void radeon_update_display_priority(struct radeon_device *rdev);
1859 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1860 extern void radeon_scratch_init(struct radeon_device *rdev);
1861 extern void radeon_wb_fini(struct radeon_device *rdev);
1862 extern int radeon_wb_init(struct radeon_device *rdev);
1863 extern void radeon_wb_disable(struct radeon_device *rdev);
1864 extern void radeon_surface_init(struct radeon_device *rdev);
1865 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1866 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1867 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1868 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1869 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1870 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1871 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1872 extern int radeon_resume_kms(struct drm_device *dev);
1873 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1874 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1879 int radeon_vm_manager_init(struct radeon_device *rdev);
1880 void radeon_vm_manager_fini(struct radeon_device *rdev);
1881 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1882 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1883 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
1884 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
1885 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
1886 struct radeon_vm *vm, int ring);
1887 void radeon_vm_fence(struct radeon_device *rdev,
1888 struct radeon_vm *vm,
1889 struct radeon_fence *fence);
1890 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
1891 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1892 struct radeon_vm *vm,
1893 struct radeon_bo *bo,
1894 struct ttm_mem_reg *mem);
1895 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1896 struct radeon_bo *bo);
1897 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
1898 struct radeon_bo *bo);
1899 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
1900 struct radeon_vm *vm,
1901 struct radeon_bo *bo);
1902 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
1903 struct radeon_bo_va *bo_va,
1906 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1907 struct radeon_bo_va *bo_va);
1910 void r600_audio_update_hdmi(struct work_struct *work);
1913 * R600 vram scratch functions
1915 int r600_vram_scratch_init(struct radeon_device *rdev);
1916 void r600_vram_scratch_fini(struct radeon_device *rdev);
1919 * r600 cs checking helper
1921 unsigned r600_mip_minify(unsigned size, unsigned level);
1922 bool r600_fmt_is_valid_color(u32 format);
1923 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1924 int r600_fmt_get_blocksize(u32 format);
1925 int r600_fmt_get_nblocksx(u32 format, u32 w);
1926 int r600_fmt_get_nblocksy(u32 format, u32 h);
1929 * r600 functions used by radeon_encoder.c
1931 struct radeon_hdmi_acr {
1945 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1947 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1948 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1949 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1950 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1951 u32 tiling_pipe_num,
1953 u32 total_max_rb_num,
1954 u32 enabled_rb_mask);
1957 * evergreen functions used by radeon_encoder.c
1960 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1962 extern int ni_init_microcode(struct radeon_device *rdev);
1963 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1966 #if defined(CONFIG_ACPI)
1967 extern int radeon_acpi_init(struct radeon_device *rdev);
1968 extern void radeon_acpi_fini(struct radeon_device *rdev);
1970 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1971 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1974 #include "radeon_object.h"