2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101 extern int radeon_runtime_pm;
102 extern int radeon_hard_reset;
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
108 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
110 /* RADEON_IB_POOL_SIZE must be a power of 2 */
111 #define RADEON_IB_POOL_SIZE 16
112 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
113 #define RADEONFB_CONN_LIMIT 4
114 #define RADEON_BIOS_NUM_SCRATCH 8
116 /* fence seq are set to this number when signaled */
117 #define RADEON_FENCE_SIGNALED_SEQ 0LL
119 /* internal ring indices */
120 /* r1xx+ has gfx CP ring */
121 #define RADEON_RING_TYPE_GFX_INDEX 0
123 /* cayman has 2 compute CP rings */
124 #define CAYMAN_RING_TYPE_CP1_INDEX 1
125 #define CAYMAN_RING_TYPE_CP2_INDEX 2
127 /* R600+ has an async dma ring */
128 #define R600_RING_TYPE_DMA_INDEX 3
129 /* cayman add a second async dma ring */
130 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
133 #define R600_RING_TYPE_UVD_INDEX 5
136 #define TN_RING_TYPE_VCE1_INDEX 6
137 #define TN_RING_TYPE_VCE2_INDEX 7
139 /* max number of rings */
140 #define RADEON_NUM_RINGS 8
142 /* number of hw syncs before falling back on blocking */
143 #define RADEON_NUM_SYNCS 4
145 /* hardcode those limit for now */
146 #define RADEON_VA_IB_OFFSET (1 << 20)
147 #define RADEON_VA_RESERVED_SIZE (8 << 20)
148 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
150 /* hard reset data */
151 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
154 #define RADEON_RESET_GFX (1 << 0)
155 #define RADEON_RESET_COMPUTE (1 << 1)
156 #define RADEON_RESET_DMA (1 << 2)
157 #define RADEON_RESET_CP (1 << 3)
158 #define RADEON_RESET_GRBM (1 << 4)
159 #define RADEON_RESET_DMA1 (1 << 5)
160 #define RADEON_RESET_RLC (1 << 6)
161 #define RADEON_RESET_SEM (1 << 7)
162 #define RADEON_RESET_IH (1 << 8)
163 #define RADEON_RESET_VMC (1 << 9)
164 #define RADEON_RESET_MC (1 << 10)
165 #define RADEON_RESET_DISPLAY (1 << 11)
168 #define RADEON_CG_BLOCK_GFX (1 << 0)
169 #define RADEON_CG_BLOCK_MC (1 << 1)
170 #define RADEON_CG_BLOCK_SDMA (1 << 2)
171 #define RADEON_CG_BLOCK_UVD (1 << 3)
172 #define RADEON_CG_BLOCK_VCE (1 << 4)
173 #define RADEON_CG_BLOCK_HDP (1 << 5)
174 #define RADEON_CG_BLOCK_BIF (1 << 6)
177 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
178 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
179 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
180 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
181 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
182 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
183 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
184 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
185 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
186 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
187 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
188 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
189 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
190 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
191 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
192 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
193 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
196 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
197 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
198 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
199 #define RADEON_PG_SUPPORT_UVD (1 << 3)
200 #define RADEON_PG_SUPPORT_VCE (1 << 4)
201 #define RADEON_PG_SUPPORT_CP (1 << 5)
202 #define RADEON_PG_SUPPORT_GDS (1 << 6)
203 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
204 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
205 #define RADEON_PG_SUPPORT_ACP (1 << 9)
206 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
208 /* max cursor sizes (in pixels) */
209 #define CURSOR_WIDTH 64
210 #define CURSOR_HEIGHT 64
212 #define CIK_CURSOR_WIDTH 128
213 #define CIK_CURSOR_HEIGHT 128
216 * Errata workarounds.
218 enum radeon_pll_errata {
219 CHIP_ERRATA_R300_CG = 0x00000001,
220 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
221 CHIP_ERRATA_PLL_DELAY = 0x00000004
225 struct radeon_device;
231 bool radeon_get_bios(struct radeon_device *rdev);
236 struct radeon_dummy_page {
240 int radeon_dummy_page_init(struct radeon_device *rdev);
241 void radeon_dummy_page_fini(struct radeon_device *rdev);
247 struct radeon_clock {
248 struct radeon_pll p1pll;
249 struct radeon_pll p2pll;
250 struct radeon_pll dcpll;
251 struct radeon_pll spll;
252 struct radeon_pll mpll;
254 uint32_t default_mclk;
255 uint32_t default_sclk;
256 uint32_t default_dispclk;
257 uint32_t current_dispclk;
259 uint32_t max_pixel_clock;
265 int radeon_pm_init(struct radeon_device *rdev);
266 int radeon_pm_late_init(struct radeon_device *rdev);
267 void radeon_pm_fini(struct radeon_device *rdev);
268 void radeon_pm_compute_clocks(struct radeon_device *rdev);
269 void radeon_pm_suspend(struct radeon_device *rdev);
270 void radeon_pm_resume(struct radeon_device *rdev);
271 void radeon_combios_get_power_modes(struct radeon_device *rdev);
272 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
273 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
277 struct atom_clock_dividers *dividers);
278 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
281 struct atom_mpll_param *mpll_param);
282 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
283 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
284 u16 voltage_level, u8 voltage_type,
285 u32 *gpio_value, u32 *gpio_mask);
286 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
287 u32 eng_clock, u32 mem_clock);
288 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
289 u8 voltage_type, u16 *voltage_step);
290 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
291 u16 voltage_id, u16 *voltage);
292 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
295 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
297 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
298 u16 *vddc, u16 *vddci,
299 u16 virtual_voltage_id,
300 u16 vbios_voltage_id);
301 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
305 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
306 u8 voltage_type, u16 *min_voltage);
307 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
308 u8 voltage_type, u16 *max_voltage);
309 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
310 u8 voltage_type, u8 voltage_mode,
311 struct atom_voltage_table *voltage_table);
312 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
313 u8 voltage_type, u8 voltage_mode);
314 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
316 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
318 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
320 struct atom_mc_reg_table *reg_table);
321 int radeon_atom_get_memory_info(struct radeon_device *rdev,
322 u8 module_index, struct atom_memory_info *mem_info);
323 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
324 bool gddr5, u8 module_index,
325 struct atom_memory_clock_range_table *mclk_range_table);
326 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
327 u16 voltage_id, u16 *voltage);
328 void rs690_pm_info(struct radeon_device *rdev);
329 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
330 unsigned *bankh, unsigned *mtaspect,
331 unsigned *tile_split);
336 struct radeon_fence_driver {
337 uint32_t scratch_reg;
339 volatile uint32_t *cpu_addr;
340 /* sync_seq is protected by ring emission lock */
341 uint64_t sync_seq[RADEON_NUM_RINGS];
346 struct radeon_fence {
347 struct radeon_device *rdev;
349 /* protected by radeon_fence.lock */
355 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
356 int radeon_fence_driver_init(struct radeon_device *rdev);
357 void radeon_fence_driver_fini(struct radeon_device *rdev);
358 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
359 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
360 void radeon_fence_process(struct radeon_device *rdev, int ring);
361 bool radeon_fence_signaled(struct radeon_fence *fence);
362 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
363 int radeon_fence_wait_locked(struct radeon_fence *fence);
364 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
365 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
366 int radeon_fence_wait_any(struct radeon_device *rdev,
367 struct radeon_fence **fences,
369 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
370 void radeon_fence_unref(struct radeon_fence **fence);
371 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
372 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
373 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
374 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
375 struct radeon_fence *b)
385 BUG_ON(a->ring != b->ring);
387 if (a->seq > b->seq) {
394 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
395 struct radeon_fence *b)
405 BUG_ON(a->ring != b->ring);
407 return a->seq < b->seq;
413 struct radeon_surface_reg {
414 struct radeon_bo *bo;
417 #define RADEON_GEM_MAX_SURFACES 8
423 struct ttm_bo_global_ref bo_global_ref;
424 struct drm_global_reference mem_global_ref;
425 struct ttm_bo_device bdev;
426 bool mem_global_referenced;
429 #if defined(CONFIG_DEBUG_FS)
435 /* bo virtual address in a specific vm */
436 struct radeon_bo_va {
437 /* protected by bo being reserved */
438 struct list_head bo_list;
445 /* protected by vm mutex */
446 struct list_head vm_list;
448 /* constant after initialization */
449 struct radeon_vm *vm;
450 struct radeon_bo *bo;
454 /* Protected by gem.mutex */
455 struct list_head list;
456 /* Protected by tbo.reserved */
458 struct ttm_placement placement;
459 struct ttm_buffer_object tbo;
460 struct ttm_bo_kmap_obj kmap;
466 /* list of all virtual address to which this bo
470 /* Constant after initialization */
471 struct radeon_device *rdev;
472 struct drm_gem_object gem_base;
474 struct ttm_bo_kmap_obj dma_buf_vmap;
477 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
479 struct radeon_bo_list {
480 struct ttm_validate_buffer tv;
481 struct radeon_bo *bo;
489 int radeon_gem_debugfs_init(struct radeon_device *rdev);
491 /* sub-allocation manager, it has to be protected by another lock.
492 * By conception this is an helper for other part of the driver
493 * like the indirect buffer or semaphore, which both have their
496 * Principe is simple, we keep a list of sub allocation in offset
497 * order (first entry has offset == 0, last entry has the highest
500 * When allocating new object we first check if there is room at
501 * the end total_size - (last_object_offset + last_object_size) >=
502 * alloc_size. If so we allocate new object there.
504 * When there is not enough room at the end, we start waiting for
505 * each sub object until we reach object_offset+object_size >=
506 * alloc_size, this object then become the sub object we return.
508 * Alignment can't be bigger than page size.
510 * Hole are not considered for allocation to keep things simple.
511 * Assumption is that there won't be hole (all object on same
514 struct radeon_sa_manager {
515 wait_queue_head_t wq;
516 struct radeon_bo *bo;
517 struct list_head *hole;
518 struct list_head flist[RADEON_NUM_RINGS];
519 struct list_head olist;
529 /* sub-allocation buffer */
530 struct radeon_sa_bo {
531 struct list_head olist;
532 struct list_head flist;
533 struct radeon_sa_manager *manager;
536 struct radeon_fence *fence;
544 struct list_head objects;
547 int radeon_gem_init(struct radeon_device *rdev);
548 void radeon_gem_fini(struct radeon_device *rdev);
549 int radeon_gem_object_create(struct radeon_device *rdev, int size,
550 int alignment, int initial_domain,
551 bool discardable, bool kernel,
552 struct drm_gem_object **obj);
554 int radeon_mode_dumb_create(struct drm_file *file_priv,
555 struct drm_device *dev,
556 struct drm_mode_create_dumb *args);
557 int radeon_mode_dumb_mmap(struct drm_file *filp,
558 struct drm_device *dev,
559 uint32_t handle, uint64_t *offset_p);
564 struct radeon_semaphore {
565 struct radeon_sa_bo *sa_bo;
568 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
571 int radeon_semaphore_create(struct radeon_device *rdev,
572 struct radeon_semaphore **semaphore);
573 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
574 struct radeon_semaphore *semaphore);
575 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
576 struct radeon_semaphore *semaphore);
577 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
578 struct radeon_fence *fence);
579 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
580 struct radeon_semaphore *semaphore,
582 void radeon_semaphore_free(struct radeon_device *rdev,
583 struct radeon_semaphore **semaphore,
584 struct radeon_fence *fence);
587 * GART structures, functions & helpers
591 #define RADEON_GPU_PAGE_SIZE 4096
592 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
593 #define RADEON_GPU_PAGE_SHIFT 12
594 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
597 dma_addr_t table_addr;
598 struct radeon_bo *robj;
600 unsigned num_gpu_pages;
601 unsigned num_cpu_pages;
604 dma_addr_t *pages_addr;
608 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
609 void radeon_gart_table_ram_free(struct radeon_device *rdev);
610 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
611 void radeon_gart_table_vram_free(struct radeon_device *rdev);
612 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
613 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
614 int radeon_gart_init(struct radeon_device *rdev);
615 void radeon_gart_fini(struct radeon_device *rdev);
616 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
618 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
619 int pages, struct page **pagelist,
620 dma_addr_t *dma_addr);
621 void radeon_gart_restore(struct radeon_device *rdev);
625 * GPU MC structures, functions & helpers
628 resource_size_t aper_size;
629 resource_size_t aper_base;
630 resource_size_t agp_base;
631 /* for some chips with <= 32MB we need to lie
632 * about vram size near mc fb location */
634 u64 visible_vram_size;
644 bool igp_sideport_enabled;
649 bool radeon_combios_sideport_present(struct radeon_device *rdev);
650 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
653 * GPU scratch registers structures, functions & helpers
655 struct radeon_scratch {
662 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
663 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
666 * GPU doorbell structures, functions & helpers
668 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
670 struct radeon_doorbell {
672 resource_size_t base;
673 resource_size_t size;
675 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
676 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
679 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
680 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
686 struct radeon_unpin_work {
687 struct work_struct work;
688 struct radeon_device *rdev;
690 struct radeon_fence *fence;
691 struct drm_pending_vblank_event *event;
692 struct radeon_bo *old_rbo;
696 struct r500_irq_stat_regs {
701 struct r600_irq_stat_regs {
711 struct evergreen_irq_stat_regs {
732 struct cik_irq_stat_regs {
742 union radeon_irq_stat_regs {
743 struct r500_irq_stat_regs r500;
744 struct r600_irq_stat_regs r600;
745 struct evergreen_irq_stat_regs evergreen;
746 struct cik_irq_stat_regs cik;
749 #define RADEON_MAX_HPD_PINS 6
750 #define RADEON_MAX_CRTCS 6
751 #define RADEON_MAX_AFMT_BLOCKS 7
756 atomic_t ring_int[RADEON_NUM_RINGS];
757 bool crtc_vblank_int[RADEON_MAX_CRTCS];
758 atomic_t pflip[RADEON_MAX_CRTCS];
759 wait_queue_head_t vblank_queue;
760 bool hpd[RADEON_MAX_HPD_PINS];
761 bool afmt[RADEON_MAX_AFMT_BLOCKS];
762 union radeon_irq_stat_regs stat_regs;
766 int radeon_irq_kms_init(struct radeon_device *rdev);
767 void radeon_irq_kms_fini(struct radeon_device *rdev);
768 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
769 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
770 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
771 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
772 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
773 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
774 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
775 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
782 struct radeon_sa_bo *sa_bo;
787 struct radeon_fence *fence;
788 struct radeon_vm *vm;
790 struct radeon_semaphore *semaphore;
794 struct radeon_bo *ring_obj;
795 volatile uint32_t *ring;
798 unsigned rptr_save_reg;
799 u64 next_rptr_gpu_addr;
800 volatile u32 *next_rptr_cpu_addr;
804 unsigned ring_free_dw;
806 unsigned long last_activity;
814 u64 last_semaphore_signal_addr;
815 u64 last_semaphore_wait_addr;
820 struct radeon_bo *mqd_obj;
826 struct radeon_bo *hpd_eop_obj;
827 u64 hpd_eop_gpu_addr;
837 /* maximum number of VMIDs */
838 #define RADEON_NUM_VM 16
840 /* defines number of bits in page table versus page directory,
841 * a page is 4KB so we have 12 bits offset, 9 bits in the page
842 * table and the remaining 19 bits are in the page directory */
843 #define RADEON_VM_BLOCK_SIZE 9
845 /* number of entries in page table */
846 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
848 /* PTBs (Page Table Blocks) need to be aligned to 32K */
849 #define RADEON_VM_PTB_ALIGN_SIZE 32768
850 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
851 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
853 #define R600_PTE_VALID (1 << 0)
854 #define R600_PTE_SYSTEM (1 << 1)
855 #define R600_PTE_SNOOPED (1 << 2)
856 #define R600_PTE_READABLE (1 << 5)
857 #define R600_PTE_WRITEABLE (1 << 6)
860 struct list_head list;
864 /* contains the page directory */
865 struct radeon_sa_bo *page_directory;
866 uint64_t pd_gpu_addr;
868 /* array of page tables, one for each page directory entry */
869 struct radeon_sa_bo **page_tables;
872 /* last fence for cs using this vm */
873 struct radeon_fence *fence;
874 /* last flush or NULL if we still need to flush */
875 struct radeon_fence *last_flush;
876 /* last use of vmid */
877 struct radeon_fence *last_id_use;
880 struct radeon_vm_manager {
882 struct list_head lru_vm;
883 struct radeon_fence *active[RADEON_NUM_VM];
884 struct radeon_sa_manager sa_manager;
886 /* number of VMIDs */
888 /* vram base address for page table entry */
889 u64 vram_base_offset;
895 * file private structure
897 struct radeon_fpriv {
905 struct radeon_bo *ring_obj;
906 volatile uint32_t *ring;
918 #include "clearstate_defs.h"
921 /* for power gating */
922 struct radeon_bo *save_restore_obj;
923 uint64_t save_restore_gpu_addr;
924 volatile uint32_t *sr_ptr;
927 /* for clear state */
928 struct radeon_bo *clear_state_obj;
929 uint64_t clear_state_gpu_addr;
930 volatile uint32_t *cs_ptr;
931 const struct cs_section_def *cs_data;
932 u32 clear_state_size;
934 struct radeon_bo *cp_table_obj;
935 uint64_t cp_table_gpu_addr;
936 volatile uint32_t *cp_table_ptr;
940 int radeon_ib_get(struct radeon_device *rdev, int ring,
941 struct radeon_ib *ib, struct radeon_vm *vm,
943 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
944 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
945 struct radeon_ib *const_ib);
946 int radeon_ib_pool_init(struct radeon_device *rdev);
947 void radeon_ib_pool_fini(struct radeon_device *rdev);
948 int radeon_ib_ring_tests(struct radeon_device *rdev);
949 /* Ring access between begin & end cannot sleep */
950 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
951 struct radeon_ring *ring);
952 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
953 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
954 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
955 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
956 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
957 void radeon_ring_undo(struct radeon_ring *ring);
958 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
959 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
960 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
961 void radeon_ring_lockup_update(struct radeon_ring *ring);
962 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
963 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
965 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
966 unsigned size, uint32_t *data);
967 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
968 unsigned rptr_offs, u32 nop);
969 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
973 void r600_dma_stop(struct radeon_device *rdev);
974 int r600_dma_resume(struct radeon_device *rdev);
975 void r600_dma_fini(struct radeon_device *rdev);
977 void cayman_dma_stop(struct radeon_device *rdev);
978 int cayman_dma_resume(struct radeon_device *rdev);
979 void cayman_dma_fini(struct radeon_device *rdev);
984 struct radeon_cs_reloc {
985 struct drm_gem_object *gobj;
986 struct radeon_bo *robj;
987 struct radeon_bo_list lobj;
992 struct radeon_cs_chunk {
996 void __user *user_ptr;
999 struct radeon_cs_parser {
1001 struct radeon_device *rdev;
1002 struct drm_file *filp;
1005 struct radeon_cs_chunk *chunks;
1006 uint64_t *chunks_array;
1011 struct radeon_cs_reloc *relocs;
1012 struct radeon_cs_reloc **relocs_ptr;
1013 struct list_head validated;
1014 unsigned dma_reloc_idx;
1015 /* indices of various chunks */
1017 int chunk_relocs_idx;
1018 int chunk_flags_idx;
1019 int chunk_const_ib_idx;
1020 struct radeon_ib ib;
1021 struct radeon_ib const_ib;
1028 struct ww_acquire_ctx ticket;
1031 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1033 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1036 return ibc->kdata[idx];
1037 return p->ib.ptr[idx];
1041 struct radeon_cs_packet {
1047 unsigned one_reg_wr;
1050 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1051 struct radeon_cs_packet *pkt,
1052 unsigned idx, unsigned reg);
1053 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1054 struct radeon_cs_packet *pkt);
1060 int radeon_agp_init(struct radeon_device *rdev);
1061 void radeon_agp_resume(struct radeon_device *rdev);
1062 void radeon_agp_suspend(struct radeon_device *rdev);
1063 void radeon_agp_fini(struct radeon_device *rdev);
1070 struct radeon_bo *wb_obj;
1071 volatile uint32_t *wb;
1077 #define RADEON_WB_SCRATCH_OFFSET 0
1078 #define RADEON_WB_RING0_NEXT_RPTR 256
1079 #define RADEON_WB_CP_RPTR_OFFSET 1024
1080 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1081 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1082 #define R600_WB_DMA_RPTR_OFFSET 1792
1083 #define R600_WB_IH_WPTR_OFFSET 2048
1084 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1085 #define R600_WB_EVENT_OFFSET 3072
1086 #define CIK_WB_CP1_WPTR_OFFSET 3328
1087 #define CIK_WB_CP2_WPTR_OFFSET 3584
1090 * struct radeon_pm - power management datas
1091 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1092 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1093 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1094 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1095 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1096 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1097 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1098 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1099 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1100 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1101 * @needed_bandwidth: current bandwidth needs
1103 * It keeps track of various data needed to take powermanagement decision.
1104 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1105 * Equation between gpu/memory clock and available bandwidth is hw dependent
1106 * (type of memory, bus size, efficiency, ...)
1109 enum radeon_pm_method {
1115 enum radeon_dynpm_state {
1116 DYNPM_STATE_DISABLED,
1117 DYNPM_STATE_MINIMUM,
1120 DYNPM_STATE_SUSPENDED,
1122 enum radeon_dynpm_action {
1124 DYNPM_ACTION_MINIMUM,
1125 DYNPM_ACTION_DOWNCLOCK,
1126 DYNPM_ACTION_UPCLOCK,
1127 DYNPM_ACTION_DEFAULT
1130 enum radeon_voltage_type {
1137 enum radeon_pm_state_type {
1138 /* not used for dpm */
1139 POWER_STATE_TYPE_DEFAULT,
1140 POWER_STATE_TYPE_POWERSAVE,
1141 /* user selectable states */
1142 POWER_STATE_TYPE_BATTERY,
1143 POWER_STATE_TYPE_BALANCED,
1144 POWER_STATE_TYPE_PERFORMANCE,
1145 /* internal states */
1146 POWER_STATE_TYPE_INTERNAL_UVD,
1147 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1148 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1149 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1150 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1151 POWER_STATE_TYPE_INTERNAL_BOOT,
1152 POWER_STATE_TYPE_INTERNAL_THERMAL,
1153 POWER_STATE_TYPE_INTERNAL_ACPI,
1154 POWER_STATE_TYPE_INTERNAL_ULV,
1155 POWER_STATE_TYPE_INTERNAL_3DPERF,
1158 enum radeon_pm_profile_type {
1166 #define PM_PROFILE_DEFAULT_IDX 0
1167 #define PM_PROFILE_LOW_SH_IDX 1
1168 #define PM_PROFILE_MID_SH_IDX 2
1169 #define PM_PROFILE_HIGH_SH_IDX 3
1170 #define PM_PROFILE_LOW_MH_IDX 4
1171 #define PM_PROFILE_MID_MH_IDX 5
1172 #define PM_PROFILE_HIGH_MH_IDX 6
1173 #define PM_PROFILE_MAX 7
1175 struct radeon_pm_profile {
1176 int dpms_off_ps_idx;
1178 int dpms_off_cm_idx;
1182 enum radeon_int_thermal_type {
1184 THERMAL_TYPE_EXTERNAL,
1185 THERMAL_TYPE_EXTERNAL_GPIO,
1188 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1189 THERMAL_TYPE_EVERGREEN,
1193 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1198 struct radeon_voltage {
1199 enum radeon_voltage_type type;
1201 struct radeon_gpio_rec gpio;
1202 u32 delay; /* delay in usec from voltage drop to sclk change */
1203 bool active_high; /* voltage drop is active when bit is high */
1205 u8 vddc_id; /* index into vddc voltage table */
1206 u8 vddci_id; /* index into vddci voltage table */
1210 /* evergreen+ vddci */
1214 /* clock mode flags */
1215 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1217 struct radeon_pm_clock_info {
1223 struct radeon_voltage voltage;
1224 /* standardized clock flags */
1229 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1231 struct radeon_power_state {
1232 enum radeon_pm_state_type type;
1233 struct radeon_pm_clock_info *clock_info;
1234 /* number of valid clock modes in this power state */
1235 int num_clock_modes;
1236 struct radeon_pm_clock_info *default_clock_mode;
1237 /* standardized state flags */
1239 u32 misc; /* vbios specific flags */
1240 u32 misc2; /* vbios specific flags */
1241 int pcie_lanes; /* pcie lanes */
1245 * Some modes are overclocked by very low value, accept them
1247 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1249 enum radeon_dpm_auto_throttle_src {
1250 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1251 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1254 enum radeon_dpm_event_src {
1255 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1256 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1257 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1258 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1259 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1262 enum radeon_vce_level {
1263 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1264 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1265 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1266 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1267 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1268 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1272 u32 caps; /* vbios flags */
1273 u32 class; /* vbios flags */
1274 u32 class2; /* vbios flags */
1282 enum radeon_vce_level vce_level;
1287 struct radeon_dpm_thermal {
1288 /* thermal interrupt work */
1289 struct work_struct work;
1290 /* low temperature threshold */
1292 /* high temperature threshold */
1294 /* was interrupt low to high or high to low */
1298 enum radeon_clk_action
1304 struct radeon_blacklist_clocks
1308 enum radeon_clk_action action;
1311 struct radeon_clock_and_voltage_limits {
1318 struct radeon_clock_array {
1323 struct radeon_clock_voltage_dependency_entry {
1328 struct radeon_clock_voltage_dependency_table {
1330 struct radeon_clock_voltage_dependency_entry *entries;
1333 union radeon_cac_leakage_entry {
1345 struct radeon_cac_leakage_table {
1347 union radeon_cac_leakage_entry *entries;
1350 struct radeon_phase_shedding_limits_entry {
1356 struct radeon_phase_shedding_limits_table {
1358 struct radeon_phase_shedding_limits_entry *entries;
1361 struct radeon_uvd_clock_voltage_dependency_entry {
1367 struct radeon_uvd_clock_voltage_dependency_table {
1369 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1372 struct radeon_vce_clock_voltage_dependency_entry {
1378 struct radeon_vce_clock_voltage_dependency_table {
1380 struct radeon_vce_clock_voltage_dependency_entry *entries;
1383 struct radeon_ppm_table {
1385 u16 cpu_core_number;
1387 u32 small_ac_platform_tdp;
1389 u32 small_ac_platform_tdc;
1396 struct radeon_cac_tdp_table {
1398 u16 configurable_tdp;
1400 u16 battery_power_limit;
1401 u16 small_power_limit;
1402 u16 low_cac_leakage;
1403 u16 high_cac_leakage;
1404 u16 maximum_power_delivery_limit;
1407 struct radeon_dpm_dynamic_state {
1408 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1409 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1410 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1411 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1412 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1413 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1414 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1415 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1416 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1417 struct radeon_clock_array valid_sclk_values;
1418 struct radeon_clock_array valid_mclk_values;
1419 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1420 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1421 u32 mclk_sclk_ratio;
1422 u32 sclk_mclk_delta;
1423 u16 vddc_vddci_delta;
1424 u16 min_vddc_for_pcie_gen2;
1425 struct radeon_cac_leakage_table cac_leakage_table;
1426 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1427 struct radeon_ppm_table *ppm_table;
1428 struct radeon_cac_tdp_table *cac_tdp_table;
1431 struct radeon_dpm_fan {
1441 bool ucode_fan_control;
1444 enum radeon_pcie_gen {
1445 RADEON_PCIE_GEN1 = 0,
1446 RADEON_PCIE_GEN2 = 1,
1447 RADEON_PCIE_GEN3 = 2,
1448 RADEON_PCIE_GEN_INVALID = 0xffff
1451 enum radeon_dpm_forced_level {
1452 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1453 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1454 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1458 struct radeon_ps *ps;
1459 /* number of valid power states */
1461 /* current power state that is active */
1462 struct radeon_ps *current_ps;
1463 /* requested power state */
1464 struct radeon_ps *requested_ps;
1465 /* boot up power state */
1466 struct radeon_ps *boot_ps;
1467 /* default uvd power state */
1468 struct radeon_ps *uvd_ps;
1469 enum radeon_pm_state_type state;
1470 enum radeon_pm_state_type user_state;
1472 u32 voltage_response_time;
1473 u32 backbias_response_time;
1475 u32 new_active_crtcs;
1476 int new_active_crtc_count;
1477 u32 current_active_crtcs;
1478 int current_active_crtc_count;
1479 struct radeon_dpm_dynamic_state dyn_state;
1480 struct radeon_dpm_fan fan;
1483 u32 near_tdp_limit_adjusted;
1484 u32 sq_ramping_threshold;
1488 u16 load_line_slope;
1491 /* special states active */
1492 bool thermal_active;
1495 /* thermal handling */
1496 struct radeon_dpm_thermal thermal;
1498 enum radeon_dpm_forced_level forced_level;
1499 /* track UVD streams */
1504 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1508 /* write locked while reprogramming mclk */
1509 struct rw_semaphore mclk_lock;
1511 int active_crtc_count;
1514 fixed20_12 max_bandwidth;
1515 fixed20_12 igp_sideport_mclk;
1516 fixed20_12 igp_system_mclk;
1517 fixed20_12 igp_ht_link_clk;
1518 fixed20_12 igp_ht_link_width;
1519 fixed20_12 k8_bandwidth;
1520 fixed20_12 sideport_bandwidth;
1521 fixed20_12 ht_bandwidth;
1522 fixed20_12 core_bandwidth;
1525 fixed20_12 needed_bandwidth;
1526 struct radeon_power_state *power_state;
1527 /* number of valid power states */
1528 int num_power_states;
1529 int current_power_state_index;
1530 int current_clock_mode_index;
1531 int requested_power_state_index;
1532 int requested_clock_mode_index;
1533 int default_power_state_index;
1542 struct radeon_i2c_chan *i2c_bus;
1543 /* selected pm method */
1544 enum radeon_pm_method pm_method;
1545 /* dynpm power management */
1546 struct delayed_work dynpm_idle_work;
1547 enum radeon_dynpm_state dynpm_state;
1548 enum radeon_dynpm_action dynpm_planned_action;
1549 unsigned long dynpm_action_timeout;
1550 bool dynpm_can_upclock;
1551 bool dynpm_can_downclock;
1552 /* profile-based power management */
1553 enum radeon_pm_profile_type profile;
1555 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1556 /* internal thermal controller on rv6xx+ */
1557 enum radeon_int_thermal_type int_thermal_type;
1558 struct device *int_hwmon_dev;
1561 struct radeon_dpm dpm;
1564 int radeon_pm_get_type_index(struct radeon_device *rdev,
1565 enum radeon_pm_state_type ps_type,
1570 #define RADEON_MAX_UVD_HANDLES 10
1571 #define RADEON_UVD_STACK_SIZE (1024*1024)
1572 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1575 struct radeon_bo *vcpu_bo;
1579 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1580 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1581 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1582 struct delayed_work idle_work;
1585 int radeon_uvd_init(struct radeon_device *rdev);
1586 void radeon_uvd_fini(struct radeon_device *rdev);
1587 int radeon_uvd_suspend(struct radeon_device *rdev);
1588 int radeon_uvd_resume(struct radeon_device *rdev);
1589 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1590 uint32_t handle, struct radeon_fence **fence);
1591 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1592 uint32_t handle, struct radeon_fence **fence);
1593 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1594 void radeon_uvd_free_handles(struct radeon_device *rdev,
1595 struct drm_file *filp);
1596 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1597 void radeon_uvd_note_usage(struct radeon_device *rdev);
1598 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1599 unsigned vclk, unsigned dclk,
1600 unsigned vco_min, unsigned vco_max,
1601 unsigned fb_factor, unsigned fb_mask,
1602 unsigned pd_min, unsigned pd_max,
1604 unsigned *optimal_fb_div,
1605 unsigned *optimal_vclk_div,
1606 unsigned *optimal_dclk_div);
1607 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1608 unsigned cg_upll_func_cntl);
1613 #define RADEON_MAX_VCE_HANDLES 16
1614 #define RADEON_VCE_STACK_SIZE (1024*1024)
1615 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1618 struct radeon_bo *vcpu_bo;
1621 unsigned fw_version;
1622 unsigned fb_version;
1623 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1624 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1627 int radeon_vce_init(struct radeon_device *rdev);
1628 void radeon_vce_fini(struct radeon_device *rdev);
1629 int radeon_vce_suspend(struct radeon_device *rdev);
1630 int radeon_vce_resume(struct radeon_device *rdev);
1631 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1632 uint32_t handle, struct radeon_fence **fence);
1633 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1634 uint32_t handle, struct radeon_fence **fence);
1635 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1636 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi);
1637 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1638 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1639 struct radeon_ring *ring,
1640 struct radeon_semaphore *semaphore,
1642 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1643 void radeon_vce_fence_emit(struct radeon_device *rdev,
1644 struct radeon_fence *fence);
1645 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1646 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1648 struct r600_audio_pin {
1651 int bits_per_sample;
1661 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1668 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1674 void radeon_test_moves(struct radeon_device *rdev);
1675 void radeon_test_ring_sync(struct radeon_device *rdev,
1676 struct radeon_ring *cpA,
1677 struct radeon_ring *cpB);
1678 void radeon_test_syncing(struct radeon_device *rdev);
1684 struct radeon_debugfs {
1685 struct drm_info_list *files;
1689 int radeon_debugfs_add_files(struct radeon_device *rdev,
1690 struct drm_info_list *files,
1692 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1695 * ASIC ring specific functions.
1697 struct radeon_asic_ring {
1698 /* ring read/write ptr handling */
1699 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1700 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1701 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1703 /* validating and patching of IBs */
1704 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1705 int (*cs_parse)(struct radeon_cs_parser *p);
1707 /* command emmit functions */
1708 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1709 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1710 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1711 struct radeon_semaphore *semaphore, bool emit_wait);
1712 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1714 /* testing functions */
1715 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1716 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1717 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1720 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1724 * ASIC specific functions.
1726 struct radeon_asic {
1727 int (*init)(struct radeon_device *rdev);
1728 void (*fini)(struct radeon_device *rdev);
1729 int (*resume)(struct radeon_device *rdev);
1730 int (*suspend)(struct radeon_device *rdev);
1731 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1732 int (*asic_reset)(struct radeon_device *rdev);
1733 /* ioctl hw specific callback. Some hw might want to perform special
1734 * operation on specific ioctl. For instance on wait idle some hw
1735 * might want to perform and HDP flush through MMIO as it seems that
1736 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1739 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1740 /* check if 3D engine is idle */
1741 bool (*gui_idle)(struct radeon_device *rdev);
1742 /* wait for mc_idle */
1743 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1744 /* get the reference clock */
1745 u32 (*get_xclk)(struct radeon_device *rdev);
1746 /* get the gpu clock counter */
1747 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1750 void (*tlb_flush)(struct radeon_device *rdev);
1751 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1754 int (*init)(struct radeon_device *rdev);
1755 void (*fini)(struct radeon_device *rdev);
1756 void (*set_page)(struct radeon_device *rdev,
1757 struct radeon_ib *ib,
1759 uint64_t addr, unsigned count,
1760 uint32_t incr, uint32_t flags);
1762 /* ring specific callbacks */
1763 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1766 int (*set)(struct radeon_device *rdev);
1767 int (*process)(struct radeon_device *rdev);
1771 /* display watermarks */
1772 void (*bandwidth_update)(struct radeon_device *rdev);
1773 /* get frame count */
1774 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1775 /* wait for vblank */
1776 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1777 /* set backlight level */
1778 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1779 /* get backlight level */
1780 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1781 /* audio callbacks */
1782 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1783 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1785 /* copy functions for bo handling */
1787 int (*blit)(struct radeon_device *rdev,
1788 uint64_t src_offset,
1789 uint64_t dst_offset,
1790 unsigned num_gpu_pages,
1791 struct radeon_fence **fence);
1792 u32 blit_ring_index;
1793 int (*dma)(struct radeon_device *rdev,
1794 uint64_t src_offset,
1795 uint64_t dst_offset,
1796 unsigned num_gpu_pages,
1797 struct radeon_fence **fence);
1799 /* method used for bo copy */
1800 int (*copy)(struct radeon_device *rdev,
1801 uint64_t src_offset,
1802 uint64_t dst_offset,
1803 unsigned num_gpu_pages,
1804 struct radeon_fence **fence);
1805 /* ring used for bo copies */
1806 u32 copy_ring_index;
1810 int (*set_reg)(struct radeon_device *rdev, int reg,
1811 uint32_t tiling_flags, uint32_t pitch,
1812 uint32_t offset, uint32_t obj_size);
1813 void (*clear_reg)(struct radeon_device *rdev, int reg);
1815 /* hotplug detect */
1817 void (*init)(struct radeon_device *rdev);
1818 void (*fini)(struct radeon_device *rdev);
1819 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1820 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1822 /* static power management */
1824 void (*misc)(struct radeon_device *rdev);
1825 void (*prepare)(struct radeon_device *rdev);
1826 void (*finish)(struct radeon_device *rdev);
1827 void (*init_profile)(struct radeon_device *rdev);
1828 void (*get_dynpm_state)(struct radeon_device *rdev);
1829 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1830 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1831 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1832 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1833 int (*get_pcie_lanes)(struct radeon_device *rdev);
1834 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1835 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1836 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1837 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1838 int (*get_temperature)(struct radeon_device *rdev);
1840 /* dynamic power management */
1842 int (*init)(struct radeon_device *rdev);
1843 void (*setup_asic)(struct radeon_device *rdev);
1844 int (*enable)(struct radeon_device *rdev);
1845 int (*late_enable)(struct radeon_device *rdev);
1846 void (*disable)(struct radeon_device *rdev);
1847 int (*pre_set_power_state)(struct radeon_device *rdev);
1848 int (*set_power_state)(struct radeon_device *rdev);
1849 void (*post_set_power_state)(struct radeon_device *rdev);
1850 void (*display_configuration_changed)(struct radeon_device *rdev);
1851 void (*fini)(struct radeon_device *rdev);
1852 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1853 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1854 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1855 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1856 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1857 bool (*vblank_too_short)(struct radeon_device *rdev);
1858 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1859 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1863 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1864 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1865 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1873 const unsigned *reg_safe_bm;
1874 unsigned reg_safe_bm_size;
1879 const unsigned *reg_safe_bm;
1880 unsigned reg_safe_bm_size;
1887 unsigned max_tile_pipes;
1889 unsigned max_backends;
1891 unsigned max_threads;
1892 unsigned max_stack_entries;
1893 unsigned max_hw_contexts;
1894 unsigned max_gs_threads;
1895 unsigned sx_max_export_size;
1896 unsigned sx_max_export_pos_size;
1897 unsigned sx_max_export_smx_size;
1898 unsigned sq_num_cf_insts;
1899 unsigned tiling_nbanks;
1900 unsigned tiling_npipes;
1901 unsigned tiling_group_size;
1902 unsigned tile_config;
1903 unsigned backend_map;
1908 unsigned max_tile_pipes;
1910 unsigned max_backends;
1912 unsigned max_threads;
1913 unsigned max_stack_entries;
1914 unsigned max_hw_contexts;
1915 unsigned max_gs_threads;
1916 unsigned sx_max_export_size;
1917 unsigned sx_max_export_pos_size;
1918 unsigned sx_max_export_smx_size;
1919 unsigned sq_num_cf_insts;
1920 unsigned sx_num_of_sets;
1921 unsigned sc_prim_fifo_size;
1922 unsigned sc_hiz_tile_fifo_size;
1923 unsigned sc_earlyz_tile_fifo_fize;
1924 unsigned tiling_nbanks;
1925 unsigned tiling_npipes;
1926 unsigned tiling_group_size;
1927 unsigned tile_config;
1928 unsigned backend_map;
1931 struct evergreen_asic {
1934 unsigned max_tile_pipes;
1936 unsigned max_backends;
1938 unsigned max_threads;
1939 unsigned max_stack_entries;
1940 unsigned max_hw_contexts;
1941 unsigned max_gs_threads;
1942 unsigned sx_max_export_size;
1943 unsigned sx_max_export_pos_size;
1944 unsigned sx_max_export_smx_size;
1945 unsigned sq_num_cf_insts;
1946 unsigned sx_num_of_sets;
1947 unsigned sc_prim_fifo_size;
1948 unsigned sc_hiz_tile_fifo_size;
1949 unsigned sc_earlyz_tile_fifo_size;
1950 unsigned tiling_nbanks;
1951 unsigned tiling_npipes;
1952 unsigned tiling_group_size;
1953 unsigned tile_config;
1954 unsigned backend_map;
1957 struct cayman_asic {
1958 unsigned max_shader_engines;
1959 unsigned max_pipes_per_simd;
1960 unsigned max_tile_pipes;
1961 unsigned max_simds_per_se;
1962 unsigned max_backends_per_se;
1963 unsigned max_texture_channel_caches;
1965 unsigned max_threads;
1966 unsigned max_gs_threads;
1967 unsigned max_stack_entries;
1968 unsigned sx_num_of_sets;
1969 unsigned sx_max_export_size;
1970 unsigned sx_max_export_pos_size;
1971 unsigned sx_max_export_smx_size;
1972 unsigned max_hw_contexts;
1973 unsigned sq_num_cf_insts;
1974 unsigned sc_prim_fifo_size;
1975 unsigned sc_hiz_tile_fifo_size;
1976 unsigned sc_earlyz_tile_fifo_size;
1978 unsigned num_shader_engines;
1979 unsigned num_shader_pipes_per_simd;
1980 unsigned num_tile_pipes;
1981 unsigned num_simds_per_se;
1982 unsigned num_backends_per_se;
1983 unsigned backend_disable_mask_per_asic;
1984 unsigned backend_map;
1985 unsigned num_texture_channel_caches;
1986 unsigned mem_max_burst_length_bytes;
1987 unsigned mem_row_size_in_kb;
1988 unsigned shader_engine_tile_size;
1990 unsigned multi_gpu_tile_size;
1992 unsigned tile_config;
1996 unsigned max_shader_engines;
1997 unsigned max_tile_pipes;
1998 unsigned max_cu_per_sh;
1999 unsigned max_sh_per_se;
2000 unsigned max_backends_per_se;
2001 unsigned max_texture_channel_caches;
2003 unsigned max_gs_threads;
2004 unsigned max_hw_contexts;
2005 unsigned sc_prim_fifo_size_frontend;
2006 unsigned sc_prim_fifo_size_backend;
2007 unsigned sc_hiz_tile_fifo_size;
2008 unsigned sc_earlyz_tile_fifo_size;
2010 unsigned num_tile_pipes;
2011 unsigned backend_enable_mask;
2012 unsigned backend_disable_mask_per_asic;
2013 unsigned backend_map;
2014 unsigned num_texture_channel_caches;
2015 unsigned mem_max_burst_length_bytes;
2016 unsigned mem_row_size_in_kb;
2017 unsigned shader_engine_tile_size;
2019 unsigned multi_gpu_tile_size;
2021 unsigned tile_config;
2022 uint32_t tile_mode_array[32];
2026 unsigned max_shader_engines;
2027 unsigned max_tile_pipes;
2028 unsigned max_cu_per_sh;
2029 unsigned max_sh_per_se;
2030 unsigned max_backends_per_se;
2031 unsigned max_texture_channel_caches;
2033 unsigned max_gs_threads;
2034 unsigned max_hw_contexts;
2035 unsigned sc_prim_fifo_size_frontend;
2036 unsigned sc_prim_fifo_size_backend;
2037 unsigned sc_hiz_tile_fifo_size;
2038 unsigned sc_earlyz_tile_fifo_size;
2040 unsigned num_tile_pipes;
2041 unsigned backend_enable_mask;
2042 unsigned backend_disable_mask_per_asic;
2043 unsigned backend_map;
2044 unsigned num_texture_channel_caches;
2045 unsigned mem_max_burst_length_bytes;
2046 unsigned mem_row_size_in_kb;
2047 unsigned shader_engine_tile_size;
2049 unsigned multi_gpu_tile_size;
2051 unsigned tile_config;
2052 uint32_t tile_mode_array[32];
2053 uint32_t macrotile_mode_array[16];
2056 union radeon_asic_config {
2057 struct r300_asic r300;
2058 struct r100_asic r100;
2059 struct r600_asic r600;
2060 struct rv770_asic rv770;
2061 struct evergreen_asic evergreen;
2062 struct cayman_asic cayman;
2064 struct cik_asic cik;
2068 * asic initizalization from radeon_asic.c
2070 void radeon_agp_disable(struct radeon_device *rdev);
2071 int radeon_asic_init(struct radeon_device *rdev);
2077 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2078 struct drm_file *filp);
2079 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2080 struct drm_file *filp);
2081 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2082 struct drm_file *file_priv);
2083 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2084 struct drm_file *file_priv);
2085 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2086 struct drm_file *file_priv);
2087 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2088 struct drm_file *file_priv);
2089 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2090 struct drm_file *filp);
2091 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2092 struct drm_file *filp);
2093 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2094 struct drm_file *filp);
2095 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2096 struct drm_file *filp);
2097 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2098 struct drm_file *filp);
2099 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2100 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2101 struct drm_file *filp);
2102 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2103 struct drm_file *filp);
2105 /* VRAM scratch page for HDP bug, default vram page */
2106 struct r600_vram_scratch {
2107 struct radeon_bo *robj;
2108 volatile uint32_t *ptr;
2115 struct radeon_atif_notification_cfg {
2120 struct radeon_atif_notifications {
2121 bool display_switch;
2122 bool expansion_mode_change;
2124 bool forced_power_state;
2125 bool system_power_state;
2126 bool display_conf_change;
2128 bool brightness_change;
2129 bool dgpu_display_event;
2132 struct radeon_atif_functions {
2134 bool sbios_requests;
2135 bool select_active_disp;
2137 bool get_tv_standard;
2138 bool set_tv_standard;
2139 bool get_panel_expansion_mode;
2140 bool set_panel_expansion_mode;
2141 bool temperature_change;
2142 bool graphics_device_types;
2145 struct radeon_atif {
2146 struct radeon_atif_notifications notifications;
2147 struct radeon_atif_functions functions;
2148 struct radeon_atif_notification_cfg notification_cfg;
2149 struct radeon_encoder *encoder_for_bl;
2152 struct radeon_atcs_functions {
2156 bool pcie_bus_width;
2159 struct radeon_atcs {
2160 struct radeon_atcs_functions functions;
2164 * Core structure, functions and helpers.
2166 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2167 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2169 struct radeon_device {
2171 struct drm_device *ddev;
2172 struct pci_dev *pdev;
2173 struct rw_semaphore exclusive_lock;
2175 union radeon_asic_config config;
2176 enum radeon_family family;
2177 unsigned long flags;
2179 enum radeon_pll_errata pll_errata;
2186 uint16_t bios_header_start;
2187 struct radeon_bo *stollen_vga_memory;
2189 resource_size_t rmmio_base;
2190 resource_size_t rmmio_size;
2191 /* protects concurrent MM_INDEX/DATA based register access */
2192 spinlock_t mmio_idx_lock;
2193 /* protects concurrent SMC based register access */
2194 spinlock_t smc_idx_lock;
2195 /* protects concurrent PLL register access */
2196 spinlock_t pll_idx_lock;
2197 /* protects concurrent MC register access */
2198 spinlock_t mc_idx_lock;
2199 /* protects concurrent PCIE register access */
2200 spinlock_t pcie_idx_lock;
2201 /* protects concurrent PCIE_PORT register access */
2202 spinlock_t pciep_idx_lock;
2203 /* protects concurrent PIF register access */
2204 spinlock_t pif_idx_lock;
2205 /* protects concurrent CG register access */
2206 spinlock_t cg_idx_lock;
2207 /* protects concurrent UVD register access */
2208 spinlock_t uvd_idx_lock;
2209 /* protects concurrent RCU register access */
2210 spinlock_t rcu_idx_lock;
2211 /* protects concurrent DIDT register access */
2212 spinlock_t didt_idx_lock;
2213 /* protects concurrent ENDPOINT (audio) register access */
2214 spinlock_t end_idx_lock;
2215 void __iomem *rmmio;
2216 radeon_rreg_t mc_rreg;
2217 radeon_wreg_t mc_wreg;
2218 radeon_rreg_t pll_rreg;
2219 radeon_wreg_t pll_wreg;
2220 uint32_t pcie_reg_mask;
2221 radeon_rreg_t pciep_rreg;
2222 radeon_wreg_t pciep_wreg;
2224 void __iomem *rio_mem;
2225 resource_size_t rio_mem_size;
2226 struct radeon_clock clock;
2227 struct radeon_mc mc;
2228 struct radeon_gart gart;
2229 struct radeon_mode_info mode_info;
2230 struct radeon_scratch scratch;
2231 struct radeon_doorbell doorbell;
2232 struct radeon_mman mman;
2233 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2234 wait_queue_head_t fence_queue;
2235 struct mutex ring_lock;
2236 struct radeon_ring ring[RADEON_NUM_RINGS];
2238 struct radeon_sa_manager ring_tmp_bo;
2239 struct radeon_irq irq;
2240 struct radeon_asic *asic;
2241 struct radeon_gem gem;
2242 struct radeon_pm pm;
2243 struct radeon_uvd uvd;
2244 struct radeon_vce vce;
2245 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2246 struct radeon_wb wb;
2247 struct radeon_dummy_page dummy_page;
2252 bool fastfb_working; /* IGP feature*/
2254 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2255 const struct firmware *me_fw; /* all family ME firmware */
2256 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2257 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2258 const struct firmware *mc_fw; /* NI MC firmware */
2259 const struct firmware *ce_fw; /* SI CE firmware */
2260 const struct firmware *mec_fw; /* CIK MEC firmware */
2261 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2262 const struct firmware *smc_fw; /* SMC firmware */
2263 const struct firmware *uvd_fw; /* UVD firmware */
2264 const struct firmware *vce_fw; /* VCE firmware */
2265 struct r600_vram_scratch vram_scratch;
2266 int msi_enabled; /* msi enabled */
2267 struct r600_ih ih; /* r6/700 interrupt ring */
2268 struct radeon_rlc rlc;
2269 struct radeon_mec mec;
2270 struct work_struct hotplug_work;
2271 struct work_struct audio_work;
2272 struct work_struct reset_work;
2273 int num_crtc; /* number of crtcs */
2274 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2276 struct r600_audio audio; /* audio stuff */
2277 struct notifier_block acpi_nb;
2278 /* only one userspace can use Hyperz features or CMASK at a time */
2279 struct drm_file *hyperz_filp;
2280 struct drm_file *cmask_filp;
2282 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2284 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2285 unsigned debugfs_count;
2286 /* virtual memory */
2287 struct radeon_vm_manager vm_manager;
2288 struct mutex gpu_clock_mutex;
2289 /* ACPI interface */
2290 struct radeon_atif atif;
2291 struct radeon_atcs atcs;
2292 /* srbm instance registers */
2293 struct mutex srbm_mutex;
2294 /* clock, powergating flags */
2298 struct dev_pm_domain vga_pm_domain;
2299 bool have_disp_power_ref;
2302 int radeon_device_init(struct radeon_device *rdev,
2303 struct drm_device *ddev,
2304 struct pci_dev *pdev,
2306 void radeon_device_fini(struct radeon_device *rdev);
2307 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2309 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2310 bool always_indirect);
2311 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2312 bool always_indirect);
2313 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2314 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2316 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2317 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2322 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2325 * Registers read & write functions.
2327 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2328 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2329 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2330 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2331 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2332 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2333 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2334 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2335 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2336 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2337 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2338 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2339 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2340 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2341 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2342 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2343 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2344 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2345 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2346 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2347 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2348 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2349 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2350 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2351 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2352 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2353 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2354 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2355 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2356 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2357 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2358 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2359 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2360 #define WREG32_P(reg, val, mask) \
2362 uint32_t tmp_ = RREG32(reg); \
2364 tmp_ |= ((val) & ~(mask)); \
2365 WREG32(reg, tmp_); \
2367 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2368 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2369 #define WREG32_PLL_P(reg, val, mask) \
2371 uint32_t tmp_ = RREG32_PLL(reg); \
2373 tmp_ |= ((val) & ~(mask)); \
2374 WREG32_PLL(reg, tmp_); \
2376 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2377 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2378 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2380 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2381 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2384 * Indirect registers accessor
2386 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2388 unsigned long flags;
2391 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2392 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2393 r = RREG32(RADEON_PCIE_DATA);
2394 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2398 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2400 unsigned long flags;
2402 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2403 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2404 WREG32(RADEON_PCIE_DATA, (v));
2405 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2408 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2410 unsigned long flags;
2413 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2414 WREG32(TN_SMC_IND_INDEX_0, (reg));
2415 r = RREG32(TN_SMC_IND_DATA_0);
2416 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2420 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2422 unsigned long flags;
2424 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2425 WREG32(TN_SMC_IND_INDEX_0, (reg));
2426 WREG32(TN_SMC_IND_DATA_0, (v));
2427 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2430 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2432 unsigned long flags;
2435 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2436 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2437 r = RREG32(R600_RCU_DATA);
2438 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2442 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2444 unsigned long flags;
2446 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2447 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2448 WREG32(R600_RCU_DATA, (v));
2449 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2452 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2454 unsigned long flags;
2457 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2458 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2459 r = RREG32(EVERGREEN_CG_IND_DATA);
2460 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2464 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2466 unsigned long flags;
2468 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2469 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2470 WREG32(EVERGREEN_CG_IND_DATA, (v));
2471 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2474 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2476 unsigned long flags;
2479 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2480 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2481 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2482 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2486 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2488 unsigned long flags;
2490 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2491 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2492 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2493 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2496 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2498 unsigned long flags;
2501 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2502 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2503 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2504 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2508 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2510 unsigned long flags;
2512 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2513 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2514 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2515 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2518 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2520 unsigned long flags;
2523 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2524 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2525 r = RREG32(R600_UVD_CTX_DATA);
2526 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2530 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2532 unsigned long flags;
2534 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2535 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2536 WREG32(R600_UVD_CTX_DATA, (v));
2537 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2541 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2543 unsigned long flags;
2546 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2547 WREG32(CIK_DIDT_IND_INDEX, (reg));
2548 r = RREG32(CIK_DIDT_IND_DATA);
2549 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2553 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2555 unsigned long flags;
2557 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2558 WREG32(CIK_DIDT_IND_INDEX, (reg));
2559 WREG32(CIK_DIDT_IND_DATA, (v));
2560 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2563 void r100_pll_errata_after_index(struct radeon_device *rdev);
2569 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2570 (rdev->pdev->device == 0x5969))
2571 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2572 (rdev->family == CHIP_RV200) || \
2573 (rdev->family == CHIP_RS100) || \
2574 (rdev->family == CHIP_RS200) || \
2575 (rdev->family == CHIP_RV250) || \
2576 (rdev->family == CHIP_RV280) || \
2577 (rdev->family == CHIP_RS300))
2578 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2579 (rdev->family == CHIP_RV350) || \
2580 (rdev->family == CHIP_R350) || \
2581 (rdev->family == CHIP_RV380) || \
2582 (rdev->family == CHIP_R420) || \
2583 (rdev->family == CHIP_R423) || \
2584 (rdev->family == CHIP_RV410) || \
2585 (rdev->family == CHIP_RS400) || \
2586 (rdev->family == CHIP_RS480))
2587 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2588 (rdev->ddev->pdev->device == 0x9443) || \
2589 (rdev->ddev->pdev->device == 0x944B) || \
2590 (rdev->ddev->pdev->device == 0x9506) || \
2591 (rdev->ddev->pdev->device == 0x9509) || \
2592 (rdev->ddev->pdev->device == 0x950F) || \
2593 (rdev->ddev->pdev->device == 0x689C) || \
2594 (rdev->ddev->pdev->device == 0x689D))
2595 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2596 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2597 (rdev->family == CHIP_RS690) || \
2598 (rdev->family == CHIP_RS740) || \
2599 (rdev->family >= CHIP_R600))
2600 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2601 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2602 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2603 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2604 (rdev->flags & RADEON_IS_IGP))
2605 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2606 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2607 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2608 (rdev->flags & RADEON_IS_IGP))
2609 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2610 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2611 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2613 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2614 (rdev->ddev->pdev->device == 0x6850) || \
2615 (rdev->ddev->pdev->device == 0x6858) || \
2616 (rdev->ddev->pdev->device == 0x6859) || \
2617 (rdev->ddev->pdev->device == 0x6840) || \
2618 (rdev->ddev->pdev->device == 0x6841) || \
2619 (rdev->ddev->pdev->device == 0x6842) || \
2620 (rdev->ddev->pdev->device == 0x6843))
2625 #define RBIOS8(i) (rdev->bios[i])
2626 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2627 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2629 int radeon_combios_init(struct radeon_device *rdev);
2630 void radeon_combios_fini(struct radeon_device *rdev);
2631 int radeon_atombios_init(struct radeon_device *rdev);
2632 void radeon_atombios_fini(struct radeon_device *rdev);
2638 #if DRM_DEBUG_CODE == 0
2639 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2641 ring->ring[ring->wptr++] = v;
2642 ring->wptr &= ring->ptr_mask;
2644 ring->ring_free_dw--;
2647 /* With debugging this is just too big to inline */
2648 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2654 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2655 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2656 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2657 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2658 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2659 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2660 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2661 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2662 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2663 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2664 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2665 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2666 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2667 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2668 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2669 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2670 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2671 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2672 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2673 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2674 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2675 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2676 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2677 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2678 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2679 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2680 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2681 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2682 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2683 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2684 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2685 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2686 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2687 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2688 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2689 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2690 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2691 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2692 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2693 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2694 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2695 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2696 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2697 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2698 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2699 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2700 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2701 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2702 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2703 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2704 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2705 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2706 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2707 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2708 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2709 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2710 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2711 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2712 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2713 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2714 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2715 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2716 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2717 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2718 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2719 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2720 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2721 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2722 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2723 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2724 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2725 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2726 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2727 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2728 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2729 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2730 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2731 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2732 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2733 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2734 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2735 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2736 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2737 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2738 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2740 /* Common functions */
2742 extern int radeon_gpu_reset(struct radeon_device *rdev);
2743 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2744 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2745 extern void radeon_agp_disable(struct radeon_device *rdev);
2746 extern int radeon_modeset_init(struct radeon_device *rdev);
2747 extern void radeon_modeset_fini(struct radeon_device *rdev);
2748 extern bool radeon_card_posted(struct radeon_device *rdev);
2749 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2750 extern void radeon_update_display_priority(struct radeon_device *rdev);
2751 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2752 extern void radeon_scratch_init(struct radeon_device *rdev);
2753 extern void radeon_wb_fini(struct radeon_device *rdev);
2754 extern int radeon_wb_init(struct radeon_device *rdev);
2755 extern void radeon_wb_disable(struct radeon_device *rdev);
2756 extern void radeon_surface_init(struct radeon_device *rdev);
2757 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2758 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2759 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2760 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2761 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2762 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2763 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2764 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2765 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2766 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2767 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2768 const u32 *registers,
2769 const u32 array_size);
2774 int radeon_vm_manager_init(struct radeon_device *rdev);
2775 void radeon_vm_manager_fini(struct radeon_device *rdev);
2776 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2777 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2778 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2779 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2780 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2781 struct radeon_vm *vm, int ring);
2782 void radeon_vm_fence(struct radeon_device *rdev,
2783 struct radeon_vm *vm,
2784 struct radeon_fence *fence);
2785 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2786 int radeon_vm_bo_update(struct radeon_device *rdev,
2787 struct radeon_vm *vm,
2788 struct radeon_bo *bo,
2789 struct ttm_mem_reg *mem);
2790 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2791 struct radeon_bo *bo);
2792 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2793 struct radeon_bo *bo);
2794 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2795 struct radeon_vm *vm,
2796 struct radeon_bo *bo);
2797 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2798 struct radeon_bo_va *bo_va,
2801 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2802 struct radeon_bo_va *bo_va);
2805 void r600_audio_update_hdmi(struct work_struct *work);
2806 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2807 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2810 * R600 vram scratch functions
2812 int r600_vram_scratch_init(struct radeon_device *rdev);
2813 void r600_vram_scratch_fini(struct radeon_device *rdev);
2816 * r600 cs checking helper
2818 unsigned r600_mip_minify(unsigned size, unsigned level);
2819 bool r600_fmt_is_valid_color(u32 format);
2820 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2821 int r600_fmt_get_blocksize(u32 format);
2822 int r600_fmt_get_nblocksx(u32 format, u32 w);
2823 int r600_fmt_get_nblocksy(u32 format, u32 h);
2826 * r600 functions used by radeon_encoder.c
2828 struct radeon_hdmi_acr {
2842 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2844 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2845 u32 tiling_pipe_num,
2847 u32 total_max_rb_num,
2848 u32 enabled_rb_mask);
2851 * evergreen functions used by radeon_encoder.c
2854 extern int ni_init_microcode(struct radeon_device *rdev);
2855 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2858 #if defined(CONFIG_ACPI)
2859 extern int radeon_acpi_init(struct radeon_device *rdev);
2860 extern void radeon_acpi_fini(struct radeon_device *rdev);
2861 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2862 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2863 u8 perf_req, bool advertise);
2864 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2866 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2867 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2870 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2871 struct radeon_cs_packet *pkt,
2873 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2874 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2875 struct radeon_cs_packet *pkt);
2876 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2877 struct radeon_cs_reloc **cs_reloc,
2879 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2880 uint32_t *vline_start_end,
2881 uint32_t *vline_status);
2883 #include "radeon_object.h"