2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
70 #include <ttm/ttm_bo_api.h>
71 #include <ttm/ttm_bo_driver.h>
72 #include <ttm/ttm_placement.h>
73 #include <ttm/ttm_module.h>
74 #include <ttm/ttm_execbuf_util.h>
76 #include "radeon_family.h"
77 #include "radeon_mode.h"
78 #include "radeon_reg.h"
83 extern int radeon_no_wb;
84 extern int radeon_modeset;
85 extern int radeon_dynclks;
86 extern int radeon_r4xx_atom;
87 extern int radeon_agpmode;
88 extern int radeon_vram_limit;
89 extern int radeon_gart_size;
90 extern int radeon_benchmarking;
91 extern int radeon_testing;
92 extern int radeon_connector_table;
94 extern int radeon_audio;
95 extern int radeon_disp_priority;
96 extern int radeon_hw_i2c;
97 extern int radeon_pcie_gen2;
98 extern int radeon_msi;
99 extern int radeon_lockup_timeout;
100 extern int radeon_fastfb;
101 extern int radeon_dpm;
102 extern int radeon_aspm;
103 extern int radeon_runtime_pm;
104 extern int radeon_hard_reset;
105 extern int radeon_vm_size;
106 extern int radeon_vm_block_size;
107 extern int radeon_deep_color;
108 extern int radeon_use_pflipirq;
109 extern int radeon_bapm;
112 * Copy from radeon_drv.h so we don't have to include both and have conflicting
115 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
116 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
117 /* RADEON_IB_POOL_SIZE must be a power of 2 */
118 #define RADEON_IB_POOL_SIZE 16
119 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
120 #define RADEONFB_CONN_LIMIT 4
121 #define RADEON_BIOS_NUM_SCRATCH 8
123 /* fence seq are set to this number when signaled */
124 #define RADEON_FENCE_SIGNALED_SEQ 0LL
126 /* internal ring indices */
127 /* r1xx+ has gfx CP ring */
128 #define RADEON_RING_TYPE_GFX_INDEX 0
130 /* cayman has 2 compute CP rings */
131 #define CAYMAN_RING_TYPE_CP1_INDEX 1
132 #define CAYMAN_RING_TYPE_CP2_INDEX 2
134 /* R600+ has an async dma ring */
135 #define R600_RING_TYPE_DMA_INDEX 3
136 /* cayman add a second async dma ring */
137 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
140 #define R600_RING_TYPE_UVD_INDEX 5
143 #define TN_RING_TYPE_VCE1_INDEX 6
144 #define TN_RING_TYPE_VCE2_INDEX 7
146 /* max number of rings */
147 #define RADEON_NUM_RINGS 8
149 /* number of hw syncs before falling back on blocking */
150 #define RADEON_NUM_SYNCS 4
152 /* number of hw syncs before falling back on blocking */
153 #define RADEON_NUM_SYNCS 4
155 /* hardcode those limit for now */
156 #define RADEON_VA_IB_OFFSET (1 << 20)
157 #define RADEON_VA_RESERVED_SIZE (8 << 20)
158 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
160 /* hard reset data */
161 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
164 #define RADEON_RESET_GFX (1 << 0)
165 #define RADEON_RESET_COMPUTE (1 << 1)
166 #define RADEON_RESET_DMA (1 << 2)
167 #define RADEON_RESET_CP (1 << 3)
168 #define RADEON_RESET_GRBM (1 << 4)
169 #define RADEON_RESET_DMA1 (1 << 5)
170 #define RADEON_RESET_RLC (1 << 6)
171 #define RADEON_RESET_SEM (1 << 7)
172 #define RADEON_RESET_IH (1 << 8)
173 #define RADEON_RESET_VMC (1 << 9)
174 #define RADEON_RESET_MC (1 << 10)
175 #define RADEON_RESET_DISPLAY (1 << 11)
178 #define RADEON_CG_BLOCK_GFX (1 << 0)
179 #define RADEON_CG_BLOCK_MC (1 << 1)
180 #define RADEON_CG_BLOCK_SDMA (1 << 2)
181 #define RADEON_CG_BLOCK_UVD (1 << 3)
182 #define RADEON_CG_BLOCK_VCE (1 << 4)
183 #define RADEON_CG_BLOCK_HDP (1 << 5)
184 #define RADEON_CG_BLOCK_BIF (1 << 6)
187 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
188 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
189 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
190 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
191 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
192 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
193 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
194 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
195 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
196 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
197 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
198 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
199 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
200 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
201 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
202 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
203 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
206 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
207 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
208 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
209 #define RADEON_PG_SUPPORT_UVD (1 << 3)
210 #define RADEON_PG_SUPPORT_VCE (1 << 4)
211 #define RADEON_PG_SUPPORT_CP (1 << 5)
212 #define RADEON_PG_SUPPORT_GDS (1 << 6)
213 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
214 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
215 #define RADEON_PG_SUPPORT_ACP (1 << 9)
216 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
218 /* max cursor sizes (in pixels) */
219 #define CURSOR_WIDTH 64
220 #define CURSOR_HEIGHT 64
222 #define CIK_CURSOR_WIDTH 128
223 #define CIK_CURSOR_HEIGHT 128
226 * Errata workarounds.
228 enum radeon_pll_errata {
229 CHIP_ERRATA_R300_CG = 0x00000001,
230 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
231 CHIP_ERRATA_PLL_DELAY = 0x00000004
235 struct radeon_device;
241 bool radeon_get_bios(struct radeon_device *rdev);
246 struct radeon_dummy_page {
250 int radeon_dummy_page_init(struct radeon_device *rdev);
251 void radeon_dummy_page_fini(struct radeon_device *rdev);
257 struct radeon_clock {
258 struct radeon_pll p1pll;
259 struct radeon_pll p2pll;
260 struct radeon_pll dcpll;
261 struct radeon_pll spll;
262 struct radeon_pll mpll;
264 uint32_t default_mclk;
265 uint32_t default_sclk;
266 uint32_t default_dispclk;
267 uint32_t current_dispclk;
269 uint32_t max_pixel_clock;
275 int radeon_pm_init(struct radeon_device *rdev);
276 int radeon_pm_late_init(struct radeon_device *rdev);
277 void radeon_pm_fini(struct radeon_device *rdev);
278 void radeon_pm_compute_clocks(struct radeon_device *rdev);
279 void radeon_pm_suspend(struct radeon_device *rdev);
280 void radeon_pm_resume(struct radeon_device *rdev);
281 void radeon_combios_get_power_modes(struct radeon_device *rdev);
282 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
283 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
287 struct atom_clock_dividers *dividers);
288 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
291 struct atom_mpll_param *mpll_param);
292 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
293 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
294 u16 voltage_level, u8 voltage_type,
295 u32 *gpio_value, u32 *gpio_mask);
296 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
297 u32 eng_clock, u32 mem_clock);
298 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
299 u8 voltage_type, u16 *voltage_step);
300 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
301 u16 voltage_id, u16 *voltage);
302 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
305 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
307 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
308 u16 *vddc, u16 *vddci,
309 u16 virtual_voltage_id,
310 u16 vbios_voltage_id);
311 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
312 u16 virtual_voltage_id,
314 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
318 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
319 u8 voltage_type, u16 *min_voltage);
320 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
321 u8 voltage_type, u16 *max_voltage);
322 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
323 u8 voltage_type, u8 voltage_mode,
324 struct atom_voltage_table *voltage_table);
325 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
326 u8 voltage_type, u8 voltage_mode);
327 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
329 u8 *svd_gpio_id, u8 *svc_gpio_id);
330 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
332 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
334 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
336 struct atom_mc_reg_table *reg_table);
337 int radeon_atom_get_memory_info(struct radeon_device *rdev,
338 u8 module_index, struct atom_memory_info *mem_info);
339 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
340 bool gddr5, u8 module_index,
341 struct atom_memory_clock_range_table *mclk_range_table);
342 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
343 u16 voltage_id, u16 *voltage);
344 void rs690_pm_info(struct radeon_device *rdev);
345 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
346 unsigned *bankh, unsigned *mtaspect,
347 unsigned *tile_split);
352 struct radeon_fence_driver {
353 struct radeon_device *rdev;
354 uint32_t scratch_reg;
356 volatile uint32_t *cpu_addr;
357 /* sync_seq is protected by ring emission lock */
358 uint64_t sync_seq[RADEON_NUM_RINGS];
361 struct delayed_work lockup_work;
364 struct radeon_fence {
365 struct radeon_device *rdev;
367 /* protected by radeon_fence.lock */
373 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
374 int radeon_fence_driver_init(struct radeon_device *rdev);
375 void radeon_fence_driver_fini(struct radeon_device *rdev);
376 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
377 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
378 void radeon_fence_process(struct radeon_device *rdev, int ring);
379 bool radeon_fence_signaled(struct radeon_fence *fence);
380 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
381 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
382 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
383 int radeon_fence_wait_any(struct radeon_device *rdev,
384 struct radeon_fence **fences,
386 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
387 void radeon_fence_unref(struct radeon_fence **fence);
388 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
389 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
390 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
391 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
392 struct radeon_fence *b)
402 BUG_ON(a->ring != b->ring);
404 if (a->seq > b->seq) {
411 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
412 struct radeon_fence *b)
422 BUG_ON(a->ring != b->ring);
424 return a->seq < b->seq;
430 struct radeon_surface_reg {
431 struct radeon_bo *bo;
434 #define RADEON_GEM_MAX_SURFACES 8
440 struct ttm_bo_global_ref bo_global_ref;
441 struct drm_global_reference mem_global_ref;
442 struct ttm_bo_device bdev;
443 bool mem_global_referenced;
446 #if defined(CONFIG_DEBUG_FS)
452 /* bo virtual address in a specific vm */
453 struct radeon_bo_va {
454 /* protected by bo being reserved */
455 struct list_head bo_list;
460 /* protected by vm mutex */
461 struct interval_tree_node it;
462 struct list_head vm_status;
464 /* constant after initialization */
465 struct radeon_vm *vm;
466 struct radeon_bo *bo;
470 /* Protected by gem.mutex */
471 struct list_head list;
472 /* Protected by tbo.reserved */
475 struct ttm_placement placement;
476 struct ttm_buffer_object tbo;
477 struct ttm_bo_kmap_obj kmap;
484 /* list of all virtual address to which this bo
488 /* Constant after initialization */
489 struct radeon_device *rdev;
490 struct drm_gem_object gem_base;
492 struct ttm_bo_kmap_obj dma_buf_vmap;
495 struct radeon_mn *mn;
496 struct interval_tree_node mn_it;
498 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
500 int radeon_gem_debugfs_init(struct radeon_device *rdev);
502 /* sub-allocation manager, it has to be protected by another lock.
503 * By conception this is an helper for other part of the driver
504 * like the indirect buffer or semaphore, which both have their
507 * Principe is simple, we keep a list of sub allocation in offset
508 * order (first entry has offset == 0, last entry has the highest
511 * When allocating new object we first check if there is room at
512 * the end total_size - (last_object_offset + last_object_size) >=
513 * alloc_size. If so we allocate new object there.
515 * When there is not enough room at the end, we start waiting for
516 * each sub object until we reach object_offset+object_size >=
517 * alloc_size, this object then become the sub object we return.
519 * Alignment can't be bigger than page size.
521 * Hole are not considered for allocation to keep things simple.
522 * Assumption is that there won't be hole (all object on same
525 struct radeon_sa_manager {
526 wait_queue_head_t wq;
527 struct radeon_bo *bo;
528 struct list_head *hole;
529 struct list_head flist[RADEON_NUM_RINGS];
530 struct list_head olist;
540 /* sub-allocation buffer */
541 struct radeon_sa_bo {
542 struct list_head olist;
543 struct list_head flist;
544 struct radeon_sa_manager *manager;
547 struct radeon_fence *fence;
555 struct list_head objects;
558 int radeon_gem_init(struct radeon_device *rdev);
559 void radeon_gem_fini(struct radeon_device *rdev);
560 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
561 int alignment, int initial_domain,
562 u32 flags, bool kernel,
563 struct drm_gem_object **obj);
565 int radeon_mode_dumb_create(struct drm_file *file_priv,
566 struct drm_device *dev,
567 struct drm_mode_create_dumb *args);
568 int radeon_mode_dumb_mmap(struct drm_file *filp,
569 struct drm_device *dev,
570 uint32_t handle, uint64_t *offset_p);
575 struct radeon_semaphore {
576 struct radeon_sa_bo *sa_bo;
579 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
582 int radeon_semaphore_create(struct radeon_device *rdev,
583 struct radeon_semaphore **semaphore);
584 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
585 struct radeon_semaphore *semaphore);
586 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
587 struct radeon_semaphore *semaphore);
588 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
589 struct radeon_fence *fence);
590 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
591 struct radeon_semaphore *semaphore,
593 void radeon_semaphore_free(struct radeon_device *rdev,
594 struct radeon_semaphore **semaphore,
595 struct radeon_fence *fence);
598 * GART structures, functions & helpers
602 #define RADEON_GPU_PAGE_SIZE 4096
603 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
604 #define RADEON_GPU_PAGE_SHIFT 12
605 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
607 #define RADEON_GART_PAGE_DUMMY 0
608 #define RADEON_GART_PAGE_VALID (1 << 0)
609 #define RADEON_GART_PAGE_READ (1 << 1)
610 #define RADEON_GART_PAGE_WRITE (1 << 2)
611 #define RADEON_GART_PAGE_SNOOP (1 << 3)
614 dma_addr_t table_addr;
615 struct radeon_bo *robj;
617 unsigned num_gpu_pages;
618 unsigned num_cpu_pages;
621 dma_addr_t *pages_addr;
625 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
626 void radeon_gart_table_ram_free(struct radeon_device *rdev);
627 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
628 void radeon_gart_table_vram_free(struct radeon_device *rdev);
629 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
630 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
631 int radeon_gart_init(struct radeon_device *rdev);
632 void radeon_gart_fini(struct radeon_device *rdev);
633 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
635 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
636 int pages, struct page **pagelist,
637 dma_addr_t *dma_addr, uint32_t flags);
641 * GPU MC structures, functions & helpers
644 resource_size_t aper_size;
645 resource_size_t aper_base;
646 resource_size_t agp_base;
647 /* for some chips with <= 32MB we need to lie
648 * about vram size near mc fb location */
650 u64 visible_vram_size;
660 bool igp_sideport_enabled;
665 bool radeon_combios_sideport_present(struct radeon_device *rdev);
666 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
669 * GPU scratch registers structures, functions & helpers
671 struct radeon_scratch {
678 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
679 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
682 * GPU doorbell structures, functions & helpers
684 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
686 struct radeon_doorbell {
688 resource_size_t base;
689 resource_size_t size;
691 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
692 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
695 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
696 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
702 struct radeon_flip_work {
703 struct work_struct flip_work;
704 struct work_struct unpin_work;
705 struct radeon_device *rdev;
708 struct drm_pending_vblank_event *event;
709 struct radeon_bo *old_rbo;
710 struct radeon_fence *fence;
713 struct r500_irq_stat_regs {
718 struct r600_irq_stat_regs {
728 struct evergreen_irq_stat_regs {
749 struct cik_irq_stat_regs {
765 union radeon_irq_stat_regs {
766 struct r500_irq_stat_regs r500;
767 struct r600_irq_stat_regs r600;
768 struct evergreen_irq_stat_regs evergreen;
769 struct cik_irq_stat_regs cik;
775 atomic_t ring_int[RADEON_NUM_RINGS];
776 bool crtc_vblank_int[RADEON_MAX_CRTCS];
777 atomic_t pflip[RADEON_MAX_CRTCS];
778 wait_queue_head_t vblank_queue;
779 bool hpd[RADEON_MAX_HPD_PINS];
780 bool afmt[RADEON_MAX_AFMT_BLOCKS];
781 union radeon_irq_stat_regs stat_regs;
785 int radeon_irq_kms_init(struct radeon_device *rdev);
786 void radeon_irq_kms_fini(struct radeon_device *rdev);
787 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
788 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
789 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
790 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
791 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
792 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
793 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
794 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
801 struct radeon_sa_bo *sa_bo;
806 struct radeon_fence *fence;
807 struct radeon_vm *vm;
809 struct radeon_semaphore *semaphore;
813 struct radeon_bo *ring_obj;
814 volatile uint32_t *ring;
816 unsigned rptr_save_reg;
817 u64 next_rptr_gpu_addr;
818 volatile u32 *next_rptr_cpu_addr;
822 unsigned ring_free_dw;
825 atomic64_t last_activity;
832 u64 last_semaphore_signal_addr;
833 u64 last_semaphore_wait_addr;
838 struct radeon_bo *mqd_obj;
844 struct radeon_bo *hpd_eop_obj;
845 u64 hpd_eop_gpu_addr;
855 /* maximum number of VMIDs */
856 #define RADEON_NUM_VM 16
858 /* number of entries in page table */
859 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
861 /* PTBs (Page Table Blocks) need to be aligned to 32K */
862 #define RADEON_VM_PTB_ALIGN_SIZE 32768
863 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
864 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
866 #define R600_PTE_VALID (1 << 0)
867 #define R600_PTE_SYSTEM (1 << 1)
868 #define R600_PTE_SNOOPED (1 << 2)
869 #define R600_PTE_READABLE (1 << 5)
870 #define R600_PTE_WRITEABLE (1 << 6)
872 /* PTE (Page Table Entry) fragment field for different page sizes */
873 #define R600_PTE_FRAG_4KB (0 << 7)
874 #define R600_PTE_FRAG_64KB (4 << 7)
875 #define R600_PTE_FRAG_256KB (6 << 7)
877 /* flags needed to be set so we can copy directly from the GART table */
878 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
879 R600_PTE_SYSTEM | R600_PTE_VALID )
881 struct radeon_vm_pt {
882 struct radeon_bo *bo;
890 /* BOs moved, but not yet updated in the PT */
891 struct list_head invalidated;
893 /* BOs freed, but not yet updated in the PT */
894 struct list_head freed;
896 /* contains the page directory */
897 struct radeon_bo *page_directory;
898 uint64_t pd_gpu_addr;
899 unsigned max_pde_used;
901 /* array of page tables, one for each page directory entry */
902 struct radeon_vm_pt *page_tables;
904 struct radeon_bo_va *ib_bo_va;
907 /* last fence for cs using this vm */
908 struct radeon_fence *fence;
909 /* last flush or NULL if we still need to flush */
910 struct radeon_fence *last_flush;
911 /* last use of vmid */
912 struct radeon_fence *last_id_use;
915 struct radeon_vm_manager {
916 struct radeon_fence *active[RADEON_NUM_VM];
918 /* number of VMIDs */
920 /* vram base address for page table entry */
921 u64 vram_base_offset;
927 * file private structure
929 struct radeon_fpriv {
937 struct radeon_bo *ring_obj;
938 volatile uint32_t *ring;
950 #include "clearstate_defs.h"
953 /* for power gating */
954 struct radeon_bo *save_restore_obj;
955 uint64_t save_restore_gpu_addr;
956 volatile uint32_t *sr_ptr;
959 /* for clear state */
960 struct radeon_bo *clear_state_obj;
961 uint64_t clear_state_gpu_addr;
962 volatile uint32_t *cs_ptr;
963 const struct cs_section_def *cs_data;
964 u32 clear_state_size;
966 struct radeon_bo *cp_table_obj;
967 uint64_t cp_table_gpu_addr;
968 volatile uint32_t *cp_table_ptr;
972 int radeon_ib_get(struct radeon_device *rdev, int ring,
973 struct radeon_ib *ib, struct radeon_vm *vm,
975 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
976 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
977 struct radeon_ib *const_ib, bool hdp_flush);
978 int radeon_ib_pool_init(struct radeon_device *rdev);
979 void radeon_ib_pool_fini(struct radeon_device *rdev);
980 int radeon_ib_ring_tests(struct radeon_device *rdev);
981 /* Ring access between begin & end cannot sleep */
982 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
983 struct radeon_ring *ring);
984 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
985 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
986 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
987 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
989 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
991 void radeon_ring_undo(struct radeon_ring *ring);
992 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
993 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
994 void radeon_ring_lockup_update(struct radeon_device *rdev,
995 struct radeon_ring *ring);
996 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
997 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
999 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1000 unsigned size, uint32_t *data);
1001 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1002 unsigned rptr_offs, u32 nop);
1003 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1006 /* r600 async dma */
1007 void r600_dma_stop(struct radeon_device *rdev);
1008 int r600_dma_resume(struct radeon_device *rdev);
1009 void r600_dma_fini(struct radeon_device *rdev);
1011 void cayman_dma_stop(struct radeon_device *rdev);
1012 int cayman_dma_resume(struct radeon_device *rdev);
1013 void cayman_dma_fini(struct radeon_device *rdev);
1018 struct radeon_cs_reloc {
1019 struct drm_gem_object *gobj;
1020 struct radeon_bo *robj;
1021 struct ttm_validate_buffer tv;
1022 uint64_t gpu_offset;
1023 unsigned prefered_domains;
1024 unsigned allowed_domains;
1025 uint32_t tiling_flags;
1029 struct radeon_cs_chunk {
1033 void __user *user_ptr;
1036 struct radeon_cs_parser {
1038 struct radeon_device *rdev;
1039 struct drm_file *filp;
1042 struct radeon_cs_chunk *chunks;
1043 uint64_t *chunks_array;
1048 struct radeon_cs_reloc *relocs;
1049 struct radeon_cs_reloc **relocs_ptr;
1050 struct radeon_cs_reloc *vm_bos;
1051 struct list_head validated;
1052 unsigned dma_reloc_idx;
1053 /* indices of various chunks */
1055 int chunk_relocs_idx;
1056 int chunk_flags_idx;
1057 int chunk_const_ib_idx;
1058 struct radeon_ib ib;
1059 struct radeon_ib const_ib;
1066 struct ww_acquire_ctx ticket;
1069 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1071 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1074 return ibc->kdata[idx];
1075 return p->ib.ptr[idx];
1079 struct radeon_cs_packet {
1085 unsigned one_reg_wr;
1088 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1089 struct radeon_cs_packet *pkt,
1090 unsigned idx, unsigned reg);
1091 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1092 struct radeon_cs_packet *pkt);
1098 int radeon_agp_init(struct radeon_device *rdev);
1099 void radeon_agp_resume(struct radeon_device *rdev);
1100 void radeon_agp_suspend(struct radeon_device *rdev);
1101 void radeon_agp_fini(struct radeon_device *rdev);
1108 struct radeon_bo *wb_obj;
1109 volatile uint32_t *wb;
1115 #define RADEON_WB_SCRATCH_OFFSET 0
1116 #define RADEON_WB_RING0_NEXT_RPTR 256
1117 #define RADEON_WB_CP_RPTR_OFFSET 1024
1118 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1119 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1120 #define R600_WB_DMA_RPTR_OFFSET 1792
1121 #define R600_WB_IH_WPTR_OFFSET 2048
1122 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1123 #define R600_WB_EVENT_OFFSET 3072
1124 #define CIK_WB_CP1_WPTR_OFFSET 3328
1125 #define CIK_WB_CP2_WPTR_OFFSET 3584
1128 * struct radeon_pm - power management datas
1129 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1130 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1131 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1132 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1133 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1134 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1135 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1136 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1137 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1138 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1139 * @needed_bandwidth: current bandwidth needs
1141 * It keeps track of various data needed to take powermanagement decision.
1142 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1143 * Equation between gpu/memory clock and available bandwidth is hw dependent
1144 * (type of memory, bus size, efficiency, ...)
1147 enum radeon_pm_method {
1153 enum radeon_dynpm_state {
1154 DYNPM_STATE_DISABLED,
1155 DYNPM_STATE_MINIMUM,
1158 DYNPM_STATE_SUSPENDED,
1160 enum radeon_dynpm_action {
1162 DYNPM_ACTION_MINIMUM,
1163 DYNPM_ACTION_DOWNCLOCK,
1164 DYNPM_ACTION_UPCLOCK,
1165 DYNPM_ACTION_DEFAULT
1168 enum radeon_voltage_type {
1175 enum radeon_pm_state_type {
1176 /* not used for dpm */
1177 POWER_STATE_TYPE_DEFAULT,
1178 POWER_STATE_TYPE_POWERSAVE,
1179 /* user selectable states */
1180 POWER_STATE_TYPE_BATTERY,
1181 POWER_STATE_TYPE_BALANCED,
1182 POWER_STATE_TYPE_PERFORMANCE,
1183 /* internal states */
1184 POWER_STATE_TYPE_INTERNAL_UVD,
1185 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1186 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1187 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1188 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1189 POWER_STATE_TYPE_INTERNAL_BOOT,
1190 POWER_STATE_TYPE_INTERNAL_THERMAL,
1191 POWER_STATE_TYPE_INTERNAL_ACPI,
1192 POWER_STATE_TYPE_INTERNAL_ULV,
1193 POWER_STATE_TYPE_INTERNAL_3DPERF,
1196 enum radeon_pm_profile_type {
1204 #define PM_PROFILE_DEFAULT_IDX 0
1205 #define PM_PROFILE_LOW_SH_IDX 1
1206 #define PM_PROFILE_MID_SH_IDX 2
1207 #define PM_PROFILE_HIGH_SH_IDX 3
1208 #define PM_PROFILE_LOW_MH_IDX 4
1209 #define PM_PROFILE_MID_MH_IDX 5
1210 #define PM_PROFILE_HIGH_MH_IDX 6
1211 #define PM_PROFILE_MAX 7
1213 struct radeon_pm_profile {
1214 int dpms_off_ps_idx;
1216 int dpms_off_cm_idx;
1220 enum radeon_int_thermal_type {
1222 THERMAL_TYPE_EXTERNAL,
1223 THERMAL_TYPE_EXTERNAL_GPIO,
1226 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1227 THERMAL_TYPE_EVERGREEN,
1231 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1236 struct radeon_voltage {
1237 enum radeon_voltage_type type;
1239 struct radeon_gpio_rec gpio;
1240 u32 delay; /* delay in usec from voltage drop to sclk change */
1241 bool active_high; /* voltage drop is active when bit is high */
1243 u8 vddc_id; /* index into vddc voltage table */
1244 u8 vddci_id; /* index into vddci voltage table */
1248 /* evergreen+ vddci */
1252 /* clock mode flags */
1253 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1255 struct radeon_pm_clock_info {
1261 struct radeon_voltage voltage;
1262 /* standardized clock flags */
1267 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1269 struct radeon_power_state {
1270 enum radeon_pm_state_type type;
1271 struct radeon_pm_clock_info *clock_info;
1272 /* number of valid clock modes in this power state */
1273 int num_clock_modes;
1274 struct radeon_pm_clock_info *default_clock_mode;
1275 /* standardized state flags */
1277 u32 misc; /* vbios specific flags */
1278 u32 misc2; /* vbios specific flags */
1279 int pcie_lanes; /* pcie lanes */
1283 * Some modes are overclocked by very low value, accept them
1285 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1287 enum radeon_dpm_auto_throttle_src {
1288 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1289 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1292 enum radeon_dpm_event_src {
1293 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1294 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1295 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1296 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1297 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1300 #define RADEON_MAX_VCE_LEVELS 6
1302 enum radeon_vce_level {
1303 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1304 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1305 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1306 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1307 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1308 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1312 u32 caps; /* vbios flags */
1313 u32 class; /* vbios flags */
1314 u32 class2; /* vbios flags */
1322 enum radeon_vce_level vce_level;
1327 struct radeon_dpm_thermal {
1328 /* thermal interrupt work */
1329 struct work_struct work;
1330 /* low temperature threshold */
1332 /* high temperature threshold */
1334 /* was interrupt low to high or high to low */
1338 enum radeon_clk_action
1344 struct radeon_blacklist_clocks
1348 enum radeon_clk_action action;
1351 struct radeon_clock_and_voltage_limits {
1358 struct radeon_clock_array {
1363 struct radeon_clock_voltage_dependency_entry {
1368 struct radeon_clock_voltage_dependency_table {
1370 struct radeon_clock_voltage_dependency_entry *entries;
1373 union radeon_cac_leakage_entry {
1385 struct radeon_cac_leakage_table {
1387 union radeon_cac_leakage_entry *entries;
1390 struct radeon_phase_shedding_limits_entry {
1396 struct radeon_phase_shedding_limits_table {
1398 struct radeon_phase_shedding_limits_entry *entries;
1401 struct radeon_uvd_clock_voltage_dependency_entry {
1407 struct radeon_uvd_clock_voltage_dependency_table {
1409 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1412 struct radeon_vce_clock_voltage_dependency_entry {
1418 struct radeon_vce_clock_voltage_dependency_table {
1420 struct radeon_vce_clock_voltage_dependency_entry *entries;
1423 struct radeon_ppm_table {
1425 u16 cpu_core_number;
1427 u32 small_ac_platform_tdp;
1429 u32 small_ac_platform_tdc;
1436 struct radeon_cac_tdp_table {
1438 u16 configurable_tdp;
1440 u16 battery_power_limit;
1441 u16 small_power_limit;
1442 u16 low_cac_leakage;
1443 u16 high_cac_leakage;
1444 u16 maximum_power_delivery_limit;
1447 struct radeon_dpm_dynamic_state {
1448 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1449 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1450 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1451 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1452 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1453 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1454 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1455 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1456 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1457 struct radeon_clock_array valid_sclk_values;
1458 struct radeon_clock_array valid_mclk_values;
1459 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1460 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1461 u32 mclk_sclk_ratio;
1462 u32 sclk_mclk_delta;
1463 u16 vddc_vddci_delta;
1464 u16 min_vddc_for_pcie_gen2;
1465 struct radeon_cac_leakage_table cac_leakage_table;
1466 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1467 struct radeon_ppm_table *ppm_table;
1468 struct radeon_cac_tdp_table *cac_tdp_table;
1471 struct radeon_dpm_fan {
1481 bool ucode_fan_control;
1484 enum radeon_pcie_gen {
1485 RADEON_PCIE_GEN1 = 0,
1486 RADEON_PCIE_GEN2 = 1,
1487 RADEON_PCIE_GEN3 = 2,
1488 RADEON_PCIE_GEN_INVALID = 0xffff
1491 enum radeon_dpm_forced_level {
1492 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1493 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1494 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1497 struct radeon_vce_state {
1509 struct radeon_ps *ps;
1510 /* number of valid power states */
1512 /* current power state that is active */
1513 struct radeon_ps *current_ps;
1514 /* requested power state */
1515 struct radeon_ps *requested_ps;
1516 /* boot up power state */
1517 struct radeon_ps *boot_ps;
1518 /* default uvd power state */
1519 struct radeon_ps *uvd_ps;
1520 /* vce requirements */
1521 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1522 enum radeon_vce_level vce_level;
1523 enum radeon_pm_state_type state;
1524 enum radeon_pm_state_type user_state;
1526 u32 voltage_response_time;
1527 u32 backbias_response_time;
1529 u32 new_active_crtcs;
1530 int new_active_crtc_count;
1531 u32 current_active_crtcs;
1532 int current_active_crtc_count;
1533 struct radeon_dpm_dynamic_state dyn_state;
1534 struct radeon_dpm_fan fan;
1537 u32 near_tdp_limit_adjusted;
1538 u32 sq_ramping_threshold;
1542 u16 load_line_slope;
1545 /* special states active */
1546 bool thermal_active;
1549 /* thermal handling */
1550 struct radeon_dpm_thermal thermal;
1552 enum radeon_dpm_forced_level forced_level;
1553 /* track UVD streams */
1558 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1559 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1563 /* write locked while reprogramming mclk */
1564 struct rw_semaphore mclk_lock;
1566 int active_crtc_count;
1569 fixed20_12 max_bandwidth;
1570 fixed20_12 igp_sideport_mclk;
1571 fixed20_12 igp_system_mclk;
1572 fixed20_12 igp_ht_link_clk;
1573 fixed20_12 igp_ht_link_width;
1574 fixed20_12 k8_bandwidth;
1575 fixed20_12 sideport_bandwidth;
1576 fixed20_12 ht_bandwidth;
1577 fixed20_12 core_bandwidth;
1580 fixed20_12 needed_bandwidth;
1581 struct radeon_power_state *power_state;
1582 /* number of valid power states */
1583 int num_power_states;
1584 int current_power_state_index;
1585 int current_clock_mode_index;
1586 int requested_power_state_index;
1587 int requested_clock_mode_index;
1588 int default_power_state_index;
1597 struct radeon_i2c_chan *i2c_bus;
1598 /* selected pm method */
1599 enum radeon_pm_method pm_method;
1600 /* dynpm power management */
1601 struct delayed_work dynpm_idle_work;
1602 enum radeon_dynpm_state dynpm_state;
1603 enum radeon_dynpm_action dynpm_planned_action;
1604 unsigned long dynpm_action_timeout;
1605 bool dynpm_can_upclock;
1606 bool dynpm_can_downclock;
1607 /* profile-based power management */
1608 enum radeon_pm_profile_type profile;
1610 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1611 /* internal thermal controller on rv6xx+ */
1612 enum radeon_int_thermal_type int_thermal_type;
1613 struct device *int_hwmon_dev;
1616 struct radeon_dpm dpm;
1619 int radeon_pm_get_type_index(struct radeon_device *rdev,
1620 enum radeon_pm_state_type ps_type,
1625 #define RADEON_MAX_UVD_HANDLES 10
1626 #define RADEON_UVD_STACK_SIZE (1024*1024)
1627 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1630 struct radeon_bo *vcpu_bo;
1634 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1635 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1636 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1637 struct delayed_work idle_work;
1640 int radeon_uvd_init(struct radeon_device *rdev);
1641 void radeon_uvd_fini(struct radeon_device *rdev);
1642 int radeon_uvd_suspend(struct radeon_device *rdev);
1643 int radeon_uvd_resume(struct radeon_device *rdev);
1644 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1645 uint32_t handle, struct radeon_fence **fence);
1646 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1647 uint32_t handle, struct radeon_fence **fence);
1648 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1649 void radeon_uvd_free_handles(struct radeon_device *rdev,
1650 struct drm_file *filp);
1651 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1652 void radeon_uvd_note_usage(struct radeon_device *rdev);
1653 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1654 unsigned vclk, unsigned dclk,
1655 unsigned vco_min, unsigned vco_max,
1656 unsigned fb_factor, unsigned fb_mask,
1657 unsigned pd_min, unsigned pd_max,
1659 unsigned *optimal_fb_div,
1660 unsigned *optimal_vclk_div,
1661 unsigned *optimal_dclk_div);
1662 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1663 unsigned cg_upll_func_cntl);
1668 #define RADEON_MAX_VCE_HANDLES 16
1669 #define RADEON_VCE_STACK_SIZE (1024*1024)
1670 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1673 struct radeon_bo *vcpu_bo;
1675 unsigned fw_version;
1676 unsigned fb_version;
1677 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1678 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1679 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1680 struct delayed_work idle_work;
1683 int radeon_vce_init(struct radeon_device *rdev);
1684 void radeon_vce_fini(struct radeon_device *rdev);
1685 int radeon_vce_suspend(struct radeon_device *rdev);
1686 int radeon_vce_resume(struct radeon_device *rdev);
1687 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1688 uint32_t handle, struct radeon_fence **fence);
1689 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1690 uint32_t handle, struct radeon_fence **fence);
1691 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1692 void radeon_vce_note_usage(struct radeon_device *rdev);
1693 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1694 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1695 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1696 struct radeon_ring *ring,
1697 struct radeon_semaphore *semaphore,
1699 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1700 void radeon_vce_fence_emit(struct radeon_device *rdev,
1701 struct radeon_fence *fence);
1702 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1703 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1705 struct r600_audio_pin {
1708 int bits_per_sample;
1718 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1725 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1731 void radeon_test_moves(struct radeon_device *rdev);
1732 void radeon_test_ring_sync(struct radeon_device *rdev,
1733 struct radeon_ring *cpA,
1734 struct radeon_ring *cpB);
1735 void radeon_test_syncing(struct radeon_device *rdev);
1740 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1741 void radeon_mn_unregister(struct radeon_bo *bo);
1746 struct radeon_debugfs {
1747 struct drm_info_list *files;
1751 int radeon_debugfs_add_files(struct radeon_device *rdev,
1752 struct drm_info_list *files,
1754 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1757 * ASIC ring specific functions.
1759 struct radeon_asic_ring {
1760 /* ring read/write ptr handling */
1761 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1762 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1763 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1765 /* validating and patching of IBs */
1766 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1767 int (*cs_parse)(struct radeon_cs_parser *p);
1769 /* command emmit functions */
1770 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1771 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1772 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1773 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1774 struct radeon_semaphore *semaphore, bool emit_wait);
1775 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1777 /* testing functions */
1778 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1779 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1780 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1783 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1787 * ASIC specific functions.
1789 struct radeon_asic {
1790 int (*init)(struct radeon_device *rdev);
1791 void (*fini)(struct radeon_device *rdev);
1792 int (*resume)(struct radeon_device *rdev);
1793 int (*suspend)(struct radeon_device *rdev);
1794 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1795 int (*asic_reset)(struct radeon_device *rdev);
1796 /* Flush the HDP cache via MMIO */
1797 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1798 /* check if 3D engine is idle */
1799 bool (*gui_idle)(struct radeon_device *rdev);
1800 /* wait for mc_idle */
1801 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1802 /* get the reference clock */
1803 u32 (*get_xclk)(struct radeon_device *rdev);
1804 /* get the gpu clock counter */
1805 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1808 void (*tlb_flush)(struct radeon_device *rdev);
1809 void (*set_page)(struct radeon_device *rdev, unsigned i,
1810 uint64_t addr, uint32_t flags);
1813 int (*init)(struct radeon_device *rdev);
1814 void (*fini)(struct radeon_device *rdev);
1815 void (*copy_pages)(struct radeon_device *rdev,
1816 struct radeon_ib *ib,
1817 uint64_t pe, uint64_t src,
1819 void (*write_pages)(struct radeon_device *rdev,
1820 struct radeon_ib *ib,
1822 uint64_t addr, unsigned count,
1823 uint32_t incr, uint32_t flags);
1824 void (*set_pages)(struct radeon_device *rdev,
1825 struct radeon_ib *ib,
1827 uint64_t addr, unsigned count,
1828 uint32_t incr, uint32_t flags);
1829 void (*pad_ib)(struct radeon_ib *ib);
1831 /* ring specific callbacks */
1832 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1835 int (*set)(struct radeon_device *rdev);
1836 int (*process)(struct radeon_device *rdev);
1840 /* display watermarks */
1841 void (*bandwidth_update)(struct radeon_device *rdev);
1842 /* get frame count */
1843 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1844 /* wait for vblank */
1845 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1846 /* set backlight level */
1847 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1848 /* get backlight level */
1849 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1850 /* audio callbacks */
1851 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1852 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1854 /* copy functions for bo handling */
1856 int (*blit)(struct radeon_device *rdev,
1857 uint64_t src_offset,
1858 uint64_t dst_offset,
1859 unsigned num_gpu_pages,
1860 struct radeon_fence **fence);
1861 u32 blit_ring_index;
1862 int (*dma)(struct radeon_device *rdev,
1863 uint64_t src_offset,
1864 uint64_t dst_offset,
1865 unsigned num_gpu_pages,
1866 struct radeon_fence **fence);
1868 /* method used for bo copy */
1869 int (*copy)(struct radeon_device *rdev,
1870 uint64_t src_offset,
1871 uint64_t dst_offset,
1872 unsigned num_gpu_pages,
1873 struct radeon_fence **fence);
1874 /* ring used for bo copies */
1875 u32 copy_ring_index;
1879 int (*set_reg)(struct radeon_device *rdev, int reg,
1880 uint32_t tiling_flags, uint32_t pitch,
1881 uint32_t offset, uint32_t obj_size);
1882 void (*clear_reg)(struct radeon_device *rdev, int reg);
1884 /* hotplug detect */
1886 void (*init)(struct radeon_device *rdev);
1887 void (*fini)(struct radeon_device *rdev);
1888 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1889 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1891 /* static power management */
1893 void (*misc)(struct radeon_device *rdev);
1894 void (*prepare)(struct radeon_device *rdev);
1895 void (*finish)(struct radeon_device *rdev);
1896 void (*init_profile)(struct radeon_device *rdev);
1897 void (*get_dynpm_state)(struct radeon_device *rdev);
1898 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1899 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1900 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1901 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1902 int (*get_pcie_lanes)(struct radeon_device *rdev);
1903 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1904 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1905 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1906 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1907 int (*get_temperature)(struct radeon_device *rdev);
1909 /* dynamic power management */
1911 int (*init)(struct radeon_device *rdev);
1912 void (*setup_asic)(struct radeon_device *rdev);
1913 int (*enable)(struct radeon_device *rdev);
1914 int (*late_enable)(struct radeon_device *rdev);
1915 void (*disable)(struct radeon_device *rdev);
1916 int (*pre_set_power_state)(struct radeon_device *rdev);
1917 int (*set_power_state)(struct radeon_device *rdev);
1918 void (*post_set_power_state)(struct radeon_device *rdev);
1919 void (*display_configuration_changed)(struct radeon_device *rdev);
1920 void (*fini)(struct radeon_device *rdev);
1921 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1922 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1923 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1924 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1925 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1926 bool (*vblank_too_short)(struct radeon_device *rdev);
1927 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1928 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1932 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1933 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1941 const unsigned *reg_safe_bm;
1942 unsigned reg_safe_bm_size;
1947 const unsigned *reg_safe_bm;
1948 unsigned reg_safe_bm_size;
1955 unsigned max_tile_pipes;
1957 unsigned max_backends;
1959 unsigned max_threads;
1960 unsigned max_stack_entries;
1961 unsigned max_hw_contexts;
1962 unsigned max_gs_threads;
1963 unsigned sx_max_export_size;
1964 unsigned sx_max_export_pos_size;
1965 unsigned sx_max_export_smx_size;
1966 unsigned sq_num_cf_insts;
1967 unsigned tiling_nbanks;
1968 unsigned tiling_npipes;
1969 unsigned tiling_group_size;
1970 unsigned tile_config;
1971 unsigned backend_map;
1972 unsigned active_simds;
1977 unsigned max_tile_pipes;
1979 unsigned max_backends;
1981 unsigned max_threads;
1982 unsigned max_stack_entries;
1983 unsigned max_hw_contexts;
1984 unsigned max_gs_threads;
1985 unsigned sx_max_export_size;
1986 unsigned sx_max_export_pos_size;
1987 unsigned sx_max_export_smx_size;
1988 unsigned sq_num_cf_insts;
1989 unsigned sx_num_of_sets;
1990 unsigned sc_prim_fifo_size;
1991 unsigned sc_hiz_tile_fifo_size;
1992 unsigned sc_earlyz_tile_fifo_fize;
1993 unsigned tiling_nbanks;
1994 unsigned tiling_npipes;
1995 unsigned tiling_group_size;
1996 unsigned tile_config;
1997 unsigned backend_map;
1998 unsigned active_simds;
2001 struct evergreen_asic {
2004 unsigned max_tile_pipes;
2006 unsigned max_backends;
2008 unsigned max_threads;
2009 unsigned max_stack_entries;
2010 unsigned max_hw_contexts;
2011 unsigned max_gs_threads;
2012 unsigned sx_max_export_size;
2013 unsigned sx_max_export_pos_size;
2014 unsigned sx_max_export_smx_size;
2015 unsigned sq_num_cf_insts;
2016 unsigned sx_num_of_sets;
2017 unsigned sc_prim_fifo_size;
2018 unsigned sc_hiz_tile_fifo_size;
2019 unsigned sc_earlyz_tile_fifo_size;
2020 unsigned tiling_nbanks;
2021 unsigned tiling_npipes;
2022 unsigned tiling_group_size;
2023 unsigned tile_config;
2024 unsigned backend_map;
2025 unsigned active_simds;
2028 struct cayman_asic {
2029 unsigned max_shader_engines;
2030 unsigned max_pipes_per_simd;
2031 unsigned max_tile_pipes;
2032 unsigned max_simds_per_se;
2033 unsigned max_backends_per_se;
2034 unsigned max_texture_channel_caches;
2036 unsigned max_threads;
2037 unsigned max_gs_threads;
2038 unsigned max_stack_entries;
2039 unsigned sx_num_of_sets;
2040 unsigned sx_max_export_size;
2041 unsigned sx_max_export_pos_size;
2042 unsigned sx_max_export_smx_size;
2043 unsigned max_hw_contexts;
2044 unsigned sq_num_cf_insts;
2045 unsigned sc_prim_fifo_size;
2046 unsigned sc_hiz_tile_fifo_size;
2047 unsigned sc_earlyz_tile_fifo_size;
2049 unsigned num_shader_engines;
2050 unsigned num_shader_pipes_per_simd;
2051 unsigned num_tile_pipes;
2052 unsigned num_simds_per_se;
2053 unsigned num_backends_per_se;
2054 unsigned backend_disable_mask_per_asic;
2055 unsigned backend_map;
2056 unsigned num_texture_channel_caches;
2057 unsigned mem_max_burst_length_bytes;
2058 unsigned mem_row_size_in_kb;
2059 unsigned shader_engine_tile_size;
2061 unsigned multi_gpu_tile_size;
2063 unsigned tile_config;
2064 unsigned active_simds;
2068 unsigned max_shader_engines;
2069 unsigned max_tile_pipes;
2070 unsigned max_cu_per_sh;
2071 unsigned max_sh_per_se;
2072 unsigned max_backends_per_se;
2073 unsigned max_texture_channel_caches;
2075 unsigned max_gs_threads;
2076 unsigned max_hw_contexts;
2077 unsigned sc_prim_fifo_size_frontend;
2078 unsigned sc_prim_fifo_size_backend;
2079 unsigned sc_hiz_tile_fifo_size;
2080 unsigned sc_earlyz_tile_fifo_size;
2082 unsigned num_tile_pipes;
2083 unsigned backend_enable_mask;
2084 unsigned backend_disable_mask_per_asic;
2085 unsigned backend_map;
2086 unsigned num_texture_channel_caches;
2087 unsigned mem_max_burst_length_bytes;
2088 unsigned mem_row_size_in_kb;
2089 unsigned shader_engine_tile_size;
2091 unsigned multi_gpu_tile_size;
2093 unsigned tile_config;
2094 uint32_t tile_mode_array[32];
2095 uint32_t active_cus;
2099 unsigned max_shader_engines;
2100 unsigned max_tile_pipes;
2101 unsigned max_cu_per_sh;
2102 unsigned max_sh_per_se;
2103 unsigned max_backends_per_se;
2104 unsigned max_texture_channel_caches;
2106 unsigned max_gs_threads;
2107 unsigned max_hw_contexts;
2108 unsigned sc_prim_fifo_size_frontend;
2109 unsigned sc_prim_fifo_size_backend;
2110 unsigned sc_hiz_tile_fifo_size;
2111 unsigned sc_earlyz_tile_fifo_size;
2113 unsigned num_tile_pipes;
2114 unsigned backend_enable_mask;
2115 unsigned backend_disable_mask_per_asic;
2116 unsigned backend_map;
2117 unsigned num_texture_channel_caches;
2118 unsigned mem_max_burst_length_bytes;
2119 unsigned mem_row_size_in_kb;
2120 unsigned shader_engine_tile_size;
2122 unsigned multi_gpu_tile_size;
2124 unsigned tile_config;
2125 uint32_t tile_mode_array[32];
2126 uint32_t macrotile_mode_array[16];
2127 uint32_t active_cus;
2130 union radeon_asic_config {
2131 struct r300_asic r300;
2132 struct r100_asic r100;
2133 struct r600_asic r600;
2134 struct rv770_asic rv770;
2135 struct evergreen_asic evergreen;
2136 struct cayman_asic cayman;
2138 struct cik_asic cik;
2142 * asic initizalization from radeon_asic.c
2144 void radeon_agp_disable(struct radeon_device *rdev);
2145 int radeon_asic_init(struct radeon_device *rdev);
2151 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2152 struct drm_file *filp);
2153 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2154 struct drm_file *filp);
2155 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2156 struct drm_file *filp);
2157 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2158 struct drm_file *file_priv);
2159 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2160 struct drm_file *file_priv);
2161 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2162 struct drm_file *file_priv);
2163 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *file_priv);
2165 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2166 struct drm_file *filp);
2167 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2168 struct drm_file *filp);
2169 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2170 struct drm_file *filp);
2171 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2172 struct drm_file *filp);
2173 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *filp);
2175 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2176 struct drm_file *filp);
2177 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2178 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2179 struct drm_file *filp);
2180 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2181 struct drm_file *filp);
2183 /* VRAM scratch page for HDP bug, default vram page */
2184 struct r600_vram_scratch {
2185 struct radeon_bo *robj;
2186 volatile uint32_t *ptr;
2193 struct radeon_atif_notification_cfg {
2198 struct radeon_atif_notifications {
2199 bool display_switch;
2200 bool expansion_mode_change;
2202 bool forced_power_state;
2203 bool system_power_state;
2204 bool display_conf_change;
2206 bool brightness_change;
2207 bool dgpu_display_event;
2210 struct radeon_atif_functions {
2212 bool sbios_requests;
2213 bool select_active_disp;
2215 bool get_tv_standard;
2216 bool set_tv_standard;
2217 bool get_panel_expansion_mode;
2218 bool set_panel_expansion_mode;
2219 bool temperature_change;
2220 bool graphics_device_types;
2223 struct radeon_atif {
2224 struct radeon_atif_notifications notifications;
2225 struct radeon_atif_functions functions;
2226 struct radeon_atif_notification_cfg notification_cfg;
2227 struct radeon_encoder *encoder_for_bl;
2230 struct radeon_atcs_functions {
2234 bool pcie_bus_width;
2237 struct radeon_atcs {
2238 struct radeon_atcs_functions functions;
2242 * Core structure, functions and helpers.
2244 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2245 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2247 struct radeon_device {
2249 struct drm_device *ddev;
2250 struct pci_dev *pdev;
2251 struct rw_semaphore exclusive_lock;
2253 union radeon_asic_config config;
2254 enum radeon_family family;
2255 unsigned long flags;
2257 enum radeon_pll_errata pll_errata;
2264 uint16_t bios_header_start;
2265 struct radeon_bo *stollen_vga_memory;
2267 resource_size_t rmmio_base;
2268 resource_size_t rmmio_size;
2269 /* protects concurrent MM_INDEX/DATA based register access */
2270 spinlock_t mmio_idx_lock;
2271 /* protects concurrent SMC based register access */
2272 spinlock_t smc_idx_lock;
2273 /* protects concurrent PLL register access */
2274 spinlock_t pll_idx_lock;
2275 /* protects concurrent MC register access */
2276 spinlock_t mc_idx_lock;
2277 /* protects concurrent PCIE register access */
2278 spinlock_t pcie_idx_lock;
2279 /* protects concurrent PCIE_PORT register access */
2280 spinlock_t pciep_idx_lock;
2281 /* protects concurrent PIF register access */
2282 spinlock_t pif_idx_lock;
2283 /* protects concurrent CG register access */
2284 spinlock_t cg_idx_lock;
2285 /* protects concurrent UVD register access */
2286 spinlock_t uvd_idx_lock;
2287 /* protects concurrent RCU register access */
2288 spinlock_t rcu_idx_lock;
2289 /* protects concurrent DIDT register access */
2290 spinlock_t didt_idx_lock;
2291 /* protects concurrent ENDPOINT (audio) register access */
2292 spinlock_t end_idx_lock;
2293 void __iomem *rmmio;
2294 radeon_rreg_t mc_rreg;
2295 radeon_wreg_t mc_wreg;
2296 radeon_rreg_t pll_rreg;
2297 radeon_wreg_t pll_wreg;
2298 uint32_t pcie_reg_mask;
2299 radeon_rreg_t pciep_rreg;
2300 radeon_wreg_t pciep_wreg;
2302 void __iomem *rio_mem;
2303 resource_size_t rio_mem_size;
2304 struct radeon_clock clock;
2305 struct radeon_mc mc;
2306 struct radeon_gart gart;
2307 struct radeon_mode_info mode_info;
2308 struct radeon_scratch scratch;
2309 struct radeon_doorbell doorbell;
2310 struct radeon_mman mman;
2311 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2312 wait_queue_head_t fence_queue;
2313 struct mutex ring_lock;
2314 struct radeon_ring ring[RADEON_NUM_RINGS];
2316 struct radeon_sa_manager ring_tmp_bo;
2317 struct radeon_irq irq;
2318 struct radeon_asic *asic;
2319 struct radeon_gem gem;
2320 struct radeon_pm pm;
2321 struct radeon_uvd uvd;
2322 struct radeon_vce vce;
2323 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2324 struct radeon_wb wb;
2325 struct radeon_dummy_page dummy_page;
2330 bool fastfb_working; /* IGP feature*/
2331 bool needs_reset, in_reset;
2332 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2333 const struct firmware *me_fw; /* all family ME firmware */
2334 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2335 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2336 const struct firmware *mc_fw; /* NI MC firmware */
2337 const struct firmware *ce_fw; /* SI CE firmware */
2338 const struct firmware *mec_fw; /* CIK MEC firmware */
2339 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2340 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2341 const struct firmware *smc_fw; /* SMC firmware */
2342 const struct firmware *uvd_fw; /* UVD firmware */
2343 const struct firmware *vce_fw; /* VCE firmware */
2345 struct r600_vram_scratch vram_scratch;
2346 int msi_enabled; /* msi enabled */
2347 struct r600_ih ih; /* r6/700 interrupt ring */
2348 struct radeon_rlc rlc;
2349 struct radeon_mec mec;
2350 struct work_struct hotplug_work;
2351 struct work_struct audio_work;
2352 struct work_struct reset_work;
2353 int num_crtc; /* number of crtcs */
2354 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2356 struct r600_audio audio; /* audio stuff */
2357 struct notifier_block acpi_nb;
2358 /* only one userspace can use Hyperz features or CMASK at a time */
2359 struct drm_file *hyperz_filp;
2360 struct drm_file *cmask_filp;
2362 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2364 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2365 unsigned debugfs_count;
2366 /* virtual memory */
2367 struct radeon_vm_manager vm_manager;
2368 struct mutex gpu_clock_mutex;
2370 atomic64_t vram_usage;
2371 atomic64_t gtt_usage;
2372 atomic64_t num_bytes_moved;
2373 /* ACPI interface */
2374 struct radeon_atif atif;
2375 struct radeon_atcs atcs;
2376 /* srbm instance registers */
2377 struct mutex srbm_mutex;
2378 /* clock, powergating flags */
2382 struct dev_pm_domain vga_pm_domain;
2383 bool have_disp_power_ref;
2386 /* tracking pinned memory */
2390 struct mutex mn_lock;
2391 DECLARE_HASHTABLE(mn_hash, 7);
2394 bool radeon_is_px(struct drm_device *dev);
2395 int radeon_device_init(struct radeon_device *rdev,
2396 struct drm_device *ddev,
2397 struct pci_dev *pdev,
2399 void radeon_device_fini(struct radeon_device *rdev);
2400 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2402 #define RADEON_MIN_MMIO_SIZE 0x10000
2404 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2405 bool always_indirect)
2407 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2408 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2409 return readl(((void __iomem *)rdev->rmmio) + reg);
2411 unsigned long flags;
2414 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2415 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2416 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2417 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2423 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2424 bool always_indirect)
2426 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2427 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2429 unsigned long flags;
2431 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2432 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2433 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2434 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2438 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2439 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2441 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2442 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2447 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2450 * Registers read & write functions.
2452 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2453 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2454 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2455 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2456 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2457 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2458 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2459 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2460 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2461 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2462 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2463 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2464 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2465 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2466 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2467 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2468 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2469 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2470 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2471 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2472 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2473 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2474 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2475 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2476 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2477 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2478 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2479 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2480 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2481 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2482 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2483 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2484 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2485 #define WREG32_P(reg, val, mask) \
2487 uint32_t tmp_ = RREG32(reg); \
2489 tmp_ |= ((val) & ~(mask)); \
2490 WREG32(reg, tmp_); \
2492 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2493 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2494 #define WREG32_PLL_P(reg, val, mask) \
2496 uint32_t tmp_ = RREG32_PLL(reg); \
2498 tmp_ |= ((val) & ~(mask)); \
2499 WREG32_PLL(reg, tmp_); \
2501 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2502 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2503 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2505 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2506 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2509 * Indirect registers accessor
2511 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2513 unsigned long flags;
2516 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2517 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2518 r = RREG32(RADEON_PCIE_DATA);
2519 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2523 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2525 unsigned long flags;
2527 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2528 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2529 WREG32(RADEON_PCIE_DATA, (v));
2530 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2533 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2535 unsigned long flags;
2538 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2539 WREG32(TN_SMC_IND_INDEX_0, (reg));
2540 r = RREG32(TN_SMC_IND_DATA_0);
2541 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2545 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2547 unsigned long flags;
2549 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2550 WREG32(TN_SMC_IND_INDEX_0, (reg));
2551 WREG32(TN_SMC_IND_DATA_0, (v));
2552 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2555 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2557 unsigned long flags;
2560 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2561 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2562 r = RREG32(R600_RCU_DATA);
2563 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2567 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2569 unsigned long flags;
2571 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2572 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2573 WREG32(R600_RCU_DATA, (v));
2574 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2577 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2579 unsigned long flags;
2582 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2583 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2584 r = RREG32(EVERGREEN_CG_IND_DATA);
2585 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2589 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2591 unsigned long flags;
2593 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2594 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2595 WREG32(EVERGREEN_CG_IND_DATA, (v));
2596 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2599 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2601 unsigned long flags;
2604 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2605 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2606 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2607 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2611 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2613 unsigned long flags;
2615 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2616 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2617 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2618 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2621 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2623 unsigned long flags;
2626 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2627 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2628 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2629 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2633 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2635 unsigned long flags;
2637 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2638 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2639 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2640 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2643 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2645 unsigned long flags;
2648 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2649 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2650 r = RREG32(R600_UVD_CTX_DATA);
2651 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2655 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2657 unsigned long flags;
2659 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2660 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2661 WREG32(R600_UVD_CTX_DATA, (v));
2662 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2666 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2668 unsigned long flags;
2671 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2672 WREG32(CIK_DIDT_IND_INDEX, (reg));
2673 r = RREG32(CIK_DIDT_IND_DATA);
2674 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2678 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2680 unsigned long flags;
2682 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2683 WREG32(CIK_DIDT_IND_INDEX, (reg));
2684 WREG32(CIK_DIDT_IND_DATA, (v));
2685 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2688 void r100_pll_errata_after_index(struct radeon_device *rdev);
2694 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2695 (rdev->pdev->device == 0x5969))
2696 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2697 (rdev->family == CHIP_RV200) || \
2698 (rdev->family == CHIP_RS100) || \
2699 (rdev->family == CHIP_RS200) || \
2700 (rdev->family == CHIP_RV250) || \
2701 (rdev->family == CHIP_RV280) || \
2702 (rdev->family == CHIP_RS300))
2703 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2704 (rdev->family == CHIP_RV350) || \
2705 (rdev->family == CHIP_R350) || \
2706 (rdev->family == CHIP_RV380) || \
2707 (rdev->family == CHIP_R420) || \
2708 (rdev->family == CHIP_R423) || \
2709 (rdev->family == CHIP_RV410) || \
2710 (rdev->family == CHIP_RS400) || \
2711 (rdev->family == CHIP_RS480))
2712 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2713 (rdev->ddev->pdev->device == 0x9443) || \
2714 (rdev->ddev->pdev->device == 0x944B) || \
2715 (rdev->ddev->pdev->device == 0x9506) || \
2716 (rdev->ddev->pdev->device == 0x9509) || \
2717 (rdev->ddev->pdev->device == 0x950F) || \
2718 (rdev->ddev->pdev->device == 0x689C) || \
2719 (rdev->ddev->pdev->device == 0x689D))
2720 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2721 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2722 (rdev->family == CHIP_RS690) || \
2723 (rdev->family == CHIP_RS740) || \
2724 (rdev->family >= CHIP_R600))
2725 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2726 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2727 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2728 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2729 (rdev->flags & RADEON_IS_IGP))
2730 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2731 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2732 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2733 (rdev->flags & RADEON_IS_IGP))
2734 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2735 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2736 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2737 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2738 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2739 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2740 (rdev->family == CHIP_MULLINS))
2742 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2743 (rdev->ddev->pdev->device == 0x6850) || \
2744 (rdev->ddev->pdev->device == 0x6858) || \
2745 (rdev->ddev->pdev->device == 0x6859) || \
2746 (rdev->ddev->pdev->device == 0x6840) || \
2747 (rdev->ddev->pdev->device == 0x6841) || \
2748 (rdev->ddev->pdev->device == 0x6842) || \
2749 (rdev->ddev->pdev->device == 0x6843))
2754 #define RBIOS8(i) (rdev->bios[i])
2755 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2756 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2758 int radeon_combios_init(struct radeon_device *rdev);
2759 void radeon_combios_fini(struct radeon_device *rdev);
2760 int radeon_atombios_init(struct radeon_device *rdev);
2761 void radeon_atombios_fini(struct radeon_device *rdev);
2767 #if DRM_DEBUG_CODE == 0
2768 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2770 ring->ring[ring->wptr++] = v;
2771 ring->wptr &= ring->ptr_mask;
2773 ring->ring_free_dw--;
2776 /* With debugging this is just too big to inline */
2777 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2783 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2784 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2785 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2786 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2787 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2788 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2789 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2790 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2791 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2792 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2793 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2794 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2795 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2796 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2797 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2798 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2799 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2800 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2801 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2802 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2803 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2804 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2805 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2806 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2807 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2808 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2809 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2810 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2811 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2812 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2813 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2814 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2815 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2816 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2817 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2818 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2819 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2820 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2821 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2822 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2823 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2824 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2825 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2826 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2827 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2828 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2829 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2830 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2831 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2832 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2833 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2834 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2835 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2836 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2837 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2838 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2839 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2840 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2841 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2842 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2843 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2844 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2845 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2846 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2847 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2848 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2849 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2850 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2851 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2852 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2853 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2854 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2855 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2856 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2857 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2858 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2859 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2860 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2861 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2862 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2863 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2864 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2865 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2866 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2867 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2868 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2869 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2871 /* Common functions */
2873 extern int radeon_gpu_reset(struct radeon_device *rdev);
2874 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2875 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2876 extern void radeon_agp_disable(struct radeon_device *rdev);
2877 extern int radeon_modeset_init(struct radeon_device *rdev);
2878 extern void radeon_modeset_fini(struct radeon_device *rdev);
2879 extern bool radeon_card_posted(struct radeon_device *rdev);
2880 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2881 extern void radeon_update_display_priority(struct radeon_device *rdev);
2882 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2883 extern void radeon_scratch_init(struct radeon_device *rdev);
2884 extern void radeon_wb_fini(struct radeon_device *rdev);
2885 extern int radeon_wb_init(struct radeon_device *rdev);
2886 extern void radeon_wb_disable(struct radeon_device *rdev);
2887 extern void radeon_surface_init(struct radeon_device *rdev);
2888 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2889 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2890 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2891 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2892 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2893 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2895 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2896 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2897 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2898 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2899 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2900 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2901 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2902 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2903 const u32 *registers,
2904 const u32 array_size);
2909 int radeon_vm_manager_init(struct radeon_device *rdev);
2910 void radeon_vm_manager_fini(struct radeon_device *rdev);
2911 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2912 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2913 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2914 struct radeon_vm *vm,
2915 struct list_head *head);
2916 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2917 struct radeon_vm *vm, int ring);
2918 void radeon_vm_flush(struct radeon_device *rdev,
2919 struct radeon_vm *vm,
2921 void radeon_vm_fence(struct radeon_device *rdev,
2922 struct radeon_vm *vm,
2923 struct radeon_fence *fence);
2924 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2925 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2926 struct radeon_vm *vm);
2927 int radeon_vm_clear_freed(struct radeon_device *rdev,
2928 struct radeon_vm *vm);
2929 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2930 struct radeon_vm *vm);
2931 int radeon_vm_bo_update(struct radeon_device *rdev,
2932 struct radeon_bo_va *bo_va,
2933 struct ttm_mem_reg *mem);
2934 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2935 struct radeon_bo *bo);
2936 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2937 struct radeon_bo *bo);
2938 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2939 struct radeon_vm *vm,
2940 struct radeon_bo *bo);
2941 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2942 struct radeon_bo_va *bo_va,
2945 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2946 struct radeon_bo_va *bo_va);
2949 void r600_audio_update_hdmi(struct work_struct *work);
2950 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2951 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2952 void r600_audio_enable(struct radeon_device *rdev,
2953 struct r600_audio_pin *pin,
2955 void dce6_audio_enable(struct radeon_device *rdev,
2956 struct r600_audio_pin *pin,
2960 * R600 vram scratch functions
2962 int r600_vram_scratch_init(struct radeon_device *rdev);
2963 void r600_vram_scratch_fini(struct radeon_device *rdev);
2966 * r600 cs checking helper
2968 unsigned r600_mip_minify(unsigned size, unsigned level);
2969 bool r600_fmt_is_valid_color(u32 format);
2970 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2971 int r600_fmt_get_blocksize(u32 format);
2972 int r600_fmt_get_nblocksx(u32 format, u32 w);
2973 int r600_fmt_get_nblocksy(u32 format, u32 h);
2976 * r600 functions used by radeon_encoder.c
2978 struct radeon_hdmi_acr {
2992 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2994 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2995 u32 tiling_pipe_num,
2997 u32 total_max_rb_num,
2998 u32 enabled_rb_mask);
3001 * evergreen functions used by radeon_encoder.c
3004 extern int ni_init_microcode(struct radeon_device *rdev);
3005 extern int ni_mc_load_microcode(struct radeon_device *rdev);
3008 #if defined(CONFIG_ACPI)
3009 extern int radeon_acpi_init(struct radeon_device *rdev);
3010 extern void radeon_acpi_fini(struct radeon_device *rdev);
3011 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3012 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
3013 u8 perf_req, bool advertise);
3014 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
3016 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3017 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3020 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3021 struct radeon_cs_packet *pkt,
3023 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3024 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3025 struct radeon_cs_packet *pkt);
3026 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3027 struct radeon_cs_reloc **cs_reloc,
3029 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3030 uint32_t *vline_start_end,
3031 uint32_t *vline_status);
3033 #include "radeon_object.h"