2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include "radeon_object.h"
33 /* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
47 #include <asm/atomic.h>
48 #include <linux/wait.h>
49 #include <linux/list.h>
50 #include <linux/kref.h>
52 #include "radeon_mode.h"
53 #include "radeon_reg.h"
58 extern int radeon_no_wb;
59 extern int radeon_modeset;
60 extern int radeon_dynclks;
61 extern int radeon_r4xx_atom;
62 extern int radeon_agpmode;
63 extern int radeon_vram_limit;
64 extern int radeon_gart_size;
65 extern int radeon_benchmarking;
66 extern int radeon_testing;
67 extern int radeon_connector_table;
71 * Copy from radeon_drv.h so we don't have to include both and have conflicting
74 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
75 #define RADEON_IB_POOL_SIZE 16
76 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
77 #define RADEONFB_CONN_LIMIT 4
122 enum radeon_chip_flags {
123 RADEON_FAMILY_MASK = 0x0000ffffUL,
124 RADEON_FLAGS_MASK = 0xffff0000UL,
125 RADEON_IS_MOBILITY = 0x00010000UL,
126 RADEON_IS_IGP = 0x00020000UL,
127 RADEON_SINGLE_CRTC = 0x00040000UL,
128 RADEON_IS_AGP = 0x00080000UL,
129 RADEON_HAS_HIERZ = 0x00100000UL,
130 RADEON_IS_PCIE = 0x00200000UL,
131 RADEON_NEW_MEMMAP = 0x00400000UL,
132 RADEON_IS_PCI = 0x00800000UL,
133 RADEON_IS_IGPGART = 0x01000000UL,
138 * Errata workarounds.
140 enum radeon_pll_errata {
141 CHIP_ERRATA_R300_CG = 0x00000001,
142 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
143 CHIP_ERRATA_PLL_DELAY = 0x00000004
147 struct radeon_device;
153 bool radeon_get_bios(struct radeon_device *rdev);
159 struct radeon_dummy_page {
163 int radeon_dummy_page_init(struct radeon_device *rdev);
164 void radeon_dummy_page_fini(struct radeon_device *rdev);
170 struct radeon_clock {
171 struct radeon_pll p1pll;
172 struct radeon_pll p2pll;
173 struct radeon_pll spll;
174 struct radeon_pll mpll;
176 uint32_t default_mclk;
177 uint32_t default_sclk;
184 struct radeon_fence_driver {
185 uint32_t scratch_reg;
188 unsigned long count_timeout;
189 wait_queue_head_t queue;
191 struct list_head created;
192 struct list_head emited;
193 struct list_head signaled;
196 struct radeon_fence {
197 struct radeon_device *rdev;
199 struct list_head list;
200 /* protected by radeon_fence.lock */
202 unsigned long timeout;
207 int radeon_fence_driver_init(struct radeon_device *rdev);
208 void radeon_fence_driver_fini(struct radeon_device *rdev);
209 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
210 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
211 void radeon_fence_process(struct radeon_device *rdev);
212 bool radeon_fence_signaled(struct radeon_fence *fence);
213 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
214 int radeon_fence_wait_next(struct radeon_device *rdev);
215 int radeon_fence_wait_last(struct radeon_device *rdev);
216 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
217 void radeon_fence_unref(struct radeon_fence **fence);
222 struct radeon_surface_reg {
223 struct radeon_object *robj;
226 #define RADEON_GEM_MAX_SURFACES 8
231 struct radeon_object;
233 struct radeon_object_list {
234 struct list_head list;
235 struct radeon_object *robj;
239 uint32_t tiling_flags;
242 int radeon_object_init(struct radeon_device *rdev);
243 void radeon_object_fini(struct radeon_device *rdev);
244 int radeon_object_create(struct radeon_device *rdev,
245 struct drm_gem_object *gobj,
250 struct radeon_object **robj_ptr);
251 int radeon_object_kmap(struct radeon_object *robj, void **ptr);
252 void radeon_object_kunmap(struct radeon_object *robj);
253 void radeon_object_unref(struct radeon_object **robj);
254 int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
256 void radeon_object_unpin(struct radeon_object *robj);
257 int radeon_object_wait(struct radeon_object *robj);
258 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
259 int radeon_object_evict_vram(struct radeon_device *rdev);
260 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
261 void radeon_object_force_delete(struct radeon_device *rdev);
262 void radeon_object_list_add_object(struct radeon_object_list *lobj,
263 struct list_head *head);
264 int radeon_object_list_validate(struct list_head *head, void *fence);
265 void radeon_object_list_unvalidate(struct list_head *head);
266 void radeon_object_list_clean(struct list_head *head);
267 int radeon_object_fbdev_mmap(struct radeon_object *robj,
268 struct vm_area_struct *vma);
269 unsigned long radeon_object_size(struct radeon_object *robj);
270 void radeon_object_clear_surface_reg(struct radeon_object *robj);
271 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
273 void radeon_object_set_tiling_flags(struct radeon_object *robj,
274 uint32_t tiling_flags, uint32_t pitch);
275 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
276 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
277 struct ttm_mem_reg *mem);
278 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
283 struct list_head objects;
286 int radeon_gem_init(struct radeon_device *rdev);
287 void radeon_gem_fini(struct radeon_device *rdev);
288 int radeon_gem_object_create(struct radeon_device *rdev, int size,
289 int alignment, int initial_domain,
290 bool discardable, bool kernel,
292 struct drm_gem_object **obj);
293 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
295 void radeon_gem_object_unpin(struct drm_gem_object *obj);
299 * GART structures, functions & helpers
303 struct radeon_gart_table_ram {
304 volatile uint32_t *ptr;
307 struct radeon_gart_table_vram {
308 struct radeon_object *robj;
309 volatile uint32_t *ptr;
312 union radeon_gart_table {
313 struct radeon_gart_table_ram ram;
314 struct radeon_gart_table_vram vram;
318 dma_addr_t table_addr;
319 unsigned num_gpu_pages;
320 unsigned num_cpu_pages;
322 union radeon_gart_table table;
324 dma_addr_t *pages_addr;
328 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
329 void radeon_gart_table_ram_free(struct radeon_device *rdev);
330 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
331 void radeon_gart_table_vram_free(struct radeon_device *rdev);
332 int radeon_gart_init(struct radeon_device *rdev);
333 void radeon_gart_fini(struct radeon_device *rdev);
334 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
336 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
337 int pages, struct page **pagelist);
341 * GPU MC structures, functions & helpers
344 resource_size_t aper_size;
345 resource_size_t aper_base;
346 resource_size_t agp_base;
347 /* for some chips with <= 32MB we need to lie
348 * about vram size near mc fb location */
363 int radeon_mc_setup(struct radeon_device *rdev);
367 * GPU scratch registers structures, functions & helpers
369 struct radeon_scratch {
375 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
376 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
385 /* FIXME: use a define max crtc rather than hardcode it */
386 bool crtc_vblank_int[2];
389 int radeon_irq_kms_init(struct radeon_device *rdev);
390 void radeon_irq_kms_fini(struct radeon_device *rdev);
397 struct list_head list;
400 struct radeon_fence *fence;
401 volatile uint32_t *ptr;
405 struct radeon_ib_pool {
407 struct radeon_object *robj;
408 struct list_head scheduled_ibs;
409 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
411 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
415 struct radeon_object *ring_obj;
416 volatile uint32_t *ring;
421 unsigned ring_free_dw;
431 struct radeon_object *shader_obj;
433 u32 vs_offset, ps_offset;
436 u32 vb_used, vb_total;
437 struct radeon_ib *vb_ib;
440 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
441 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
442 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
443 int radeon_ib_pool_init(struct radeon_device *rdev);
444 void radeon_ib_pool_fini(struct radeon_device *rdev);
445 int radeon_ib_test(struct radeon_device *rdev);
446 /* Ring access between begin & end cannot sleep */
447 void radeon_ring_free_size(struct radeon_device *rdev);
448 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
449 void radeon_ring_unlock_commit(struct radeon_device *rdev);
450 void radeon_ring_unlock_undo(struct radeon_device *rdev);
451 int radeon_ring_test(struct radeon_device *rdev);
452 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
453 void radeon_ring_fini(struct radeon_device *rdev);
459 struct radeon_cs_reloc {
460 struct drm_gem_object *gobj;
461 struct radeon_object *robj;
462 struct radeon_object_list lobj;
467 struct radeon_cs_chunk {
473 struct radeon_cs_parser {
474 struct radeon_device *rdev;
475 struct drm_file *filp;
478 struct radeon_cs_chunk *chunks;
479 uint64_t *chunks_array;
484 struct radeon_cs_reloc *relocs;
485 struct radeon_cs_reloc **relocs_ptr;
486 struct list_head validated;
487 /* indices of various chunks */
489 int chunk_relocs_idx;
490 struct radeon_ib *ib;
495 struct radeon_cs_packet {
504 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
505 struct radeon_cs_packet *pkt,
506 unsigned idx, unsigned reg);
507 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
508 struct radeon_cs_packet *pkt);
514 int radeon_agp_init(struct radeon_device *rdev);
515 void radeon_agp_fini(struct radeon_device *rdev);
522 struct radeon_object *wb_obj;
523 volatile uint32_t *wb;
528 * struct radeon_pm - power management datas
529 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
530 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
531 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
532 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
533 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
534 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
535 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
536 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
537 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
538 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
539 * @needed_bandwidth: current bandwidth needs
541 * It keeps track of various data needed to take powermanagement decision.
542 * Bandwith need is used to determine minimun clock of the GPU and memory.
543 * Equation between gpu/memory clock and available bandwidth is hw dependent
544 * (type of memory, bus size, efficiency, ...)
547 fixed20_12 max_bandwidth;
548 fixed20_12 igp_sideport_mclk;
549 fixed20_12 igp_system_mclk;
550 fixed20_12 igp_ht_link_clk;
551 fixed20_12 igp_ht_link_width;
552 fixed20_12 k8_bandwidth;
553 fixed20_12 sideport_bandwidth;
554 fixed20_12 ht_bandwidth;
555 fixed20_12 core_bandwidth;
557 fixed20_12 needed_bandwidth;
564 void radeon_benchmark(struct radeon_device *rdev);
570 void radeon_test_moves(struct radeon_device *rdev);
576 int radeon_debugfs_add_files(struct radeon_device *rdev,
577 struct drm_info_list *files,
579 int radeon_debugfs_fence_init(struct radeon_device *rdev);
580 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
581 int r100_debugfs_cp_init(struct radeon_device *rdev);
585 * ASIC specific functions.
588 int (*init)(struct radeon_device *rdev);
589 void (*fini)(struct radeon_device *rdev);
590 int (*resume)(struct radeon_device *rdev);
591 int (*suspend)(struct radeon_device *rdev);
592 void (*errata)(struct radeon_device *rdev);
593 void (*vram_info)(struct radeon_device *rdev);
594 int (*gpu_reset)(struct radeon_device *rdev);
595 int (*mc_init)(struct radeon_device *rdev);
596 void (*mc_fini)(struct radeon_device *rdev);
597 int (*wb_init)(struct radeon_device *rdev);
598 void (*wb_fini)(struct radeon_device *rdev);
599 int (*gart_init)(struct radeon_device *rdev);
600 void (*gart_fini)(struct radeon_device *rdev);
601 int (*gart_enable)(struct radeon_device *rdev);
602 void (*gart_disable)(struct radeon_device *rdev);
603 void (*gart_tlb_flush)(struct radeon_device *rdev);
604 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
605 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
606 void (*cp_fini)(struct radeon_device *rdev);
607 void (*cp_disable)(struct radeon_device *rdev);
608 void (*cp_commit)(struct radeon_device *rdev);
609 void (*ring_start)(struct radeon_device *rdev);
610 int (*ring_test)(struct radeon_device *rdev);
611 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
612 int (*ib_test)(struct radeon_device *rdev);
613 int (*irq_set)(struct radeon_device *rdev);
614 int (*irq_process)(struct radeon_device *rdev);
615 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
616 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
617 int (*cs_parse)(struct radeon_cs_parser *p);
618 int (*copy_blit)(struct radeon_device *rdev,
622 struct radeon_fence *fence);
623 int (*copy_dma)(struct radeon_device *rdev,
627 struct radeon_fence *fence);
628 int (*copy)(struct radeon_device *rdev,
632 struct radeon_fence *fence);
633 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
634 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
635 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
636 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
637 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
638 uint32_t tiling_flags, uint32_t pitch,
639 uint32_t offset, uint32_t obj_size);
640 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
641 void (*bandwidth_update)(struct radeon_device *rdev);
648 const unsigned *reg_safe_bm;
649 unsigned reg_safe_bm_size;
653 const unsigned *reg_safe_bm;
654 unsigned reg_safe_bm_size;
659 unsigned max_tile_pipes;
661 unsigned max_backends;
663 unsigned max_threads;
664 unsigned max_stack_entries;
665 unsigned max_hw_contexts;
666 unsigned max_gs_threads;
667 unsigned sx_max_export_size;
668 unsigned sx_max_export_pos_size;
669 unsigned sx_max_export_smx_size;
670 unsigned sq_num_cf_insts;
675 unsigned max_tile_pipes;
677 unsigned max_backends;
679 unsigned max_threads;
680 unsigned max_stack_entries;
681 unsigned max_hw_contexts;
682 unsigned max_gs_threads;
683 unsigned sx_max_export_size;
684 unsigned sx_max_export_pos_size;
685 unsigned sx_max_export_smx_size;
686 unsigned sq_num_cf_insts;
687 unsigned sx_num_of_sets;
688 unsigned sc_prim_fifo_size;
689 unsigned sc_hiz_tile_fifo_size;
690 unsigned sc_earlyz_tile_fifo_fize;
693 union radeon_asic_config {
694 struct r300_asic r300;
695 struct r100_asic r100;
696 struct r600_asic r600;
697 struct rv770_asic rv770;
704 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
705 struct drm_file *filp);
706 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
707 struct drm_file *filp);
708 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
709 struct drm_file *file_priv);
710 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
711 struct drm_file *file_priv);
712 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
713 struct drm_file *file_priv);
714 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
715 struct drm_file *file_priv);
716 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
717 struct drm_file *filp);
718 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
719 struct drm_file *filp);
720 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
721 struct drm_file *filp);
722 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
723 struct drm_file *filp);
724 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
725 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
726 struct drm_file *filp);
727 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
728 struct drm_file *filp);
732 * Core structure, functions and helpers.
734 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
735 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
737 struct radeon_device {
739 struct drm_device *ddev;
740 struct pci_dev *pdev;
742 union radeon_asic_config config;
743 enum radeon_family family;
746 enum radeon_pll_errata pll_errata;
753 uint16_t bios_header_start;
754 struct radeon_object *stollen_vga_memory;
755 struct fb_info *fbdev_info;
756 struct radeon_object *fbdev_robj;
757 struct radeon_framebuffer *fbdev_rfb;
759 resource_size_t rmmio_base;
760 resource_size_t rmmio_size;
762 radeon_rreg_t mc_rreg;
763 radeon_wreg_t mc_wreg;
764 radeon_rreg_t pll_rreg;
765 radeon_wreg_t pll_wreg;
766 uint32_t pcie_reg_mask;
767 radeon_rreg_t pciep_rreg;
768 radeon_wreg_t pciep_wreg;
769 struct radeon_clock clock;
771 struct radeon_gart gart;
772 struct radeon_mode_info mode_info;
773 struct radeon_scratch scratch;
774 struct radeon_mman mman;
775 struct radeon_fence_driver fence_drv;
777 struct radeon_ib_pool ib_pool;
778 struct radeon_irq irq;
779 struct radeon_asic *asic;
780 struct radeon_gem gem;
782 struct mutex cs_mutex;
784 struct radeon_dummy_page dummy_page;
790 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
791 const struct firmware *me_fw; /* all family ME firmware */
792 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
793 struct r600_blit r600_blit;
796 int radeon_device_init(struct radeon_device *rdev,
797 struct drm_device *ddev,
798 struct pci_dev *pdev,
800 void radeon_device_fini(struct radeon_device *rdev);
801 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
804 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
805 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
806 void r600_kms_blit_copy(struct radeon_device *rdev,
807 u64 src_gpu_addr, u64 dst_gpu_addr,
810 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
813 return readl(((void __iomem *)rdev->rmmio) + reg);
815 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
816 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
820 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
823 writel(v, ((void __iomem *)rdev->rmmio) + reg);
825 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
826 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
832 * Registers read & write functions.
834 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
835 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
836 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
837 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
838 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
839 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
840 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
841 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
842 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
843 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
844 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
845 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
846 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
847 #define WREG32_P(reg, val, mask) \
849 uint32_t tmp_ = RREG32(reg); \
851 tmp_ |= ((val) & ~(mask)); \
854 #define WREG32_PLL_P(reg, val, mask) \
856 uint32_t tmp_ = RREG32_PLL(reg); \
858 tmp_ |= ((val) & ~(mask)); \
859 WREG32_PLL(reg, tmp_); \
861 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
864 * Indirect registers accessor
866 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
870 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
871 r = RREG32(RADEON_PCIE_DATA);
875 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
877 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
878 WREG32(RADEON_PCIE_DATA, (v));
881 void r100_pll_errata_after_index(struct radeon_device *rdev);
887 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
888 (rdev->pdev->device == 0x5969))
889 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
890 (rdev->family == CHIP_RV200) || \
891 (rdev->family == CHIP_RS100) || \
892 (rdev->family == CHIP_RS200) || \
893 (rdev->family == CHIP_RV250) || \
894 (rdev->family == CHIP_RV280) || \
895 (rdev->family == CHIP_RS300))
896 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
897 (rdev->family == CHIP_RV350) || \
898 (rdev->family == CHIP_R350) || \
899 (rdev->family == CHIP_RV380) || \
900 (rdev->family == CHIP_R420) || \
901 (rdev->family == CHIP_R423) || \
902 (rdev->family == CHIP_RV410) || \
903 (rdev->family == CHIP_RS400) || \
904 (rdev->family == CHIP_RS480))
905 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
906 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
907 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
913 #define RBIOS8(i) (rdev->bios[i])
914 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
915 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
917 int radeon_combios_init(struct radeon_device *rdev);
918 void radeon_combios_fini(struct radeon_device *rdev);
919 int radeon_atombios_init(struct radeon_device *rdev);
920 void radeon_atombios_fini(struct radeon_device *rdev);
926 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
929 if (rdev->cp.count_dw <= 0) {
930 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
933 rdev->cp.ring[rdev->cp.wptr++] = v;
934 rdev->cp.wptr &= rdev->cp.ptr_mask;
936 rdev->cp.ring_free_dw--;
943 #define radeon_init(rdev) (rdev)->asic->init((rdev))
944 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
945 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
946 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
947 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
948 #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
949 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
950 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
951 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
952 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
953 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
954 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
955 #define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
956 #define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
957 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
958 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
959 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
960 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
961 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
962 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
963 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
964 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
965 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
966 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
967 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
968 #define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
969 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
970 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
971 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
972 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
973 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
974 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
975 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
976 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
977 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
978 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
979 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
980 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
981 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
982 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
984 /* Common functions */
985 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
986 extern int radeon_modeset_init(struct radeon_device *rdev);
987 extern void radeon_modeset_fini(struct radeon_device *rdev);
988 extern bool radeon_card_posted(struct radeon_device *rdev);
989 extern int radeon_clocks_init(struct radeon_device *rdev);
990 extern void radeon_clocks_fini(struct radeon_device *rdev);
991 extern void radeon_scratch_init(struct radeon_device *rdev);
992 extern void radeon_surface_init(struct radeon_device *rdev);
993 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
995 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
996 struct r100_mc_save {
1004 extern void r100_cp_disable(struct radeon_device *rdev);
1005 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1006 extern void r100_cp_fini(struct radeon_device *rdev);
1007 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1008 extern int r100_pci_gart_init(struct radeon_device *rdev);
1009 extern void r100_pci_gart_fini(struct radeon_device *rdev);
1010 extern int r100_pci_gart_enable(struct radeon_device *rdev);
1011 extern void r100_pci_gart_disable(struct radeon_device *rdev);
1012 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1013 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1014 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1015 extern void r100_ib_fini(struct radeon_device *rdev);
1016 extern int r100_ib_init(struct radeon_device *rdev);
1017 extern void r100_irq_disable(struct radeon_device *rdev);
1018 extern int r100_irq_set(struct radeon_device *rdev);
1019 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1020 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1021 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1022 extern void r100_wb_disable(struct radeon_device *rdev);
1023 extern void r100_wb_fini(struct radeon_device *rdev);
1024 extern int r100_wb_init(struct radeon_device *rdev);
1026 /* r300,r350,rv350,rv370,rv380 */
1027 extern void r300_set_reg_safe(struct radeon_device *rdev);
1028 extern void r300_mc_program(struct radeon_device *rdev);
1029 extern void r300_vram_info(struct radeon_device *rdev);
1030 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1031 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1032 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1033 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1035 /* r420,r423,rv410 */
1036 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1037 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1038 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1041 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1044 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1045 struct drm_display_mode *mode1,
1046 struct drm_display_mode *mode2);
1048 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1049 extern bool r600_card_posted(struct radeon_device *rdev);
1050 extern void r600_cp_stop(struct radeon_device *rdev);
1051 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1052 extern int r600_cp_resume(struct radeon_device *rdev);
1053 extern int r600_count_pipe_bits(uint32_t val);
1054 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1055 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1056 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1057 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1058 extern int r600_ib_test(struct radeon_device *rdev);
1059 extern int r600_ring_test(struct radeon_device *rdev);
1060 extern int r600_wb_init(struct radeon_device *rdev);
1061 extern void r600_wb_fini(struct radeon_device *rdev);
1062 extern void r600_scratch_init(struct radeon_device *rdev);
1063 extern int r600_blit_init(struct radeon_device *rdev);
1064 extern void r600_blit_fini(struct radeon_device *rdev);
1065 extern int r600_cp_init_microcode(struct radeon_device *rdev);