2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
102 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
105 #define RADEON_IB_POOL_SIZE 16
106 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
107 #define RADEONFB_CONN_LIMIT 4
108 #define RADEON_BIOS_NUM_SCRATCH 8
111 * Errata workarounds.
113 enum radeon_pll_errata {
114 CHIP_ERRATA_R300_CG = 0x00000001,
115 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
116 CHIP_ERRATA_PLL_DELAY = 0x00000004
120 struct radeon_device;
126 #define ATRM_BIOS_PAGE 4096
128 #if defined(CONFIG_VGA_SWITCHEROO)
129 bool radeon_atrm_supported(struct pci_dev *pdev);
130 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
132 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
137 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
141 bool radeon_get_bios(struct radeon_device *rdev);
147 struct radeon_dummy_page {
151 int radeon_dummy_page_init(struct radeon_device *rdev);
152 void radeon_dummy_page_fini(struct radeon_device *rdev);
158 struct radeon_clock {
159 struct radeon_pll p1pll;
160 struct radeon_pll p2pll;
161 struct radeon_pll dcpll;
162 struct radeon_pll spll;
163 struct radeon_pll mpll;
165 uint32_t default_mclk;
166 uint32_t default_sclk;
167 uint32_t default_dispclk;
169 uint32_t max_pixel_clock;
175 int radeon_pm_init(struct radeon_device *rdev);
176 void radeon_pm_fini(struct radeon_device *rdev);
177 void radeon_pm_compute_clocks(struct radeon_device *rdev);
178 void radeon_pm_suspend(struct radeon_device *rdev);
179 void radeon_pm_resume(struct radeon_device *rdev);
180 void radeon_combios_get_power_modes(struct radeon_device *rdev);
181 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
182 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
183 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
184 void rs690_pm_info(struct radeon_device *rdev);
185 extern int rv6xx_get_temp(struct radeon_device *rdev);
186 extern int rv770_get_temp(struct radeon_device *rdev);
187 extern int evergreen_get_temp(struct radeon_device *rdev);
188 extern int sumo_get_temp(struct radeon_device *rdev);
193 struct radeon_fence_driver {
194 uint32_t scratch_reg;
197 unsigned long last_jiffies;
198 unsigned long last_timeout;
199 wait_queue_head_t queue;
201 struct list_head created;
202 struct list_head emitted;
203 struct list_head signaled;
207 struct radeon_fence {
208 struct radeon_device *rdev;
210 struct list_head list;
211 /* protected by radeon_fence.lock */
217 int radeon_fence_driver_init(struct radeon_device *rdev);
218 void radeon_fence_driver_fini(struct radeon_device *rdev);
219 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
220 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
221 void radeon_fence_process(struct radeon_device *rdev);
222 bool radeon_fence_signaled(struct radeon_fence *fence);
223 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
224 int radeon_fence_wait_next(struct radeon_device *rdev);
225 int radeon_fence_wait_last(struct radeon_device *rdev);
226 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
227 void radeon_fence_unref(struct radeon_fence **fence);
232 struct radeon_surface_reg {
233 struct radeon_bo *bo;
236 #define RADEON_GEM_MAX_SURFACES 8
242 struct ttm_bo_global_ref bo_global_ref;
243 struct drm_global_reference mem_global_ref;
244 struct ttm_bo_device bdev;
245 bool mem_global_referenced;
250 /* Protected by gem.mutex */
251 struct list_head list;
252 /* Protected by tbo.reserved */
254 struct ttm_placement placement;
255 struct ttm_buffer_object tbo;
256 struct ttm_bo_kmap_obj kmap;
262 /* Constant after initialization */
263 struct radeon_device *rdev;
264 struct drm_gem_object gem_base;
266 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
268 struct radeon_bo_list {
269 struct ttm_validate_buffer tv;
270 struct radeon_bo *bo;
282 struct list_head objects;
285 int radeon_gem_init(struct radeon_device *rdev);
286 void radeon_gem_fini(struct radeon_device *rdev);
287 int radeon_gem_object_create(struct radeon_device *rdev, int size,
288 int alignment, int initial_domain,
289 bool discardable, bool kernel,
290 struct drm_gem_object **obj);
291 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
293 void radeon_gem_object_unpin(struct drm_gem_object *obj);
295 int radeon_mode_dumb_create(struct drm_file *file_priv,
296 struct drm_device *dev,
297 struct drm_mode_create_dumb *args);
298 int radeon_mode_dumb_mmap(struct drm_file *filp,
299 struct drm_device *dev,
300 uint32_t handle, uint64_t *offset_p);
301 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
302 struct drm_device *dev,
306 * GART structures, functions & helpers
310 #define RADEON_GPU_PAGE_SIZE 4096
311 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
312 #define RADEON_GPU_PAGE_SHIFT 12
315 dma_addr_t table_addr;
316 struct radeon_bo *robj;
318 unsigned num_gpu_pages;
319 unsigned num_cpu_pages;
322 dma_addr_t *pages_addr;
326 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
327 void radeon_gart_table_ram_free(struct radeon_device *rdev);
328 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
329 void radeon_gart_table_vram_free(struct radeon_device *rdev);
330 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
331 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
332 int radeon_gart_init(struct radeon_device *rdev);
333 void radeon_gart_fini(struct radeon_device *rdev);
334 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
336 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
337 int pages, struct page **pagelist,
338 dma_addr_t *dma_addr);
339 void radeon_gart_restore(struct radeon_device *rdev);
343 * GPU MC structures, functions & helpers
346 resource_size_t aper_size;
347 resource_size_t aper_base;
348 resource_size_t agp_base;
349 /* for some chips with <= 32MB we need to lie
350 * about vram size near mc fb location */
352 u64 visible_vram_size;
362 bool igp_sideport_enabled;
366 bool radeon_combios_sideport_present(struct radeon_device *rdev);
367 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
370 * GPU scratch registers structures, functions & helpers
372 struct radeon_scratch {
379 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
380 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
387 struct radeon_unpin_work {
388 struct work_struct work;
389 struct radeon_device *rdev;
391 struct radeon_fence *fence;
392 struct drm_pending_vblank_event *event;
393 struct radeon_bo *old_rbo;
397 struct r500_irq_stat_regs {
401 struct r600_irq_stat_regs {
409 struct evergreen_irq_stat_regs {
424 union radeon_irq_stat_regs {
425 struct r500_irq_stat_regs r500;
426 struct r600_irq_stat_regs r600;
427 struct evergreen_irq_stat_regs evergreen;
430 #define RADEON_MAX_HPD_PINS 6
431 #define RADEON_MAX_CRTCS 6
432 #define RADEON_MAX_HDMI_BLOCKS 2
437 bool crtc_vblank_int[RADEON_MAX_CRTCS];
438 bool pflip[RADEON_MAX_CRTCS];
439 wait_queue_head_t vblank_queue;
440 bool hpd[RADEON_MAX_HPD_PINS];
443 wait_queue_head_t idle_queue;
444 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
447 union radeon_irq_stat_regs stat_regs;
448 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
449 int pflip_refcount[RADEON_MAX_CRTCS];
452 int radeon_irq_kms_init(struct radeon_device *rdev);
453 void radeon_irq_kms_fini(struct radeon_device *rdev);
454 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
455 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
456 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
457 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
463 struct list_head list;
466 struct radeon_fence *fence;
474 * mutex protects scheduled_ibs, ready, alloc_bm
476 struct radeon_ib_pool {
478 struct radeon_bo *robj;
479 struct list_head bogus_ib;
480 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
486 struct radeon_bo *ring_obj;
487 volatile uint32_t *ring;
492 unsigned ring_free_dw;
505 struct radeon_bo *ring_obj;
506 volatile uint32_t *ring;
517 struct r600_blit_cp_primitives {
518 void (*set_render_target)(struct radeon_device *rdev, int format,
519 int w, int h, u64 gpu_addr);
520 void (*cp_set_surface_sync)(struct radeon_device *rdev,
521 u32 sync_type, u32 size,
523 void (*set_shaders)(struct radeon_device *rdev);
524 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
525 void (*set_tex_resource)(struct radeon_device *rdev,
526 int format, int w, int h, int pitch,
527 u64 gpu_addr, u32 size);
528 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
530 void (*draw_auto)(struct radeon_device *rdev);
531 void (*set_default_state)(struct radeon_device *rdev);
536 struct radeon_bo *shader_obj;
537 struct r600_blit_cp_primitives primitives;
539 int ring_size_common;
540 int ring_size_per_loop;
542 u32 vs_offset, ps_offset;
545 u32 vb_used, vb_total;
546 struct radeon_ib *vb_ib;
549 void r600_blit_suspend(struct radeon_device *rdev);
551 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
552 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
553 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
554 int radeon_ib_pool_init(struct radeon_device *rdev);
555 void radeon_ib_pool_fini(struct radeon_device *rdev);
556 int radeon_ib_test(struct radeon_device *rdev);
557 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
558 /* Ring access between begin & end cannot sleep */
559 void radeon_ring_free_size(struct radeon_device *rdev);
560 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
561 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
562 void radeon_ring_commit(struct radeon_device *rdev);
563 void radeon_ring_unlock_commit(struct radeon_device *rdev);
564 void radeon_ring_unlock_undo(struct radeon_device *rdev);
565 int radeon_ring_test(struct radeon_device *rdev);
566 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
567 void radeon_ring_fini(struct radeon_device *rdev);
573 struct radeon_cs_reloc {
574 struct drm_gem_object *gobj;
575 struct radeon_bo *robj;
576 struct radeon_bo_list lobj;
581 struct radeon_cs_chunk {
587 void __user *user_ptr;
588 int last_copied_page;
592 struct radeon_cs_parser {
594 struct radeon_device *rdev;
595 struct drm_file *filp;
598 struct radeon_cs_chunk *chunks;
599 uint64_t *chunks_array;
604 struct radeon_cs_reloc *relocs;
605 struct radeon_cs_reloc **relocs_ptr;
606 struct list_head validated;
607 /* indices of various chunks */
609 int chunk_relocs_idx;
610 struct radeon_ib *ib;
614 bool keep_tiling_flags;
617 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
618 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
619 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
621 struct radeon_cs_packet {
630 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
631 struct radeon_cs_packet *pkt,
632 unsigned idx, unsigned reg);
633 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
634 struct radeon_cs_packet *pkt);
640 int radeon_agp_init(struct radeon_device *rdev);
641 void radeon_agp_resume(struct radeon_device *rdev);
642 void radeon_agp_suspend(struct radeon_device *rdev);
643 void radeon_agp_fini(struct radeon_device *rdev);
650 struct radeon_bo *wb_obj;
651 volatile uint32_t *wb;
657 #define RADEON_WB_SCRATCH_OFFSET 0
658 #define RADEON_WB_CP_RPTR_OFFSET 1024
659 #define RADEON_WB_CP1_RPTR_OFFSET 1280
660 #define RADEON_WB_CP2_RPTR_OFFSET 1536
661 #define R600_WB_IH_WPTR_OFFSET 2048
662 #define R600_WB_EVENT_OFFSET 3072
665 * struct radeon_pm - power management datas
666 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
667 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
668 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
669 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
670 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
671 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
672 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
673 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
674 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
675 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
676 * @needed_bandwidth: current bandwidth needs
678 * It keeps track of various data needed to take powermanagement decision.
679 * Bandwidth need is used to determine minimun clock of the GPU and memory.
680 * Equation between gpu/memory clock and available bandwidth is hw dependent
681 * (type of memory, bus size, efficiency, ...)
684 enum radeon_pm_method {
689 enum radeon_dynpm_state {
690 DYNPM_STATE_DISABLED,
694 DYNPM_STATE_SUSPENDED,
696 enum radeon_dynpm_action {
698 DYNPM_ACTION_MINIMUM,
699 DYNPM_ACTION_DOWNCLOCK,
700 DYNPM_ACTION_UPCLOCK,
704 enum radeon_voltage_type {
711 enum radeon_pm_state_type {
712 POWER_STATE_TYPE_DEFAULT,
713 POWER_STATE_TYPE_POWERSAVE,
714 POWER_STATE_TYPE_BATTERY,
715 POWER_STATE_TYPE_BALANCED,
716 POWER_STATE_TYPE_PERFORMANCE,
719 enum radeon_pm_profile_type {
727 #define PM_PROFILE_DEFAULT_IDX 0
728 #define PM_PROFILE_LOW_SH_IDX 1
729 #define PM_PROFILE_MID_SH_IDX 2
730 #define PM_PROFILE_HIGH_SH_IDX 3
731 #define PM_PROFILE_LOW_MH_IDX 4
732 #define PM_PROFILE_MID_MH_IDX 5
733 #define PM_PROFILE_HIGH_MH_IDX 6
734 #define PM_PROFILE_MAX 7
736 struct radeon_pm_profile {
743 enum radeon_int_thermal_type {
747 THERMAL_TYPE_EVERGREEN,
752 struct radeon_voltage {
753 enum radeon_voltage_type type;
755 struct radeon_gpio_rec gpio;
756 u32 delay; /* delay in usec from voltage drop to sclk change */
757 bool active_high; /* voltage drop is active when bit is high */
759 u8 vddc_id; /* index into vddc voltage table */
760 u8 vddci_id; /* index into vddci voltage table */
764 /* evergreen+ vddci */
768 /* clock mode flags */
769 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
771 struct radeon_pm_clock_info {
777 struct radeon_voltage voltage;
778 /* standardized clock flags */
783 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
785 struct radeon_power_state {
786 enum radeon_pm_state_type type;
787 struct radeon_pm_clock_info *clock_info;
788 /* number of valid clock modes in this power state */
790 struct radeon_pm_clock_info *default_clock_mode;
791 /* standardized state flags */
793 u32 misc; /* vbios specific flags */
794 u32 misc2; /* vbios specific flags */
795 int pcie_lanes; /* pcie lanes */
799 * Some modes are overclocked by very low value, accept them
801 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
806 int active_crtc_count;
810 fixed20_12 max_bandwidth;
811 fixed20_12 igp_sideport_mclk;
812 fixed20_12 igp_system_mclk;
813 fixed20_12 igp_ht_link_clk;
814 fixed20_12 igp_ht_link_width;
815 fixed20_12 k8_bandwidth;
816 fixed20_12 sideport_bandwidth;
817 fixed20_12 ht_bandwidth;
818 fixed20_12 core_bandwidth;
821 fixed20_12 needed_bandwidth;
822 struct radeon_power_state *power_state;
823 /* number of valid power states */
824 int num_power_states;
825 int current_power_state_index;
826 int current_clock_mode_index;
827 int requested_power_state_index;
828 int requested_clock_mode_index;
829 int default_power_state_index;
838 struct radeon_i2c_chan *i2c_bus;
839 /* selected pm method */
840 enum radeon_pm_method pm_method;
841 /* dynpm power management */
842 struct delayed_work dynpm_idle_work;
843 enum radeon_dynpm_state dynpm_state;
844 enum radeon_dynpm_action dynpm_planned_action;
845 unsigned long dynpm_action_timeout;
846 bool dynpm_can_upclock;
847 bool dynpm_can_downclock;
848 /* profile-based power management */
849 enum radeon_pm_profile_type profile;
851 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
852 /* internal thermal controller on rv6xx+ */
853 enum radeon_int_thermal_type int_thermal_type;
854 struct device *int_hwmon_dev;
857 int radeon_pm_get_type_index(struct radeon_device *rdev,
858 enum radeon_pm_state_type ps_type,
864 void radeon_benchmark(struct radeon_device *rdev, int test_number);
870 void radeon_test_moves(struct radeon_device *rdev);
876 struct radeon_debugfs {
877 struct drm_info_list *files;
881 int radeon_debugfs_add_files(struct radeon_device *rdev,
882 struct drm_info_list *files,
884 int radeon_debugfs_fence_init(struct radeon_device *rdev);
888 * ASIC specific functions.
891 int (*init)(struct radeon_device *rdev);
892 void (*fini)(struct radeon_device *rdev);
893 int (*resume)(struct radeon_device *rdev);
894 int (*suspend)(struct radeon_device *rdev);
895 void (*vga_set_state)(struct radeon_device *rdev, bool state);
896 bool (*gpu_is_lockup)(struct radeon_device *rdev);
897 int (*asic_reset)(struct radeon_device *rdev);
898 void (*gart_tlb_flush)(struct radeon_device *rdev);
899 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
900 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
901 void (*cp_fini)(struct radeon_device *rdev);
902 void (*cp_disable)(struct radeon_device *rdev);
903 void (*cp_commit)(struct radeon_device *rdev);
904 void (*ring_start)(struct radeon_device *rdev);
905 int (*ring_test)(struct radeon_device *rdev);
906 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
907 int (*irq_set)(struct radeon_device *rdev);
908 int (*irq_process)(struct radeon_device *rdev);
909 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
910 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
911 int (*cs_parse)(struct radeon_cs_parser *p);
912 int (*copy_blit)(struct radeon_device *rdev,
915 unsigned num_gpu_pages,
916 struct radeon_fence *fence);
917 int (*copy_dma)(struct radeon_device *rdev,
920 unsigned num_gpu_pages,
921 struct radeon_fence *fence);
922 int (*copy)(struct radeon_device *rdev,
925 unsigned num_gpu_pages,
926 struct radeon_fence *fence);
927 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
928 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
929 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
930 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
931 int (*get_pcie_lanes)(struct radeon_device *rdev);
932 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
933 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
934 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
935 uint32_t tiling_flags, uint32_t pitch,
936 uint32_t offset, uint32_t obj_size);
937 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
938 void (*bandwidth_update)(struct radeon_device *rdev);
939 void (*hpd_init)(struct radeon_device *rdev);
940 void (*hpd_fini)(struct radeon_device *rdev);
941 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
942 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
943 /* ioctl hw specific callback. Some hw might want to perform special
944 * operation on specific ioctl. For instance on wait idle some hw
945 * might want to perform and HDP flush through MMIO as it seems that
946 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
949 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
950 bool (*gui_idle)(struct radeon_device *rdev);
951 /* power management */
952 void (*pm_misc)(struct radeon_device *rdev);
953 void (*pm_prepare)(struct radeon_device *rdev);
954 void (*pm_finish)(struct radeon_device *rdev);
955 void (*pm_init_profile)(struct radeon_device *rdev);
956 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
958 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
959 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
960 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
966 struct r100_gpu_lockup {
967 unsigned long last_jiffies;
972 const unsigned *reg_safe_bm;
973 unsigned reg_safe_bm_size;
975 struct r100_gpu_lockup lockup;
979 const unsigned *reg_safe_bm;
980 unsigned reg_safe_bm_size;
983 struct r100_gpu_lockup lockup;
988 unsigned max_tile_pipes;
990 unsigned max_backends;
992 unsigned max_threads;
993 unsigned max_stack_entries;
994 unsigned max_hw_contexts;
995 unsigned max_gs_threads;
996 unsigned sx_max_export_size;
997 unsigned sx_max_export_pos_size;
998 unsigned sx_max_export_smx_size;
999 unsigned sq_num_cf_insts;
1000 unsigned tiling_nbanks;
1001 unsigned tiling_npipes;
1002 unsigned tiling_group_size;
1003 unsigned tile_config;
1004 unsigned backend_map;
1005 struct r100_gpu_lockup lockup;
1010 unsigned max_tile_pipes;
1012 unsigned max_backends;
1014 unsigned max_threads;
1015 unsigned max_stack_entries;
1016 unsigned max_hw_contexts;
1017 unsigned max_gs_threads;
1018 unsigned sx_max_export_size;
1019 unsigned sx_max_export_pos_size;
1020 unsigned sx_max_export_smx_size;
1021 unsigned sq_num_cf_insts;
1022 unsigned sx_num_of_sets;
1023 unsigned sc_prim_fifo_size;
1024 unsigned sc_hiz_tile_fifo_size;
1025 unsigned sc_earlyz_tile_fifo_fize;
1026 unsigned tiling_nbanks;
1027 unsigned tiling_npipes;
1028 unsigned tiling_group_size;
1029 unsigned tile_config;
1030 unsigned backend_map;
1031 struct r100_gpu_lockup lockup;
1034 struct evergreen_asic {
1037 unsigned max_tile_pipes;
1039 unsigned max_backends;
1041 unsigned max_threads;
1042 unsigned max_stack_entries;
1043 unsigned max_hw_contexts;
1044 unsigned max_gs_threads;
1045 unsigned sx_max_export_size;
1046 unsigned sx_max_export_pos_size;
1047 unsigned sx_max_export_smx_size;
1048 unsigned sq_num_cf_insts;
1049 unsigned sx_num_of_sets;
1050 unsigned sc_prim_fifo_size;
1051 unsigned sc_hiz_tile_fifo_size;
1052 unsigned sc_earlyz_tile_fifo_size;
1053 unsigned tiling_nbanks;
1054 unsigned tiling_npipes;
1055 unsigned tiling_group_size;
1056 unsigned tile_config;
1057 unsigned backend_map;
1058 struct r100_gpu_lockup lockup;
1061 struct cayman_asic {
1062 unsigned max_shader_engines;
1063 unsigned max_pipes_per_simd;
1064 unsigned max_tile_pipes;
1065 unsigned max_simds_per_se;
1066 unsigned max_backends_per_se;
1067 unsigned max_texture_channel_caches;
1069 unsigned max_threads;
1070 unsigned max_gs_threads;
1071 unsigned max_stack_entries;
1072 unsigned sx_num_of_sets;
1073 unsigned sx_max_export_size;
1074 unsigned sx_max_export_pos_size;
1075 unsigned sx_max_export_smx_size;
1076 unsigned max_hw_contexts;
1077 unsigned sq_num_cf_insts;
1078 unsigned sc_prim_fifo_size;
1079 unsigned sc_hiz_tile_fifo_size;
1080 unsigned sc_earlyz_tile_fifo_size;
1082 unsigned num_shader_engines;
1083 unsigned num_shader_pipes_per_simd;
1084 unsigned num_tile_pipes;
1085 unsigned num_simds_per_se;
1086 unsigned num_backends_per_se;
1087 unsigned backend_disable_mask_per_asic;
1088 unsigned backend_map;
1089 unsigned num_texture_channel_caches;
1090 unsigned mem_max_burst_length_bytes;
1091 unsigned mem_row_size_in_kb;
1092 unsigned shader_engine_tile_size;
1094 unsigned multi_gpu_tile_size;
1096 unsigned tile_config;
1097 struct r100_gpu_lockup lockup;
1100 union radeon_asic_config {
1101 struct r300_asic r300;
1102 struct r100_asic r100;
1103 struct r600_asic r600;
1104 struct rv770_asic rv770;
1105 struct evergreen_asic evergreen;
1106 struct cayman_asic cayman;
1110 * asic initizalization from radeon_asic.c
1112 void radeon_agp_disable(struct radeon_device *rdev);
1113 int radeon_asic_init(struct radeon_device *rdev);
1119 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1120 struct drm_file *filp);
1121 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1122 struct drm_file *filp);
1123 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1124 struct drm_file *file_priv);
1125 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1126 struct drm_file *file_priv);
1127 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1128 struct drm_file *file_priv);
1129 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1130 struct drm_file *file_priv);
1131 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1132 struct drm_file *filp);
1133 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1134 struct drm_file *filp);
1135 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *filp);
1137 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1138 struct drm_file *filp);
1139 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1140 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1141 struct drm_file *filp);
1142 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1143 struct drm_file *filp);
1145 /* VRAM scratch page for HDP bug, default vram page */
1146 struct r600_vram_scratch {
1147 struct radeon_bo *robj;
1148 volatile uint32_t *ptr;
1154 * Mutex which allows recursive locking from the same process.
1156 struct radeon_mutex {
1158 struct task_struct *owner;
1162 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
1164 mutex_init(&mutex->mutex);
1165 mutex->owner = NULL;
1169 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
1171 if (mutex_trylock(&mutex->mutex)) {
1172 /* The mutex was unlocked before, so it's ours now */
1173 mutex->owner = current;
1174 } else if (mutex->owner != current) {
1175 /* Another process locked the mutex, take it */
1176 mutex_lock(&mutex->mutex);
1177 mutex->owner = current;
1179 /* Otherwise the mutex was already locked by this process */
1184 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
1186 if (--mutex->level > 0)
1189 mutex->owner = NULL;
1190 mutex_unlock(&mutex->mutex);
1195 * Core structure, functions and helpers.
1197 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1198 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1200 struct radeon_device {
1202 struct drm_device *ddev;
1203 struct pci_dev *pdev;
1205 union radeon_asic_config config;
1206 enum radeon_family family;
1207 unsigned long flags;
1209 enum radeon_pll_errata pll_errata;
1216 uint16_t bios_header_start;
1217 struct radeon_bo *stollen_vga_memory;
1219 resource_size_t rmmio_base;
1220 resource_size_t rmmio_size;
1221 void __iomem *rmmio;
1222 radeon_rreg_t mc_rreg;
1223 radeon_wreg_t mc_wreg;
1224 radeon_rreg_t pll_rreg;
1225 radeon_wreg_t pll_wreg;
1226 uint32_t pcie_reg_mask;
1227 radeon_rreg_t pciep_rreg;
1228 radeon_wreg_t pciep_wreg;
1230 void __iomem *rio_mem;
1231 resource_size_t rio_mem_size;
1232 struct radeon_clock clock;
1233 struct radeon_mc mc;
1234 struct radeon_gart gart;
1235 struct radeon_mode_info mode_info;
1236 struct radeon_scratch scratch;
1237 struct radeon_mman mman;
1238 struct radeon_fence_driver fence_drv;
1239 struct radeon_cp cp;
1240 /* cayman compute rings */
1241 struct radeon_cp cp1;
1242 struct radeon_cp cp2;
1243 struct radeon_ib_pool ib_pool;
1244 struct radeon_irq irq;
1245 struct radeon_asic *asic;
1246 struct radeon_gem gem;
1247 struct radeon_pm pm;
1248 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1249 struct radeon_mutex cs_mutex;
1250 struct radeon_wb wb;
1251 struct radeon_dummy_page dummy_page;
1257 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1258 const struct firmware *me_fw; /* all family ME firmware */
1259 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1260 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1261 const struct firmware *mc_fw; /* NI MC firmware */
1262 struct r600_blit r600_blit;
1263 struct r600_vram_scratch vram_scratch;
1264 int msi_enabled; /* msi enabled */
1265 struct r600_ih ih; /* r6/700 interrupt ring */
1266 struct work_struct hotplug_work;
1267 int num_crtc; /* number of crtcs */
1268 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1269 struct mutex vram_mutex;
1273 struct timer_list audio_timer;
1276 int audio_bits_per_sample;
1277 uint8_t audio_status_bits;
1278 uint8_t audio_category_code;
1280 struct notifier_block acpi_nb;
1281 /* only one userspace can use Hyperz features or CMASK at a time */
1282 struct drm_file *hyperz_filp;
1283 struct drm_file *cmask_filp;
1285 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1287 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1288 unsigned debugfs_count;
1291 int radeon_device_init(struct radeon_device *rdev,
1292 struct drm_device *ddev,
1293 struct pci_dev *pdev,
1295 void radeon_device_fini(struct radeon_device *rdev);
1296 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1298 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1299 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1300 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1301 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1306 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1309 * Registers read & write functions.
1311 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1312 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1313 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1314 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1315 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1316 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1317 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1318 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1319 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1320 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1321 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1322 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1323 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1324 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1325 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1326 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1327 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1328 #define WREG32_P(reg, val, mask) \
1330 uint32_t tmp_ = RREG32(reg); \
1332 tmp_ |= ((val) & ~(mask)); \
1333 WREG32(reg, tmp_); \
1335 #define WREG32_PLL_P(reg, val, mask) \
1337 uint32_t tmp_ = RREG32_PLL(reg); \
1339 tmp_ |= ((val) & ~(mask)); \
1340 WREG32_PLL(reg, tmp_); \
1342 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1343 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1344 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1347 * Indirect registers accessor
1349 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1353 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1354 r = RREG32(RADEON_PCIE_DATA);
1358 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1360 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1361 WREG32(RADEON_PCIE_DATA, (v));
1364 void r100_pll_errata_after_index(struct radeon_device *rdev);
1370 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1371 (rdev->pdev->device == 0x5969))
1372 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1373 (rdev->family == CHIP_RV200) || \
1374 (rdev->family == CHIP_RS100) || \
1375 (rdev->family == CHIP_RS200) || \
1376 (rdev->family == CHIP_RV250) || \
1377 (rdev->family == CHIP_RV280) || \
1378 (rdev->family == CHIP_RS300))
1379 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1380 (rdev->family == CHIP_RV350) || \
1381 (rdev->family == CHIP_R350) || \
1382 (rdev->family == CHIP_RV380) || \
1383 (rdev->family == CHIP_R420) || \
1384 (rdev->family == CHIP_R423) || \
1385 (rdev->family == CHIP_RV410) || \
1386 (rdev->family == CHIP_RS400) || \
1387 (rdev->family == CHIP_RS480))
1388 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1389 (rdev->ddev->pdev->device == 0x9443) || \
1390 (rdev->ddev->pdev->device == 0x944B) || \
1391 (rdev->ddev->pdev->device == 0x9506) || \
1392 (rdev->ddev->pdev->device == 0x9509) || \
1393 (rdev->ddev->pdev->device == 0x950F) || \
1394 (rdev->ddev->pdev->device == 0x689C) || \
1395 (rdev->ddev->pdev->device == 0x689D))
1396 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1397 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1398 (rdev->family == CHIP_RS690) || \
1399 (rdev->family == CHIP_RS740) || \
1400 (rdev->family >= CHIP_R600))
1401 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1402 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1403 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1404 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1405 (rdev->flags & RADEON_IS_IGP))
1406 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1411 #define RBIOS8(i) (rdev->bios[i])
1412 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1413 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1415 int radeon_combios_init(struct radeon_device *rdev);
1416 void radeon_combios_fini(struct radeon_device *rdev);
1417 int radeon_atombios_init(struct radeon_device *rdev);
1418 void radeon_atombios_fini(struct radeon_device *rdev);
1425 #if DRM_DEBUG_CODE == 0
1426 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1428 rdev->cp.ring[rdev->cp.wptr++] = v;
1429 rdev->cp.wptr &= rdev->cp.ptr_mask;
1430 rdev->cp.count_dw--;
1431 rdev->cp.ring_free_dw--;
1434 /* With debugging this is just too big to inline */
1435 void radeon_ring_write(struct radeon_device *rdev, uint32_t v);
1441 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1442 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1443 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1444 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1445 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1446 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1447 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1448 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1449 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1450 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1451 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1452 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1453 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1454 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1455 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1456 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1457 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1458 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1459 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1460 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1461 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1462 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1463 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1464 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1465 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1466 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1467 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1468 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1469 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1470 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1471 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1472 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1473 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1474 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1475 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1476 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1477 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1478 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1479 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1480 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1481 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1482 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1483 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1484 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1486 /* Common functions */
1488 extern int radeon_gpu_reset(struct radeon_device *rdev);
1489 extern void radeon_agp_disable(struct radeon_device *rdev);
1490 extern int radeon_modeset_init(struct radeon_device *rdev);
1491 extern void radeon_modeset_fini(struct radeon_device *rdev);
1492 extern bool radeon_card_posted(struct radeon_device *rdev);
1493 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1494 extern void radeon_update_display_priority(struct radeon_device *rdev);
1495 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1496 extern void radeon_scratch_init(struct radeon_device *rdev);
1497 extern void radeon_wb_fini(struct radeon_device *rdev);
1498 extern int radeon_wb_init(struct radeon_device *rdev);
1499 extern void radeon_wb_disable(struct radeon_device *rdev);
1500 extern void radeon_surface_init(struct radeon_device *rdev);
1501 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1502 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1503 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1504 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1505 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1506 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1507 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1508 extern int radeon_resume_kms(struct drm_device *dev);
1509 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1510 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1513 * R600 vram scratch functions
1515 int r600_vram_scratch_init(struct radeon_device *rdev);
1516 void r600_vram_scratch_fini(struct radeon_device *rdev);
1519 * r600 functions used by radeon_encoder.c
1521 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1522 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1523 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1525 extern int ni_init_microcode(struct radeon_device *rdev);
1526 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1529 #if defined(CONFIG_ACPI)
1530 extern int radeon_acpi_init(struct radeon_device *rdev);
1532 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1535 #include "radeon_object.h"