2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101 extern int radeon_runtime_pm;
102 extern int radeon_hard_reset;
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
108 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
110 /* RADEON_IB_POOL_SIZE must be a power of 2 */
111 #define RADEON_IB_POOL_SIZE 16
112 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
113 #define RADEONFB_CONN_LIMIT 4
114 #define RADEON_BIOS_NUM_SCRATCH 8
116 /* fence seq are set to this number when signaled */
117 #define RADEON_FENCE_SIGNALED_SEQ 0LL
119 /* internal ring indices */
120 /* r1xx+ has gfx CP ring */
121 #define RADEON_RING_TYPE_GFX_INDEX 0
123 /* cayman has 2 compute CP rings */
124 #define CAYMAN_RING_TYPE_CP1_INDEX 1
125 #define CAYMAN_RING_TYPE_CP2_INDEX 2
127 /* R600+ has an async dma ring */
128 #define R600_RING_TYPE_DMA_INDEX 3
129 /* cayman add a second async dma ring */
130 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
133 #define R600_RING_TYPE_UVD_INDEX 5
136 #define TN_RING_TYPE_VCE1_INDEX 6
137 #define TN_RING_TYPE_VCE2_INDEX 7
139 /* max number of rings */
140 #define RADEON_NUM_RINGS 8
142 /* number of hw syncs before falling back on blocking */
143 #define RADEON_NUM_SYNCS 4
145 /* number of hw syncs before falling back on blocking */
146 #define RADEON_NUM_SYNCS 4
148 /* hardcode those limit for now */
149 #define RADEON_VA_IB_OFFSET (1 << 20)
150 #define RADEON_VA_RESERVED_SIZE (8 << 20)
151 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
153 /* hard reset data */
154 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
157 #define RADEON_RESET_GFX (1 << 0)
158 #define RADEON_RESET_COMPUTE (1 << 1)
159 #define RADEON_RESET_DMA (1 << 2)
160 #define RADEON_RESET_CP (1 << 3)
161 #define RADEON_RESET_GRBM (1 << 4)
162 #define RADEON_RESET_DMA1 (1 << 5)
163 #define RADEON_RESET_RLC (1 << 6)
164 #define RADEON_RESET_SEM (1 << 7)
165 #define RADEON_RESET_IH (1 << 8)
166 #define RADEON_RESET_VMC (1 << 9)
167 #define RADEON_RESET_MC (1 << 10)
168 #define RADEON_RESET_DISPLAY (1 << 11)
171 #define RADEON_CG_BLOCK_GFX (1 << 0)
172 #define RADEON_CG_BLOCK_MC (1 << 1)
173 #define RADEON_CG_BLOCK_SDMA (1 << 2)
174 #define RADEON_CG_BLOCK_UVD (1 << 3)
175 #define RADEON_CG_BLOCK_VCE (1 << 4)
176 #define RADEON_CG_BLOCK_HDP (1 << 5)
177 #define RADEON_CG_BLOCK_BIF (1 << 6)
180 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
181 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
182 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
183 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
184 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
185 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
186 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
187 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
188 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
189 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
190 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
191 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
192 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
193 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
194 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
195 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
196 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
199 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
200 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
201 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
202 #define RADEON_PG_SUPPORT_UVD (1 << 3)
203 #define RADEON_PG_SUPPORT_VCE (1 << 4)
204 #define RADEON_PG_SUPPORT_CP (1 << 5)
205 #define RADEON_PG_SUPPORT_GDS (1 << 6)
206 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
207 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
208 #define RADEON_PG_SUPPORT_ACP (1 << 9)
209 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
211 /* max cursor sizes (in pixels) */
212 #define CURSOR_WIDTH 64
213 #define CURSOR_HEIGHT 64
215 #define CIK_CURSOR_WIDTH 128
216 #define CIK_CURSOR_HEIGHT 128
219 * Errata workarounds.
221 enum radeon_pll_errata {
222 CHIP_ERRATA_R300_CG = 0x00000001,
223 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
224 CHIP_ERRATA_PLL_DELAY = 0x00000004
228 struct radeon_device;
234 bool radeon_get_bios(struct radeon_device *rdev);
239 struct radeon_dummy_page {
243 int radeon_dummy_page_init(struct radeon_device *rdev);
244 void radeon_dummy_page_fini(struct radeon_device *rdev);
250 struct radeon_clock {
251 struct radeon_pll p1pll;
252 struct radeon_pll p2pll;
253 struct radeon_pll dcpll;
254 struct radeon_pll spll;
255 struct radeon_pll mpll;
257 uint32_t default_mclk;
258 uint32_t default_sclk;
259 uint32_t default_dispclk;
260 uint32_t current_dispclk;
262 uint32_t max_pixel_clock;
268 int radeon_pm_init(struct radeon_device *rdev);
269 int radeon_pm_late_init(struct radeon_device *rdev);
270 void radeon_pm_fini(struct radeon_device *rdev);
271 void radeon_pm_compute_clocks(struct radeon_device *rdev);
272 void radeon_pm_suspend(struct radeon_device *rdev);
273 void radeon_pm_resume(struct radeon_device *rdev);
274 void radeon_combios_get_power_modes(struct radeon_device *rdev);
275 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
276 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
280 struct atom_clock_dividers *dividers);
281 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
284 struct atom_mpll_param *mpll_param);
285 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
286 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
287 u16 voltage_level, u8 voltage_type,
288 u32 *gpio_value, u32 *gpio_mask);
289 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
290 u32 eng_clock, u32 mem_clock);
291 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
292 u8 voltage_type, u16 *voltage_step);
293 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
294 u16 voltage_id, u16 *voltage);
295 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
298 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
300 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
301 u16 *vddc, u16 *vddci,
302 u16 virtual_voltage_id,
303 u16 vbios_voltage_id);
304 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
308 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
309 u8 voltage_type, u16 *min_voltage);
310 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
311 u8 voltage_type, u16 *max_voltage);
312 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
313 u8 voltage_type, u8 voltage_mode,
314 struct atom_voltage_table *voltage_table);
315 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode);
317 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
319 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
321 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
323 struct atom_mc_reg_table *reg_table);
324 int radeon_atom_get_memory_info(struct radeon_device *rdev,
325 u8 module_index, struct atom_memory_info *mem_info);
326 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
327 bool gddr5, u8 module_index,
328 struct atom_memory_clock_range_table *mclk_range_table);
329 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
330 u16 voltage_id, u16 *voltage);
331 void rs690_pm_info(struct radeon_device *rdev);
332 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
333 unsigned *bankh, unsigned *mtaspect,
334 unsigned *tile_split);
339 struct radeon_fence_driver {
340 uint32_t scratch_reg;
342 volatile uint32_t *cpu_addr;
343 /* sync_seq is protected by ring emission lock */
344 uint64_t sync_seq[RADEON_NUM_RINGS];
349 struct radeon_fence {
350 struct radeon_device *rdev;
352 /* protected by radeon_fence.lock */
358 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
359 int radeon_fence_driver_init(struct radeon_device *rdev);
360 void radeon_fence_driver_fini(struct radeon_device *rdev);
361 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
362 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
363 void radeon_fence_process(struct radeon_device *rdev, int ring);
364 bool radeon_fence_signaled(struct radeon_fence *fence);
365 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
366 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
367 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
368 int radeon_fence_wait_any(struct radeon_device *rdev,
369 struct radeon_fence **fences,
371 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
372 void radeon_fence_unref(struct radeon_fence **fence);
373 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
374 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
375 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
376 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
377 struct radeon_fence *b)
387 BUG_ON(a->ring != b->ring);
389 if (a->seq > b->seq) {
396 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
397 struct radeon_fence *b)
407 BUG_ON(a->ring != b->ring);
409 return a->seq < b->seq;
415 struct radeon_surface_reg {
416 struct radeon_bo *bo;
419 #define RADEON_GEM_MAX_SURFACES 8
425 struct ttm_bo_global_ref bo_global_ref;
426 struct drm_global_reference mem_global_ref;
427 struct ttm_bo_device bdev;
428 bool mem_global_referenced;
431 #if defined(CONFIG_DEBUG_FS)
437 /* bo virtual address in a specific vm */
438 struct radeon_bo_va {
439 /* protected by bo being reserved */
440 struct list_head bo_list;
447 /* protected by vm mutex */
448 struct list_head vm_list;
450 /* constant after initialization */
451 struct radeon_vm *vm;
452 struct radeon_bo *bo;
456 /* Protected by gem.mutex */
457 struct list_head list;
458 /* Protected by tbo.reserved */
461 struct ttm_placement placement;
462 struct ttm_buffer_object tbo;
463 struct ttm_bo_kmap_obj kmap;
469 /* list of all virtual address to which this bo
473 /* Constant after initialization */
474 struct radeon_device *rdev;
475 struct drm_gem_object gem_base;
477 struct ttm_bo_kmap_obj dma_buf_vmap;
480 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
482 int radeon_gem_debugfs_init(struct radeon_device *rdev);
484 /* sub-allocation manager, it has to be protected by another lock.
485 * By conception this is an helper for other part of the driver
486 * like the indirect buffer or semaphore, which both have their
489 * Principe is simple, we keep a list of sub allocation in offset
490 * order (first entry has offset == 0, last entry has the highest
493 * When allocating new object we first check if there is room at
494 * the end total_size - (last_object_offset + last_object_size) >=
495 * alloc_size. If so we allocate new object there.
497 * When there is not enough room at the end, we start waiting for
498 * each sub object until we reach object_offset+object_size >=
499 * alloc_size, this object then become the sub object we return.
501 * Alignment can't be bigger than page size.
503 * Hole are not considered for allocation to keep things simple.
504 * Assumption is that there won't be hole (all object on same
507 struct radeon_sa_manager {
508 wait_queue_head_t wq;
509 struct radeon_bo *bo;
510 struct list_head *hole;
511 struct list_head flist[RADEON_NUM_RINGS];
512 struct list_head olist;
522 /* sub-allocation buffer */
523 struct radeon_sa_bo {
524 struct list_head olist;
525 struct list_head flist;
526 struct radeon_sa_manager *manager;
529 struct radeon_fence *fence;
537 struct list_head objects;
540 int radeon_gem_init(struct radeon_device *rdev);
541 void radeon_gem_fini(struct radeon_device *rdev);
542 int radeon_gem_object_create(struct radeon_device *rdev, int size,
543 int alignment, int initial_domain,
544 bool discardable, bool kernel,
545 struct drm_gem_object **obj);
547 int radeon_mode_dumb_create(struct drm_file *file_priv,
548 struct drm_device *dev,
549 struct drm_mode_create_dumb *args);
550 int radeon_mode_dumb_mmap(struct drm_file *filp,
551 struct drm_device *dev,
552 uint32_t handle, uint64_t *offset_p);
557 struct radeon_semaphore {
558 struct radeon_sa_bo *sa_bo;
561 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
564 int radeon_semaphore_create(struct radeon_device *rdev,
565 struct radeon_semaphore **semaphore);
566 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
567 struct radeon_semaphore *semaphore);
568 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
569 struct radeon_semaphore *semaphore);
570 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
571 struct radeon_fence *fence);
572 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
573 struct radeon_semaphore *semaphore,
575 void radeon_semaphore_free(struct radeon_device *rdev,
576 struct radeon_semaphore **semaphore,
577 struct radeon_fence *fence);
580 * GART structures, functions & helpers
584 #define RADEON_GPU_PAGE_SIZE 4096
585 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
586 #define RADEON_GPU_PAGE_SHIFT 12
587 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
590 dma_addr_t table_addr;
591 struct radeon_bo *robj;
593 unsigned num_gpu_pages;
594 unsigned num_cpu_pages;
597 dma_addr_t *pages_addr;
601 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
602 void radeon_gart_table_ram_free(struct radeon_device *rdev);
603 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
604 void radeon_gart_table_vram_free(struct radeon_device *rdev);
605 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
606 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
607 int radeon_gart_init(struct radeon_device *rdev);
608 void radeon_gart_fini(struct radeon_device *rdev);
609 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
611 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
612 int pages, struct page **pagelist,
613 dma_addr_t *dma_addr);
614 void radeon_gart_restore(struct radeon_device *rdev);
618 * GPU MC structures, functions & helpers
621 resource_size_t aper_size;
622 resource_size_t aper_base;
623 resource_size_t agp_base;
624 /* for some chips with <= 32MB we need to lie
625 * about vram size near mc fb location */
627 u64 visible_vram_size;
637 bool igp_sideport_enabled;
642 bool radeon_combios_sideport_present(struct radeon_device *rdev);
643 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
646 * GPU scratch registers structures, functions & helpers
648 struct radeon_scratch {
655 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
656 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
659 * GPU doorbell structures, functions & helpers
661 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
663 struct radeon_doorbell {
665 resource_size_t base;
666 resource_size_t size;
668 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
669 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
672 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
673 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
679 struct radeon_unpin_work {
680 struct work_struct work;
681 struct radeon_device *rdev;
683 struct radeon_fence *fence;
684 struct drm_pending_vblank_event *event;
685 struct radeon_bo *old_rbo;
689 struct r500_irq_stat_regs {
694 struct r600_irq_stat_regs {
704 struct evergreen_irq_stat_regs {
725 struct cik_irq_stat_regs {
741 union radeon_irq_stat_regs {
742 struct r500_irq_stat_regs r500;
743 struct r600_irq_stat_regs r600;
744 struct evergreen_irq_stat_regs evergreen;
745 struct cik_irq_stat_regs cik;
748 #define RADEON_MAX_HPD_PINS 7
749 #define RADEON_MAX_CRTCS 6
750 #define RADEON_MAX_AFMT_BLOCKS 7
755 atomic_t ring_int[RADEON_NUM_RINGS];
756 bool crtc_vblank_int[RADEON_MAX_CRTCS];
757 atomic_t pflip[RADEON_MAX_CRTCS];
758 wait_queue_head_t vblank_queue;
759 bool hpd[RADEON_MAX_HPD_PINS];
760 bool afmt[RADEON_MAX_AFMT_BLOCKS];
761 union radeon_irq_stat_regs stat_regs;
765 int radeon_irq_kms_init(struct radeon_device *rdev);
766 void radeon_irq_kms_fini(struct radeon_device *rdev);
767 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
768 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
769 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
770 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
771 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
772 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
773 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
774 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
781 struct radeon_sa_bo *sa_bo;
786 struct radeon_fence *fence;
787 struct radeon_vm *vm;
789 struct radeon_semaphore *semaphore;
793 struct radeon_bo *ring_obj;
794 volatile uint32_t *ring;
796 unsigned rptr_save_reg;
797 u64 next_rptr_gpu_addr;
798 volatile u32 *next_rptr_cpu_addr;
802 unsigned ring_free_dw;
805 atomic64_t last_activity;
812 u64 last_semaphore_signal_addr;
813 u64 last_semaphore_wait_addr;
818 struct radeon_bo *mqd_obj;
824 struct radeon_bo *hpd_eop_obj;
825 u64 hpd_eop_gpu_addr;
835 /* maximum number of VMIDs */
836 #define RADEON_NUM_VM 16
838 /* defines number of bits in page table versus page directory,
839 * a page is 4KB so we have 12 bits offset, 9 bits in the page
840 * table and the remaining 19 bits are in the page directory */
841 #define RADEON_VM_BLOCK_SIZE 9
843 /* number of entries in page table */
844 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
846 /* PTBs (Page Table Blocks) need to be aligned to 32K */
847 #define RADEON_VM_PTB_ALIGN_SIZE 32768
848 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
849 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
851 #define R600_PTE_VALID (1 << 0)
852 #define R600_PTE_SYSTEM (1 << 1)
853 #define R600_PTE_SNOOPED (1 << 2)
854 #define R600_PTE_READABLE (1 << 5)
855 #define R600_PTE_WRITEABLE (1 << 6)
857 struct radeon_vm_pt {
858 struct radeon_bo *bo;
866 /* contains the page directory */
867 struct radeon_bo *page_directory;
868 uint64_t pd_gpu_addr;
869 unsigned max_pde_used;
871 /* array of page tables, one for each page directory entry */
872 struct radeon_vm_pt *page_tables;
875 /* last fence for cs using this vm */
876 struct radeon_fence *fence;
877 /* last flush or NULL if we still need to flush */
878 struct radeon_fence *last_flush;
879 /* last use of vmid */
880 struct radeon_fence *last_id_use;
883 struct radeon_vm_manager {
884 struct radeon_fence *active[RADEON_NUM_VM];
886 /* number of VMIDs */
888 /* vram base address for page table entry */
889 u64 vram_base_offset;
895 * file private structure
897 struct radeon_fpriv {
905 struct radeon_bo *ring_obj;
906 volatile uint32_t *ring;
918 #include "clearstate_defs.h"
921 /* for power gating */
922 struct radeon_bo *save_restore_obj;
923 uint64_t save_restore_gpu_addr;
924 volatile uint32_t *sr_ptr;
927 /* for clear state */
928 struct radeon_bo *clear_state_obj;
929 uint64_t clear_state_gpu_addr;
930 volatile uint32_t *cs_ptr;
931 const struct cs_section_def *cs_data;
932 u32 clear_state_size;
934 struct radeon_bo *cp_table_obj;
935 uint64_t cp_table_gpu_addr;
936 volatile uint32_t *cp_table_ptr;
940 int radeon_ib_get(struct radeon_device *rdev, int ring,
941 struct radeon_ib *ib, struct radeon_vm *vm,
943 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
944 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
945 struct radeon_ib *const_ib);
946 int radeon_ib_pool_init(struct radeon_device *rdev);
947 void radeon_ib_pool_fini(struct radeon_device *rdev);
948 int radeon_ib_ring_tests(struct radeon_device *rdev);
949 /* Ring access between begin & end cannot sleep */
950 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
951 struct radeon_ring *ring);
952 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
953 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
954 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
955 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
956 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
957 void radeon_ring_undo(struct radeon_ring *ring);
958 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
959 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
960 void radeon_ring_lockup_update(struct radeon_device *rdev,
961 struct radeon_ring *ring);
962 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
963 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
965 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
966 unsigned size, uint32_t *data);
967 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
968 unsigned rptr_offs, u32 nop);
969 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
973 void r600_dma_stop(struct radeon_device *rdev);
974 int r600_dma_resume(struct radeon_device *rdev);
975 void r600_dma_fini(struct radeon_device *rdev);
977 void cayman_dma_stop(struct radeon_device *rdev);
978 int cayman_dma_resume(struct radeon_device *rdev);
979 void cayman_dma_fini(struct radeon_device *rdev);
984 struct radeon_cs_reloc {
985 struct drm_gem_object *gobj;
986 struct radeon_bo *robj;
987 struct ttm_validate_buffer tv;
991 uint32_t tiling_flags;
995 struct radeon_cs_chunk {
999 void __user *user_ptr;
1002 struct radeon_cs_parser {
1004 struct radeon_device *rdev;
1005 struct drm_file *filp;
1008 struct radeon_cs_chunk *chunks;
1009 uint64_t *chunks_array;
1014 struct radeon_cs_reloc *relocs;
1015 struct radeon_cs_reloc **relocs_ptr;
1016 struct radeon_cs_reloc *vm_bos;
1017 struct list_head validated;
1018 unsigned dma_reloc_idx;
1019 /* indices of various chunks */
1021 int chunk_relocs_idx;
1022 int chunk_flags_idx;
1023 int chunk_const_ib_idx;
1024 struct radeon_ib ib;
1025 struct radeon_ib const_ib;
1032 struct ww_acquire_ctx ticket;
1035 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1037 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1040 return ibc->kdata[idx];
1041 return p->ib.ptr[idx];
1045 struct radeon_cs_packet {
1051 unsigned one_reg_wr;
1054 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1055 struct radeon_cs_packet *pkt,
1056 unsigned idx, unsigned reg);
1057 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1058 struct radeon_cs_packet *pkt);
1064 int radeon_agp_init(struct radeon_device *rdev);
1065 void radeon_agp_resume(struct radeon_device *rdev);
1066 void radeon_agp_suspend(struct radeon_device *rdev);
1067 void radeon_agp_fini(struct radeon_device *rdev);
1074 struct radeon_bo *wb_obj;
1075 volatile uint32_t *wb;
1081 #define RADEON_WB_SCRATCH_OFFSET 0
1082 #define RADEON_WB_RING0_NEXT_RPTR 256
1083 #define RADEON_WB_CP_RPTR_OFFSET 1024
1084 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1085 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1086 #define R600_WB_DMA_RPTR_OFFSET 1792
1087 #define R600_WB_IH_WPTR_OFFSET 2048
1088 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1089 #define R600_WB_EVENT_OFFSET 3072
1090 #define CIK_WB_CP1_WPTR_OFFSET 3328
1091 #define CIK_WB_CP2_WPTR_OFFSET 3584
1094 * struct radeon_pm - power management datas
1095 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1096 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1097 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1098 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1099 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1100 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1101 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1102 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1103 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1104 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1105 * @needed_bandwidth: current bandwidth needs
1107 * It keeps track of various data needed to take powermanagement decision.
1108 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1109 * Equation between gpu/memory clock and available bandwidth is hw dependent
1110 * (type of memory, bus size, efficiency, ...)
1113 enum radeon_pm_method {
1119 enum radeon_dynpm_state {
1120 DYNPM_STATE_DISABLED,
1121 DYNPM_STATE_MINIMUM,
1124 DYNPM_STATE_SUSPENDED,
1126 enum radeon_dynpm_action {
1128 DYNPM_ACTION_MINIMUM,
1129 DYNPM_ACTION_DOWNCLOCK,
1130 DYNPM_ACTION_UPCLOCK,
1131 DYNPM_ACTION_DEFAULT
1134 enum radeon_voltage_type {
1141 enum radeon_pm_state_type {
1142 /* not used for dpm */
1143 POWER_STATE_TYPE_DEFAULT,
1144 POWER_STATE_TYPE_POWERSAVE,
1145 /* user selectable states */
1146 POWER_STATE_TYPE_BATTERY,
1147 POWER_STATE_TYPE_BALANCED,
1148 POWER_STATE_TYPE_PERFORMANCE,
1149 /* internal states */
1150 POWER_STATE_TYPE_INTERNAL_UVD,
1151 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1152 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1153 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1154 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1155 POWER_STATE_TYPE_INTERNAL_BOOT,
1156 POWER_STATE_TYPE_INTERNAL_THERMAL,
1157 POWER_STATE_TYPE_INTERNAL_ACPI,
1158 POWER_STATE_TYPE_INTERNAL_ULV,
1159 POWER_STATE_TYPE_INTERNAL_3DPERF,
1162 enum radeon_pm_profile_type {
1170 #define PM_PROFILE_DEFAULT_IDX 0
1171 #define PM_PROFILE_LOW_SH_IDX 1
1172 #define PM_PROFILE_MID_SH_IDX 2
1173 #define PM_PROFILE_HIGH_SH_IDX 3
1174 #define PM_PROFILE_LOW_MH_IDX 4
1175 #define PM_PROFILE_MID_MH_IDX 5
1176 #define PM_PROFILE_HIGH_MH_IDX 6
1177 #define PM_PROFILE_MAX 7
1179 struct radeon_pm_profile {
1180 int dpms_off_ps_idx;
1182 int dpms_off_cm_idx;
1186 enum radeon_int_thermal_type {
1188 THERMAL_TYPE_EXTERNAL,
1189 THERMAL_TYPE_EXTERNAL_GPIO,
1192 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1193 THERMAL_TYPE_EVERGREEN,
1197 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1202 struct radeon_voltage {
1203 enum radeon_voltage_type type;
1205 struct radeon_gpio_rec gpio;
1206 u32 delay; /* delay in usec from voltage drop to sclk change */
1207 bool active_high; /* voltage drop is active when bit is high */
1209 u8 vddc_id; /* index into vddc voltage table */
1210 u8 vddci_id; /* index into vddci voltage table */
1214 /* evergreen+ vddci */
1218 /* clock mode flags */
1219 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1221 struct radeon_pm_clock_info {
1227 struct radeon_voltage voltage;
1228 /* standardized clock flags */
1233 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1235 struct radeon_power_state {
1236 enum radeon_pm_state_type type;
1237 struct radeon_pm_clock_info *clock_info;
1238 /* number of valid clock modes in this power state */
1239 int num_clock_modes;
1240 struct radeon_pm_clock_info *default_clock_mode;
1241 /* standardized state flags */
1243 u32 misc; /* vbios specific flags */
1244 u32 misc2; /* vbios specific flags */
1245 int pcie_lanes; /* pcie lanes */
1249 * Some modes are overclocked by very low value, accept them
1251 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1253 enum radeon_dpm_auto_throttle_src {
1254 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1255 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1258 enum radeon_dpm_event_src {
1259 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1260 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1261 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1262 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1263 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1266 #define RADEON_MAX_VCE_LEVELS 6
1268 enum radeon_vce_level {
1269 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1270 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1271 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1272 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1273 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1274 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1278 u32 caps; /* vbios flags */
1279 u32 class; /* vbios flags */
1280 u32 class2; /* vbios flags */
1288 enum radeon_vce_level vce_level;
1293 struct radeon_dpm_thermal {
1294 /* thermal interrupt work */
1295 struct work_struct work;
1296 /* low temperature threshold */
1298 /* high temperature threshold */
1300 /* was interrupt low to high or high to low */
1304 enum radeon_clk_action
1310 struct radeon_blacklist_clocks
1314 enum radeon_clk_action action;
1317 struct radeon_clock_and_voltage_limits {
1324 struct radeon_clock_array {
1329 struct radeon_clock_voltage_dependency_entry {
1334 struct radeon_clock_voltage_dependency_table {
1336 struct radeon_clock_voltage_dependency_entry *entries;
1339 union radeon_cac_leakage_entry {
1351 struct radeon_cac_leakage_table {
1353 union radeon_cac_leakage_entry *entries;
1356 struct radeon_phase_shedding_limits_entry {
1362 struct radeon_phase_shedding_limits_table {
1364 struct radeon_phase_shedding_limits_entry *entries;
1367 struct radeon_uvd_clock_voltage_dependency_entry {
1373 struct radeon_uvd_clock_voltage_dependency_table {
1375 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1378 struct radeon_vce_clock_voltage_dependency_entry {
1384 struct radeon_vce_clock_voltage_dependency_table {
1386 struct radeon_vce_clock_voltage_dependency_entry *entries;
1389 struct radeon_ppm_table {
1391 u16 cpu_core_number;
1393 u32 small_ac_platform_tdp;
1395 u32 small_ac_platform_tdc;
1402 struct radeon_cac_tdp_table {
1404 u16 configurable_tdp;
1406 u16 battery_power_limit;
1407 u16 small_power_limit;
1408 u16 low_cac_leakage;
1409 u16 high_cac_leakage;
1410 u16 maximum_power_delivery_limit;
1413 struct radeon_dpm_dynamic_state {
1414 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1415 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1416 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1417 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1418 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1419 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1420 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1421 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1422 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1423 struct radeon_clock_array valid_sclk_values;
1424 struct radeon_clock_array valid_mclk_values;
1425 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1426 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1427 u32 mclk_sclk_ratio;
1428 u32 sclk_mclk_delta;
1429 u16 vddc_vddci_delta;
1430 u16 min_vddc_for_pcie_gen2;
1431 struct radeon_cac_leakage_table cac_leakage_table;
1432 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1433 struct radeon_ppm_table *ppm_table;
1434 struct radeon_cac_tdp_table *cac_tdp_table;
1437 struct radeon_dpm_fan {
1447 bool ucode_fan_control;
1450 enum radeon_pcie_gen {
1451 RADEON_PCIE_GEN1 = 0,
1452 RADEON_PCIE_GEN2 = 1,
1453 RADEON_PCIE_GEN3 = 2,
1454 RADEON_PCIE_GEN_INVALID = 0xffff
1457 enum radeon_dpm_forced_level {
1458 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1459 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1460 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1463 struct radeon_vce_state {
1475 struct radeon_ps *ps;
1476 /* number of valid power states */
1478 /* current power state that is active */
1479 struct radeon_ps *current_ps;
1480 /* requested power state */
1481 struct radeon_ps *requested_ps;
1482 /* boot up power state */
1483 struct radeon_ps *boot_ps;
1484 /* default uvd power state */
1485 struct radeon_ps *uvd_ps;
1486 /* vce requirements */
1487 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1488 enum radeon_vce_level vce_level;
1489 enum radeon_pm_state_type state;
1490 enum radeon_pm_state_type user_state;
1492 u32 voltage_response_time;
1493 u32 backbias_response_time;
1495 u32 new_active_crtcs;
1496 int new_active_crtc_count;
1497 u32 current_active_crtcs;
1498 int current_active_crtc_count;
1499 struct radeon_dpm_dynamic_state dyn_state;
1500 struct radeon_dpm_fan fan;
1503 u32 near_tdp_limit_adjusted;
1504 u32 sq_ramping_threshold;
1508 u16 load_line_slope;
1511 /* special states active */
1512 bool thermal_active;
1515 /* thermal handling */
1516 struct radeon_dpm_thermal thermal;
1518 enum radeon_dpm_forced_level forced_level;
1519 /* track UVD streams */
1524 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1525 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1529 /* write locked while reprogramming mclk */
1530 struct rw_semaphore mclk_lock;
1532 int active_crtc_count;
1535 fixed20_12 max_bandwidth;
1536 fixed20_12 igp_sideport_mclk;
1537 fixed20_12 igp_system_mclk;
1538 fixed20_12 igp_ht_link_clk;
1539 fixed20_12 igp_ht_link_width;
1540 fixed20_12 k8_bandwidth;
1541 fixed20_12 sideport_bandwidth;
1542 fixed20_12 ht_bandwidth;
1543 fixed20_12 core_bandwidth;
1546 fixed20_12 needed_bandwidth;
1547 struct radeon_power_state *power_state;
1548 /* number of valid power states */
1549 int num_power_states;
1550 int current_power_state_index;
1551 int current_clock_mode_index;
1552 int requested_power_state_index;
1553 int requested_clock_mode_index;
1554 int default_power_state_index;
1563 struct radeon_i2c_chan *i2c_bus;
1564 /* selected pm method */
1565 enum radeon_pm_method pm_method;
1566 /* dynpm power management */
1567 struct delayed_work dynpm_idle_work;
1568 enum radeon_dynpm_state dynpm_state;
1569 enum radeon_dynpm_action dynpm_planned_action;
1570 unsigned long dynpm_action_timeout;
1571 bool dynpm_can_upclock;
1572 bool dynpm_can_downclock;
1573 /* profile-based power management */
1574 enum radeon_pm_profile_type profile;
1576 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1577 /* internal thermal controller on rv6xx+ */
1578 enum radeon_int_thermal_type int_thermal_type;
1579 struct device *int_hwmon_dev;
1582 struct radeon_dpm dpm;
1585 int radeon_pm_get_type_index(struct radeon_device *rdev,
1586 enum radeon_pm_state_type ps_type,
1591 #define RADEON_MAX_UVD_HANDLES 10
1592 #define RADEON_UVD_STACK_SIZE (1024*1024)
1593 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1596 struct radeon_bo *vcpu_bo;
1600 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1601 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1602 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1603 struct delayed_work idle_work;
1606 int radeon_uvd_init(struct radeon_device *rdev);
1607 void radeon_uvd_fini(struct radeon_device *rdev);
1608 int radeon_uvd_suspend(struct radeon_device *rdev);
1609 int radeon_uvd_resume(struct radeon_device *rdev);
1610 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1611 uint32_t handle, struct radeon_fence **fence);
1612 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1613 uint32_t handle, struct radeon_fence **fence);
1614 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1615 void radeon_uvd_free_handles(struct radeon_device *rdev,
1616 struct drm_file *filp);
1617 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1618 void radeon_uvd_note_usage(struct radeon_device *rdev);
1619 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1620 unsigned vclk, unsigned dclk,
1621 unsigned vco_min, unsigned vco_max,
1622 unsigned fb_factor, unsigned fb_mask,
1623 unsigned pd_min, unsigned pd_max,
1625 unsigned *optimal_fb_div,
1626 unsigned *optimal_vclk_div,
1627 unsigned *optimal_dclk_div);
1628 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1629 unsigned cg_upll_func_cntl);
1634 #define RADEON_MAX_VCE_HANDLES 16
1635 #define RADEON_VCE_STACK_SIZE (1024*1024)
1636 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1639 struct radeon_bo *vcpu_bo;
1641 unsigned fw_version;
1642 unsigned fb_version;
1643 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1644 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1645 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1646 struct delayed_work idle_work;
1649 int radeon_vce_init(struct radeon_device *rdev);
1650 void radeon_vce_fini(struct radeon_device *rdev);
1651 int radeon_vce_suspend(struct radeon_device *rdev);
1652 int radeon_vce_resume(struct radeon_device *rdev);
1653 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1654 uint32_t handle, struct radeon_fence **fence);
1655 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1656 uint32_t handle, struct radeon_fence **fence);
1657 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1658 void radeon_vce_note_usage(struct radeon_device *rdev);
1659 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1660 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1661 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1662 struct radeon_ring *ring,
1663 struct radeon_semaphore *semaphore,
1665 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1666 void radeon_vce_fence_emit(struct radeon_device *rdev,
1667 struct radeon_fence *fence);
1668 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1669 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1671 struct r600_audio_pin {
1674 int bits_per_sample;
1684 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1691 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1697 void radeon_test_moves(struct radeon_device *rdev);
1698 void radeon_test_ring_sync(struct radeon_device *rdev,
1699 struct radeon_ring *cpA,
1700 struct radeon_ring *cpB);
1701 void radeon_test_syncing(struct radeon_device *rdev);
1707 struct radeon_debugfs {
1708 struct drm_info_list *files;
1712 int radeon_debugfs_add_files(struct radeon_device *rdev,
1713 struct drm_info_list *files,
1715 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1718 * ASIC ring specific functions.
1720 struct radeon_asic_ring {
1721 /* ring read/write ptr handling */
1722 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1723 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1724 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1726 /* validating and patching of IBs */
1727 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1728 int (*cs_parse)(struct radeon_cs_parser *p);
1730 /* command emmit functions */
1731 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1732 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1733 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1734 struct radeon_semaphore *semaphore, bool emit_wait);
1735 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1737 /* testing functions */
1738 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1739 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1740 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1743 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1747 * ASIC specific functions.
1749 struct radeon_asic {
1750 int (*init)(struct radeon_device *rdev);
1751 void (*fini)(struct radeon_device *rdev);
1752 int (*resume)(struct radeon_device *rdev);
1753 int (*suspend)(struct radeon_device *rdev);
1754 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1755 int (*asic_reset)(struct radeon_device *rdev);
1756 /* ioctl hw specific callback. Some hw might want to perform special
1757 * operation on specific ioctl. For instance on wait idle some hw
1758 * might want to perform and HDP flush through MMIO as it seems that
1759 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1762 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1763 /* check if 3D engine is idle */
1764 bool (*gui_idle)(struct radeon_device *rdev);
1765 /* wait for mc_idle */
1766 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1767 /* get the reference clock */
1768 u32 (*get_xclk)(struct radeon_device *rdev);
1769 /* get the gpu clock counter */
1770 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1773 void (*tlb_flush)(struct radeon_device *rdev);
1774 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1777 int (*init)(struct radeon_device *rdev);
1778 void (*fini)(struct radeon_device *rdev);
1779 void (*set_page)(struct radeon_device *rdev,
1780 struct radeon_ib *ib,
1782 uint64_t addr, unsigned count,
1783 uint32_t incr, uint32_t flags);
1785 /* ring specific callbacks */
1786 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1789 int (*set)(struct radeon_device *rdev);
1790 int (*process)(struct radeon_device *rdev);
1794 /* display watermarks */
1795 void (*bandwidth_update)(struct radeon_device *rdev);
1796 /* get frame count */
1797 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1798 /* wait for vblank */
1799 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1800 /* set backlight level */
1801 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1802 /* get backlight level */
1803 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1804 /* audio callbacks */
1805 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1806 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1808 /* copy functions for bo handling */
1810 int (*blit)(struct radeon_device *rdev,
1811 uint64_t src_offset,
1812 uint64_t dst_offset,
1813 unsigned num_gpu_pages,
1814 struct radeon_fence **fence);
1815 u32 blit_ring_index;
1816 int (*dma)(struct radeon_device *rdev,
1817 uint64_t src_offset,
1818 uint64_t dst_offset,
1819 unsigned num_gpu_pages,
1820 struct radeon_fence **fence);
1822 /* method used for bo copy */
1823 int (*copy)(struct radeon_device *rdev,
1824 uint64_t src_offset,
1825 uint64_t dst_offset,
1826 unsigned num_gpu_pages,
1827 struct radeon_fence **fence);
1828 /* ring used for bo copies */
1829 u32 copy_ring_index;
1833 int (*set_reg)(struct radeon_device *rdev, int reg,
1834 uint32_t tiling_flags, uint32_t pitch,
1835 uint32_t offset, uint32_t obj_size);
1836 void (*clear_reg)(struct radeon_device *rdev, int reg);
1838 /* hotplug detect */
1840 void (*init)(struct radeon_device *rdev);
1841 void (*fini)(struct radeon_device *rdev);
1842 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1843 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1845 /* static power management */
1847 void (*misc)(struct radeon_device *rdev);
1848 void (*prepare)(struct radeon_device *rdev);
1849 void (*finish)(struct radeon_device *rdev);
1850 void (*init_profile)(struct radeon_device *rdev);
1851 void (*get_dynpm_state)(struct radeon_device *rdev);
1852 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1853 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1854 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1855 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1856 int (*get_pcie_lanes)(struct radeon_device *rdev);
1857 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1858 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1859 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1860 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1861 int (*get_temperature)(struct radeon_device *rdev);
1863 /* dynamic power management */
1865 int (*init)(struct radeon_device *rdev);
1866 void (*setup_asic)(struct radeon_device *rdev);
1867 int (*enable)(struct radeon_device *rdev);
1868 int (*late_enable)(struct radeon_device *rdev);
1869 void (*disable)(struct radeon_device *rdev);
1870 int (*pre_set_power_state)(struct radeon_device *rdev);
1871 int (*set_power_state)(struct radeon_device *rdev);
1872 void (*post_set_power_state)(struct radeon_device *rdev);
1873 void (*display_configuration_changed)(struct radeon_device *rdev);
1874 void (*fini)(struct radeon_device *rdev);
1875 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1876 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1877 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1878 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1879 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1880 bool (*vblank_too_short)(struct radeon_device *rdev);
1881 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1882 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1886 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1887 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1888 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1896 const unsigned *reg_safe_bm;
1897 unsigned reg_safe_bm_size;
1902 const unsigned *reg_safe_bm;
1903 unsigned reg_safe_bm_size;
1910 unsigned max_tile_pipes;
1912 unsigned max_backends;
1914 unsigned max_threads;
1915 unsigned max_stack_entries;
1916 unsigned max_hw_contexts;
1917 unsigned max_gs_threads;
1918 unsigned sx_max_export_size;
1919 unsigned sx_max_export_pos_size;
1920 unsigned sx_max_export_smx_size;
1921 unsigned sq_num_cf_insts;
1922 unsigned tiling_nbanks;
1923 unsigned tiling_npipes;
1924 unsigned tiling_group_size;
1925 unsigned tile_config;
1926 unsigned backend_map;
1931 unsigned max_tile_pipes;
1933 unsigned max_backends;
1935 unsigned max_threads;
1936 unsigned max_stack_entries;
1937 unsigned max_hw_contexts;
1938 unsigned max_gs_threads;
1939 unsigned sx_max_export_size;
1940 unsigned sx_max_export_pos_size;
1941 unsigned sx_max_export_smx_size;
1942 unsigned sq_num_cf_insts;
1943 unsigned sx_num_of_sets;
1944 unsigned sc_prim_fifo_size;
1945 unsigned sc_hiz_tile_fifo_size;
1946 unsigned sc_earlyz_tile_fifo_fize;
1947 unsigned tiling_nbanks;
1948 unsigned tiling_npipes;
1949 unsigned tiling_group_size;
1950 unsigned tile_config;
1951 unsigned backend_map;
1954 struct evergreen_asic {
1957 unsigned max_tile_pipes;
1959 unsigned max_backends;
1961 unsigned max_threads;
1962 unsigned max_stack_entries;
1963 unsigned max_hw_contexts;
1964 unsigned max_gs_threads;
1965 unsigned sx_max_export_size;
1966 unsigned sx_max_export_pos_size;
1967 unsigned sx_max_export_smx_size;
1968 unsigned sq_num_cf_insts;
1969 unsigned sx_num_of_sets;
1970 unsigned sc_prim_fifo_size;
1971 unsigned sc_hiz_tile_fifo_size;
1972 unsigned sc_earlyz_tile_fifo_size;
1973 unsigned tiling_nbanks;
1974 unsigned tiling_npipes;
1975 unsigned tiling_group_size;
1976 unsigned tile_config;
1977 unsigned backend_map;
1980 struct cayman_asic {
1981 unsigned max_shader_engines;
1982 unsigned max_pipes_per_simd;
1983 unsigned max_tile_pipes;
1984 unsigned max_simds_per_se;
1985 unsigned max_backends_per_se;
1986 unsigned max_texture_channel_caches;
1988 unsigned max_threads;
1989 unsigned max_gs_threads;
1990 unsigned max_stack_entries;
1991 unsigned sx_num_of_sets;
1992 unsigned sx_max_export_size;
1993 unsigned sx_max_export_pos_size;
1994 unsigned sx_max_export_smx_size;
1995 unsigned max_hw_contexts;
1996 unsigned sq_num_cf_insts;
1997 unsigned sc_prim_fifo_size;
1998 unsigned sc_hiz_tile_fifo_size;
1999 unsigned sc_earlyz_tile_fifo_size;
2001 unsigned num_shader_engines;
2002 unsigned num_shader_pipes_per_simd;
2003 unsigned num_tile_pipes;
2004 unsigned num_simds_per_se;
2005 unsigned num_backends_per_se;
2006 unsigned backend_disable_mask_per_asic;
2007 unsigned backend_map;
2008 unsigned num_texture_channel_caches;
2009 unsigned mem_max_burst_length_bytes;
2010 unsigned mem_row_size_in_kb;
2011 unsigned shader_engine_tile_size;
2013 unsigned multi_gpu_tile_size;
2015 unsigned tile_config;
2019 unsigned max_shader_engines;
2020 unsigned max_tile_pipes;
2021 unsigned max_cu_per_sh;
2022 unsigned max_sh_per_se;
2023 unsigned max_backends_per_se;
2024 unsigned max_texture_channel_caches;
2026 unsigned max_gs_threads;
2027 unsigned max_hw_contexts;
2028 unsigned sc_prim_fifo_size_frontend;
2029 unsigned sc_prim_fifo_size_backend;
2030 unsigned sc_hiz_tile_fifo_size;
2031 unsigned sc_earlyz_tile_fifo_size;
2033 unsigned num_tile_pipes;
2034 unsigned backend_enable_mask;
2035 unsigned backend_disable_mask_per_asic;
2036 unsigned backend_map;
2037 unsigned num_texture_channel_caches;
2038 unsigned mem_max_burst_length_bytes;
2039 unsigned mem_row_size_in_kb;
2040 unsigned shader_engine_tile_size;
2042 unsigned multi_gpu_tile_size;
2044 unsigned tile_config;
2045 uint32_t tile_mode_array[32];
2049 unsigned max_shader_engines;
2050 unsigned max_tile_pipes;
2051 unsigned max_cu_per_sh;
2052 unsigned max_sh_per_se;
2053 unsigned max_backends_per_se;
2054 unsigned max_texture_channel_caches;
2056 unsigned max_gs_threads;
2057 unsigned max_hw_contexts;
2058 unsigned sc_prim_fifo_size_frontend;
2059 unsigned sc_prim_fifo_size_backend;
2060 unsigned sc_hiz_tile_fifo_size;
2061 unsigned sc_earlyz_tile_fifo_size;
2063 unsigned num_tile_pipes;
2064 unsigned backend_enable_mask;
2065 unsigned backend_disable_mask_per_asic;
2066 unsigned backend_map;
2067 unsigned num_texture_channel_caches;
2068 unsigned mem_max_burst_length_bytes;
2069 unsigned mem_row_size_in_kb;
2070 unsigned shader_engine_tile_size;
2072 unsigned multi_gpu_tile_size;
2074 unsigned tile_config;
2075 uint32_t tile_mode_array[32];
2076 uint32_t macrotile_mode_array[16];
2079 union radeon_asic_config {
2080 struct r300_asic r300;
2081 struct r100_asic r100;
2082 struct r600_asic r600;
2083 struct rv770_asic rv770;
2084 struct evergreen_asic evergreen;
2085 struct cayman_asic cayman;
2087 struct cik_asic cik;
2091 * asic initizalization from radeon_asic.c
2093 void radeon_agp_disable(struct radeon_device *rdev);
2094 int radeon_asic_init(struct radeon_device *rdev);
2100 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2101 struct drm_file *filp);
2102 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2103 struct drm_file *filp);
2104 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2105 struct drm_file *file_priv);
2106 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2107 struct drm_file *file_priv);
2108 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *file_priv);
2110 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2111 struct drm_file *file_priv);
2112 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *filp);
2114 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *filp);
2116 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2117 struct drm_file *filp);
2118 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *filp);
2120 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2121 struct drm_file *filp);
2122 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2123 struct drm_file *filp);
2124 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2125 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2126 struct drm_file *filp);
2127 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2128 struct drm_file *filp);
2130 /* VRAM scratch page for HDP bug, default vram page */
2131 struct r600_vram_scratch {
2132 struct radeon_bo *robj;
2133 volatile uint32_t *ptr;
2140 struct radeon_atif_notification_cfg {
2145 struct radeon_atif_notifications {
2146 bool display_switch;
2147 bool expansion_mode_change;
2149 bool forced_power_state;
2150 bool system_power_state;
2151 bool display_conf_change;
2153 bool brightness_change;
2154 bool dgpu_display_event;
2157 struct radeon_atif_functions {
2159 bool sbios_requests;
2160 bool select_active_disp;
2162 bool get_tv_standard;
2163 bool set_tv_standard;
2164 bool get_panel_expansion_mode;
2165 bool set_panel_expansion_mode;
2166 bool temperature_change;
2167 bool graphics_device_types;
2170 struct radeon_atif {
2171 struct radeon_atif_notifications notifications;
2172 struct radeon_atif_functions functions;
2173 struct radeon_atif_notification_cfg notification_cfg;
2174 struct radeon_encoder *encoder_for_bl;
2177 struct radeon_atcs_functions {
2181 bool pcie_bus_width;
2184 struct radeon_atcs {
2185 struct radeon_atcs_functions functions;
2189 * Core structure, functions and helpers.
2191 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2192 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2194 struct radeon_device {
2196 struct drm_device *ddev;
2197 struct pci_dev *pdev;
2198 struct rw_semaphore exclusive_lock;
2200 union radeon_asic_config config;
2201 enum radeon_family family;
2202 unsigned long flags;
2204 enum radeon_pll_errata pll_errata;
2211 uint16_t bios_header_start;
2212 struct radeon_bo *stollen_vga_memory;
2214 resource_size_t rmmio_base;
2215 resource_size_t rmmio_size;
2216 /* protects concurrent MM_INDEX/DATA based register access */
2217 spinlock_t mmio_idx_lock;
2218 /* protects concurrent SMC based register access */
2219 spinlock_t smc_idx_lock;
2220 /* protects concurrent PLL register access */
2221 spinlock_t pll_idx_lock;
2222 /* protects concurrent MC register access */
2223 spinlock_t mc_idx_lock;
2224 /* protects concurrent PCIE register access */
2225 spinlock_t pcie_idx_lock;
2226 /* protects concurrent PCIE_PORT register access */
2227 spinlock_t pciep_idx_lock;
2228 /* protects concurrent PIF register access */
2229 spinlock_t pif_idx_lock;
2230 /* protects concurrent CG register access */
2231 spinlock_t cg_idx_lock;
2232 /* protects concurrent UVD register access */
2233 spinlock_t uvd_idx_lock;
2234 /* protects concurrent RCU register access */
2235 spinlock_t rcu_idx_lock;
2236 /* protects concurrent DIDT register access */
2237 spinlock_t didt_idx_lock;
2238 /* protects concurrent ENDPOINT (audio) register access */
2239 spinlock_t end_idx_lock;
2240 void __iomem *rmmio;
2241 radeon_rreg_t mc_rreg;
2242 radeon_wreg_t mc_wreg;
2243 radeon_rreg_t pll_rreg;
2244 radeon_wreg_t pll_wreg;
2245 uint32_t pcie_reg_mask;
2246 radeon_rreg_t pciep_rreg;
2247 radeon_wreg_t pciep_wreg;
2249 void __iomem *rio_mem;
2250 resource_size_t rio_mem_size;
2251 struct radeon_clock clock;
2252 struct radeon_mc mc;
2253 struct radeon_gart gart;
2254 struct radeon_mode_info mode_info;
2255 struct radeon_scratch scratch;
2256 struct radeon_doorbell doorbell;
2257 struct radeon_mman mman;
2258 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2259 wait_queue_head_t fence_queue;
2260 struct mutex ring_lock;
2261 struct radeon_ring ring[RADEON_NUM_RINGS];
2263 struct radeon_sa_manager ring_tmp_bo;
2264 struct radeon_irq irq;
2265 struct radeon_asic *asic;
2266 struct radeon_gem gem;
2267 struct radeon_pm pm;
2268 struct radeon_uvd uvd;
2269 struct radeon_vce vce;
2270 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2271 struct radeon_wb wb;
2272 struct radeon_dummy_page dummy_page;
2277 bool fastfb_working; /* IGP feature*/
2279 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2280 const struct firmware *me_fw; /* all family ME firmware */
2281 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2282 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2283 const struct firmware *mc_fw; /* NI MC firmware */
2284 const struct firmware *ce_fw; /* SI CE firmware */
2285 const struct firmware *mec_fw; /* CIK MEC firmware */
2286 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2287 const struct firmware *smc_fw; /* SMC firmware */
2288 const struct firmware *uvd_fw; /* UVD firmware */
2289 const struct firmware *vce_fw; /* VCE firmware */
2290 struct r600_vram_scratch vram_scratch;
2291 int msi_enabled; /* msi enabled */
2292 struct r600_ih ih; /* r6/700 interrupt ring */
2293 struct radeon_rlc rlc;
2294 struct radeon_mec mec;
2295 struct work_struct hotplug_work;
2296 struct work_struct audio_work;
2297 struct work_struct reset_work;
2298 int num_crtc; /* number of crtcs */
2299 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2301 struct r600_audio audio; /* audio stuff */
2302 struct notifier_block acpi_nb;
2303 /* only one userspace can use Hyperz features or CMASK at a time */
2304 struct drm_file *hyperz_filp;
2305 struct drm_file *cmask_filp;
2307 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2309 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2310 unsigned debugfs_count;
2311 /* virtual memory */
2312 struct radeon_vm_manager vm_manager;
2313 struct mutex gpu_clock_mutex;
2315 atomic64_t vram_usage;
2316 atomic64_t gtt_usage;
2317 atomic64_t num_bytes_moved;
2318 /* ACPI interface */
2319 struct radeon_atif atif;
2320 struct radeon_atcs atcs;
2321 /* srbm instance registers */
2322 struct mutex srbm_mutex;
2323 /* clock, powergating flags */
2327 struct dev_pm_domain vga_pm_domain;
2328 bool have_disp_power_ref;
2331 bool radeon_is_px(struct drm_device *dev);
2332 int radeon_device_init(struct radeon_device *rdev,
2333 struct drm_device *ddev,
2334 struct pci_dev *pdev,
2336 void radeon_device_fini(struct radeon_device *rdev);
2337 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2339 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2340 bool always_indirect);
2341 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2342 bool always_indirect);
2343 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2344 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2346 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2347 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2352 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2355 * Registers read & write functions.
2357 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2358 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2359 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2360 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2361 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2362 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2363 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2364 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2365 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2366 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2367 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2368 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2369 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2370 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2371 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2372 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2373 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2374 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2375 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2376 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2377 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2378 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2379 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2380 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2381 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2382 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2383 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2384 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2385 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2386 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2387 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2388 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2389 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2390 #define WREG32_P(reg, val, mask) \
2392 uint32_t tmp_ = RREG32(reg); \
2394 tmp_ |= ((val) & ~(mask)); \
2395 WREG32(reg, tmp_); \
2397 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2398 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2399 #define WREG32_PLL_P(reg, val, mask) \
2401 uint32_t tmp_ = RREG32_PLL(reg); \
2403 tmp_ |= ((val) & ~(mask)); \
2404 WREG32_PLL(reg, tmp_); \
2406 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2407 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2408 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2410 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2411 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2414 * Indirect registers accessor
2416 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2418 unsigned long flags;
2421 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2422 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2423 r = RREG32(RADEON_PCIE_DATA);
2424 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2428 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2430 unsigned long flags;
2432 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2433 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2434 WREG32(RADEON_PCIE_DATA, (v));
2435 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2438 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2440 unsigned long flags;
2443 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2444 WREG32(TN_SMC_IND_INDEX_0, (reg));
2445 r = RREG32(TN_SMC_IND_DATA_0);
2446 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2450 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2452 unsigned long flags;
2454 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2455 WREG32(TN_SMC_IND_INDEX_0, (reg));
2456 WREG32(TN_SMC_IND_DATA_0, (v));
2457 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2460 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2462 unsigned long flags;
2465 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2466 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2467 r = RREG32(R600_RCU_DATA);
2468 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2472 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2474 unsigned long flags;
2476 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2477 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2478 WREG32(R600_RCU_DATA, (v));
2479 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2482 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2484 unsigned long flags;
2487 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2488 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2489 r = RREG32(EVERGREEN_CG_IND_DATA);
2490 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2494 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2496 unsigned long flags;
2498 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2499 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2500 WREG32(EVERGREEN_CG_IND_DATA, (v));
2501 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2504 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2506 unsigned long flags;
2509 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2510 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2511 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2512 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2516 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2518 unsigned long flags;
2520 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2521 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2522 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2523 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2526 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2528 unsigned long flags;
2531 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2532 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2533 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2534 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2538 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2540 unsigned long flags;
2542 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2543 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2544 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2545 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2548 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2550 unsigned long flags;
2553 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2554 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2555 r = RREG32(R600_UVD_CTX_DATA);
2556 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2560 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2562 unsigned long flags;
2564 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2565 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2566 WREG32(R600_UVD_CTX_DATA, (v));
2567 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2571 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2573 unsigned long flags;
2576 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2577 WREG32(CIK_DIDT_IND_INDEX, (reg));
2578 r = RREG32(CIK_DIDT_IND_DATA);
2579 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2583 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2585 unsigned long flags;
2587 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2588 WREG32(CIK_DIDT_IND_INDEX, (reg));
2589 WREG32(CIK_DIDT_IND_DATA, (v));
2590 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2593 void r100_pll_errata_after_index(struct radeon_device *rdev);
2599 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2600 (rdev->pdev->device == 0x5969))
2601 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2602 (rdev->family == CHIP_RV200) || \
2603 (rdev->family == CHIP_RS100) || \
2604 (rdev->family == CHIP_RS200) || \
2605 (rdev->family == CHIP_RV250) || \
2606 (rdev->family == CHIP_RV280) || \
2607 (rdev->family == CHIP_RS300))
2608 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2609 (rdev->family == CHIP_RV350) || \
2610 (rdev->family == CHIP_R350) || \
2611 (rdev->family == CHIP_RV380) || \
2612 (rdev->family == CHIP_R420) || \
2613 (rdev->family == CHIP_R423) || \
2614 (rdev->family == CHIP_RV410) || \
2615 (rdev->family == CHIP_RS400) || \
2616 (rdev->family == CHIP_RS480))
2617 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2618 (rdev->ddev->pdev->device == 0x9443) || \
2619 (rdev->ddev->pdev->device == 0x944B) || \
2620 (rdev->ddev->pdev->device == 0x9506) || \
2621 (rdev->ddev->pdev->device == 0x9509) || \
2622 (rdev->ddev->pdev->device == 0x950F) || \
2623 (rdev->ddev->pdev->device == 0x689C) || \
2624 (rdev->ddev->pdev->device == 0x689D))
2625 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2626 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2627 (rdev->family == CHIP_RS690) || \
2628 (rdev->family == CHIP_RS740) || \
2629 (rdev->family >= CHIP_R600))
2630 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2631 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2632 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2633 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2634 (rdev->flags & RADEON_IS_IGP))
2635 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2636 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2637 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2638 (rdev->flags & RADEON_IS_IGP))
2639 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2640 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2641 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2642 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2643 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2644 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2645 (rdev->family == CHIP_MULLINS))
2647 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2648 (rdev->ddev->pdev->device == 0x6850) || \
2649 (rdev->ddev->pdev->device == 0x6858) || \
2650 (rdev->ddev->pdev->device == 0x6859) || \
2651 (rdev->ddev->pdev->device == 0x6840) || \
2652 (rdev->ddev->pdev->device == 0x6841) || \
2653 (rdev->ddev->pdev->device == 0x6842) || \
2654 (rdev->ddev->pdev->device == 0x6843))
2659 #define RBIOS8(i) (rdev->bios[i])
2660 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2661 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2663 int radeon_combios_init(struct radeon_device *rdev);
2664 void radeon_combios_fini(struct radeon_device *rdev);
2665 int radeon_atombios_init(struct radeon_device *rdev);
2666 void radeon_atombios_fini(struct radeon_device *rdev);
2672 #if DRM_DEBUG_CODE == 0
2673 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2675 ring->ring[ring->wptr++] = v;
2676 ring->wptr &= ring->ptr_mask;
2678 ring->ring_free_dw--;
2681 /* With debugging this is just too big to inline */
2682 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2688 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2689 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2690 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2691 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2692 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2693 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2694 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2695 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2696 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2697 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2698 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2699 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2700 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2701 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2702 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2703 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2704 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2705 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2706 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2707 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2708 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2709 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2710 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2711 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2712 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2713 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2714 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2715 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2716 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2717 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2718 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2719 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2720 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2721 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2722 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2723 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2724 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2725 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2726 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2727 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2728 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2729 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2730 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2731 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2732 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2733 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2734 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2735 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2736 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2737 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2738 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2739 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2740 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2741 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2742 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2743 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2744 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2745 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2746 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2747 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2748 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2749 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2750 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2751 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2752 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2753 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2754 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2755 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2756 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2757 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2758 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2759 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2760 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2761 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2762 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2763 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2764 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2765 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2766 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2767 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2768 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2769 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2770 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2771 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2772 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2774 /* Common functions */
2776 extern int radeon_gpu_reset(struct radeon_device *rdev);
2777 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2778 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2779 extern void radeon_agp_disable(struct radeon_device *rdev);
2780 extern int radeon_modeset_init(struct radeon_device *rdev);
2781 extern void radeon_modeset_fini(struct radeon_device *rdev);
2782 extern bool radeon_card_posted(struct radeon_device *rdev);
2783 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2784 extern void radeon_update_display_priority(struct radeon_device *rdev);
2785 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2786 extern void radeon_scratch_init(struct radeon_device *rdev);
2787 extern void radeon_wb_fini(struct radeon_device *rdev);
2788 extern int radeon_wb_init(struct radeon_device *rdev);
2789 extern void radeon_wb_disable(struct radeon_device *rdev);
2790 extern void radeon_surface_init(struct radeon_device *rdev);
2791 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2792 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2793 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2794 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2795 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2796 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2797 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2798 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2799 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2800 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2801 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2802 const u32 *registers,
2803 const u32 array_size);
2808 int radeon_vm_manager_init(struct radeon_device *rdev);
2809 void radeon_vm_manager_fini(struct radeon_device *rdev);
2810 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2811 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2812 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2813 struct radeon_vm *vm,
2814 struct list_head *head);
2815 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2816 struct radeon_vm *vm, int ring);
2817 void radeon_vm_flush(struct radeon_device *rdev,
2818 struct radeon_vm *vm,
2820 void radeon_vm_fence(struct radeon_device *rdev,
2821 struct radeon_vm *vm,
2822 struct radeon_fence *fence);
2823 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2824 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2825 struct radeon_vm *vm);
2826 int radeon_vm_bo_update(struct radeon_device *rdev,
2827 struct radeon_vm *vm,
2828 struct radeon_bo *bo,
2829 struct ttm_mem_reg *mem);
2830 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2831 struct radeon_bo *bo);
2832 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2833 struct radeon_bo *bo);
2834 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2835 struct radeon_vm *vm,
2836 struct radeon_bo *bo);
2837 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2838 struct radeon_bo_va *bo_va,
2841 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2842 struct radeon_bo_va *bo_va);
2845 void r600_audio_update_hdmi(struct work_struct *work);
2846 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2847 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2848 void r600_audio_enable(struct radeon_device *rdev,
2849 struct r600_audio_pin *pin,
2851 void dce6_audio_enable(struct radeon_device *rdev,
2852 struct r600_audio_pin *pin,
2856 * R600 vram scratch functions
2858 int r600_vram_scratch_init(struct radeon_device *rdev);
2859 void r600_vram_scratch_fini(struct radeon_device *rdev);
2862 * r600 cs checking helper
2864 unsigned r600_mip_minify(unsigned size, unsigned level);
2865 bool r600_fmt_is_valid_color(u32 format);
2866 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2867 int r600_fmt_get_blocksize(u32 format);
2868 int r600_fmt_get_nblocksx(u32 format, u32 w);
2869 int r600_fmt_get_nblocksy(u32 format, u32 h);
2872 * r600 functions used by radeon_encoder.c
2874 struct radeon_hdmi_acr {
2888 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2890 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2891 u32 tiling_pipe_num,
2893 u32 total_max_rb_num,
2894 u32 enabled_rb_mask);
2897 * evergreen functions used by radeon_encoder.c
2900 extern int ni_init_microcode(struct radeon_device *rdev);
2901 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2904 #if defined(CONFIG_ACPI)
2905 extern int radeon_acpi_init(struct radeon_device *rdev);
2906 extern void radeon_acpi_fini(struct radeon_device *rdev);
2907 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2908 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2909 u8 perf_req, bool advertise);
2910 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2912 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2913 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2916 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2917 struct radeon_cs_packet *pkt,
2919 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2920 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2921 struct radeon_cs_packet *pkt);
2922 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2923 struct radeon_cs_reloc **cs_reloc,
2925 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2926 uint32_t *vline_start_end,
2927 uint32_t *vline_status);
2929 #include "radeon_object.h"