drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129
 130         if (rdev->family >= CHIP_BONAIRE) {
 131                 rdev->pciep_rreg = &cik_pciep_rreg;
 132                 rdev->pciep_wreg = &cik_pciep_wreg;
 133         } else if (rdev->family >= CHIP_R600) {
 134                 rdev->pciep_rreg = &r600_pciep_rreg;
 135                 rdev->pciep_wreg = &r600_pciep_wreg;
 136         }
 137 }
 138
 139
 140 /* helper to disable agp */
 141 /**
 142  * radeon_agp_disable - AGP disable helper function
 143  *
 144  * @rdev: radeon device pointer
 145  *
 146  * Removes AGP flags and changes the gart callbacks on AGP
 147  * cards when using the internal gart rather than AGP (all asics).
 148  */
 149 void radeon_agp_disable(struct radeon_device *rdev)
 150 {
 151         rdev->flags &= ~RADEON_IS_AGP;
 152         if (rdev->family >= CHIP_R600) {
 153                 DRM_INFO("Forcing AGP to PCIE mode\n");
 154                 rdev->flags |= RADEON_IS_PCIE;
 155         } else if (rdev->family >= CHIP_RV515 ||
 156                         rdev->family == CHIP_RV380 ||
 157                         rdev->family == CHIP_RV410 ||
 158                         rdev->family == CHIP_R423) {
 159                 DRM_INFO("Forcing AGP to PCIE mode\n");
 160                 rdev->flags |= RADEON_IS_PCIE;
 161                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 162                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 163         } else {
 164                 DRM_INFO("Forcing AGP to PCI mode\n");
 165                 rdev->flags |= RADEON_IS_PCI;
 166                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 167                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 168         }
 169         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 170 }
 171
 172 /*
 173  * ASIC
 174  */
 175
 176 static struct radeon_asic_ring r100_gfx_ring = {
 177         .ib_execute = &r100_ring_ib_execute,
 178         .emit_fence = &r100_fence_ring_emit,
 179         .emit_semaphore = &r100_semaphore_ring_emit,
 180         .cs_parse = &r100_cs_parse,
 181         .ring_start = &r100_ring_start,
 182         .ring_test = &r100_ring_test,
 183         .ib_test = &r100_ib_test,
 184         .is_lockup = &r100_gpu_is_lockup,
 185         .get_rptr = &r100_gfx_get_rptr,
 186         .get_wptr = &r100_gfx_get_wptr,
 187         .set_wptr = &r100_gfx_set_wptr,
 188 };
 189
 190 static struct radeon_asic r100_asic = {
 191         .init = &r100_init,
 192         .fini = &r100_fini,
 193         .suspend = &r100_suspend,
 194         .resume = &r100_resume,
 195         .vga_set_state = &r100_vga_set_state,
 196         .asic_reset = &r100_asic_reset,
 197         .ioctl_wait_idle = NULL,
 198         .gui_idle = &r100_gui_idle,
 199         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 200         .gart = {
 201                 .tlb_flush = &r100_pci_gart_tlb_flush,
 202                 .set_page = &r100_pci_gart_set_page,
 203         },
 204         .ring = {
 205                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 206         },
 207         .irq = {
 208                 .set = &r100_irq_set,
 209                 .process = &r100_irq_process,
 210         },
 211         .display = {
 212                 .bandwidth_update = &r100_bandwidth_update,
 213                 .get_vblank_counter = &r100_get_vblank_counter,
 214                 .wait_for_vblank = &r100_wait_for_vblank,
 215                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 216                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 217         },
 218         .copy = {
 219                 .blit = &r100_copy_blit,
 220                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 221                 .dma = NULL,
 222                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 223                 .copy = &r100_copy_blit,
 224                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 225         },
 226         .surface = {
 227                 .set_reg = r100_set_surface_reg,
 228                 .clear_reg = r100_clear_surface_reg,
 229         },
 230         .hpd = {
 231                 .init = &r100_hpd_init,
 232                 .fini = &r100_hpd_fini,
 233                 .sense = &r100_hpd_sense,
 234                 .set_polarity = &r100_hpd_set_polarity,
 235         },
 236         .pm = {
 237                 .misc = &r100_pm_misc,
 238                 .prepare = &r100_pm_prepare,
 239                 .finish = &r100_pm_finish,
 240                 .init_profile = &r100_pm_init_profile,
 241                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 242                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 243                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 244                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 245                 .set_memory_clock = NULL,
 246                 .get_pcie_lanes = NULL,
 247                 .set_pcie_lanes = NULL,
 248                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 249         },
 250         .pflip = {
 251                 .page_flip = &r100_page_flip,
 252         },
 253 };
 254
 255 static struct radeon_asic r200_asic = {
 256         .init = &r100_init,
 257         .fini = &r100_fini,
 258         .suspend = &r100_suspend,
 259         .resume = &r100_resume,
 260         .vga_set_state = &r100_vga_set_state,
 261         .asic_reset = &r100_asic_reset,
 262         .ioctl_wait_idle = NULL,
 263         .gui_idle = &r100_gui_idle,
 264         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 265         .gart = {
 266                 .tlb_flush = &r100_pci_gart_tlb_flush,
 267                 .set_page = &r100_pci_gart_set_page,
 268         },
 269         .ring = {
 270                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 271         },
 272         .irq = {
 273                 .set = &r100_irq_set,
 274                 .process = &r100_irq_process,
 275         },
 276         .display = {
 277                 .bandwidth_update = &r100_bandwidth_update,
 278                 .get_vblank_counter = &r100_get_vblank_counter,
 279                 .wait_for_vblank = &r100_wait_for_vblank,
 280                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 281                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 282         },
 283         .copy = {
 284                 .blit = &r100_copy_blit,
 285                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 286                 .dma = &r200_copy_dma,
 287                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 288                 .copy = &r100_copy_blit,
 289                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 290         },
 291         .surface = {
 292                 .set_reg = r100_set_surface_reg,
 293                 .clear_reg = r100_clear_surface_reg,
 294         },
 295         .hpd = {
 296                 .init = &r100_hpd_init,
 297                 .fini = &r100_hpd_fini,
 298                 .sense = &r100_hpd_sense,
 299                 .set_polarity = &r100_hpd_set_polarity,
 300         },
 301         .pm = {
 302                 .misc = &r100_pm_misc,
 303                 .prepare = &r100_pm_prepare,
 304                 .finish = &r100_pm_finish,
 305                 .init_profile = &r100_pm_init_profile,
 306                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 307                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 308                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 309                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 310                 .set_memory_clock = NULL,
 311                 .get_pcie_lanes = NULL,
 312                 .set_pcie_lanes = NULL,
 313                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 314         },
 315         .pflip = {
 316                 .page_flip = &r100_page_flip,
 317         },
 318 };
 319
 320 static struct radeon_asic_ring r300_gfx_ring = {
 321         .ib_execute = &r100_ring_ib_execute,
 322         .emit_fence = &r300_fence_ring_emit,
 323         .emit_semaphore = &r100_semaphore_ring_emit,
 324         .cs_parse = &r300_cs_parse,
 325         .ring_start = &r300_ring_start,
 326         .ring_test = &r100_ring_test,
 327         .ib_test = &r100_ib_test,
 328         .is_lockup = &r100_gpu_is_lockup,
 329         .get_rptr = &r100_gfx_get_rptr,
 330         .get_wptr = &r100_gfx_get_wptr,
 331         .set_wptr = &r100_gfx_set_wptr,
 332 };
 333
 334 static struct radeon_asic r300_asic = {
 335         .init = &r300_init,
 336         .fini = &r300_fini,
 337         .suspend = &r300_suspend,
 338         .resume = &r300_resume,
 339         .vga_set_state = &r100_vga_set_state,
 340         .asic_reset = &r300_asic_reset,
 341         .ioctl_wait_idle = NULL,
 342         .gui_idle = &r100_gui_idle,
 343         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 344         .gart = {
 345                 .tlb_flush = &r100_pci_gart_tlb_flush,
 346                 .set_page = &r100_pci_gart_set_page,
 347         },
 348         .ring = {
 349                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 350         },
 351         .irq = {
 352                 .set = &r100_irq_set,
 353                 .process = &r100_irq_process,
 354         },
 355         .display = {
 356                 .bandwidth_update = &r100_bandwidth_update,
 357                 .get_vblank_counter = &r100_get_vblank_counter,
 358                 .wait_for_vblank = &r100_wait_for_vblank,
 359                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 360                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 361         },
 362         .copy = {
 363                 .blit = &r100_copy_blit,
 364                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 365                 .dma = &r200_copy_dma,
 366                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 367                 .copy = &r100_copy_blit,
 368                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 369         },
 370         .surface = {
 371                 .set_reg = r100_set_surface_reg,
 372                 .clear_reg = r100_clear_surface_reg,
 373         },
 374         .hpd = {
 375                 .init = &r100_hpd_init,
 376                 .fini = &r100_hpd_fini,
 377                 .sense = &r100_hpd_sense,
 378                 .set_polarity = &r100_hpd_set_polarity,
 379         },
 380         .pm = {
 381                 .misc = &r100_pm_misc,
 382                 .prepare = &r100_pm_prepare,
 383                 .finish = &r100_pm_finish,
 384                 .init_profile = &r100_pm_init_profile,
 385                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 386                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 387                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 388                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 389                 .set_memory_clock = NULL,
 390                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 391                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 392                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 393         },
 394         .pflip = {
 395                 .page_flip = &r100_page_flip,
 396         },
 397 };
 398
 399 static struct radeon_asic r300_asic_pcie = {
 400         .init = &r300_init,
 401         .fini = &r300_fini,
 402         .suspend = &r300_suspend,
 403         .resume = &r300_resume,
 404         .vga_set_state = &r100_vga_set_state,
 405         .asic_reset = &r300_asic_reset,
 406         .ioctl_wait_idle = NULL,
 407         .gui_idle = &r100_gui_idle,
 408         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 409         .gart = {
 410                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 411                 .set_page = &rv370_pcie_gart_set_page,
 412         },
 413         .ring = {
 414                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 415         },
 416         .irq = {
 417                 .set = &r100_irq_set,
 418                 .process = &r100_irq_process,
 419         },
 420         .display = {
 421                 .bandwidth_update = &r100_bandwidth_update,
 422                 .get_vblank_counter = &r100_get_vblank_counter,
 423                 .wait_for_vblank = &r100_wait_for_vblank,
 424                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 425                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 426         },
 427         .copy = {
 428                 .blit = &r100_copy_blit,
 429                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 430                 .dma = &r200_copy_dma,
 431                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 432                 .copy = &r100_copy_blit,
 433                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 434         },
 435         .surface = {
 436                 .set_reg = r100_set_surface_reg,
 437                 .clear_reg = r100_clear_surface_reg,
 438         },
 439         .hpd = {
 440                 .init = &r100_hpd_init,
 441                 .fini = &r100_hpd_fini,
 442                 .sense = &r100_hpd_sense,
 443                 .set_polarity = &r100_hpd_set_polarity,
 444         },
 445         .pm = {
 446                 .misc = &r100_pm_misc,
 447                 .prepare = &r100_pm_prepare,
 448                 .finish = &r100_pm_finish,
 449                 .init_profile = &r100_pm_init_profile,
 450                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 451                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 452                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 453                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 454                 .set_memory_clock = NULL,
 455                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 456                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 457                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 458         },
 459         .pflip = {
 460                 .page_flip = &r100_page_flip,
 461         },
 462 };
 463
 464 static struct radeon_asic r420_asic = {
 465         .init = &r420_init,
 466         .fini = &r420_fini,
 467         .suspend = &r420_suspend,
 468         .resume = &r420_resume,
 469         .vga_set_state = &r100_vga_set_state,
 470         .asic_reset = &r300_asic_reset,
 471         .ioctl_wait_idle = NULL,
 472         .gui_idle = &r100_gui_idle,
 473         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 474         .gart = {
 475                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 476                 .set_page = &rv370_pcie_gart_set_page,
 477         },
 478         .ring = {
 479                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 480         },
 481         .irq = {
 482                 .set = &r100_irq_set,
 483                 .process = &r100_irq_process,
 484         },
 485         .display = {
 486                 .bandwidth_update = &r100_bandwidth_update,
 487                 .get_vblank_counter = &r100_get_vblank_counter,
 488                 .wait_for_vblank = &r100_wait_for_vblank,
 489                 .set_backlight_level = &atombios_set_backlight_level,
 490                 .get_backlight_level = &atombios_get_backlight_level,
 491         },
 492         .copy = {
 493                 .blit = &r100_copy_blit,
 494                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 495                 .dma = &r200_copy_dma,
 496                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 497                 .copy = &r100_copy_blit,
 498                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 499         },
 500         .surface = {
 501                 .set_reg = r100_set_surface_reg,
 502                 .clear_reg = r100_clear_surface_reg,
 503         },
 504         .hpd = {
 505                 .init = &r100_hpd_init,
 506                 .fini = &r100_hpd_fini,
 507                 .sense = &r100_hpd_sense,
 508                 .set_polarity = &r100_hpd_set_polarity,
 509         },
 510         .pm = {
 511                 .misc = &r100_pm_misc,
 512                 .prepare = &r100_pm_prepare,
 513                 .finish = &r100_pm_finish,
 514                 .init_profile = &r420_pm_init_profile,
 515                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 516                 .get_engine_clock = &radeon_atom_get_engine_clock,
 517                 .set_engine_clock = &radeon_atom_set_engine_clock,
 518                 .get_memory_clock = &radeon_atom_get_memory_clock,
 519                 .set_memory_clock = &radeon_atom_set_memory_clock,
 520                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 521                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 522                 .set_clock_gating = &radeon_atom_set_clock_gating,
 523         },
 524         .pflip = {
 525                 .page_flip = &r100_page_flip,
 526         },
 527 };
 528
 529 static struct radeon_asic rs400_asic = {
 530         .init = &rs400_init,
 531         .fini = &rs400_fini,
 532         .suspend = &rs400_suspend,
 533         .resume = &rs400_resume,
 534         .vga_set_state = &r100_vga_set_state,
 535         .asic_reset = &r300_asic_reset,
 536         .ioctl_wait_idle = NULL,
 537         .gui_idle = &r100_gui_idle,
 538         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 539         .gart = {
 540                 .tlb_flush = &rs400_gart_tlb_flush,
 541                 .set_page = &rs400_gart_set_page,
 542         },
 543         .ring = {
 544                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 545         },
 546         .irq = {
 547                 .set = &r100_irq_set,
 548                 .process = &r100_irq_process,
 549         },
 550         .display = {
 551                 .bandwidth_update = &r100_bandwidth_update,
 552                 .get_vblank_counter = &r100_get_vblank_counter,
 553                 .wait_for_vblank = &r100_wait_for_vblank,
 554                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 555                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 556         },
 557         .copy = {
 558                 .blit = &r100_copy_blit,
 559                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 560                 .dma = &r200_copy_dma,
 561                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 562                 .copy = &r100_copy_blit,
 563                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 564         },
 565         .surface = {
 566                 .set_reg = r100_set_surface_reg,
 567                 .clear_reg = r100_clear_surface_reg,
 568         },
 569         .hpd = {
 570                 .init = &r100_hpd_init,
 571                 .fini = &r100_hpd_fini,
 572                 .sense = &r100_hpd_sense,
 573                 .set_polarity = &r100_hpd_set_polarity,
 574         },
 575         .pm = {
 576                 .misc = &r100_pm_misc,
 577                 .prepare = &r100_pm_prepare,
 578                 .finish = &r100_pm_finish,
 579                 .init_profile = &r100_pm_init_profile,
 580                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 581                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 582                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 583                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 584                 .set_memory_clock = NULL,
 585                 .get_pcie_lanes = NULL,
 586                 .set_pcie_lanes = NULL,
 587                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 588         },
 589         .pflip = {
 590                 .page_flip = &r100_page_flip,
 591         },
 592 };
 593
 594 static struct radeon_asic rs600_asic = {
 595         .init = &rs600_init,
 596         .fini = &rs600_fini,
 597         .suspend = &rs600_suspend,
 598         .resume = &rs600_resume,
 599         .vga_set_state = &r100_vga_set_state,
 600         .asic_reset = &rs600_asic_reset,
 601         .ioctl_wait_idle = NULL,
 602         .gui_idle = &r100_gui_idle,
 603         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 604         .gart = {
 605                 .tlb_flush = &rs600_gart_tlb_flush,
 606                 .set_page = &rs600_gart_set_page,
 607         },
 608         .ring = {
 609                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 610         },
 611         .irq = {
 612                 .set = &rs600_irq_set,
 613                 .process = &rs600_irq_process,
 614         },
 615         .display = {
 616                 .bandwidth_update = &rs600_bandwidth_update,
 617                 .get_vblank_counter = &rs600_get_vblank_counter,
 618                 .wait_for_vblank = &avivo_wait_for_vblank,
 619                 .set_backlight_level = &atombios_set_backlight_level,
 620                 .get_backlight_level = &atombios_get_backlight_level,
 621                 .hdmi_enable = &r600_hdmi_enable,
 622                 .hdmi_setmode = &r600_hdmi_setmode,
 623         },
 624         .copy = {
 625                 .blit = &r100_copy_blit,
 626                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 627                 .dma = &r200_copy_dma,
 628                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 629                 .copy = &r100_copy_blit,
 630                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 631         },
 632         .surface = {
 633                 .set_reg = r100_set_surface_reg,
 634                 .clear_reg = r100_clear_surface_reg,
 635         },
 636         .hpd = {
 637                 .init = &rs600_hpd_init,
 638                 .fini = &rs600_hpd_fini,
 639                 .sense = &rs600_hpd_sense,
 640                 .set_polarity = &rs600_hpd_set_polarity,
 641         },
 642         .pm = {
 643                 .misc = &rs600_pm_misc,
 644                 .prepare = &rs600_pm_prepare,
 645                 .finish = &rs600_pm_finish,
 646                 .init_profile = &r420_pm_init_profile,
 647                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 648                 .get_engine_clock = &radeon_atom_get_engine_clock,
 649                 .set_engine_clock = &radeon_atom_set_engine_clock,
 650                 .get_memory_clock = &radeon_atom_get_memory_clock,
 651                 .set_memory_clock = &radeon_atom_set_memory_clock,
 652                 .get_pcie_lanes = NULL,
 653                 .set_pcie_lanes = NULL,
 654                 .set_clock_gating = &radeon_atom_set_clock_gating,
 655         },
 656         .pflip = {
 657                 .page_flip = &rs600_page_flip,
 658         },
 659 };
 660
 661 static struct radeon_asic rs690_asic = {
 662         .init = &rs690_init,
 663         .fini = &rs690_fini,
 664         .suspend = &rs690_suspend,
 665         .resume = &rs690_resume,
 666         .vga_set_state = &r100_vga_set_state,
 667         .asic_reset = &rs600_asic_reset,
 668         .ioctl_wait_idle = NULL,
 669         .gui_idle = &r100_gui_idle,
 670         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 671         .gart = {
 672                 .tlb_flush = &rs400_gart_tlb_flush,
 673                 .set_page = &rs400_gart_set_page,
 674         },
 675         .ring = {
 676                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 677         },
 678         .irq = {
 679                 .set = &rs600_irq_set,
 680                 .process = &rs600_irq_process,
 681         },
 682         .display = {
 683                 .get_vblank_counter = &rs600_get_vblank_counter,
 684                 .bandwidth_update = &rs690_bandwidth_update,
 685                 .wait_for_vblank = &avivo_wait_for_vblank,
 686                 .set_backlight_level = &atombios_set_backlight_level,
 687                 .get_backlight_level = &atombios_get_backlight_level,
 688                 .hdmi_enable = &r600_hdmi_enable,
 689                 .hdmi_setmode = &r600_hdmi_setmode,
 690         },
 691         .copy = {
 692                 .blit = &r100_copy_blit,
 693                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 694                 .dma = &r200_copy_dma,
 695                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 696                 .copy = &r200_copy_dma,
 697                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 698         },
 699         .surface = {
 700                 .set_reg = r100_set_surface_reg,
 701                 .clear_reg = r100_clear_surface_reg,
 702         },
 703         .hpd = {
 704                 .init = &rs600_hpd_init,
 705                 .fini = &rs600_hpd_fini,
 706                 .sense = &rs600_hpd_sense,
 707                 .set_polarity = &rs600_hpd_set_polarity,
 708         },
 709         .pm = {
 710                 .misc = &rs600_pm_misc,
 711                 .prepare = &rs600_pm_prepare,
 712                 .finish = &rs600_pm_finish,
 713                 .init_profile = &r420_pm_init_profile,
 714                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 715                 .get_engine_clock = &radeon_atom_get_engine_clock,
 716                 .set_engine_clock = &radeon_atom_set_engine_clock,
 717                 .get_memory_clock = &radeon_atom_get_memory_clock,
 718                 .set_memory_clock = &radeon_atom_set_memory_clock,
 719                 .get_pcie_lanes = NULL,
 720                 .set_pcie_lanes = NULL,
 721                 .set_clock_gating = &radeon_atom_set_clock_gating,
 722         },
 723         .pflip = {
 724                 .page_flip = &rs600_page_flip,
 725         },
 726 };
 727
 728 static struct radeon_asic rv515_asic = {
 729         .init = &rv515_init,
 730         .fini = &rv515_fini,
 731         .suspend = &rv515_suspend,
 732         .resume = &rv515_resume,
 733         .vga_set_state = &r100_vga_set_state,
 734         .asic_reset = &rs600_asic_reset,
 735         .ioctl_wait_idle = NULL,
 736         .gui_idle = &r100_gui_idle,
 737         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 738         .gart = {
 739                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 740                 .set_page = &rv370_pcie_gart_set_page,
 741         },
 742         .ring = {
 743                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 744         },
 745         .irq = {
 746                 .set = &rs600_irq_set,
 747                 .process = &rs600_irq_process,
 748         },
 749         .display = {
 750                 .get_vblank_counter = &rs600_get_vblank_counter,
 751                 .bandwidth_update = &rv515_bandwidth_update,
 752                 .wait_for_vblank = &avivo_wait_for_vblank,
 753                 .set_backlight_level = &atombios_set_backlight_level,
 754                 .get_backlight_level = &atombios_get_backlight_level,
 755         },
 756         .copy = {
 757                 .blit = &r100_copy_blit,
 758                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 759                 .dma = &r200_copy_dma,
 760                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 761                 .copy = &r100_copy_blit,
 762                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 763         },
 764         .surface = {
 765                 .set_reg = r100_set_surface_reg,
 766                 .clear_reg = r100_clear_surface_reg,
 767         },
 768         .hpd = {
 769                 .init = &rs600_hpd_init,
 770                 .fini = &rs600_hpd_fini,
 771                 .sense = &rs600_hpd_sense,
 772                 .set_polarity = &rs600_hpd_set_polarity,
 773         },
 774         .pm = {
 775                 .misc = &rs600_pm_misc,
 776                 .prepare = &rs600_pm_prepare,
 777                 .finish = &rs600_pm_finish,
 778                 .init_profile = &r420_pm_init_profile,
 779                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 780                 .get_engine_clock = &radeon_atom_get_engine_clock,
 781                 .set_engine_clock = &radeon_atom_set_engine_clock,
 782                 .get_memory_clock = &radeon_atom_get_memory_clock,
 783                 .set_memory_clock = &radeon_atom_set_memory_clock,
 784                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 785                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 786                 .set_clock_gating = &radeon_atom_set_clock_gating,
 787         },
 788         .pflip = {
 789                 .page_flip = &rs600_page_flip,
 790         },
 791 };
 792
 793 static struct radeon_asic r520_asic = {
 794         .init = &r520_init,
 795         .fini = &rv515_fini,
 796         .suspend = &rv515_suspend,
 797         .resume = &r520_resume,
 798         .vga_set_state = &r100_vga_set_state,
 799         .asic_reset = &rs600_asic_reset,
 800         .ioctl_wait_idle = NULL,
 801         .gui_idle = &r100_gui_idle,
 802         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 803         .gart = {
 804                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 805                 .set_page = &rv370_pcie_gart_set_page,
 806         },
 807         .ring = {
 808                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 809         },
 810         .irq = {
 811                 .set = &rs600_irq_set,
 812                 .process = &rs600_irq_process,
 813         },
 814         .display = {
 815                 .bandwidth_update = &rv515_bandwidth_update,
 816                 .get_vblank_counter = &rs600_get_vblank_counter,
 817                 .wait_for_vblank = &avivo_wait_for_vblank,
 818                 .set_backlight_level = &atombios_set_backlight_level,
 819                 .get_backlight_level = &atombios_get_backlight_level,
 820         },
 821         .copy = {
 822                 .blit = &r100_copy_blit,
 823                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 824                 .dma = &r200_copy_dma,
 825                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 826                 .copy = &r100_copy_blit,
 827                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 828         },
 829         .surface = {
 830                 .set_reg = r100_set_surface_reg,
 831                 .clear_reg = r100_clear_surface_reg,
 832         },
 833         .hpd = {
 834                 .init = &rs600_hpd_init,
 835                 .fini = &rs600_hpd_fini,
 836                 .sense = &rs600_hpd_sense,
 837                 .set_polarity = &rs600_hpd_set_polarity,
 838         },
 839         .pm = {
 840                 .misc = &rs600_pm_misc,
 841                 .prepare = &rs600_pm_prepare,
 842                 .finish = &rs600_pm_finish,
 843                 .init_profile = &r420_pm_init_profile,
 844                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 845                 .get_engine_clock = &radeon_atom_get_engine_clock,
 846                 .set_engine_clock = &radeon_atom_set_engine_clock,
 847                 .get_memory_clock = &radeon_atom_get_memory_clock,
 848                 .set_memory_clock = &radeon_atom_set_memory_clock,
 849                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 850                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 851                 .set_clock_gating = &radeon_atom_set_clock_gating,
 852         },
 853         .pflip = {
 854                 .page_flip = &rs600_page_flip,
 855         },
 856 };
 857
 858 static struct radeon_asic_ring r600_gfx_ring = {
 859         .ib_execute = &r600_ring_ib_execute,
 860         .emit_fence = &r600_fence_ring_emit,
 861         .emit_semaphore = &r600_semaphore_ring_emit,
 862         .cs_parse = &r600_cs_parse,
 863         .ring_test = &r600_ring_test,
 864         .ib_test = &r600_ib_test,
 865         .is_lockup = &r600_gfx_is_lockup,
 866         .get_rptr = &r600_gfx_get_rptr,
 867         .get_wptr = &r600_gfx_get_wptr,
 868         .set_wptr = &r600_gfx_set_wptr,
 869 };
 870
 871 static struct radeon_asic_ring r600_dma_ring = {
 872         .ib_execute = &r600_dma_ring_ib_execute,
 873         .emit_fence = &r600_dma_fence_ring_emit,
 874         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 875         .cs_parse = &r600_dma_cs_parse,
 876         .ring_test = &r600_dma_ring_test,
 877         .ib_test = &r600_dma_ib_test,
 878         .is_lockup = &r600_dma_is_lockup,
 879         .get_rptr = &r600_dma_get_rptr,
 880         .get_wptr = &r600_dma_get_wptr,
 881         .set_wptr = &r600_dma_set_wptr,
 882 };
 883
 884 static struct radeon_asic r600_asic = {
 885         .init = &r600_init,
 886         .fini = &r600_fini,
 887         .suspend = &r600_suspend,
 888         .resume = &r600_resume,
 889         .vga_set_state = &r600_vga_set_state,
 890         .asic_reset = &r600_asic_reset,
 891         .ioctl_wait_idle = r600_ioctl_wait_idle,
 892         .gui_idle = &r600_gui_idle,
 893         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 894         .get_xclk = &r600_get_xclk,
 895         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 896         .gart = {
 897                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 898                 .set_page = &rs600_gart_set_page,
 899         },
 900         .ring = {
 901                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 902                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 903         },
 904         .irq = {
 905                 .set = &r600_irq_set,
 906                 .process = &r600_irq_process,
 907         },
 908         .display = {
 909                 .bandwidth_update = &rv515_bandwidth_update,
 910                 .get_vblank_counter = &rs600_get_vblank_counter,
 911                 .wait_for_vblank = &avivo_wait_for_vblank,
 912                 .set_backlight_level = &atombios_set_backlight_level,
 913                 .get_backlight_level = &atombios_get_backlight_level,
 914                 .hdmi_enable = &r600_hdmi_enable,
 915                 .hdmi_setmode = &r600_hdmi_setmode,
 916         },
 917         .copy = {
 918                 .blit = &r600_copy_cpdma,
 919                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 920                 .dma = &r600_copy_dma,
 921                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 922                 .copy = &r600_copy_cpdma,
 923                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 924         },
 925         .surface = {
 926                 .set_reg = r600_set_surface_reg,
 927                 .clear_reg = r600_clear_surface_reg,
 928         },
 929         .hpd = {
 930                 .init = &r600_hpd_init,
 931                 .fini = &r600_hpd_fini,
 932                 .sense = &r600_hpd_sense,
 933                 .set_polarity = &r600_hpd_set_polarity,
 934         },
 935         .pm = {
 936                 .misc = &r600_pm_misc,
 937                 .prepare = &rs600_pm_prepare,
 938                 .finish = &rs600_pm_finish,
 939                 .init_profile = &r600_pm_init_profile,
 940                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 941                 .get_engine_clock = &radeon_atom_get_engine_clock,
 942                 .set_engine_clock = &radeon_atom_set_engine_clock,
 943                 .get_memory_clock = &radeon_atom_get_memory_clock,
 944                 .set_memory_clock = &radeon_atom_set_memory_clock,
 945                 .get_pcie_lanes = &r600_get_pcie_lanes,
 946                 .set_pcie_lanes = &r600_set_pcie_lanes,
 947                 .set_clock_gating = NULL,
 948                 .get_temperature = &rv6xx_get_temp,
 949         },
 950         .pflip = {
 951                 .page_flip = &rs600_page_flip,
 952         },
 953 };
 954
 955 static struct radeon_asic rv6xx_asic = {
 956         .init = &r600_init,
 957         .fini = &r600_fini,
 958         .suspend = &r600_suspend,
 959         .resume = &r600_resume,
 960         .vga_set_state = &r600_vga_set_state,
 961         .asic_reset = &r600_asic_reset,
 962         .ioctl_wait_idle = r600_ioctl_wait_idle,
 963         .gui_idle = &r600_gui_idle,
 964         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 965         .get_xclk = &r600_get_xclk,
 966         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 967         .gart = {
 968                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 969                 .set_page = &rs600_gart_set_page,
 970         },
 971         .ring = {
 972                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 973                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 974         },
 975         .irq = {
 976                 .set = &r600_irq_set,
 977                 .process = &r600_irq_process,
 978         },
 979         .display = {
 980                 .bandwidth_update = &rv515_bandwidth_update,
 981                 .get_vblank_counter = &rs600_get_vblank_counter,
 982                 .wait_for_vblank = &avivo_wait_for_vblank,
 983                 .set_backlight_level = &atombios_set_backlight_level,
 984                 .get_backlight_level = &atombios_get_backlight_level,
 985                 .hdmi_enable = &r600_hdmi_enable,
 986                 .hdmi_setmode = &r600_hdmi_setmode,
 987         },
 988         .copy = {
 989                 .blit = &r600_copy_cpdma,
 990                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 991                 .dma = &r600_copy_dma,
 992                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 993                 .copy = &r600_copy_cpdma,
 994                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 995         },
 996         .surface = {
 997                 .set_reg = r600_set_surface_reg,
 998                 .clear_reg = r600_clear_surface_reg,
 999         },
1000         .hpd = {
1001                 .init = &r600_hpd_init,
1002                 .fini = &r600_hpd_fini,
1003                 .sense = &r600_hpd_sense,
1004                 .set_polarity = &r600_hpd_set_polarity,
1005         },
1006         .pm = {
1007                 .misc = &r600_pm_misc,
1008                 .prepare = &rs600_pm_prepare,
1009                 .finish = &rs600_pm_finish,
1010                 .init_profile = &r600_pm_init_profile,
1011                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1012                 .get_engine_clock = &radeon_atom_get_engine_clock,
1013                 .set_engine_clock = &radeon_atom_set_engine_clock,
1014                 .get_memory_clock = &radeon_atom_get_memory_clock,
1015                 .set_memory_clock = &radeon_atom_set_memory_clock,
1016                 .get_pcie_lanes = &r600_get_pcie_lanes,
1017                 .set_pcie_lanes = &r600_set_pcie_lanes,
1018                 .set_clock_gating = NULL,
1019                 .get_temperature = &rv6xx_get_temp,
1020                 .set_uvd_clocks = &r600_set_uvd_clocks,
1021         },
1022         .dpm = {
1023                 .init = &rv6xx_dpm_init,
1024                 .setup_asic = &rv6xx_setup_asic,
1025                 .enable = &rv6xx_dpm_enable,
1026                 .late_enable = &r600_dpm_late_enable,
1027                 .disable = &rv6xx_dpm_disable,
1028                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1029                 .set_power_state = &rv6xx_dpm_set_power_state,
1030                 .post_set_power_state = &r600_dpm_post_set_power_state,
1031                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1032                 .fini = &rv6xx_dpm_fini,
1033                 .get_sclk = &rv6xx_dpm_get_sclk,
1034                 .get_mclk = &rv6xx_dpm_get_mclk,
1035                 .print_power_state = &rv6xx_dpm_print_power_state,
1036                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1037                 .force_performance_level = &rv6xx_dpm_force_performance_level,
1038         },
1039         .pflip = {
1040                 .page_flip = &rs600_page_flip,
1041         },
1042 };
1043
1044 static struct radeon_asic rs780_asic = {
1045         .init = &r600_init,
1046         .fini = &r600_fini,
1047         .suspend = &r600_suspend,
1048         .resume = &r600_resume,
1049         .vga_set_state = &r600_vga_set_state,
1050         .asic_reset = &r600_asic_reset,
1051         .ioctl_wait_idle = r600_ioctl_wait_idle,
1052         .gui_idle = &r600_gui_idle,
1053         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1054         .get_xclk = &r600_get_xclk,
1055         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1056         .gart = {
1057                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1058                 .set_page = &rs600_gart_set_page,
1059         },
1060         .ring = {
1061                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1062                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1063         },
1064         .irq = {
1065                 .set = &r600_irq_set,
1066                 .process = &r600_irq_process,
1067         },
1068         .display = {
1069                 .bandwidth_update = &rs690_bandwidth_update,
1070                 .get_vblank_counter = &rs600_get_vblank_counter,
1071                 .wait_for_vblank = &avivo_wait_for_vblank,
1072                 .set_backlight_level = &atombios_set_backlight_level,
1073                 .get_backlight_level = &atombios_get_backlight_level,
1074                 .hdmi_enable = &r600_hdmi_enable,
1075                 .hdmi_setmode = &r600_hdmi_setmode,
1076         },
1077         .copy = {
1078                 .blit = &r600_copy_cpdma,
1079                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1080                 .dma = &r600_copy_dma,
1081                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1082                 .copy = &r600_copy_cpdma,
1083                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1084         },
1085         .surface = {
1086                 .set_reg = r600_set_surface_reg,
1087                 .clear_reg = r600_clear_surface_reg,
1088         },
1089         .hpd = {
1090                 .init = &r600_hpd_init,
1091                 .fini = &r600_hpd_fini,
1092                 .sense = &r600_hpd_sense,
1093                 .set_polarity = &r600_hpd_set_polarity,
1094         },
1095         .pm = {
1096                 .misc = &r600_pm_misc,
1097                 .prepare = &rs600_pm_prepare,
1098                 .finish = &rs600_pm_finish,
1099                 .init_profile = &rs780_pm_init_profile,
1100                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1101                 .get_engine_clock = &radeon_atom_get_engine_clock,
1102                 .set_engine_clock = &radeon_atom_set_engine_clock,
1103                 .get_memory_clock = NULL,
1104                 .set_memory_clock = NULL,
1105                 .get_pcie_lanes = NULL,
1106                 .set_pcie_lanes = NULL,
1107                 .set_clock_gating = NULL,
1108                 .get_temperature = &rv6xx_get_temp,
1109                 .set_uvd_clocks = &r600_set_uvd_clocks,
1110         },
1111         .dpm = {
1112                 .init = &rs780_dpm_init,
1113                 .setup_asic = &rs780_dpm_setup_asic,
1114                 .enable = &rs780_dpm_enable,
1115                 .late_enable = &r600_dpm_late_enable,
1116                 .disable = &rs780_dpm_disable,
1117                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1118                 .set_power_state = &rs780_dpm_set_power_state,
1119                 .post_set_power_state = &r600_dpm_post_set_power_state,
1120                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1121                 .fini = &rs780_dpm_fini,
1122                 .get_sclk = &rs780_dpm_get_sclk,
1123                 .get_mclk = &rs780_dpm_get_mclk,
1124                 .print_power_state = &rs780_dpm_print_power_state,
1125                 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1126                 .force_performance_level = &rs780_dpm_force_performance_level,
1127         },
1128         .pflip = {
1129                 .page_flip = &rs600_page_flip,
1130         },
1131 };
1132
1133 static struct radeon_asic_ring rv770_uvd_ring = {
1134         .ib_execute = &uvd_v1_0_ib_execute,
1135         .emit_fence = &uvd_v2_2_fence_emit,
1136         .emit_semaphore = &uvd_v1_0_semaphore_emit,
1137         .cs_parse = &radeon_uvd_cs_parse,
1138         .ring_test = &uvd_v1_0_ring_test,
1139         .ib_test = &uvd_v1_0_ib_test,
1140         .is_lockup = &radeon_ring_test_lockup,
1141         .get_rptr = &uvd_v1_0_get_rptr,
1142         .get_wptr = &uvd_v1_0_get_wptr,
1143         .set_wptr = &uvd_v1_0_set_wptr,
1144 };
1145
1146 static struct radeon_asic rv770_asic = {
1147         .init = &rv770_init,
1148         .fini = &rv770_fini,
1149         .suspend = &rv770_suspend,
1150         .resume = &rv770_resume,
1151         .asic_reset = &r600_asic_reset,
1152         .vga_set_state = &r600_vga_set_state,
1153         .ioctl_wait_idle = r600_ioctl_wait_idle,
1154         .gui_idle = &r600_gui_idle,
1155         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1156         .get_xclk = &rv770_get_xclk,
1157         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1158         .gart = {
1159                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1160                 .set_page = &rs600_gart_set_page,
1161         },
1162         .ring = {
1163                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1164                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1165                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1166         },
1167         .irq = {
1168                 .set = &r600_irq_set,
1169                 .process = &r600_irq_process,
1170         },
1171         .display = {
1172                 .bandwidth_update = &rv515_bandwidth_update,
1173                 .get_vblank_counter = &rs600_get_vblank_counter,
1174                 .wait_for_vblank = &avivo_wait_for_vblank,
1175                 .set_backlight_level = &atombios_set_backlight_level,
1176                 .get_backlight_level = &atombios_get_backlight_level,
1177                 .hdmi_enable = &r600_hdmi_enable,
1178                 .hdmi_setmode = &dce3_1_hdmi_setmode,
1179         },
1180         .copy = {
1181                 .blit = &r600_copy_cpdma,
1182                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1183                 .dma = &rv770_copy_dma,
1184                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1185                 .copy = &rv770_copy_dma,
1186                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1187         },
1188         .surface = {
1189                 .set_reg = r600_set_surface_reg,
1190                 .clear_reg = r600_clear_surface_reg,
1191         },
1192         .hpd = {
1193                 .init = &r600_hpd_init,
1194                 .fini = &r600_hpd_fini,
1195                 .sense = &r600_hpd_sense,
1196                 .set_polarity = &r600_hpd_set_polarity,
1197         },
1198         .pm = {
1199                 .misc = &rv770_pm_misc,
1200                 .prepare = &rs600_pm_prepare,
1201                 .finish = &rs600_pm_finish,
1202                 .init_profile = &r600_pm_init_profile,
1203                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1204                 .get_engine_clock = &radeon_atom_get_engine_clock,
1205                 .set_engine_clock = &radeon_atom_set_engine_clock,
1206                 .get_memory_clock = &radeon_atom_get_memory_clock,
1207                 .set_memory_clock = &radeon_atom_set_memory_clock,
1208                 .get_pcie_lanes = &r600_get_pcie_lanes,
1209                 .set_pcie_lanes = &r600_set_pcie_lanes,
1210                 .set_clock_gating = &radeon_atom_set_clock_gating,
1211                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1212                 .get_temperature = &rv770_get_temp,
1213         },
1214         .dpm = {
1215                 .init = &rv770_dpm_init,
1216                 .setup_asic = &rv770_dpm_setup_asic,
1217                 .enable = &rv770_dpm_enable,
1218                 .late_enable = &rv770_dpm_late_enable,
1219                 .disable = &rv770_dpm_disable,
1220                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1221                 .set_power_state = &rv770_dpm_set_power_state,
1222                 .post_set_power_state = &r600_dpm_post_set_power_state,
1223                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1224                 .fini = &rv770_dpm_fini,
1225                 .get_sclk = &rv770_dpm_get_sclk,
1226                 .get_mclk = &rv770_dpm_get_mclk,
1227                 .print_power_state = &rv770_dpm_print_power_state,
1228                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1229                 .force_performance_level = &rv770_dpm_force_performance_level,
1230                 .vblank_too_short = &rv770_dpm_vblank_too_short,
1231         },
1232         .pflip = {
1233                 .page_flip = &rv770_page_flip,
1234         },
1235 };
1236
1237 static struct radeon_asic_ring evergreen_gfx_ring = {
1238         .ib_execute = &evergreen_ring_ib_execute,
1239         .emit_fence = &r600_fence_ring_emit,
1240         .emit_semaphore = &r600_semaphore_ring_emit,
1241         .cs_parse = &evergreen_cs_parse,
1242         .ring_test = &r600_ring_test,
1243         .ib_test = &r600_ib_test,
1244         .is_lockup = &evergreen_gfx_is_lockup,
1245         .get_rptr = &r600_gfx_get_rptr,
1246         .get_wptr = &r600_gfx_get_wptr,
1247         .set_wptr = &r600_gfx_set_wptr,
1248 };
1249
1250 static struct radeon_asic_ring evergreen_dma_ring = {
1251         .ib_execute = &evergreen_dma_ring_ib_execute,
1252         .emit_fence = &evergreen_dma_fence_ring_emit,
1253         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1254         .cs_parse = &evergreen_dma_cs_parse,
1255         .ring_test = &r600_dma_ring_test,
1256         .ib_test = &r600_dma_ib_test,
1257         .is_lockup = &evergreen_dma_is_lockup,
1258         .get_rptr = &r600_dma_get_rptr,
1259         .get_wptr = &r600_dma_get_wptr,
1260         .set_wptr = &r600_dma_set_wptr,
1261 };
1262
1263 static struct radeon_asic evergreen_asic = {
1264         .init = &evergreen_init,
1265         .fini = &evergreen_fini,
1266         .suspend = &evergreen_suspend,
1267         .resume = &evergreen_resume,
1268         .asic_reset = &evergreen_asic_reset,
1269         .vga_set_state = &r600_vga_set_state,
1270         .ioctl_wait_idle = r600_ioctl_wait_idle,
1271         .gui_idle = &r600_gui_idle,
1272         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1273         .get_xclk = &rv770_get_xclk,
1274         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1275         .gart = {
1276                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1277                 .set_page = &rs600_gart_set_page,
1278         },
1279         .ring = {
1280                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1281                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1282                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1283         },
1284         .irq = {
1285                 .set = &evergreen_irq_set,
1286                 .process = &evergreen_irq_process,
1287         },
1288         .display = {
1289                 .bandwidth_update = &evergreen_bandwidth_update,
1290                 .get_vblank_counter = &evergreen_get_vblank_counter,
1291                 .wait_for_vblank = &dce4_wait_for_vblank,
1292                 .set_backlight_level = &atombios_set_backlight_level,
1293                 .get_backlight_level = &atombios_get_backlight_level,
1294                 .hdmi_enable = &evergreen_hdmi_enable,
1295                 .hdmi_setmode = &evergreen_hdmi_setmode,
1296         },
1297         .copy = {
1298                 .blit = &r600_copy_cpdma,
1299                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1300                 .dma = &evergreen_copy_dma,
1301                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1302                 .copy = &evergreen_copy_dma,
1303                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1304         },
1305         .surface = {
1306                 .set_reg = r600_set_surface_reg,
1307                 .clear_reg = r600_clear_surface_reg,
1308         },
1309         .hpd = {
1310                 .init = &evergreen_hpd_init,
1311                 .fini = &evergreen_hpd_fini,
1312                 .sense = &evergreen_hpd_sense,
1313                 .set_polarity = &evergreen_hpd_set_polarity,
1314         },
1315         .pm = {
1316                 .misc = &evergreen_pm_misc,
1317                 .prepare = &evergreen_pm_prepare,
1318                 .finish = &evergreen_pm_finish,
1319                 .init_profile = &r600_pm_init_profile,
1320                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1321                 .get_engine_clock = &radeon_atom_get_engine_clock,
1322                 .set_engine_clock = &radeon_atom_set_engine_clock,
1323                 .get_memory_clock = &radeon_atom_get_memory_clock,
1324                 .set_memory_clock = &radeon_atom_set_memory_clock,
1325                 .get_pcie_lanes = &r600_get_pcie_lanes,
1326                 .set_pcie_lanes = &r600_set_pcie_lanes,
1327                 .set_clock_gating = NULL,
1328                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1329                 .get_temperature = &evergreen_get_temp,
1330         },
1331         .dpm = {
1332                 .init = &cypress_dpm_init,
1333                 .setup_asic = &cypress_dpm_setup_asic,
1334                 .enable = &cypress_dpm_enable,
1335                 .late_enable = &rv770_dpm_late_enable,
1336                 .disable = &cypress_dpm_disable,
1337                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1338                 .set_power_state = &cypress_dpm_set_power_state,
1339                 .post_set_power_state = &r600_dpm_post_set_power_state,
1340                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1341                 .fini = &cypress_dpm_fini,
1342                 .get_sclk = &rv770_dpm_get_sclk,
1343                 .get_mclk = &rv770_dpm_get_mclk,
1344                 .print_power_state = &rv770_dpm_print_power_state,
1345                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1346                 .force_performance_level = &rv770_dpm_force_performance_level,
1347                 .vblank_too_short = &cypress_dpm_vblank_too_short,
1348         },
1349         .pflip = {
1350                 .page_flip = &evergreen_page_flip,
1351         },
1352 };
1353
1354 static struct radeon_asic sumo_asic = {
1355         .init = &evergreen_init,
1356         .fini = &evergreen_fini,
1357         .suspend = &evergreen_suspend,
1358         .resume = &evergreen_resume,
1359         .asic_reset = &evergreen_asic_reset,
1360         .vga_set_state = &r600_vga_set_state,
1361         .ioctl_wait_idle = r600_ioctl_wait_idle,
1362         .gui_idle = &r600_gui_idle,
1363         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1364         .get_xclk = &r600_get_xclk,
1365         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1366         .gart = {
1367                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1368                 .set_page = &rs600_gart_set_page,
1369         },
1370         .ring = {
1371                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1372                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1373                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1374         },
1375         .irq = {
1376                 .set = &evergreen_irq_set,
1377                 .process = &evergreen_irq_process,
1378         },
1379         .display = {
1380                 .bandwidth_update = &evergreen_bandwidth_update,
1381                 .get_vblank_counter = &evergreen_get_vblank_counter,
1382                 .wait_for_vblank = &dce4_wait_for_vblank,
1383                 .set_backlight_level = &atombios_set_backlight_level,
1384                 .get_backlight_level = &atombios_get_backlight_level,
1385                 .hdmi_enable = &evergreen_hdmi_enable,
1386                 .hdmi_setmode = &evergreen_hdmi_setmode,
1387         },
1388         .copy = {
1389                 .blit = &r600_copy_cpdma,
1390                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1391                 .dma = &evergreen_copy_dma,
1392                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1393                 .copy = &evergreen_copy_dma,
1394                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1395         },
1396         .surface = {
1397                 .set_reg = r600_set_surface_reg,
1398                 .clear_reg = r600_clear_surface_reg,
1399         },
1400         .hpd = {
1401                 .init = &evergreen_hpd_init,
1402                 .fini = &evergreen_hpd_fini,
1403                 .sense = &evergreen_hpd_sense,
1404                 .set_polarity = &evergreen_hpd_set_polarity,
1405         },
1406         .pm = {
1407                 .misc = &evergreen_pm_misc,
1408                 .prepare = &evergreen_pm_prepare,
1409                 .finish = &evergreen_pm_finish,
1410                 .init_profile = &sumo_pm_init_profile,
1411                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1412                 .get_engine_clock = &radeon_atom_get_engine_clock,
1413                 .set_engine_clock = &radeon_atom_set_engine_clock,
1414                 .get_memory_clock = NULL,
1415                 .set_memory_clock = NULL,
1416                 .get_pcie_lanes = NULL,
1417                 .set_pcie_lanes = NULL,
1418                 .set_clock_gating = NULL,
1419                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1420                 .get_temperature = &sumo_get_temp,
1421         },
1422         .dpm = {
1423                 .init = &sumo_dpm_init,
1424                 .setup_asic = &sumo_dpm_setup_asic,
1425                 .enable = &sumo_dpm_enable,
1426                 .late_enable = &sumo_dpm_late_enable,
1427                 .disable = &sumo_dpm_disable,
1428                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1429                 .set_power_state = &sumo_dpm_set_power_state,
1430                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1431                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1432                 .fini = &sumo_dpm_fini,
1433                 .get_sclk = &sumo_dpm_get_sclk,
1434                 .get_mclk = &sumo_dpm_get_mclk,
1435                 .print_power_state = &sumo_dpm_print_power_state,
1436                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1437                 .force_performance_level = &sumo_dpm_force_performance_level,
1438         },
1439         .pflip = {
1440                 .page_flip = &evergreen_page_flip,
1441         },
1442 };
1443
1444 static struct radeon_asic btc_asic = {
1445         .init = &evergreen_init,
1446         .fini = &evergreen_fini,
1447         .suspend = &evergreen_suspend,
1448         .resume = &evergreen_resume,
1449         .asic_reset = &evergreen_asic_reset,
1450         .vga_set_state = &r600_vga_set_state,
1451         .ioctl_wait_idle = r600_ioctl_wait_idle,
1452         .gui_idle = &r600_gui_idle,
1453         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1454         .get_xclk = &rv770_get_xclk,
1455         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1456         .gart = {
1457                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1458                 .set_page = &rs600_gart_set_page,
1459         },
1460         .ring = {
1461                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1462                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1463                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1464         },
1465         .irq = {
1466                 .set = &evergreen_irq_set,
1467                 .process = &evergreen_irq_process,
1468         },
1469         .display = {
1470                 .bandwidth_update = &evergreen_bandwidth_update,
1471                 .get_vblank_counter = &evergreen_get_vblank_counter,
1472                 .wait_for_vblank = &dce4_wait_for_vblank,
1473                 .set_backlight_level = &atombios_set_backlight_level,
1474                 .get_backlight_level = &atombios_get_backlight_level,
1475                 .hdmi_enable = &evergreen_hdmi_enable,
1476                 .hdmi_setmode = &evergreen_hdmi_setmode,
1477         },
1478         .copy = {
1479                 .blit = &r600_copy_cpdma,
1480                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1481                 .dma = &evergreen_copy_dma,
1482                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1483                 .copy = &evergreen_copy_dma,
1484                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1485         },
1486         .surface = {
1487                 .set_reg = r600_set_surface_reg,
1488                 .clear_reg = r600_clear_surface_reg,
1489         },
1490         .hpd = {
1491                 .init = &evergreen_hpd_init,
1492                 .fini = &evergreen_hpd_fini,
1493                 .sense = &evergreen_hpd_sense,
1494                 .set_polarity = &evergreen_hpd_set_polarity,
1495         },
1496         .pm = {
1497                 .misc = &evergreen_pm_misc,
1498                 .prepare = &evergreen_pm_prepare,
1499                 .finish = &evergreen_pm_finish,
1500                 .init_profile = &btc_pm_init_profile,
1501                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1502                 .get_engine_clock = &radeon_atom_get_engine_clock,
1503                 .set_engine_clock = &radeon_atom_set_engine_clock,
1504                 .get_memory_clock = &radeon_atom_get_memory_clock,
1505                 .set_memory_clock = &radeon_atom_set_memory_clock,
1506                 .get_pcie_lanes = &r600_get_pcie_lanes,
1507                 .set_pcie_lanes = &r600_set_pcie_lanes,
1508                 .set_clock_gating = NULL,
1509                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1510                 .get_temperature = &evergreen_get_temp,
1511         },
1512         .dpm = {
1513                 .init = &btc_dpm_init,
1514                 .setup_asic = &btc_dpm_setup_asic,
1515                 .enable = &btc_dpm_enable,
1516                 .late_enable = &rv770_dpm_late_enable,
1517                 .disable = &btc_dpm_disable,
1518                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1519                 .set_power_state = &btc_dpm_set_power_state,
1520                 .post_set_power_state = &btc_dpm_post_set_power_state,
1521                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1522                 .fini = &btc_dpm_fini,
1523                 .get_sclk = &btc_dpm_get_sclk,
1524                 .get_mclk = &btc_dpm_get_mclk,
1525                 .print_power_state = &rv770_dpm_print_power_state,
1526                 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1527                 .force_performance_level = &rv770_dpm_force_performance_level,
1528                 .vblank_too_short = &btc_dpm_vblank_too_short,
1529         },
1530         .pflip = {
1531                 .page_flip = &evergreen_page_flip,
1532         },
1533 };
1534
1535 static struct radeon_asic_ring cayman_gfx_ring = {
1536         .ib_execute = &cayman_ring_ib_execute,
1537         .ib_parse = &evergreen_ib_parse,
1538         .emit_fence = &cayman_fence_ring_emit,
1539         .emit_semaphore = &r600_semaphore_ring_emit,
1540         .cs_parse = &evergreen_cs_parse,
1541         .ring_test = &r600_ring_test,
1542         .ib_test = &r600_ib_test,
1543         .is_lockup = &cayman_gfx_is_lockup,
1544         .vm_flush = &cayman_vm_flush,
1545         .get_rptr = &cayman_gfx_get_rptr,
1546         .get_wptr = &cayman_gfx_get_wptr,
1547         .set_wptr = &cayman_gfx_set_wptr,
1548 };
1549
1550 static struct radeon_asic_ring cayman_dma_ring = {
1551         .ib_execute = &cayman_dma_ring_ib_execute,
1552         .ib_parse = &evergreen_dma_ib_parse,
1553         .emit_fence = &evergreen_dma_fence_ring_emit,
1554         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1555         .cs_parse = &evergreen_dma_cs_parse,
1556         .ring_test = &r600_dma_ring_test,
1557         .ib_test = &r600_dma_ib_test,
1558         .is_lockup = &cayman_dma_is_lockup,
1559         .vm_flush = &cayman_dma_vm_flush,
1560         .get_rptr = &cayman_dma_get_rptr,
1561         .get_wptr = &cayman_dma_get_wptr,
1562         .set_wptr = &cayman_dma_set_wptr
1563 };
1564
1565 static struct radeon_asic_ring cayman_uvd_ring = {
1566         .ib_execute = &uvd_v1_0_ib_execute,
1567         .emit_fence = &uvd_v2_2_fence_emit,
1568         .emit_semaphore = &uvd_v3_1_semaphore_emit,
1569         .cs_parse = &radeon_uvd_cs_parse,
1570         .ring_test = &uvd_v1_0_ring_test,
1571         .ib_test = &uvd_v1_0_ib_test,
1572         .is_lockup = &radeon_ring_test_lockup,
1573         .get_rptr = &uvd_v1_0_get_rptr,
1574         .get_wptr = &uvd_v1_0_get_wptr,
1575         .set_wptr = &uvd_v1_0_set_wptr,
1576 };
1577
1578 static struct radeon_asic cayman_asic = {
1579         .init = &cayman_init,
1580         .fini = &cayman_fini,
1581         .suspend = &cayman_suspend,
1582         .resume = &cayman_resume,
1583         .asic_reset = &cayman_asic_reset,
1584         .vga_set_state = &r600_vga_set_state,
1585         .ioctl_wait_idle = r600_ioctl_wait_idle,
1586         .gui_idle = &r600_gui_idle,
1587         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1588         .get_xclk = &rv770_get_xclk,
1589         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1590         .gart = {
1591                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1592                 .set_page = &rs600_gart_set_page,
1593         },
1594         .vm = {
1595                 .init = &cayman_vm_init,
1596                 .fini = &cayman_vm_fini,
1597                 .set_page = &cayman_dma_vm_set_page,
1598         },
1599         .ring = {
1600                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1601                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1602                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1603                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1604                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1605                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1606         },
1607         .irq = {
1608                 .set = &evergreen_irq_set,
1609                 .process = &evergreen_irq_process,
1610         },
1611         .display = {
1612                 .bandwidth_update = &evergreen_bandwidth_update,
1613                 .get_vblank_counter = &evergreen_get_vblank_counter,
1614                 .wait_for_vblank = &dce4_wait_for_vblank,
1615                 .set_backlight_level = &atombios_set_backlight_level,
1616                 .get_backlight_level = &atombios_get_backlight_level,
1617                 .hdmi_enable = &evergreen_hdmi_enable,
1618                 .hdmi_setmode = &evergreen_hdmi_setmode,
1619         },
1620         .copy = {
1621                 .blit = &r600_copy_cpdma,
1622                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1623                 .dma = &evergreen_copy_dma,
1624                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1625                 .copy = &evergreen_copy_dma,
1626                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1627         },
1628         .surface = {
1629                 .set_reg = r600_set_surface_reg,
1630                 .clear_reg = r600_clear_surface_reg,
1631         },
1632         .hpd = {
1633                 .init = &evergreen_hpd_init,
1634                 .fini = &evergreen_hpd_fini,
1635                 .sense = &evergreen_hpd_sense,
1636                 .set_polarity = &evergreen_hpd_set_polarity,
1637         },
1638         .pm = {
1639                 .misc = &evergreen_pm_misc,
1640                 .prepare = &evergreen_pm_prepare,
1641                 .finish = &evergreen_pm_finish,
1642                 .init_profile = &btc_pm_init_profile,
1643                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1644                 .get_engine_clock = &radeon_atom_get_engine_clock,
1645                 .set_engine_clock = &radeon_atom_set_engine_clock,
1646                 .get_memory_clock = &radeon_atom_get_memory_clock,
1647                 .set_memory_clock = &radeon_atom_set_memory_clock,
1648                 .get_pcie_lanes = &r600_get_pcie_lanes,
1649                 .set_pcie_lanes = &r600_set_pcie_lanes,
1650                 .set_clock_gating = NULL,
1651                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1652                 .get_temperature = &evergreen_get_temp,
1653         },
1654         .dpm = {
1655                 .init = &ni_dpm_init,
1656                 .setup_asic = &ni_dpm_setup_asic,
1657                 .enable = &ni_dpm_enable,
1658                 .late_enable = &rv770_dpm_late_enable,
1659                 .disable = &ni_dpm_disable,
1660                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1661                 .set_power_state = &ni_dpm_set_power_state,
1662                 .post_set_power_state = &ni_dpm_post_set_power_state,
1663                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1664                 .fini = &ni_dpm_fini,
1665                 .get_sclk = &ni_dpm_get_sclk,
1666                 .get_mclk = &ni_dpm_get_mclk,
1667                 .print_power_state = &ni_dpm_print_power_state,
1668                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1669                 .force_performance_level = &ni_dpm_force_performance_level,
1670                 .vblank_too_short = &ni_dpm_vblank_too_short,
1671         },
1672         .pflip = {
1673                 .page_flip = &evergreen_page_flip,
1674         },
1675 };
1676
1677 static struct radeon_asic trinity_asic = {
1678         .init = &cayman_init,
1679         .fini = &cayman_fini,
1680         .suspend = &cayman_suspend,
1681         .resume = &cayman_resume,
1682         .asic_reset = &cayman_asic_reset,
1683         .vga_set_state = &r600_vga_set_state,
1684         .ioctl_wait_idle = r600_ioctl_wait_idle,
1685         .gui_idle = &r600_gui_idle,
1686         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1687         .get_xclk = &r600_get_xclk,
1688         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1689         .gart = {
1690                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1691                 .set_page = &rs600_gart_set_page,
1692         },
1693         .vm = {
1694                 .init = &cayman_vm_init,
1695                 .fini = &cayman_vm_fini,
1696                 .set_page = &cayman_dma_vm_set_page,
1697         },
1698         .ring = {
1699                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1700                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1701                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1702                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1703                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1704                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1705         },
1706         .irq = {
1707                 .set = &evergreen_irq_set,
1708                 .process = &evergreen_irq_process,
1709         },
1710         .display = {
1711                 .bandwidth_update = &dce6_bandwidth_update,
1712                 .get_vblank_counter = &evergreen_get_vblank_counter,
1713                 .wait_for_vblank = &dce4_wait_for_vblank,
1714                 .set_backlight_level = &atombios_set_backlight_level,
1715                 .get_backlight_level = &atombios_get_backlight_level,
1716                 .hdmi_enable = &evergreen_hdmi_enable,
1717                 .hdmi_setmode = &evergreen_hdmi_setmode,
1718         },
1719         .copy = {
1720                 .blit = &r600_copy_cpdma,
1721                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1722                 .dma = &evergreen_copy_dma,
1723                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1724                 .copy = &evergreen_copy_dma,
1725                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1726         },
1727         .surface = {
1728                 .set_reg = r600_set_surface_reg,
1729                 .clear_reg = r600_clear_surface_reg,
1730         },
1731         .hpd = {
1732                 .init = &evergreen_hpd_init,
1733                 .fini = &evergreen_hpd_fini,
1734                 .sense = &evergreen_hpd_sense,
1735                 .set_polarity = &evergreen_hpd_set_polarity,
1736         },
1737         .pm = {
1738                 .misc = &evergreen_pm_misc,
1739                 .prepare = &evergreen_pm_prepare,
1740                 .finish = &evergreen_pm_finish,
1741                 .init_profile = &sumo_pm_init_profile,
1742                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1743                 .get_engine_clock = &radeon_atom_get_engine_clock,
1744                 .set_engine_clock = &radeon_atom_set_engine_clock,
1745                 .get_memory_clock = NULL,
1746                 .set_memory_clock = NULL,
1747                 .get_pcie_lanes = NULL,
1748                 .set_pcie_lanes = NULL,
1749                 .set_clock_gating = NULL,
1750                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1751                 .get_temperature = &tn_get_temp,
1752         },
1753         .dpm = {
1754                 .init = &trinity_dpm_init,
1755                 .setup_asic = &trinity_dpm_setup_asic,
1756                 .enable = &trinity_dpm_enable,
1757                 .late_enable = &trinity_dpm_late_enable,
1758                 .disable = &trinity_dpm_disable,
1759                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1760                 .set_power_state = &trinity_dpm_set_power_state,
1761                 .post_set_power_state = &trinity_dpm_post_set_power_state,
1762                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1763                 .fini = &trinity_dpm_fini,
1764                 .get_sclk = &trinity_dpm_get_sclk,
1765                 .get_mclk = &trinity_dpm_get_mclk,
1766                 .print_power_state = &trinity_dpm_print_power_state,
1767                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1768                 .force_performance_level = &trinity_dpm_force_performance_level,
1769                 .enable_bapm = &trinity_dpm_enable_bapm,
1770         },
1771         .pflip = {
1772                 .page_flip = &evergreen_page_flip,
1773         },
1774 };
1775
1776 static struct radeon_asic_ring si_gfx_ring = {
1777         .ib_execute = &si_ring_ib_execute,
1778         .ib_parse = &si_ib_parse,
1779         .emit_fence = &si_fence_ring_emit,
1780         .emit_semaphore = &r600_semaphore_ring_emit,
1781         .cs_parse = NULL,
1782         .ring_test = &r600_ring_test,
1783         .ib_test = &r600_ib_test,
1784         .is_lockup = &si_gfx_is_lockup,
1785         .vm_flush = &si_vm_flush,
1786         .get_rptr = &cayman_gfx_get_rptr,
1787         .get_wptr = &cayman_gfx_get_wptr,
1788         .set_wptr = &cayman_gfx_set_wptr,
1789 };
1790
1791 static struct radeon_asic_ring si_dma_ring = {
1792         .ib_execute = &cayman_dma_ring_ib_execute,
1793         .ib_parse = &evergreen_dma_ib_parse,
1794         .emit_fence = &evergreen_dma_fence_ring_emit,
1795         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1796         .cs_parse = NULL,
1797         .ring_test = &r600_dma_ring_test,
1798         .ib_test = &r600_dma_ib_test,
1799         .is_lockup = &si_dma_is_lockup,
1800         .vm_flush = &si_dma_vm_flush,
1801         .get_rptr = &cayman_dma_get_rptr,
1802         .get_wptr = &cayman_dma_get_wptr,
1803         .set_wptr = &cayman_dma_set_wptr,
1804 };
1805
1806 static struct radeon_asic si_asic = {
1807         .init = &si_init,
1808         .fini = &si_fini,
1809         .suspend = &si_suspend,
1810         .resume = &si_resume,
1811         .asic_reset = &si_asic_reset,
1812         .vga_set_state = &r600_vga_set_state,
1813         .ioctl_wait_idle = r600_ioctl_wait_idle,
1814         .gui_idle = &r600_gui_idle,
1815         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1816         .get_xclk = &si_get_xclk,
1817         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1818         .gart = {
1819                 .tlb_flush = &si_pcie_gart_tlb_flush,
1820                 .set_page = &rs600_gart_set_page,
1821         },
1822         .vm = {
1823                 .init = &si_vm_init,
1824                 .fini = &si_vm_fini,
1825                 .set_page = &si_dma_vm_set_page,
1826         },
1827         .ring = {
1828                 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1829                 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1830                 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1831                 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1832                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1833                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1834         },
1835         .irq = {
1836                 .set = &si_irq_set,
1837                 .process = &si_irq_process,
1838         },
1839         .display = {
1840                 .bandwidth_update = &dce6_bandwidth_update,
1841                 .get_vblank_counter = &evergreen_get_vblank_counter,
1842                 .wait_for_vblank = &dce4_wait_for_vblank,
1843                 .set_backlight_level = &atombios_set_backlight_level,
1844                 .get_backlight_level = &atombios_get_backlight_level,
1845                 .hdmi_enable = &evergreen_hdmi_enable,
1846                 .hdmi_setmode = &evergreen_hdmi_setmode,
1847         },
1848         .copy = {
1849                 .blit = &r600_copy_cpdma,
1850                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1851                 .dma = &si_copy_dma,
1852                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1853                 .copy = &si_copy_dma,
1854                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1855         },
1856         .surface = {
1857                 .set_reg = r600_set_surface_reg,
1858                 .clear_reg = r600_clear_surface_reg,
1859         },
1860         .hpd = {
1861                 .init = &evergreen_hpd_init,
1862                 .fini = &evergreen_hpd_fini,
1863                 .sense = &evergreen_hpd_sense,
1864                 .set_polarity = &evergreen_hpd_set_polarity,
1865         },
1866         .pm = {
1867                 .misc = &evergreen_pm_misc,
1868                 .prepare = &evergreen_pm_prepare,
1869                 .finish = &evergreen_pm_finish,
1870                 .init_profile = &sumo_pm_init_profile,
1871                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1872                 .get_engine_clock = &radeon_atom_get_engine_clock,
1873                 .set_engine_clock = &radeon_atom_set_engine_clock,
1874                 .get_memory_clock = &radeon_atom_get_memory_clock,
1875                 .set_memory_clock = &radeon_atom_set_memory_clock,
1876                 .get_pcie_lanes = &r600_get_pcie_lanes,
1877                 .set_pcie_lanes = &r600_set_pcie_lanes,
1878                 .set_clock_gating = NULL,
1879                 .set_uvd_clocks = &si_set_uvd_clocks,
1880                 .get_temperature = &si_get_temp,
1881         },
1882         .dpm = {
1883                 .init = &si_dpm_init,
1884                 .setup_asic = &si_dpm_setup_asic,
1885                 .enable = &si_dpm_enable,
1886                 .late_enable = &si_dpm_late_enable,
1887                 .disable = &si_dpm_disable,
1888                 .pre_set_power_state = &si_dpm_pre_set_power_state,
1889                 .set_power_state = &si_dpm_set_power_state,
1890                 .post_set_power_state = &si_dpm_post_set_power_state,
1891                 .display_configuration_changed = &si_dpm_display_configuration_changed,
1892                 .fini = &si_dpm_fini,
1893                 .get_sclk = &ni_dpm_get_sclk,
1894                 .get_mclk = &ni_dpm_get_mclk,
1895                 .print_power_state = &ni_dpm_print_power_state,
1896                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1897                 .force_performance_level = &si_dpm_force_performance_level,
1898                 .vblank_too_short = &ni_dpm_vblank_too_short,
1899         },
1900         .pflip = {
1901                 .page_flip = &evergreen_page_flip,
1902         },
1903 };
1904
1905 static struct radeon_asic_ring ci_gfx_ring = {
1906         .ib_execute = &cik_ring_ib_execute,
1907         .ib_parse = &cik_ib_parse,
1908         .emit_fence = &cik_fence_gfx_ring_emit,
1909         .emit_semaphore = &cik_semaphore_ring_emit,
1910         .cs_parse = NULL,
1911         .ring_test = &cik_ring_test,
1912         .ib_test = &cik_ib_test,
1913         .is_lockup = &cik_gfx_is_lockup,
1914         .vm_flush = &cik_vm_flush,
1915         .get_rptr = &cik_gfx_get_rptr,
1916         .get_wptr = &cik_gfx_get_wptr,
1917         .set_wptr = &cik_gfx_set_wptr,
1918 };
1919
1920 static struct radeon_asic_ring ci_cp_ring = {
1921         .ib_execute = &cik_ring_ib_execute,
1922         .ib_parse = &cik_ib_parse,
1923         .emit_fence = &cik_fence_compute_ring_emit,
1924         .emit_semaphore = &cik_semaphore_ring_emit,
1925         .cs_parse = NULL,
1926         .ring_test = &cik_ring_test,
1927         .ib_test = &cik_ib_test,
1928         .is_lockup = &cik_gfx_is_lockup,
1929         .vm_flush = &cik_vm_flush,
1930         .get_rptr = &cik_compute_get_rptr,
1931         .get_wptr = &cik_compute_get_wptr,
1932         .set_wptr = &cik_compute_set_wptr,
1933 };
1934
1935 static struct radeon_asic_ring ci_dma_ring = {
1936         .ib_execute = &cik_sdma_ring_ib_execute,
1937         .ib_parse = &cik_ib_parse,
1938         .emit_fence = &cik_sdma_fence_ring_emit,
1939         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1940         .cs_parse = NULL,
1941         .ring_test = &cik_sdma_ring_test,
1942         .ib_test = &cik_sdma_ib_test,
1943         .is_lockup = &cik_sdma_is_lockup,
1944         .vm_flush = &cik_dma_vm_flush,
1945         .get_rptr = &cik_sdma_get_rptr,
1946         .get_wptr = &cik_sdma_get_wptr,
1947         .set_wptr = &cik_sdma_set_wptr,
1948 };
1949
1950 static struct radeon_asic_ring ci_vce_ring = {
1951         .ib_execute = &radeon_vce_ib_execute,
1952         .emit_fence = &radeon_vce_fence_emit,
1953         .emit_semaphore = &radeon_vce_semaphore_emit,
1954         .cs_parse = &radeon_vce_cs_parse,
1955         .ring_test = &radeon_vce_ring_test,
1956         .ib_test = &radeon_vce_ib_test,
1957         .is_lockup = &radeon_ring_test_lockup,
1958         .get_rptr = &vce_v1_0_get_rptr,
1959         .get_wptr = &vce_v1_0_get_wptr,
1960         .set_wptr = &vce_v1_0_set_wptr,
1961 };
1962
1963 static struct radeon_asic ci_asic = {
1964         .init = &cik_init,
1965         .fini = &cik_fini,
1966         .suspend = &cik_suspend,
1967         .resume = &cik_resume,
1968         .asic_reset = &cik_asic_reset,
1969         .vga_set_state = &r600_vga_set_state,
1970         .ioctl_wait_idle = NULL,
1971         .gui_idle = &r600_gui_idle,
1972         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1973         .get_xclk = &cik_get_xclk,
1974         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
1975         .gart = {
1976                 .tlb_flush = &cik_pcie_gart_tlb_flush,
1977                 .set_page = &rs600_gart_set_page,
1978         },
1979         .vm = {
1980                 .init = &cik_vm_init,
1981                 .fini = &cik_vm_fini,
1982                 .set_page = &cik_sdma_vm_set_page,
1983         },
1984         .ring = {
1985                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
1986                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
1987                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
1988                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
1989                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
1990                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1991                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
1992                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
1993         },
1994         .irq = {
1995                 .set = &cik_irq_set,
1996                 .process = &cik_irq_process,
1997         },
1998         .display = {
1999                 .bandwidth_update = &dce8_bandwidth_update,
2000                 .get_vblank_counter = &evergreen_get_vblank_counter,
2001                 .wait_for_vblank = &dce4_wait_for_vblank,
2002                 .set_backlight_level = &atombios_set_backlight_level,
2003                 .get_backlight_level = &atombios_get_backlight_level,
2004                 .hdmi_enable = &evergreen_hdmi_enable,
2005                 .hdmi_setmode = &evergreen_hdmi_setmode,
2006         },
2007         .copy = {
2008                 .blit = &cik_copy_cpdma,
2009                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2010                 .dma = &cik_copy_dma,
2011                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2012                 .copy = &cik_copy_dma,
2013                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2014         },
2015         .surface = {
2016                 .set_reg = r600_set_surface_reg,
2017                 .clear_reg = r600_clear_surface_reg,
2018         },
2019         .hpd = {
2020                 .init = &evergreen_hpd_init,
2021                 .fini = &evergreen_hpd_fini,
2022                 .sense = &evergreen_hpd_sense,
2023                 .set_polarity = &evergreen_hpd_set_polarity,
2024         },
2025         .pm = {
2026                 .misc = &evergreen_pm_misc,
2027                 .prepare = &evergreen_pm_prepare,
2028                 .finish = &evergreen_pm_finish,
2029                 .init_profile = &sumo_pm_init_profile,
2030                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2031                 .get_engine_clock = &radeon_atom_get_engine_clock,
2032                 .set_engine_clock = &radeon_atom_set_engine_clock,
2033                 .get_memory_clock = &radeon_atom_get_memory_clock,
2034                 .set_memory_clock = &radeon_atom_set_memory_clock,
2035                 .get_pcie_lanes = NULL,
2036                 .set_pcie_lanes = NULL,
2037                 .set_clock_gating = NULL,
2038                 .set_uvd_clocks = &cik_set_uvd_clocks,
2039                 .set_vce_clocks = &cik_set_vce_clocks,
2040                 .get_temperature = &ci_get_temp,
2041         },
2042         .dpm = {
2043                 .init = &ci_dpm_init,
2044                 .setup_asic = &ci_dpm_setup_asic,
2045                 .enable = &ci_dpm_enable,
2046                 .late_enable = &ci_dpm_late_enable,
2047                 .disable = &ci_dpm_disable,
2048                 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2049                 .set_power_state = &ci_dpm_set_power_state,
2050                 .post_set_power_state = &ci_dpm_post_set_power_state,
2051                 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2052                 .fini = &ci_dpm_fini,
2053                 .get_sclk = &ci_dpm_get_sclk,
2054                 .get_mclk = &ci_dpm_get_mclk,
2055                 .print_power_state = &ci_dpm_print_power_state,
2056                 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2057                 .force_performance_level = &ci_dpm_force_performance_level,
2058                 .vblank_too_short = &ci_dpm_vblank_too_short,
2059                 .powergate_uvd = &ci_dpm_powergate_uvd,
2060         },
2061         .pflip = {
2062                 .page_flip = &evergreen_page_flip,
2063         },
2064 };
2065
2066 static struct radeon_asic kv_asic = {
2067         .init = &cik_init,
2068         .fini = &cik_fini,
2069         .suspend = &cik_suspend,
2070         .resume = &cik_resume,
2071         .asic_reset = &cik_asic_reset,
2072         .vga_set_state = &r600_vga_set_state,
2073         .ioctl_wait_idle = NULL,
2074         .gui_idle = &r600_gui_idle,
2075         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2076         .get_xclk = &cik_get_xclk,
2077         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2078         .gart = {
2079                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2080                 .set_page = &rs600_gart_set_page,
2081         },
2082         .vm = {
2083                 .init = &cik_vm_init,
2084                 .fini = &cik_vm_fini,
2085                 .set_page = &cik_sdma_vm_set_page,
2086         },
2087         .ring = {
2088                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2089                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2090                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2091                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2092                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2093                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2094                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2095                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2096         },
2097         .irq = {
2098                 .set = &cik_irq_set,
2099                 .process = &cik_irq_process,
2100         },
2101         .display = {
2102                 .bandwidth_update = &dce8_bandwidth_update,
2103                 .get_vblank_counter = &evergreen_get_vblank_counter,
2104                 .wait_for_vblank = &dce4_wait_for_vblank,
2105                 .set_backlight_level = &atombios_set_backlight_level,
2106                 .get_backlight_level = &atombios_get_backlight_level,
2107                 .hdmi_enable = &evergreen_hdmi_enable,
2108                 .hdmi_setmode = &evergreen_hdmi_setmode,
2109         },
2110         .copy = {
2111                 .blit = &cik_copy_cpdma,
2112                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2113                 .dma = &cik_copy_dma,
2114                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2115                 .copy = &cik_copy_dma,
2116                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2117         },
2118         .surface = {
2119                 .set_reg = r600_set_surface_reg,
2120                 .clear_reg = r600_clear_surface_reg,
2121         },
2122         .hpd = {
2123                 .init = &evergreen_hpd_init,
2124                 .fini = &evergreen_hpd_fini,
2125                 .sense = &evergreen_hpd_sense,
2126                 .set_polarity = &evergreen_hpd_set_polarity,
2127         },
2128         .pm = {
2129                 .misc = &evergreen_pm_misc,
2130                 .prepare = &evergreen_pm_prepare,
2131                 .finish = &evergreen_pm_finish,
2132                 .init_profile = &sumo_pm_init_profile,
2133                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2134                 .get_engine_clock = &radeon_atom_get_engine_clock,
2135                 .set_engine_clock = &radeon_atom_set_engine_clock,
2136                 .get_memory_clock = &radeon_atom_get_memory_clock,
2137                 .set_memory_clock = &radeon_atom_set_memory_clock,
2138                 .get_pcie_lanes = NULL,
2139                 .set_pcie_lanes = NULL,
2140                 .set_clock_gating = NULL,
2141                 .set_uvd_clocks = &cik_set_uvd_clocks,
2142                 .set_vce_clocks = &cik_set_vce_clocks,
2143                 .get_temperature = &kv_get_temp,
2144         },
2145         .dpm = {
2146                 .init = &kv_dpm_init,
2147                 .setup_asic = &kv_dpm_setup_asic,
2148                 .enable = &kv_dpm_enable,
2149                 .late_enable = &kv_dpm_late_enable,
2150                 .disable = &kv_dpm_disable,
2151                 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2152                 .set_power_state = &kv_dpm_set_power_state,
2153                 .post_set_power_state = &kv_dpm_post_set_power_state,
2154                 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2155                 .fini = &kv_dpm_fini,
2156                 .get_sclk = &kv_dpm_get_sclk,
2157                 .get_mclk = &kv_dpm_get_mclk,
2158                 .print_power_state = &kv_dpm_print_power_state,
2159                 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2160                 .force_performance_level = &kv_dpm_force_performance_level,
2161                 .powergate_uvd = &kv_dpm_powergate_uvd,
2162                 .enable_bapm = &kv_dpm_enable_bapm,
2163         },
2164         .pflip = {
2165                 .page_flip = &evergreen_page_flip,
2166         },
2167 };
2168
2169 /**
2170  * radeon_asic_init - register asic specific callbacks
2171  *
2172  * @rdev: radeon device pointer
2173  *
2174  * Registers the appropriate asic specific callbacks for each
2175  * chip family.  Also sets other asics specific info like the number
2176  * of crtcs and the register aperture accessors (all asics).
2177  * Returns 0 for success.
2178  */
2179 int radeon_asic_init(struct radeon_device *rdev)
2180 {
2181         radeon_register_accessor_init(rdev);
2182
2183         /* set the number of crtcs */
2184         if (rdev->flags & RADEON_SINGLE_CRTC)
2185                 rdev->num_crtc = 1;
2186         else
2187                 rdev->num_crtc = 2;
2188
2189         rdev->has_uvd = false;
2190
2191         switch (rdev->family) {
2192         case CHIP_R100:
2193         case CHIP_RV100:
2194         case CHIP_RS100:
2195         case CHIP_RV200:
2196         case CHIP_RS200:
2197                 rdev->asic = &r100_asic;
2198                 break;
2199         case CHIP_R200:
2200         case CHIP_RV250:
2201         case CHIP_RS300:
2202         case CHIP_RV280:
2203                 rdev->asic = &r200_asic;
2204                 break;
2205         case CHIP_R300:
2206         case CHIP_R350:
2207         case CHIP_RV350:
2208         case CHIP_RV380:
2209                 if (rdev->flags & RADEON_IS_PCIE)
2210                         rdev->asic = &r300_asic_pcie;
2211                 else
2212                         rdev->asic = &r300_asic;
2213                 break;
2214         case CHIP_R420:
2215         case CHIP_R423:
2216         case CHIP_RV410:
2217                 rdev->asic = &r420_asic;
2218                 /* handle macs */
2219                 if (rdev->bios == NULL) {
2220                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2221                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2222                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2223                         rdev->asic->pm.set_memory_clock = NULL;
2224                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2225                 }
2226                 break;
2227         case CHIP_RS400:
2228         case CHIP_RS480:
2229                 rdev->asic = &rs400_asic;
2230                 break;
2231         case CHIP_RS600:
2232                 rdev->asic = &rs600_asic;
2233                 break;
2234         case CHIP_RS690:
2235         case CHIP_RS740:
2236                 rdev->asic = &rs690_asic;
2237                 break;
2238         case CHIP_RV515:
2239                 rdev->asic = &rv515_asic;
2240                 break;
2241         case CHIP_R520:
2242         case CHIP_RV530:
2243         case CHIP_RV560:
2244         case CHIP_RV570:
2245         case CHIP_R580:
2246                 rdev->asic = &r520_asic;
2247                 break;
2248         case CHIP_R600:
2249                 rdev->asic = &r600_asic;
2250                 break;
2251         case CHIP_RV610:
2252         case CHIP_RV630:
2253         case CHIP_RV620:
2254         case CHIP_RV635:
2255         case CHIP_RV670:
2256                 rdev->asic = &rv6xx_asic;
2257                 rdev->has_uvd = true;
2258                 break;
2259         case CHIP_RS780:
2260         case CHIP_RS880:
2261                 rdev->asic = &rs780_asic;
2262                 rdev->has_uvd = true;
2263                 break;
2264         case CHIP_RV770:
2265         case CHIP_RV730:
2266         case CHIP_RV710:
2267         case CHIP_RV740:
2268                 rdev->asic = &rv770_asic;
2269                 rdev->has_uvd = true;
2270                 break;
2271         case CHIP_CEDAR:
2272         case CHIP_REDWOOD:
2273         case CHIP_JUNIPER:
2274         case CHIP_CYPRESS:
2275         case CHIP_HEMLOCK:
2276                 /* set num crtcs */
2277                 if (rdev->family == CHIP_CEDAR)
2278                         rdev->num_crtc = 4;
2279                 else
2280                         rdev->num_crtc = 6;
2281                 rdev->asic = &evergreen_asic;
2282                 rdev->has_uvd = true;
2283                 break;
2284         case CHIP_PALM:
2285         case CHIP_SUMO:
2286         case CHIP_SUMO2:
2287                 rdev->asic = &sumo_asic;
2288                 rdev->has_uvd = true;
2289                 break;
2290         case CHIP_BARTS:
2291         case CHIP_TURKS:
2292         case CHIP_CAICOS:
2293                 /* set num crtcs */
2294                 if (rdev->family == CHIP_CAICOS)
2295                         rdev->num_crtc = 4;
2296                 else
2297                         rdev->num_crtc = 6;
2298                 rdev->asic = &btc_asic;
2299                 rdev->has_uvd = true;
2300                 break;
2301         case CHIP_CAYMAN:
2302                 rdev->asic = &cayman_asic;
2303                 /* set num crtcs */
2304                 rdev->num_crtc = 6;
2305                 rdev->has_uvd = true;
2306                 break;
2307         case CHIP_ARUBA:
2308                 rdev->asic = &trinity_asic;
2309                 /* set num crtcs */
2310                 rdev->num_crtc = 4;
2311                 rdev->has_uvd = true;
2312                 break;
2313         case CHIP_TAHITI:
2314         case CHIP_PITCAIRN:
2315         case CHIP_VERDE:
2316         case CHIP_OLAND:
2317         case CHIP_HAINAN:
2318                 rdev->asic = &si_asic;
2319                 /* set num crtcs */
2320                 if (rdev->family == CHIP_HAINAN)
2321                         rdev->num_crtc = 0;
2322                 else if (rdev->family == CHIP_OLAND)
2323                         rdev->num_crtc = 2;
2324                 else
2325                         rdev->num_crtc = 6;
2326                 if (rdev->family == CHIP_HAINAN)
2327                         rdev->has_uvd = false;
2328                 else
2329                         rdev->has_uvd = true;
2330                 switch (rdev->family) {
2331                 case CHIP_TAHITI:
2332                         rdev->cg_flags =
2333                                 RADEON_CG_SUPPORT_GFX_MGCG |
2334                                 RADEON_CG_SUPPORT_GFX_MGLS |
2335                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2336                                 RADEON_CG_SUPPORT_GFX_CGLS |
2337                                 RADEON_CG_SUPPORT_GFX_CGTS |
2338                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2339                                 RADEON_CG_SUPPORT_MC_MGCG |
2340                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2341                                 RADEON_CG_SUPPORT_BIF_LS |
2342                                 RADEON_CG_SUPPORT_VCE_MGCG |
2343                                 RADEON_CG_SUPPORT_UVD_MGCG |
2344                                 RADEON_CG_SUPPORT_HDP_LS |
2345                                 RADEON_CG_SUPPORT_HDP_MGCG;
2346                         rdev->pg_flags = 0;
2347                         break;
2348                 case CHIP_PITCAIRN:
2349                         rdev->cg_flags =
2350                                 RADEON_CG_SUPPORT_GFX_MGCG |
2351                                 RADEON_CG_SUPPORT_GFX_MGLS |
2352                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2353                                 RADEON_CG_SUPPORT_GFX_CGLS |
2354                                 RADEON_CG_SUPPORT_GFX_CGTS |
2355                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2356                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2357                                 RADEON_CG_SUPPORT_MC_LS |
2358                                 RADEON_CG_SUPPORT_MC_MGCG |
2359                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2360                                 RADEON_CG_SUPPORT_BIF_LS |
2361                                 RADEON_CG_SUPPORT_VCE_MGCG |
2362                                 RADEON_CG_SUPPORT_UVD_MGCG |
2363                                 RADEON_CG_SUPPORT_HDP_LS |
2364                                 RADEON_CG_SUPPORT_HDP_MGCG;
2365                         rdev->pg_flags = 0;
2366                         break;
2367                 case CHIP_VERDE:
2368                         rdev->cg_flags =
2369                                 RADEON_CG_SUPPORT_GFX_MGCG |
2370                                 RADEON_CG_SUPPORT_GFX_MGLS |
2371                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2372                                 RADEON_CG_SUPPORT_GFX_CGLS |
2373                                 RADEON_CG_SUPPORT_GFX_CGTS |
2374                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2375                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2376                                 RADEON_CG_SUPPORT_MC_LS |
2377                                 RADEON_CG_SUPPORT_MC_MGCG |
2378                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2379                                 RADEON_CG_SUPPORT_BIF_LS |
2380                                 RADEON_CG_SUPPORT_VCE_MGCG |
2381                                 RADEON_CG_SUPPORT_UVD_MGCG |
2382                                 RADEON_CG_SUPPORT_HDP_LS |
2383                                 RADEON_CG_SUPPORT_HDP_MGCG;
2384                         rdev->pg_flags = 0 |
2385                                 /*RADEON_PG_SUPPORT_GFX_PG | */
2386                                 RADEON_PG_SUPPORT_SDMA;
2387                         break;
2388                 case CHIP_OLAND:
2389                         rdev->cg_flags =
2390                                 RADEON_CG_SUPPORT_GFX_MGCG |
2391                                 RADEON_CG_SUPPORT_GFX_MGLS |
2392                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2393                                 RADEON_CG_SUPPORT_GFX_CGLS |
2394                                 RADEON_CG_SUPPORT_GFX_CGTS |
2395                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2396                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2397                                 RADEON_CG_SUPPORT_MC_LS |
2398                                 RADEON_CG_SUPPORT_MC_MGCG |
2399                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2400                                 RADEON_CG_SUPPORT_BIF_LS |
2401                                 RADEON_CG_SUPPORT_UVD_MGCG |
2402                                 RADEON_CG_SUPPORT_HDP_LS |
2403                                 RADEON_CG_SUPPORT_HDP_MGCG;
2404                         rdev->pg_flags = 0;
2405                         break;
2406                 case CHIP_HAINAN:
2407                         rdev->cg_flags =
2408                                 RADEON_CG_SUPPORT_GFX_MGCG |
2409                                 RADEON_CG_SUPPORT_GFX_MGLS |
2410                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2411                                 RADEON_CG_SUPPORT_GFX_CGLS |
2412                                 RADEON_CG_SUPPORT_GFX_CGTS |
2413                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2414                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2415                                 RADEON_CG_SUPPORT_MC_LS |
2416                                 RADEON_CG_SUPPORT_MC_MGCG |
2417                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2418                                 RADEON_CG_SUPPORT_BIF_LS |
2419                                 RADEON_CG_SUPPORT_HDP_LS |
2420                                 RADEON_CG_SUPPORT_HDP_MGCG;
2421                         rdev->pg_flags = 0;
2422                         break;
2423                 default:
2424                         rdev->cg_flags = 0;
2425                         rdev->pg_flags = 0;
2426                         break;
2427                 }
2428                 break;
2429         case CHIP_BONAIRE:
2430         case CHIP_HAWAII:
2431                 rdev->asic = &ci_asic;
2432                 rdev->num_crtc = 6;
2433                 rdev->has_uvd = true;
2434                 if (rdev->family == CHIP_BONAIRE) {
2435                         rdev->cg_flags =
2436                                 RADEON_CG_SUPPORT_GFX_MGCG |
2437                                 RADEON_CG_SUPPORT_GFX_MGLS |
2438                                 RADEON_CG_SUPPORT_GFX_CGCG |
2439                                 RADEON_CG_SUPPORT_GFX_CGLS |
2440                                 RADEON_CG_SUPPORT_GFX_CGTS |
2441                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2442                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2443                                 RADEON_CG_SUPPORT_MC_LS |
2444                                 RADEON_CG_SUPPORT_MC_MGCG |
2445                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2446                                 RADEON_CG_SUPPORT_SDMA_LS |
2447                                 RADEON_CG_SUPPORT_BIF_LS |
2448                                 RADEON_CG_SUPPORT_VCE_MGCG |
2449                                 RADEON_CG_SUPPORT_UVD_MGCG |
2450                                 RADEON_CG_SUPPORT_HDP_LS |
2451                                 RADEON_CG_SUPPORT_HDP_MGCG;
2452                         rdev->pg_flags = 0;
2453                 } else {
2454                         rdev->cg_flags =
2455                                 RADEON_CG_SUPPORT_GFX_MGCG |
2456                                 RADEON_CG_SUPPORT_GFX_MGLS |
2457                                 RADEON_CG_SUPPORT_GFX_CGCG |
2458                                 RADEON_CG_SUPPORT_GFX_CGLS |
2459                                 RADEON_CG_SUPPORT_GFX_CGTS |
2460                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2461                                 RADEON_CG_SUPPORT_MC_LS |
2462                                 RADEON_CG_SUPPORT_MC_MGCG |
2463                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2464                                 RADEON_CG_SUPPORT_SDMA_LS |
2465                                 RADEON_CG_SUPPORT_BIF_LS |
2466                                 RADEON_CG_SUPPORT_VCE_MGCG |
2467                                 RADEON_CG_SUPPORT_UVD_MGCG |
2468                                 RADEON_CG_SUPPORT_HDP_LS |
2469                                 RADEON_CG_SUPPORT_HDP_MGCG;
2470                         rdev->pg_flags = 0;
2471                 }
2472                 break;
2473         case CHIP_KAVERI:
2474         case CHIP_KABINI:
2475                 rdev->asic = &kv_asic;
2476                 /* set num crtcs */
2477                 if (rdev->family == CHIP_KAVERI) {
2478                         rdev->num_crtc = 4;
2479                         rdev->cg_flags =
2480                                 RADEON_CG_SUPPORT_GFX_MGCG |
2481                                 RADEON_CG_SUPPORT_GFX_MGLS |
2482                                 RADEON_CG_SUPPORT_GFX_CGCG |
2483                                 RADEON_CG_SUPPORT_GFX_CGLS |
2484                                 RADEON_CG_SUPPORT_GFX_CGTS |
2485                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2486                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2487                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2488                                 RADEON_CG_SUPPORT_SDMA_LS |
2489                                 RADEON_CG_SUPPORT_BIF_LS |
2490                                 RADEON_CG_SUPPORT_VCE_MGCG |
2491                                 RADEON_CG_SUPPORT_UVD_MGCG |
2492                                 RADEON_CG_SUPPORT_HDP_LS |
2493                                 RADEON_CG_SUPPORT_HDP_MGCG;
2494                         rdev->pg_flags = 0;
2495                                 /*RADEON_PG_SUPPORT_GFX_PG |
2496                                 RADEON_PG_SUPPORT_GFX_SMG |
2497                                 RADEON_PG_SUPPORT_GFX_DMG |
2498                                 RADEON_PG_SUPPORT_UVD |
2499                                 RADEON_PG_SUPPORT_VCE |
2500                                 RADEON_PG_SUPPORT_CP |
2501                                 RADEON_PG_SUPPORT_GDS |
2502                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2503                                 RADEON_PG_SUPPORT_ACP |
2504                                 RADEON_PG_SUPPORT_SAMU;*/
2505                 } else {
2506                         rdev->num_crtc = 2;
2507                         rdev->cg_flags =
2508                                 RADEON_CG_SUPPORT_GFX_MGCG |
2509                                 RADEON_CG_SUPPORT_GFX_MGLS |
2510                                 RADEON_CG_SUPPORT_GFX_CGCG |
2511                                 RADEON_CG_SUPPORT_GFX_CGLS |
2512                                 RADEON_CG_SUPPORT_GFX_CGTS |
2513                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2514                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2515                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2516                                 RADEON_CG_SUPPORT_SDMA_LS |
2517                                 RADEON_CG_SUPPORT_BIF_LS |
2518                                 RADEON_CG_SUPPORT_VCE_MGCG |
2519                                 RADEON_CG_SUPPORT_UVD_MGCG |
2520                                 RADEON_CG_SUPPORT_HDP_LS |
2521                                 RADEON_CG_SUPPORT_HDP_MGCG;
2522                         rdev->pg_flags = 0;
2523                                 /*RADEON_PG_SUPPORT_GFX_PG |
2524                                 RADEON_PG_SUPPORT_GFX_SMG |
2525                                 RADEON_PG_SUPPORT_UVD |
2526                                 RADEON_PG_SUPPORT_VCE |
2527                                 RADEON_PG_SUPPORT_CP |
2528                                 RADEON_PG_SUPPORT_GDS |
2529                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2530                                 RADEON_PG_SUPPORT_SAMU;*/
2531                 }
2532                 rdev->has_uvd = true;
2533                 break;
2534         default:
2535                 /* FIXME: not supported yet */
2536                 return -EINVAL;
2537         }
2538
2539         if (rdev->flags & RADEON_IS_IGP) {
2540                 rdev->asic->pm.get_memory_clock = NULL;
2541                 rdev->asic->pm.set_memory_clock = NULL;
2542         }
2543
2544         return 0;
2545 }
2546