drm/radeon/ni: implement get_current_sclk/mclk
[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / radeon / radeon_asic.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28
29 #include <linux/console.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "atom.h"
39
40 /*
41  * Registers accessors functions.
42  */
43 /**
44  * radeon_invalid_rreg - dummy reg read function
45  *
46  * @rdev: radeon device pointer
47  * @reg: offset of register
48  *
49  * Dummy register read function.  Used for register blocks
50  * that certain asics don't have (all asics).
51  * Returns the value in the register.
52  */
53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54 {
55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56         BUG_ON(1);
57         return 0;
58 }
59
60 /**
61  * radeon_invalid_wreg - dummy reg write function
62  *
63  * @rdev: radeon device pointer
64  * @reg: offset of register
65  * @v: value to write to the register
66  *
67  * Dummy register read function.  Used for register blocks
68  * that certain asics don't have (all asics).
69  */
70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71 {
72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73                   reg, v);
74         BUG_ON(1);
75 }
76
77 /**
78  * radeon_register_accessor_init - sets up the register accessor callbacks
79  *
80  * @rdev: radeon device pointer
81  *
82  * Sets up the register accessor callbacks for various register
83  * apertures.  Not all asics have all apertures (all asics).
84  */
85 static void radeon_register_accessor_init(struct radeon_device *rdev)
86 {
87         rdev->mc_rreg = &radeon_invalid_rreg;
88         rdev->mc_wreg = &radeon_invalid_wreg;
89         rdev->pll_rreg = &radeon_invalid_rreg;
90         rdev->pll_wreg = &radeon_invalid_wreg;
91         rdev->pciep_rreg = &radeon_invalid_rreg;
92         rdev->pciep_wreg = &radeon_invalid_wreg;
93
94         /* Don't change order as we are overridding accessor. */
95         if (rdev->family < CHIP_RV515) {
96                 rdev->pcie_reg_mask = 0xff;
97         } else {
98                 rdev->pcie_reg_mask = 0x7ff;
99         }
100         /* FIXME: not sure here */
101         if (rdev->family <= CHIP_R580) {
102                 rdev->pll_rreg = &r100_pll_rreg;
103                 rdev->pll_wreg = &r100_pll_wreg;
104         }
105         if (rdev->family >= CHIP_R420) {
106                 rdev->mc_rreg = &r420_mc_rreg;
107                 rdev->mc_wreg = &r420_mc_wreg;
108         }
109         if (rdev->family >= CHIP_RV515) {
110                 rdev->mc_rreg = &rv515_mc_rreg;
111                 rdev->mc_wreg = &rv515_mc_wreg;
112         }
113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114                 rdev->mc_rreg = &rs400_mc_rreg;
115                 rdev->mc_wreg = &rs400_mc_wreg;
116         }
117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118                 rdev->mc_rreg = &rs690_mc_rreg;
119                 rdev->mc_wreg = &rs690_mc_wreg;
120         }
121         if (rdev->family == CHIP_RS600) {
122                 rdev->mc_rreg = &rs600_mc_rreg;
123                 rdev->mc_wreg = &rs600_mc_wreg;
124         }
125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126                 rdev->mc_rreg = &rs780_mc_rreg;
127                 rdev->mc_wreg = &rs780_mc_wreg;
128         }
129
130         if (rdev->family >= CHIP_BONAIRE) {
131                 rdev->pciep_rreg = &cik_pciep_rreg;
132                 rdev->pciep_wreg = &cik_pciep_wreg;
133         } else if (rdev->family >= CHIP_R600) {
134                 rdev->pciep_rreg = &r600_pciep_rreg;
135                 rdev->pciep_wreg = &r600_pciep_wreg;
136         }
137 }
138
139
140 /* helper to disable agp */
141 /**
142  * radeon_agp_disable - AGP disable helper function
143  *
144  * @rdev: radeon device pointer
145  *
146  * Removes AGP flags and changes the gart callbacks on AGP
147  * cards when using the internal gart rather than AGP (all asics).
148  */
149 void radeon_agp_disable(struct radeon_device *rdev)
150 {
151         rdev->flags &= ~RADEON_IS_AGP;
152         if (rdev->family >= CHIP_R600) {
153                 DRM_INFO("Forcing AGP to PCIE mode\n");
154                 rdev->flags |= RADEON_IS_PCIE;
155         } else if (rdev->family >= CHIP_RV515 ||
156                         rdev->family == CHIP_RV380 ||
157                         rdev->family == CHIP_RV410 ||
158                         rdev->family == CHIP_R423) {
159                 DRM_INFO("Forcing AGP to PCIE mode\n");
160                 rdev->flags |= RADEON_IS_PCIE;
161                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162                 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
163                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
164         } else {
165                 DRM_INFO("Forcing AGP to PCI mode\n");
166                 rdev->flags |= RADEON_IS_PCI;
167                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
168                 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
169                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
170         }
171         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
172 }
173
174 /*
175  * ASIC
176  */
177
178 static struct radeon_asic_ring r100_gfx_ring = {
179         .ib_execute = &r100_ring_ib_execute,
180         .emit_fence = &r100_fence_ring_emit,
181         .emit_semaphore = &r100_semaphore_ring_emit,
182         .cs_parse = &r100_cs_parse,
183         .ring_start = &r100_ring_start,
184         .ring_test = &r100_ring_test,
185         .ib_test = &r100_ib_test,
186         .is_lockup = &r100_gpu_is_lockup,
187         .get_rptr = &r100_gfx_get_rptr,
188         .get_wptr = &r100_gfx_get_wptr,
189         .set_wptr = &r100_gfx_set_wptr,
190 };
191
192 static struct radeon_asic r100_asic = {
193         .init = &r100_init,
194         .fini = &r100_fini,
195         .suspend = &r100_suspend,
196         .resume = &r100_resume,
197         .vga_set_state = &r100_vga_set_state,
198         .asic_reset = &r100_asic_reset,
199         .mmio_hdp_flush = NULL,
200         .gui_idle = &r100_gui_idle,
201         .mc_wait_for_idle = &r100_mc_wait_for_idle,
202         .gart = {
203                 .tlb_flush = &r100_pci_gart_tlb_flush,
204                 .get_page_entry = &r100_pci_gart_get_page_entry,
205                 .set_page = &r100_pci_gart_set_page,
206         },
207         .ring = {
208                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
209         },
210         .irq = {
211                 .set = &r100_irq_set,
212                 .process = &r100_irq_process,
213         },
214         .display = {
215                 .bandwidth_update = &r100_bandwidth_update,
216                 .get_vblank_counter = &r100_get_vblank_counter,
217                 .wait_for_vblank = &r100_wait_for_vblank,
218                 .set_backlight_level = &radeon_legacy_set_backlight_level,
219                 .get_backlight_level = &radeon_legacy_get_backlight_level,
220         },
221         .copy = {
222                 .blit = &r100_copy_blit,
223                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
224                 .dma = NULL,
225                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
226                 .copy = &r100_copy_blit,
227                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
228         },
229         .surface = {
230                 .set_reg = r100_set_surface_reg,
231                 .clear_reg = r100_clear_surface_reg,
232         },
233         .hpd = {
234                 .init = &r100_hpd_init,
235                 .fini = &r100_hpd_fini,
236                 .sense = &r100_hpd_sense,
237                 .set_polarity = &r100_hpd_set_polarity,
238         },
239         .pm = {
240                 .misc = &r100_pm_misc,
241                 .prepare = &r100_pm_prepare,
242                 .finish = &r100_pm_finish,
243                 .init_profile = &r100_pm_init_profile,
244                 .get_dynpm_state = &r100_pm_get_dynpm_state,
245                 .get_engine_clock = &radeon_legacy_get_engine_clock,
246                 .set_engine_clock = &radeon_legacy_set_engine_clock,
247                 .get_memory_clock = &radeon_legacy_get_memory_clock,
248                 .set_memory_clock = NULL,
249                 .get_pcie_lanes = NULL,
250                 .set_pcie_lanes = NULL,
251                 .set_clock_gating = &radeon_legacy_set_clock_gating,
252         },
253         .pflip = {
254                 .page_flip = &r100_page_flip,
255                 .page_flip_pending = &r100_page_flip_pending,
256         },
257 };
258
259 static struct radeon_asic r200_asic = {
260         .init = &r100_init,
261         .fini = &r100_fini,
262         .suspend = &r100_suspend,
263         .resume = &r100_resume,
264         .vga_set_state = &r100_vga_set_state,
265         .asic_reset = &r100_asic_reset,
266         .mmio_hdp_flush = NULL,
267         .gui_idle = &r100_gui_idle,
268         .mc_wait_for_idle = &r100_mc_wait_for_idle,
269         .gart = {
270                 .tlb_flush = &r100_pci_gart_tlb_flush,
271                 .get_page_entry = &r100_pci_gart_get_page_entry,
272                 .set_page = &r100_pci_gart_set_page,
273         },
274         .ring = {
275                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
276         },
277         .irq = {
278                 .set = &r100_irq_set,
279                 .process = &r100_irq_process,
280         },
281         .display = {
282                 .bandwidth_update = &r100_bandwidth_update,
283                 .get_vblank_counter = &r100_get_vblank_counter,
284                 .wait_for_vblank = &r100_wait_for_vblank,
285                 .set_backlight_level = &radeon_legacy_set_backlight_level,
286                 .get_backlight_level = &radeon_legacy_get_backlight_level,
287         },
288         .copy = {
289                 .blit = &r100_copy_blit,
290                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
291                 .dma = &r200_copy_dma,
292                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
293                 .copy = &r100_copy_blit,
294                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
295         },
296         .surface = {
297                 .set_reg = r100_set_surface_reg,
298                 .clear_reg = r100_clear_surface_reg,
299         },
300         .hpd = {
301                 .init = &r100_hpd_init,
302                 .fini = &r100_hpd_fini,
303                 .sense = &r100_hpd_sense,
304                 .set_polarity = &r100_hpd_set_polarity,
305         },
306         .pm = {
307                 .misc = &r100_pm_misc,
308                 .prepare = &r100_pm_prepare,
309                 .finish = &r100_pm_finish,
310                 .init_profile = &r100_pm_init_profile,
311                 .get_dynpm_state = &r100_pm_get_dynpm_state,
312                 .get_engine_clock = &radeon_legacy_get_engine_clock,
313                 .set_engine_clock = &radeon_legacy_set_engine_clock,
314                 .get_memory_clock = &radeon_legacy_get_memory_clock,
315                 .set_memory_clock = NULL,
316                 .get_pcie_lanes = NULL,
317                 .set_pcie_lanes = NULL,
318                 .set_clock_gating = &radeon_legacy_set_clock_gating,
319         },
320         .pflip = {
321                 .page_flip = &r100_page_flip,
322                 .page_flip_pending = &r100_page_flip_pending,
323         },
324 };
325
326 static struct radeon_asic_ring r300_gfx_ring = {
327         .ib_execute = &r100_ring_ib_execute,
328         .emit_fence = &r300_fence_ring_emit,
329         .emit_semaphore = &r100_semaphore_ring_emit,
330         .cs_parse = &r300_cs_parse,
331         .ring_start = &r300_ring_start,
332         .ring_test = &r100_ring_test,
333         .ib_test = &r100_ib_test,
334         .is_lockup = &r100_gpu_is_lockup,
335         .get_rptr = &r100_gfx_get_rptr,
336         .get_wptr = &r100_gfx_get_wptr,
337         .set_wptr = &r100_gfx_set_wptr,
338 };
339
340 static struct radeon_asic_ring rv515_gfx_ring = {
341         .ib_execute = &r100_ring_ib_execute,
342         .emit_fence = &r300_fence_ring_emit,
343         .emit_semaphore = &r100_semaphore_ring_emit,
344         .cs_parse = &r300_cs_parse,
345         .ring_start = &rv515_ring_start,
346         .ring_test = &r100_ring_test,
347         .ib_test = &r100_ib_test,
348         .is_lockup = &r100_gpu_is_lockup,
349         .get_rptr = &r100_gfx_get_rptr,
350         .get_wptr = &r100_gfx_get_wptr,
351         .set_wptr = &r100_gfx_set_wptr,
352 };
353
354 static struct radeon_asic r300_asic = {
355         .init = &r300_init,
356         .fini = &r300_fini,
357         .suspend = &r300_suspend,
358         .resume = &r300_resume,
359         .vga_set_state = &r100_vga_set_state,
360         .asic_reset = &r300_asic_reset,
361         .mmio_hdp_flush = NULL,
362         .gui_idle = &r100_gui_idle,
363         .mc_wait_for_idle = &r300_mc_wait_for_idle,
364         .gart = {
365                 .tlb_flush = &r100_pci_gart_tlb_flush,
366                 .get_page_entry = &r100_pci_gart_get_page_entry,
367                 .set_page = &r100_pci_gart_set_page,
368         },
369         .ring = {
370                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
371         },
372         .irq = {
373                 .set = &r100_irq_set,
374                 .process = &r100_irq_process,
375         },
376         .display = {
377                 .bandwidth_update = &r100_bandwidth_update,
378                 .get_vblank_counter = &r100_get_vblank_counter,
379                 .wait_for_vblank = &r100_wait_for_vblank,
380                 .set_backlight_level = &radeon_legacy_set_backlight_level,
381                 .get_backlight_level = &radeon_legacy_get_backlight_level,
382         },
383         .copy = {
384                 .blit = &r100_copy_blit,
385                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
386                 .dma = &r200_copy_dma,
387                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
388                 .copy = &r100_copy_blit,
389                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
390         },
391         .surface = {
392                 .set_reg = r100_set_surface_reg,
393                 .clear_reg = r100_clear_surface_reg,
394         },
395         .hpd = {
396                 .init = &r100_hpd_init,
397                 .fini = &r100_hpd_fini,
398                 .sense = &r100_hpd_sense,
399                 .set_polarity = &r100_hpd_set_polarity,
400         },
401         .pm = {
402                 .misc = &r100_pm_misc,
403                 .prepare = &r100_pm_prepare,
404                 .finish = &r100_pm_finish,
405                 .init_profile = &r100_pm_init_profile,
406                 .get_dynpm_state = &r100_pm_get_dynpm_state,
407                 .get_engine_clock = &radeon_legacy_get_engine_clock,
408                 .set_engine_clock = &radeon_legacy_set_engine_clock,
409                 .get_memory_clock = &radeon_legacy_get_memory_clock,
410                 .set_memory_clock = NULL,
411                 .get_pcie_lanes = &rv370_get_pcie_lanes,
412                 .set_pcie_lanes = &rv370_set_pcie_lanes,
413                 .set_clock_gating = &radeon_legacy_set_clock_gating,
414         },
415         .pflip = {
416                 .page_flip = &r100_page_flip,
417                 .page_flip_pending = &r100_page_flip_pending,
418         },
419 };
420
421 static struct radeon_asic r300_asic_pcie = {
422         .init = &r300_init,
423         .fini = &r300_fini,
424         .suspend = &r300_suspend,
425         .resume = &r300_resume,
426         .vga_set_state = &r100_vga_set_state,
427         .asic_reset = &r300_asic_reset,
428         .mmio_hdp_flush = NULL,
429         .gui_idle = &r100_gui_idle,
430         .mc_wait_for_idle = &r300_mc_wait_for_idle,
431         .gart = {
432                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
433                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
434                 .set_page = &rv370_pcie_gart_set_page,
435         },
436         .ring = {
437                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
438         },
439         .irq = {
440                 .set = &r100_irq_set,
441                 .process = &r100_irq_process,
442         },
443         .display = {
444                 .bandwidth_update = &r100_bandwidth_update,
445                 .get_vblank_counter = &r100_get_vblank_counter,
446                 .wait_for_vblank = &r100_wait_for_vblank,
447                 .set_backlight_level = &radeon_legacy_set_backlight_level,
448                 .get_backlight_level = &radeon_legacy_get_backlight_level,
449         },
450         .copy = {
451                 .blit = &r100_copy_blit,
452                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
453                 .dma = &r200_copy_dma,
454                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
455                 .copy = &r100_copy_blit,
456                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
457         },
458         .surface = {
459                 .set_reg = r100_set_surface_reg,
460                 .clear_reg = r100_clear_surface_reg,
461         },
462         .hpd = {
463                 .init = &r100_hpd_init,
464                 .fini = &r100_hpd_fini,
465                 .sense = &r100_hpd_sense,
466                 .set_polarity = &r100_hpd_set_polarity,
467         },
468         .pm = {
469                 .misc = &r100_pm_misc,
470                 .prepare = &r100_pm_prepare,
471                 .finish = &r100_pm_finish,
472                 .init_profile = &r100_pm_init_profile,
473                 .get_dynpm_state = &r100_pm_get_dynpm_state,
474                 .get_engine_clock = &radeon_legacy_get_engine_clock,
475                 .set_engine_clock = &radeon_legacy_set_engine_clock,
476                 .get_memory_clock = &radeon_legacy_get_memory_clock,
477                 .set_memory_clock = NULL,
478                 .get_pcie_lanes = &rv370_get_pcie_lanes,
479                 .set_pcie_lanes = &rv370_set_pcie_lanes,
480                 .set_clock_gating = &radeon_legacy_set_clock_gating,
481         },
482         .pflip = {
483                 .page_flip = &r100_page_flip,
484                 .page_flip_pending = &r100_page_flip_pending,
485         },
486 };
487
488 static struct radeon_asic r420_asic = {
489         .init = &r420_init,
490         .fini = &r420_fini,
491         .suspend = &r420_suspend,
492         .resume = &r420_resume,
493         .vga_set_state = &r100_vga_set_state,
494         .asic_reset = &r300_asic_reset,
495         .mmio_hdp_flush = NULL,
496         .gui_idle = &r100_gui_idle,
497         .mc_wait_for_idle = &r300_mc_wait_for_idle,
498         .gart = {
499                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
500                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
501                 .set_page = &rv370_pcie_gart_set_page,
502         },
503         .ring = {
504                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
505         },
506         .irq = {
507                 .set = &r100_irq_set,
508                 .process = &r100_irq_process,
509         },
510         .display = {
511                 .bandwidth_update = &r100_bandwidth_update,
512                 .get_vblank_counter = &r100_get_vblank_counter,
513                 .wait_for_vblank = &r100_wait_for_vblank,
514                 .set_backlight_level = &atombios_set_backlight_level,
515                 .get_backlight_level = &atombios_get_backlight_level,
516         },
517         .copy = {
518                 .blit = &r100_copy_blit,
519                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
520                 .dma = &r200_copy_dma,
521                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
522                 .copy = &r100_copy_blit,
523                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
524         },
525         .surface = {
526                 .set_reg = r100_set_surface_reg,
527                 .clear_reg = r100_clear_surface_reg,
528         },
529         .hpd = {
530                 .init = &r100_hpd_init,
531                 .fini = &r100_hpd_fini,
532                 .sense = &r100_hpd_sense,
533                 .set_polarity = &r100_hpd_set_polarity,
534         },
535         .pm = {
536                 .misc = &r100_pm_misc,
537                 .prepare = &r100_pm_prepare,
538                 .finish = &r100_pm_finish,
539                 .init_profile = &r420_pm_init_profile,
540                 .get_dynpm_state = &r100_pm_get_dynpm_state,
541                 .get_engine_clock = &radeon_atom_get_engine_clock,
542                 .set_engine_clock = &radeon_atom_set_engine_clock,
543                 .get_memory_clock = &radeon_atom_get_memory_clock,
544                 .set_memory_clock = &radeon_atom_set_memory_clock,
545                 .get_pcie_lanes = &rv370_get_pcie_lanes,
546                 .set_pcie_lanes = &rv370_set_pcie_lanes,
547                 .set_clock_gating = &radeon_atom_set_clock_gating,
548         },
549         .pflip = {
550                 .page_flip = &r100_page_flip,
551                 .page_flip_pending = &r100_page_flip_pending,
552         },
553 };
554
555 static struct radeon_asic rs400_asic = {
556         .init = &rs400_init,
557         .fini = &rs400_fini,
558         .suspend = &rs400_suspend,
559         .resume = &rs400_resume,
560         .vga_set_state = &r100_vga_set_state,
561         .asic_reset = &r300_asic_reset,
562         .mmio_hdp_flush = NULL,
563         .gui_idle = &r100_gui_idle,
564         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
565         .gart = {
566                 .tlb_flush = &rs400_gart_tlb_flush,
567                 .get_page_entry = &rs400_gart_get_page_entry,
568                 .set_page = &rs400_gart_set_page,
569         },
570         .ring = {
571                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
572         },
573         .irq = {
574                 .set = &r100_irq_set,
575                 .process = &r100_irq_process,
576         },
577         .display = {
578                 .bandwidth_update = &r100_bandwidth_update,
579                 .get_vblank_counter = &r100_get_vblank_counter,
580                 .wait_for_vblank = &r100_wait_for_vblank,
581                 .set_backlight_level = &radeon_legacy_set_backlight_level,
582                 .get_backlight_level = &radeon_legacy_get_backlight_level,
583         },
584         .copy = {
585                 .blit = &r100_copy_blit,
586                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
587                 .dma = &r200_copy_dma,
588                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
589                 .copy = &r100_copy_blit,
590                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
591         },
592         .surface = {
593                 .set_reg = r100_set_surface_reg,
594                 .clear_reg = r100_clear_surface_reg,
595         },
596         .hpd = {
597                 .init = &r100_hpd_init,
598                 .fini = &r100_hpd_fini,
599                 .sense = &r100_hpd_sense,
600                 .set_polarity = &r100_hpd_set_polarity,
601         },
602         .pm = {
603                 .misc = &r100_pm_misc,
604                 .prepare = &r100_pm_prepare,
605                 .finish = &r100_pm_finish,
606                 .init_profile = &r100_pm_init_profile,
607                 .get_dynpm_state = &r100_pm_get_dynpm_state,
608                 .get_engine_clock = &radeon_legacy_get_engine_clock,
609                 .set_engine_clock = &radeon_legacy_set_engine_clock,
610                 .get_memory_clock = &radeon_legacy_get_memory_clock,
611                 .set_memory_clock = NULL,
612                 .get_pcie_lanes = NULL,
613                 .set_pcie_lanes = NULL,
614                 .set_clock_gating = &radeon_legacy_set_clock_gating,
615         },
616         .pflip = {
617                 .page_flip = &r100_page_flip,
618                 .page_flip_pending = &r100_page_flip_pending,
619         },
620 };
621
622 static struct radeon_asic rs600_asic = {
623         .init = &rs600_init,
624         .fini = &rs600_fini,
625         .suspend = &rs600_suspend,
626         .resume = &rs600_resume,
627         .vga_set_state = &r100_vga_set_state,
628         .asic_reset = &rs600_asic_reset,
629         .mmio_hdp_flush = NULL,
630         .gui_idle = &r100_gui_idle,
631         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
632         .gart = {
633                 .tlb_flush = &rs600_gart_tlb_flush,
634                 .get_page_entry = &rs600_gart_get_page_entry,
635                 .set_page = &rs600_gart_set_page,
636         },
637         .ring = {
638                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
639         },
640         .irq = {
641                 .set = &rs600_irq_set,
642                 .process = &rs600_irq_process,
643         },
644         .display = {
645                 .bandwidth_update = &rs600_bandwidth_update,
646                 .get_vblank_counter = &rs600_get_vblank_counter,
647                 .wait_for_vblank = &avivo_wait_for_vblank,
648                 .set_backlight_level = &atombios_set_backlight_level,
649                 .get_backlight_level = &atombios_get_backlight_level,
650         },
651         .copy = {
652                 .blit = &r100_copy_blit,
653                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
654                 .dma = &r200_copy_dma,
655                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
656                 .copy = &r100_copy_blit,
657                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
658         },
659         .surface = {
660                 .set_reg = r100_set_surface_reg,
661                 .clear_reg = r100_clear_surface_reg,
662         },
663         .hpd = {
664                 .init = &rs600_hpd_init,
665                 .fini = &rs600_hpd_fini,
666                 .sense = &rs600_hpd_sense,
667                 .set_polarity = &rs600_hpd_set_polarity,
668         },
669         .pm = {
670                 .misc = &rs600_pm_misc,
671                 .prepare = &rs600_pm_prepare,
672                 .finish = &rs600_pm_finish,
673                 .init_profile = &r420_pm_init_profile,
674                 .get_dynpm_state = &r100_pm_get_dynpm_state,
675                 .get_engine_clock = &radeon_atom_get_engine_clock,
676                 .set_engine_clock = &radeon_atom_set_engine_clock,
677                 .get_memory_clock = &radeon_atom_get_memory_clock,
678                 .set_memory_clock = &radeon_atom_set_memory_clock,
679                 .get_pcie_lanes = NULL,
680                 .set_pcie_lanes = NULL,
681                 .set_clock_gating = &radeon_atom_set_clock_gating,
682         },
683         .pflip = {
684                 .page_flip = &rs600_page_flip,
685                 .page_flip_pending = &rs600_page_flip_pending,
686         },
687 };
688
689 static struct radeon_asic rs690_asic = {
690         .init = &rs690_init,
691         .fini = &rs690_fini,
692         .suspend = &rs690_suspend,
693         .resume = &rs690_resume,
694         .vga_set_state = &r100_vga_set_state,
695         .asic_reset = &rs600_asic_reset,
696         .mmio_hdp_flush = NULL,
697         .gui_idle = &r100_gui_idle,
698         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
699         .gart = {
700                 .tlb_flush = &rs400_gart_tlb_flush,
701                 .get_page_entry = &rs400_gart_get_page_entry,
702                 .set_page = &rs400_gart_set_page,
703         },
704         .ring = {
705                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
706         },
707         .irq = {
708                 .set = &rs600_irq_set,
709                 .process = &rs600_irq_process,
710         },
711         .display = {
712                 .get_vblank_counter = &rs600_get_vblank_counter,
713                 .bandwidth_update = &rs690_bandwidth_update,
714                 .wait_for_vblank = &avivo_wait_for_vblank,
715                 .set_backlight_level = &atombios_set_backlight_level,
716                 .get_backlight_level = &atombios_get_backlight_level,
717         },
718         .copy = {
719                 .blit = &r100_copy_blit,
720                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
721                 .dma = &r200_copy_dma,
722                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
723                 .copy = &r200_copy_dma,
724                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
725         },
726         .surface = {
727                 .set_reg = r100_set_surface_reg,
728                 .clear_reg = r100_clear_surface_reg,
729         },
730         .hpd = {
731                 .init = &rs600_hpd_init,
732                 .fini = &rs600_hpd_fini,
733                 .sense = &rs600_hpd_sense,
734                 .set_polarity = &rs600_hpd_set_polarity,
735         },
736         .pm = {
737                 .misc = &rs600_pm_misc,
738                 .prepare = &rs600_pm_prepare,
739                 .finish = &rs600_pm_finish,
740                 .init_profile = &r420_pm_init_profile,
741                 .get_dynpm_state = &r100_pm_get_dynpm_state,
742                 .get_engine_clock = &radeon_atom_get_engine_clock,
743                 .set_engine_clock = &radeon_atom_set_engine_clock,
744                 .get_memory_clock = &radeon_atom_get_memory_clock,
745                 .set_memory_clock = &radeon_atom_set_memory_clock,
746                 .get_pcie_lanes = NULL,
747                 .set_pcie_lanes = NULL,
748                 .set_clock_gating = &radeon_atom_set_clock_gating,
749         },
750         .pflip = {
751                 .page_flip = &rs600_page_flip,
752                 .page_flip_pending = &rs600_page_flip_pending,
753         },
754 };
755
756 static struct radeon_asic rv515_asic = {
757         .init = &rv515_init,
758         .fini = &rv515_fini,
759         .suspend = &rv515_suspend,
760         .resume = &rv515_resume,
761         .vga_set_state = &r100_vga_set_state,
762         .asic_reset = &rs600_asic_reset,
763         .mmio_hdp_flush = NULL,
764         .gui_idle = &r100_gui_idle,
765         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
766         .gart = {
767                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
768                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
769                 .set_page = &rv370_pcie_gart_set_page,
770         },
771         .ring = {
772                 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
773         },
774         .irq = {
775                 .set = &rs600_irq_set,
776                 .process = &rs600_irq_process,
777         },
778         .display = {
779                 .get_vblank_counter = &rs600_get_vblank_counter,
780                 .bandwidth_update = &rv515_bandwidth_update,
781                 .wait_for_vblank = &avivo_wait_for_vblank,
782                 .set_backlight_level = &atombios_set_backlight_level,
783                 .get_backlight_level = &atombios_get_backlight_level,
784         },
785         .copy = {
786                 .blit = &r100_copy_blit,
787                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
788                 .dma = &r200_copy_dma,
789                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
790                 .copy = &r100_copy_blit,
791                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
792         },
793         .surface = {
794                 .set_reg = r100_set_surface_reg,
795                 .clear_reg = r100_clear_surface_reg,
796         },
797         .hpd = {
798                 .init = &rs600_hpd_init,
799                 .fini = &rs600_hpd_fini,
800                 .sense = &rs600_hpd_sense,
801                 .set_polarity = &rs600_hpd_set_polarity,
802         },
803         .pm = {
804                 .misc = &rs600_pm_misc,
805                 .prepare = &rs600_pm_prepare,
806                 .finish = &rs600_pm_finish,
807                 .init_profile = &r420_pm_init_profile,
808                 .get_dynpm_state = &r100_pm_get_dynpm_state,
809                 .get_engine_clock = &radeon_atom_get_engine_clock,
810                 .set_engine_clock = &radeon_atom_set_engine_clock,
811                 .get_memory_clock = &radeon_atom_get_memory_clock,
812                 .set_memory_clock = &radeon_atom_set_memory_clock,
813                 .get_pcie_lanes = &rv370_get_pcie_lanes,
814                 .set_pcie_lanes = &rv370_set_pcie_lanes,
815                 .set_clock_gating = &radeon_atom_set_clock_gating,
816         },
817         .pflip = {
818                 .page_flip = &rs600_page_flip,
819                 .page_flip_pending = &rs600_page_flip_pending,
820         },
821 };
822
823 static struct radeon_asic r520_asic = {
824         .init = &r520_init,
825         .fini = &rv515_fini,
826         .suspend = &rv515_suspend,
827         .resume = &r520_resume,
828         .vga_set_state = &r100_vga_set_state,
829         .asic_reset = &rs600_asic_reset,
830         .mmio_hdp_flush = NULL,
831         .gui_idle = &r100_gui_idle,
832         .mc_wait_for_idle = &r520_mc_wait_for_idle,
833         .gart = {
834                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
835                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
836                 .set_page = &rv370_pcie_gart_set_page,
837         },
838         .ring = {
839                 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
840         },
841         .irq = {
842                 .set = &rs600_irq_set,
843                 .process = &rs600_irq_process,
844         },
845         .display = {
846                 .bandwidth_update = &rv515_bandwidth_update,
847                 .get_vblank_counter = &rs600_get_vblank_counter,
848                 .wait_for_vblank = &avivo_wait_for_vblank,
849                 .set_backlight_level = &atombios_set_backlight_level,
850                 .get_backlight_level = &atombios_get_backlight_level,
851         },
852         .copy = {
853                 .blit = &r100_copy_blit,
854                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
855                 .dma = &r200_copy_dma,
856                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
857                 .copy = &r100_copy_blit,
858                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
859         },
860         .surface = {
861                 .set_reg = r100_set_surface_reg,
862                 .clear_reg = r100_clear_surface_reg,
863         },
864         .hpd = {
865                 .init = &rs600_hpd_init,
866                 .fini = &rs600_hpd_fini,
867                 .sense = &rs600_hpd_sense,
868                 .set_polarity = &rs600_hpd_set_polarity,
869         },
870         .pm = {
871                 .misc = &rs600_pm_misc,
872                 .prepare = &rs600_pm_prepare,
873                 .finish = &rs600_pm_finish,
874                 .init_profile = &r420_pm_init_profile,
875                 .get_dynpm_state = &r100_pm_get_dynpm_state,
876                 .get_engine_clock = &radeon_atom_get_engine_clock,
877                 .set_engine_clock = &radeon_atom_set_engine_clock,
878                 .get_memory_clock = &radeon_atom_get_memory_clock,
879                 .set_memory_clock = &radeon_atom_set_memory_clock,
880                 .get_pcie_lanes = &rv370_get_pcie_lanes,
881                 .set_pcie_lanes = &rv370_set_pcie_lanes,
882                 .set_clock_gating = &radeon_atom_set_clock_gating,
883         },
884         .pflip = {
885                 .page_flip = &rs600_page_flip,
886                 .page_flip_pending = &rs600_page_flip_pending,
887         },
888 };
889
890 static struct radeon_asic_ring r600_gfx_ring = {
891         .ib_execute = &r600_ring_ib_execute,
892         .emit_fence = &r600_fence_ring_emit,
893         .emit_semaphore = &r600_semaphore_ring_emit,
894         .cs_parse = &r600_cs_parse,
895         .ring_test = &r600_ring_test,
896         .ib_test = &r600_ib_test,
897         .is_lockup = &r600_gfx_is_lockup,
898         .get_rptr = &r600_gfx_get_rptr,
899         .get_wptr = &r600_gfx_get_wptr,
900         .set_wptr = &r600_gfx_set_wptr,
901 };
902
903 static struct radeon_asic_ring r600_dma_ring = {
904         .ib_execute = &r600_dma_ring_ib_execute,
905         .emit_fence = &r600_dma_fence_ring_emit,
906         .emit_semaphore = &r600_dma_semaphore_ring_emit,
907         .cs_parse = &r600_dma_cs_parse,
908         .ring_test = &r600_dma_ring_test,
909         .ib_test = &r600_dma_ib_test,
910         .is_lockup = &r600_dma_is_lockup,
911         .get_rptr = &r600_dma_get_rptr,
912         .get_wptr = &r600_dma_get_wptr,
913         .set_wptr = &r600_dma_set_wptr,
914 };
915
916 static struct radeon_asic r600_asic = {
917         .init = &r600_init,
918         .fini = &r600_fini,
919         .suspend = &r600_suspend,
920         .resume = &r600_resume,
921         .vga_set_state = &r600_vga_set_state,
922         .asic_reset = &r600_asic_reset,
923         .mmio_hdp_flush = r600_mmio_hdp_flush,
924         .gui_idle = &r600_gui_idle,
925         .mc_wait_for_idle = &r600_mc_wait_for_idle,
926         .get_xclk = &r600_get_xclk,
927         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
928         .gart = {
929                 .tlb_flush = &r600_pcie_gart_tlb_flush,
930                 .get_page_entry = &rs600_gart_get_page_entry,
931                 .set_page = &rs600_gart_set_page,
932         },
933         .ring = {
934                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
935                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
936         },
937         .irq = {
938                 .set = &r600_irq_set,
939                 .process = &r600_irq_process,
940         },
941         .display = {
942                 .bandwidth_update = &rv515_bandwidth_update,
943                 .get_vblank_counter = &rs600_get_vblank_counter,
944                 .wait_for_vblank = &avivo_wait_for_vblank,
945                 .set_backlight_level = &atombios_set_backlight_level,
946                 .get_backlight_level = &atombios_get_backlight_level,
947         },
948         .copy = {
949                 .blit = &r600_copy_cpdma,
950                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
951                 .dma = &r600_copy_dma,
952                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
953                 .copy = &r600_copy_cpdma,
954                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
955         },
956         .surface = {
957                 .set_reg = r600_set_surface_reg,
958                 .clear_reg = r600_clear_surface_reg,
959         },
960         .hpd = {
961                 .init = &r600_hpd_init,
962                 .fini = &r600_hpd_fini,
963                 .sense = &r600_hpd_sense,
964                 .set_polarity = &r600_hpd_set_polarity,
965         },
966         .pm = {
967                 .misc = &r600_pm_misc,
968                 .prepare = &rs600_pm_prepare,
969                 .finish = &rs600_pm_finish,
970                 .init_profile = &r600_pm_init_profile,
971                 .get_dynpm_state = &r600_pm_get_dynpm_state,
972                 .get_engine_clock = &radeon_atom_get_engine_clock,
973                 .set_engine_clock = &radeon_atom_set_engine_clock,
974                 .get_memory_clock = &radeon_atom_get_memory_clock,
975                 .set_memory_clock = &radeon_atom_set_memory_clock,
976                 .get_pcie_lanes = &r600_get_pcie_lanes,
977                 .set_pcie_lanes = &r600_set_pcie_lanes,
978                 .set_clock_gating = NULL,
979                 .get_temperature = &rv6xx_get_temp,
980         },
981         .pflip = {
982                 .page_flip = &rs600_page_flip,
983                 .page_flip_pending = &rs600_page_flip_pending,
984         },
985 };
986
987 static struct radeon_asic_ring rv6xx_uvd_ring = {
988         .ib_execute = &uvd_v1_0_ib_execute,
989         .emit_fence = &uvd_v1_0_fence_emit,
990         .emit_semaphore = &uvd_v1_0_semaphore_emit,
991         .cs_parse = &radeon_uvd_cs_parse,
992         .ring_test = &uvd_v1_0_ring_test,
993         .ib_test = &uvd_v1_0_ib_test,
994         .is_lockup = &radeon_ring_test_lockup,
995         .get_rptr = &uvd_v1_0_get_rptr,
996         .get_wptr = &uvd_v1_0_get_wptr,
997         .set_wptr = &uvd_v1_0_set_wptr,
998 };
999
1000 static struct radeon_asic rv6xx_asic = {
1001         .init = &r600_init,
1002         .fini = &r600_fini,
1003         .suspend = &r600_suspend,
1004         .resume = &r600_resume,
1005         .vga_set_state = &r600_vga_set_state,
1006         .asic_reset = &r600_asic_reset,
1007         .mmio_hdp_flush = r600_mmio_hdp_flush,
1008         .gui_idle = &r600_gui_idle,
1009         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1010         .get_xclk = &r600_get_xclk,
1011         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1012         .gart = {
1013                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1014                 .get_page_entry = &rs600_gart_get_page_entry,
1015                 .set_page = &rs600_gart_set_page,
1016         },
1017         .ring = {
1018                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1019                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1020                 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1021         },
1022         .irq = {
1023                 .set = &r600_irq_set,
1024                 .process = &r600_irq_process,
1025         },
1026         .display = {
1027                 .bandwidth_update = &rv515_bandwidth_update,
1028                 .get_vblank_counter = &rs600_get_vblank_counter,
1029                 .wait_for_vblank = &avivo_wait_for_vblank,
1030                 .set_backlight_level = &atombios_set_backlight_level,
1031                 .get_backlight_level = &atombios_get_backlight_level,
1032         },
1033         .copy = {
1034                 .blit = &r600_copy_cpdma,
1035                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1036                 .dma = &r600_copy_dma,
1037                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1038                 .copy = &r600_copy_cpdma,
1039                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1040         },
1041         .surface = {
1042                 .set_reg = r600_set_surface_reg,
1043                 .clear_reg = r600_clear_surface_reg,
1044         },
1045         .hpd = {
1046                 .init = &r600_hpd_init,
1047                 .fini = &r600_hpd_fini,
1048                 .sense = &r600_hpd_sense,
1049                 .set_polarity = &r600_hpd_set_polarity,
1050         },
1051         .pm = {
1052                 .misc = &r600_pm_misc,
1053                 .prepare = &rs600_pm_prepare,
1054                 .finish = &rs600_pm_finish,
1055                 .init_profile = &r600_pm_init_profile,
1056                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1057                 .get_engine_clock = &radeon_atom_get_engine_clock,
1058                 .set_engine_clock = &radeon_atom_set_engine_clock,
1059                 .get_memory_clock = &radeon_atom_get_memory_clock,
1060                 .set_memory_clock = &radeon_atom_set_memory_clock,
1061                 .get_pcie_lanes = &r600_get_pcie_lanes,
1062                 .set_pcie_lanes = &r600_set_pcie_lanes,
1063                 .set_clock_gating = NULL,
1064                 .get_temperature = &rv6xx_get_temp,
1065                 .set_uvd_clocks = &r600_set_uvd_clocks,
1066         },
1067         .dpm = {
1068                 .init = &rv6xx_dpm_init,
1069                 .setup_asic = &rv6xx_setup_asic,
1070                 .enable = &rv6xx_dpm_enable,
1071                 .late_enable = &r600_dpm_late_enable,
1072                 .disable = &rv6xx_dpm_disable,
1073                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1074                 .set_power_state = &rv6xx_dpm_set_power_state,
1075                 .post_set_power_state = &r600_dpm_post_set_power_state,
1076                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1077                 .fini = &rv6xx_dpm_fini,
1078                 .get_sclk = &rv6xx_dpm_get_sclk,
1079                 .get_mclk = &rv6xx_dpm_get_mclk,
1080                 .print_power_state = &rv6xx_dpm_print_power_state,
1081                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1082                 .force_performance_level = &rv6xx_dpm_force_performance_level,
1083                 .get_current_sclk = &rv6xx_dpm_get_current_sclk,
1084                 .get_current_mclk = &rv6xx_dpm_get_current_mclk,
1085         },
1086         .pflip = {
1087                 .page_flip = &rs600_page_flip,
1088                 .page_flip_pending = &rs600_page_flip_pending,
1089         },
1090 };
1091
1092 static struct radeon_asic rs780_asic = {
1093         .init = &r600_init,
1094         .fini = &r600_fini,
1095         .suspend = &r600_suspend,
1096         .resume = &r600_resume,
1097         .vga_set_state = &r600_vga_set_state,
1098         .asic_reset = &r600_asic_reset,
1099         .mmio_hdp_flush = r600_mmio_hdp_flush,
1100         .gui_idle = &r600_gui_idle,
1101         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1102         .get_xclk = &r600_get_xclk,
1103         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1104         .gart = {
1105                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1106                 .get_page_entry = &rs600_gart_get_page_entry,
1107                 .set_page = &rs600_gart_set_page,
1108         },
1109         .ring = {
1110                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1111                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1112                 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1113         },
1114         .irq = {
1115                 .set = &r600_irq_set,
1116                 .process = &r600_irq_process,
1117         },
1118         .display = {
1119                 .bandwidth_update = &rs690_bandwidth_update,
1120                 .get_vblank_counter = &rs600_get_vblank_counter,
1121                 .wait_for_vblank = &avivo_wait_for_vblank,
1122                 .set_backlight_level = &atombios_set_backlight_level,
1123                 .get_backlight_level = &atombios_get_backlight_level,
1124         },
1125         .copy = {
1126                 .blit = &r600_copy_cpdma,
1127                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1128                 .dma = &r600_copy_dma,
1129                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1130                 .copy = &r600_copy_cpdma,
1131                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1132         },
1133         .surface = {
1134                 .set_reg = r600_set_surface_reg,
1135                 .clear_reg = r600_clear_surface_reg,
1136         },
1137         .hpd = {
1138                 .init = &r600_hpd_init,
1139                 .fini = &r600_hpd_fini,
1140                 .sense = &r600_hpd_sense,
1141                 .set_polarity = &r600_hpd_set_polarity,
1142         },
1143         .pm = {
1144                 .misc = &r600_pm_misc,
1145                 .prepare = &rs600_pm_prepare,
1146                 .finish = &rs600_pm_finish,
1147                 .init_profile = &rs780_pm_init_profile,
1148                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1149                 .get_engine_clock = &radeon_atom_get_engine_clock,
1150                 .set_engine_clock = &radeon_atom_set_engine_clock,
1151                 .get_memory_clock = NULL,
1152                 .set_memory_clock = NULL,
1153                 .get_pcie_lanes = NULL,
1154                 .set_pcie_lanes = NULL,
1155                 .set_clock_gating = NULL,
1156                 .get_temperature = &rv6xx_get_temp,
1157                 .set_uvd_clocks = &r600_set_uvd_clocks,
1158         },
1159         .dpm = {
1160                 .init = &rs780_dpm_init,
1161                 .setup_asic = &rs780_dpm_setup_asic,
1162                 .enable = &rs780_dpm_enable,
1163                 .late_enable = &r600_dpm_late_enable,
1164                 .disable = &rs780_dpm_disable,
1165                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1166                 .set_power_state = &rs780_dpm_set_power_state,
1167                 .post_set_power_state = &r600_dpm_post_set_power_state,
1168                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1169                 .fini = &rs780_dpm_fini,
1170                 .get_sclk = &rs780_dpm_get_sclk,
1171                 .get_mclk = &rs780_dpm_get_mclk,
1172                 .print_power_state = &rs780_dpm_print_power_state,
1173                 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1174                 .force_performance_level = &rs780_dpm_force_performance_level,
1175                 .get_current_sclk = &rs780_dpm_get_current_sclk,
1176                 .get_current_mclk = &rs780_dpm_get_current_mclk,
1177         },
1178         .pflip = {
1179                 .page_flip = &rs600_page_flip,
1180                 .page_flip_pending = &rs600_page_flip_pending,
1181         },
1182 };
1183
1184 static struct radeon_asic_ring rv770_uvd_ring = {
1185         .ib_execute = &uvd_v1_0_ib_execute,
1186         .emit_fence = &uvd_v2_2_fence_emit,
1187         .emit_semaphore = &uvd_v1_0_semaphore_emit,
1188         .cs_parse = &radeon_uvd_cs_parse,
1189         .ring_test = &uvd_v1_0_ring_test,
1190         .ib_test = &uvd_v1_0_ib_test,
1191         .is_lockup = &radeon_ring_test_lockup,
1192         .get_rptr = &uvd_v1_0_get_rptr,
1193         .get_wptr = &uvd_v1_0_get_wptr,
1194         .set_wptr = &uvd_v1_0_set_wptr,
1195 };
1196
1197 static struct radeon_asic rv770_asic = {
1198         .init = &rv770_init,
1199         .fini = &rv770_fini,
1200         .suspend = &rv770_suspend,
1201         .resume = &rv770_resume,
1202         .asic_reset = &r600_asic_reset,
1203         .vga_set_state = &r600_vga_set_state,
1204         .mmio_hdp_flush = r600_mmio_hdp_flush,
1205         .gui_idle = &r600_gui_idle,
1206         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1207         .get_xclk = &rv770_get_xclk,
1208         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1209         .gart = {
1210                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1211                 .get_page_entry = &rs600_gart_get_page_entry,
1212                 .set_page = &rs600_gart_set_page,
1213         },
1214         .ring = {
1215                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1216                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1217                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1218         },
1219         .irq = {
1220                 .set = &r600_irq_set,
1221                 .process = &r600_irq_process,
1222         },
1223         .display = {
1224                 .bandwidth_update = &rv515_bandwidth_update,
1225                 .get_vblank_counter = &rs600_get_vblank_counter,
1226                 .wait_for_vblank = &avivo_wait_for_vblank,
1227                 .set_backlight_level = &atombios_set_backlight_level,
1228                 .get_backlight_level = &atombios_get_backlight_level,
1229         },
1230         .copy = {
1231                 .blit = &r600_copy_cpdma,
1232                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1233                 .dma = &rv770_copy_dma,
1234                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1235                 .copy = &rv770_copy_dma,
1236                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1237         },
1238         .surface = {
1239                 .set_reg = r600_set_surface_reg,
1240                 .clear_reg = r600_clear_surface_reg,
1241         },
1242         .hpd = {
1243                 .init = &r600_hpd_init,
1244                 .fini = &r600_hpd_fini,
1245                 .sense = &r600_hpd_sense,
1246                 .set_polarity = &r600_hpd_set_polarity,
1247         },
1248         .pm = {
1249                 .misc = &rv770_pm_misc,
1250                 .prepare = &rs600_pm_prepare,
1251                 .finish = &rs600_pm_finish,
1252                 .init_profile = &r600_pm_init_profile,
1253                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1254                 .get_engine_clock = &radeon_atom_get_engine_clock,
1255                 .set_engine_clock = &radeon_atom_set_engine_clock,
1256                 .get_memory_clock = &radeon_atom_get_memory_clock,
1257                 .set_memory_clock = &radeon_atom_set_memory_clock,
1258                 .get_pcie_lanes = &r600_get_pcie_lanes,
1259                 .set_pcie_lanes = &r600_set_pcie_lanes,
1260                 .set_clock_gating = &radeon_atom_set_clock_gating,
1261                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1262                 .get_temperature = &rv770_get_temp,
1263         },
1264         .dpm = {
1265                 .init = &rv770_dpm_init,
1266                 .setup_asic = &rv770_dpm_setup_asic,
1267                 .enable = &rv770_dpm_enable,
1268                 .late_enable = &rv770_dpm_late_enable,
1269                 .disable = &rv770_dpm_disable,
1270                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1271                 .set_power_state = &rv770_dpm_set_power_state,
1272                 .post_set_power_state = &r600_dpm_post_set_power_state,
1273                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1274                 .fini = &rv770_dpm_fini,
1275                 .get_sclk = &rv770_dpm_get_sclk,
1276                 .get_mclk = &rv770_dpm_get_mclk,
1277                 .print_power_state = &rv770_dpm_print_power_state,
1278                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1279                 .force_performance_level = &rv770_dpm_force_performance_level,
1280                 .vblank_too_short = &rv770_dpm_vblank_too_short,
1281                 .get_current_sclk = &rv770_dpm_get_current_sclk,
1282                 .get_current_mclk = &rv770_dpm_get_current_mclk,
1283         },
1284         .pflip = {
1285                 .page_flip = &rv770_page_flip,
1286                 .page_flip_pending = &rv770_page_flip_pending,
1287         },
1288 };
1289
1290 static struct radeon_asic_ring evergreen_gfx_ring = {
1291         .ib_execute = &evergreen_ring_ib_execute,
1292         .emit_fence = &r600_fence_ring_emit,
1293         .emit_semaphore = &r600_semaphore_ring_emit,
1294         .cs_parse = &evergreen_cs_parse,
1295         .ring_test = &r600_ring_test,
1296         .ib_test = &r600_ib_test,
1297         .is_lockup = &evergreen_gfx_is_lockup,
1298         .get_rptr = &r600_gfx_get_rptr,
1299         .get_wptr = &r600_gfx_get_wptr,
1300         .set_wptr = &r600_gfx_set_wptr,
1301 };
1302
1303 static struct radeon_asic_ring evergreen_dma_ring = {
1304         .ib_execute = &evergreen_dma_ring_ib_execute,
1305         .emit_fence = &evergreen_dma_fence_ring_emit,
1306         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1307         .cs_parse = &evergreen_dma_cs_parse,
1308         .ring_test = &r600_dma_ring_test,
1309         .ib_test = &r600_dma_ib_test,
1310         .is_lockup = &evergreen_dma_is_lockup,
1311         .get_rptr = &r600_dma_get_rptr,
1312         .get_wptr = &r600_dma_get_wptr,
1313         .set_wptr = &r600_dma_set_wptr,
1314 };
1315
1316 static struct radeon_asic evergreen_asic = {
1317         .init = &evergreen_init,
1318         .fini = &evergreen_fini,
1319         .suspend = &evergreen_suspend,
1320         .resume = &evergreen_resume,
1321         .asic_reset = &evergreen_asic_reset,
1322         .vga_set_state = &r600_vga_set_state,
1323         .mmio_hdp_flush = r600_mmio_hdp_flush,
1324         .gui_idle = &r600_gui_idle,
1325         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1326         .get_xclk = &rv770_get_xclk,
1327         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1328         .gart = {
1329                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1330                 .get_page_entry = &rs600_gart_get_page_entry,
1331                 .set_page = &rs600_gart_set_page,
1332         },
1333         .ring = {
1334                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1335                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1336                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1337         },
1338         .irq = {
1339                 .set = &evergreen_irq_set,
1340                 .process = &evergreen_irq_process,
1341         },
1342         .display = {
1343                 .bandwidth_update = &evergreen_bandwidth_update,
1344                 .get_vblank_counter = &evergreen_get_vblank_counter,
1345                 .wait_for_vblank = &dce4_wait_for_vblank,
1346                 .set_backlight_level = &atombios_set_backlight_level,
1347                 .get_backlight_level = &atombios_get_backlight_level,
1348         },
1349         .copy = {
1350                 .blit = &r600_copy_cpdma,
1351                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1352                 .dma = &evergreen_copy_dma,
1353                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1354                 .copy = &evergreen_copy_dma,
1355                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1356         },
1357         .surface = {
1358                 .set_reg = r600_set_surface_reg,
1359                 .clear_reg = r600_clear_surface_reg,
1360         },
1361         .hpd = {
1362                 .init = &evergreen_hpd_init,
1363                 .fini = &evergreen_hpd_fini,
1364                 .sense = &evergreen_hpd_sense,
1365                 .set_polarity = &evergreen_hpd_set_polarity,
1366         },
1367         .pm = {
1368                 .misc = &evergreen_pm_misc,
1369                 .prepare = &evergreen_pm_prepare,
1370                 .finish = &evergreen_pm_finish,
1371                 .init_profile = &r600_pm_init_profile,
1372                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1373                 .get_engine_clock = &radeon_atom_get_engine_clock,
1374                 .set_engine_clock = &radeon_atom_set_engine_clock,
1375                 .get_memory_clock = &radeon_atom_get_memory_clock,
1376                 .set_memory_clock = &radeon_atom_set_memory_clock,
1377                 .get_pcie_lanes = &r600_get_pcie_lanes,
1378                 .set_pcie_lanes = &r600_set_pcie_lanes,
1379                 .set_clock_gating = NULL,
1380                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1381                 .get_temperature = &evergreen_get_temp,
1382         },
1383         .dpm = {
1384                 .init = &cypress_dpm_init,
1385                 .setup_asic = &cypress_dpm_setup_asic,
1386                 .enable = &cypress_dpm_enable,
1387                 .late_enable = &rv770_dpm_late_enable,
1388                 .disable = &cypress_dpm_disable,
1389                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1390                 .set_power_state = &cypress_dpm_set_power_state,
1391                 .post_set_power_state = &r600_dpm_post_set_power_state,
1392                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1393                 .fini = &cypress_dpm_fini,
1394                 .get_sclk = &rv770_dpm_get_sclk,
1395                 .get_mclk = &rv770_dpm_get_mclk,
1396                 .print_power_state = &rv770_dpm_print_power_state,
1397                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1398                 .force_performance_level = &rv770_dpm_force_performance_level,
1399                 .vblank_too_short = &cypress_dpm_vblank_too_short,
1400                 .get_current_sclk = &rv770_dpm_get_current_sclk,
1401                 .get_current_mclk = &rv770_dpm_get_current_mclk,
1402         },
1403         .pflip = {
1404                 .page_flip = &evergreen_page_flip,
1405                 .page_flip_pending = &evergreen_page_flip_pending,
1406         },
1407 };
1408
1409 static struct radeon_asic sumo_asic = {
1410         .init = &evergreen_init,
1411         .fini = &evergreen_fini,
1412         .suspend = &evergreen_suspend,
1413         .resume = &evergreen_resume,
1414         .asic_reset = &evergreen_asic_reset,
1415         .vga_set_state = &r600_vga_set_state,
1416         .mmio_hdp_flush = r600_mmio_hdp_flush,
1417         .gui_idle = &r600_gui_idle,
1418         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1419         .get_xclk = &r600_get_xclk,
1420         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1421         .gart = {
1422                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1423                 .get_page_entry = &rs600_gart_get_page_entry,
1424                 .set_page = &rs600_gart_set_page,
1425         },
1426         .ring = {
1427                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1428                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1429                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1430         },
1431         .irq = {
1432                 .set = &evergreen_irq_set,
1433                 .process = &evergreen_irq_process,
1434         },
1435         .display = {
1436                 .bandwidth_update = &evergreen_bandwidth_update,
1437                 .get_vblank_counter = &evergreen_get_vblank_counter,
1438                 .wait_for_vblank = &dce4_wait_for_vblank,
1439                 .set_backlight_level = &atombios_set_backlight_level,
1440                 .get_backlight_level = &atombios_get_backlight_level,
1441         },
1442         .copy = {
1443                 .blit = &r600_copy_cpdma,
1444                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1445                 .dma = &evergreen_copy_dma,
1446                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1447                 .copy = &evergreen_copy_dma,
1448                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1449         },
1450         .surface = {
1451                 .set_reg = r600_set_surface_reg,
1452                 .clear_reg = r600_clear_surface_reg,
1453         },
1454         .hpd = {
1455                 .init = &evergreen_hpd_init,
1456                 .fini = &evergreen_hpd_fini,
1457                 .sense = &evergreen_hpd_sense,
1458                 .set_polarity = &evergreen_hpd_set_polarity,
1459         },
1460         .pm = {
1461                 .misc = &evergreen_pm_misc,
1462                 .prepare = &evergreen_pm_prepare,
1463                 .finish = &evergreen_pm_finish,
1464                 .init_profile = &sumo_pm_init_profile,
1465                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1466                 .get_engine_clock = &radeon_atom_get_engine_clock,
1467                 .set_engine_clock = &radeon_atom_set_engine_clock,
1468                 .get_memory_clock = NULL,
1469                 .set_memory_clock = NULL,
1470                 .get_pcie_lanes = NULL,
1471                 .set_pcie_lanes = NULL,
1472                 .set_clock_gating = NULL,
1473                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1474                 .get_temperature = &sumo_get_temp,
1475         },
1476         .dpm = {
1477                 .init = &sumo_dpm_init,
1478                 .setup_asic = &sumo_dpm_setup_asic,
1479                 .enable = &sumo_dpm_enable,
1480                 .late_enable = &sumo_dpm_late_enable,
1481                 .disable = &sumo_dpm_disable,
1482                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1483                 .set_power_state = &sumo_dpm_set_power_state,
1484                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1485                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1486                 .fini = &sumo_dpm_fini,
1487                 .get_sclk = &sumo_dpm_get_sclk,
1488                 .get_mclk = &sumo_dpm_get_mclk,
1489                 .print_power_state = &sumo_dpm_print_power_state,
1490                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1491                 .force_performance_level = &sumo_dpm_force_performance_level,
1492         },
1493         .pflip = {
1494                 .page_flip = &evergreen_page_flip,
1495                 .page_flip_pending = &evergreen_page_flip_pending,
1496         },
1497 };
1498
1499 static struct radeon_asic btc_asic = {
1500         .init = &evergreen_init,
1501         .fini = &evergreen_fini,
1502         .suspend = &evergreen_suspend,
1503         .resume = &evergreen_resume,
1504         .asic_reset = &evergreen_asic_reset,
1505         .vga_set_state = &r600_vga_set_state,
1506         .mmio_hdp_flush = r600_mmio_hdp_flush,
1507         .gui_idle = &r600_gui_idle,
1508         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1509         .get_xclk = &rv770_get_xclk,
1510         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1511         .gart = {
1512                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1513                 .get_page_entry = &rs600_gart_get_page_entry,
1514                 .set_page = &rs600_gart_set_page,
1515         },
1516         .ring = {
1517                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1518                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1519                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1520         },
1521         .irq = {
1522                 .set = &evergreen_irq_set,
1523                 .process = &evergreen_irq_process,
1524         },
1525         .display = {
1526                 .bandwidth_update = &evergreen_bandwidth_update,
1527                 .get_vblank_counter = &evergreen_get_vblank_counter,
1528                 .wait_for_vblank = &dce4_wait_for_vblank,
1529                 .set_backlight_level = &atombios_set_backlight_level,
1530                 .get_backlight_level = &atombios_get_backlight_level,
1531         },
1532         .copy = {
1533                 .blit = &r600_copy_cpdma,
1534                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1535                 .dma = &evergreen_copy_dma,
1536                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1537                 .copy = &evergreen_copy_dma,
1538                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1539         },
1540         .surface = {
1541                 .set_reg = r600_set_surface_reg,
1542                 .clear_reg = r600_clear_surface_reg,
1543         },
1544         .hpd = {
1545                 .init = &evergreen_hpd_init,
1546                 .fini = &evergreen_hpd_fini,
1547                 .sense = &evergreen_hpd_sense,
1548                 .set_polarity = &evergreen_hpd_set_polarity,
1549         },
1550         .pm = {
1551                 .misc = &evergreen_pm_misc,
1552                 .prepare = &evergreen_pm_prepare,
1553                 .finish = &evergreen_pm_finish,
1554                 .init_profile = &btc_pm_init_profile,
1555                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1556                 .get_engine_clock = &radeon_atom_get_engine_clock,
1557                 .set_engine_clock = &radeon_atom_set_engine_clock,
1558                 .get_memory_clock = &radeon_atom_get_memory_clock,
1559                 .set_memory_clock = &radeon_atom_set_memory_clock,
1560                 .get_pcie_lanes = &r600_get_pcie_lanes,
1561                 .set_pcie_lanes = &r600_set_pcie_lanes,
1562                 .set_clock_gating = NULL,
1563                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1564                 .get_temperature = &evergreen_get_temp,
1565         },
1566         .dpm = {
1567                 .init = &btc_dpm_init,
1568                 .setup_asic = &btc_dpm_setup_asic,
1569                 .enable = &btc_dpm_enable,
1570                 .late_enable = &rv770_dpm_late_enable,
1571                 .disable = &btc_dpm_disable,
1572                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1573                 .set_power_state = &btc_dpm_set_power_state,
1574                 .post_set_power_state = &btc_dpm_post_set_power_state,
1575                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1576                 .fini = &btc_dpm_fini,
1577                 .get_sclk = &btc_dpm_get_sclk,
1578                 .get_mclk = &btc_dpm_get_mclk,
1579                 .print_power_state = &rv770_dpm_print_power_state,
1580                 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1581                 .force_performance_level = &rv770_dpm_force_performance_level,
1582                 .vblank_too_short = &btc_dpm_vblank_too_short,
1583                 .get_current_sclk = &btc_dpm_get_current_sclk,
1584                 .get_current_mclk = &btc_dpm_get_current_mclk,
1585         },
1586         .pflip = {
1587                 .page_flip = &evergreen_page_flip,
1588                 .page_flip_pending = &evergreen_page_flip_pending,
1589         },
1590 };
1591
1592 static struct radeon_asic_ring cayman_gfx_ring = {
1593         .ib_execute = &cayman_ring_ib_execute,
1594         .ib_parse = &evergreen_ib_parse,
1595         .emit_fence = &cayman_fence_ring_emit,
1596         .emit_semaphore = &r600_semaphore_ring_emit,
1597         .cs_parse = &evergreen_cs_parse,
1598         .ring_test = &r600_ring_test,
1599         .ib_test = &r600_ib_test,
1600         .is_lockup = &cayman_gfx_is_lockup,
1601         .vm_flush = &cayman_vm_flush,
1602         .get_rptr = &cayman_gfx_get_rptr,
1603         .get_wptr = &cayman_gfx_get_wptr,
1604         .set_wptr = &cayman_gfx_set_wptr,
1605 };
1606
1607 static struct radeon_asic_ring cayman_dma_ring = {
1608         .ib_execute = &cayman_dma_ring_ib_execute,
1609         .ib_parse = &evergreen_dma_ib_parse,
1610         .emit_fence = &evergreen_dma_fence_ring_emit,
1611         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1612         .cs_parse = &evergreen_dma_cs_parse,
1613         .ring_test = &r600_dma_ring_test,
1614         .ib_test = &r600_dma_ib_test,
1615         .is_lockup = &cayman_dma_is_lockup,
1616         .vm_flush = &cayman_dma_vm_flush,
1617         .get_rptr = &cayman_dma_get_rptr,
1618         .get_wptr = &cayman_dma_get_wptr,
1619         .set_wptr = &cayman_dma_set_wptr
1620 };
1621
1622 static struct radeon_asic_ring cayman_uvd_ring = {
1623         .ib_execute = &uvd_v1_0_ib_execute,
1624         .emit_fence = &uvd_v2_2_fence_emit,
1625         .emit_semaphore = &uvd_v3_1_semaphore_emit,
1626         .cs_parse = &radeon_uvd_cs_parse,
1627         .ring_test = &uvd_v1_0_ring_test,
1628         .ib_test = &uvd_v1_0_ib_test,
1629         .is_lockup = &radeon_ring_test_lockup,
1630         .get_rptr = &uvd_v1_0_get_rptr,
1631         .get_wptr = &uvd_v1_0_get_wptr,
1632         .set_wptr = &uvd_v1_0_set_wptr,
1633 };
1634
1635 static struct radeon_asic cayman_asic = {
1636         .init = &cayman_init,
1637         .fini = &cayman_fini,
1638         .suspend = &cayman_suspend,
1639         .resume = &cayman_resume,
1640         .asic_reset = &cayman_asic_reset,
1641         .vga_set_state = &r600_vga_set_state,
1642         .mmio_hdp_flush = r600_mmio_hdp_flush,
1643         .gui_idle = &r600_gui_idle,
1644         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1645         .get_xclk = &rv770_get_xclk,
1646         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1647         .gart = {
1648                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1649                 .get_page_entry = &rs600_gart_get_page_entry,
1650                 .set_page = &rs600_gart_set_page,
1651         },
1652         .vm = {
1653                 .init = &cayman_vm_init,
1654                 .fini = &cayman_vm_fini,
1655                 .copy_pages = &cayman_dma_vm_copy_pages,
1656                 .write_pages = &cayman_dma_vm_write_pages,
1657                 .set_pages = &cayman_dma_vm_set_pages,
1658                 .pad_ib = &cayman_dma_vm_pad_ib,
1659         },
1660         .ring = {
1661                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1662                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1663                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1664                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1665                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1666                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1667         },
1668         .irq = {
1669                 .set = &evergreen_irq_set,
1670                 .process = &evergreen_irq_process,
1671         },
1672         .display = {
1673                 .bandwidth_update = &evergreen_bandwidth_update,
1674                 .get_vblank_counter = &evergreen_get_vblank_counter,
1675                 .wait_for_vblank = &dce4_wait_for_vblank,
1676                 .set_backlight_level = &atombios_set_backlight_level,
1677                 .get_backlight_level = &atombios_get_backlight_level,
1678         },
1679         .copy = {
1680                 .blit = &r600_copy_cpdma,
1681                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1682                 .dma = &evergreen_copy_dma,
1683                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1684                 .copy = &evergreen_copy_dma,
1685                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1686         },
1687         .surface = {
1688                 .set_reg = r600_set_surface_reg,
1689                 .clear_reg = r600_clear_surface_reg,
1690         },
1691         .hpd = {
1692                 .init = &evergreen_hpd_init,
1693                 .fini = &evergreen_hpd_fini,
1694                 .sense = &evergreen_hpd_sense,
1695                 .set_polarity = &evergreen_hpd_set_polarity,
1696         },
1697         .pm = {
1698                 .misc = &evergreen_pm_misc,
1699                 .prepare = &evergreen_pm_prepare,
1700                 .finish = &evergreen_pm_finish,
1701                 .init_profile = &btc_pm_init_profile,
1702                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1703                 .get_engine_clock = &radeon_atom_get_engine_clock,
1704                 .set_engine_clock = &radeon_atom_set_engine_clock,
1705                 .get_memory_clock = &radeon_atom_get_memory_clock,
1706                 .set_memory_clock = &radeon_atom_set_memory_clock,
1707                 .get_pcie_lanes = &r600_get_pcie_lanes,
1708                 .set_pcie_lanes = &r600_set_pcie_lanes,
1709                 .set_clock_gating = NULL,
1710                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1711                 .get_temperature = &evergreen_get_temp,
1712         },
1713         .dpm = {
1714                 .init = &ni_dpm_init,
1715                 .setup_asic = &ni_dpm_setup_asic,
1716                 .enable = &ni_dpm_enable,
1717                 .late_enable = &rv770_dpm_late_enable,
1718                 .disable = &ni_dpm_disable,
1719                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1720                 .set_power_state = &ni_dpm_set_power_state,
1721                 .post_set_power_state = &ni_dpm_post_set_power_state,
1722                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1723                 .fini = &ni_dpm_fini,
1724                 .get_sclk = &ni_dpm_get_sclk,
1725                 .get_mclk = &ni_dpm_get_mclk,
1726                 .print_power_state = &ni_dpm_print_power_state,
1727                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1728                 .force_performance_level = &ni_dpm_force_performance_level,
1729                 .vblank_too_short = &ni_dpm_vblank_too_short,
1730                 .get_current_sclk = &ni_dpm_get_current_sclk,
1731                 .get_current_mclk = &ni_dpm_get_current_mclk,
1732         },
1733         .pflip = {
1734                 .page_flip = &evergreen_page_flip,
1735                 .page_flip_pending = &evergreen_page_flip_pending,
1736         },
1737 };
1738
1739 static struct radeon_asic trinity_asic = {
1740         .init = &cayman_init,
1741         .fini = &cayman_fini,
1742         .suspend = &cayman_suspend,
1743         .resume = &cayman_resume,
1744         .asic_reset = &cayman_asic_reset,
1745         .vga_set_state = &r600_vga_set_state,
1746         .mmio_hdp_flush = r600_mmio_hdp_flush,
1747         .gui_idle = &r600_gui_idle,
1748         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1749         .get_xclk = &r600_get_xclk,
1750         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1751         .gart = {
1752                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1753                 .get_page_entry = &rs600_gart_get_page_entry,
1754                 .set_page = &rs600_gart_set_page,
1755         },
1756         .vm = {
1757                 .init = &cayman_vm_init,
1758                 .fini = &cayman_vm_fini,
1759                 .copy_pages = &cayman_dma_vm_copy_pages,
1760                 .write_pages = &cayman_dma_vm_write_pages,
1761                 .set_pages = &cayman_dma_vm_set_pages,
1762                 .pad_ib = &cayman_dma_vm_pad_ib,
1763         },
1764         .ring = {
1765                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1766                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1767                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1768                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1769                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1770                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1771         },
1772         .irq = {
1773                 .set = &evergreen_irq_set,
1774                 .process = &evergreen_irq_process,
1775         },
1776         .display = {
1777                 .bandwidth_update = &dce6_bandwidth_update,
1778                 .get_vblank_counter = &evergreen_get_vblank_counter,
1779                 .wait_for_vblank = &dce4_wait_for_vblank,
1780                 .set_backlight_level = &atombios_set_backlight_level,
1781                 .get_backlight_level = &atombios_get_backlight_level,
1782         },
1783         .copy = {
1784                 .blit = &r600_copy_cpdma,
1785                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1786                 .dma = &evergreen_copy_dma,
1787                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1788                 .copy = &evergreen_copy_dma,
1789                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1790         },
1791         .surface = {
1792                 .set_reg = r600_set_surface_reg,
1793                 .clear_reg = r600_clear_surface_reg,
1794         },
1795         .hpd = {
1796                 .init = &evergreen_hpd_init,
1797                 .fini = &evergreen_hpd_fini,
1798                 .sense = &evergreen_hpd_sense,
1799                 .set_polarity = &evergreen_hpd_set_polarity,
1800         },
1801         .pm = {
1802                 .misc = &evergreen_pm_misc,
1803                 .prepare = &evergreen_pm_prepare,
1804                 .finish = &evergreen_pm_finish,
1805                 .init_profile = &sumo_pm_init_profile,
1806                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1807                 .get_engine_clock = &radeon_atom_get_engine_clock,
1808                 .set_engine_clock = &radeon_atom_set_engine_clock,
1809                 .get_memory_clock = NULL,
1810                 .set_memory_clock = NULL,
1811                 .get_pcie_lanes = NULL,
1812                 .set_pcie_lanes = NULL,
1813                 .set_clock_gating = NULL,
1814                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1815                 .get_temperature = &tn_get_temp,
1816         },
1817         .dpm = {
1818                 .init = &trinity_dpm_init,
1819                 .setup_asic = &trinity_dpm_setup_asic,
1820                 .enable = &trinity_dpm_enable,
1821                 .late_enable = &trinity_dpm_late_enable,
1822                 .disable = &trinity_dpm_disable,
1823                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1824                 .set_power_state = &trinity_dpm_set_power_state,
1825                 .post_set_power_state = &trinity_dpm_post_set_power_state,
1826                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1827                 .fini = &trinity_dpm_fini,
1828                 .get_sclk = &trinity_dpm_get_sclk,
1829                 .get_mclk = &trinity_dpm_get_mclk,
1830                 .print_power_state = &trinity_dpm_print_power_state,
1831                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1832                 .force_performance_level = &trinity_dpm_force_performance_level,
1833                 .enable_bapm = &trinity_dpm_enable_bapm,
1834         },
1835         .pflip = {
1836                 .page_flip = &evergreen_page_flip,
1837                 .page_flip_pending = &evergreen_page_flip_pending,
1838         },
1839 };
1840
1841 static struct radeon_asic_ring si_gfx_ring = {
1842         .ib_execute = &si_ring_ib_execute,
1843         .ib_parse = &si_ib_parse,
1844         .emit_fence = &si_fence_ring_emit,
1845         .emit_semaphore = &r600_semaphore_ring_emit,
1846         .cs_parse = NULL,
1847         .ring_test = &r600_ring_test,
1848         .ib_test = &r600_ib_test,
1849         .is_lockup = &si_gfx_is_lockup,
1850         .vm_flush = &si_vm_flush,
1851         .get_rptr = &cayman_gfx_get_rptr,
1852         .get_wptr = &cayman_gfx_get_wptr,
1853         .set_wptr = &cayman_gfx_set_wptr,
1854 };
1855
1856 static struct radeon_asic_ring si_dma_ring = {
1857         .ib_execute = &cayman_dma_ring_ib_execute,
1858         .ib_parse = &evergreen_dma_ib_parse,
1859         .emit_fence = &evergreen_dma_fence_ring_emit,
1860         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1861         .cs_parse = NULL,
1862         .ring_test = &r600_dma_ring_test,
1863         .ib_test = &r600_dma_ib_test,
1864         .is_lockup = &si_dma_is_lockup,
1865         .vm_flush = &si_dma_vm_flush,
1866         .get_rptr = &cayman_dma_get_rptr,
1867         .get_wptr = &cayman_dma_get_wptr,
1868         .set_wptr = &cayman_dma_set_wptr,
1869 };
1870
1871 static struct radeon_asic si_asic = {
1872         .init = &si_init,
1873         .fini = &si_fini,
1874         .suspend = &si_suspend,
1875         .resume = &si_resume,
1876         .asic_reset = &si_asic_reset,
1877         .vga_set_state = &r600_vga_set_state,
1878         .mmio_hdp_flush = r600_mmio_hdp_flush,
1879         .gui_idle = &r600_gui_idle,
1880         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1881         .get_xclk = &si_get_xclk,
1882         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1883         .gart = {
1884                 .tlb_flush = &si_pcie_gart_tlb_flush,
1885                 .get_page_entry = &rs600_gart_get_page_entry,
1886                 .set_page = &rs600_gart_set_page,
1887         },
1888         .vm = {
1889                 .init = &si_vm_init,
1890                 .fini = &si_vm_fini,
1891                 .copy_pages = &si_dma_vm_copy_pages,
1892                 .write_pages = &si_dma_vm_write_pages,
1893                 .set_pages = &si_dma_vm_set_pages,
1894                 .pad_ib = &cayman_dma_vm_pad_ib,
1895         },
1896         .ring = {
1897                 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1898                 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1899                 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1900                 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1901                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1902                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1903         },
1904         .irq = {
1905                 .set = &si_irq_set,
1906                 .process = &si_irq_process,
1907         },
1908         .display = {
1909                 .bandwidth_update = &dce6_bandwidth_update,
1910                 .get_vblank_counter = &evergreen_get_vblank_counter,
1911                 .wait_for_vblank = &dce4_wait_for_vblank,
1912                 .set_backlight_level = &atombios_set_backlight_level,
1913                 .get_backlight_level = &atombios_get_backlight_level,
1914         },
1915         .copy = {
1916                 .blit = &r600_copy_cpdma,
1917                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1918                 .dma = &si_copy_dma,
1919                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1920                 .copy = &si_copy_dma,
1921                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1922         },
1923         .surface = {
1924                 .set_reg = r600_set_surface_reg,
1925                 .clear_reg = r600_clear_surface_reg,
1926         },
1927         .hpd = {
1928                 .init = &evergreen_hpd_init,
1929                 .fini = &evergreen_hpd_fini,
1930                 .sense = &evergreen_hpd_sense,
1931                 .set_polarity = &evergreen_hpd_set_polarity,
1932         },
1933         .pm = {
1934                 .misc = &evergreen_pm_misc,
1935                 .prepare = &evergreen_pm_prepare,
1936                 .finish = &evergreen_pm_finish,
1937                 .init_profile = &sumo_pm_init_profile,
1938                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1939                 .get_engine_clock = &radeon_atom_get_engine_clock,
1940                 .set_engine_clock = &radeon_atom_set_engine_clock,
1941                 .get_memory_clock = &radeon_atom_get_memory_clock,
1942                 .set_memory_clock = &radeon_atom_set_memory_clock,
1943                 .get_pcie_lanes = &r600_get_pcie_lanes,
1944                 .set_pcie_lanes = &r600_set_pcie_lanes,
1945                 .set_clock_gating = NULL,
1946                 .set_uvd_clocks = &si_set_uvd_clocks,
1947                 .get_temperature = &si_get_temp,
1948         },
1949         .dpm = {
1950                 .init = &si_dpm_init,
1951                 .setup_asic = &si_dpm_setup_asic,
1952                 .enable = &si_dpm_enable,
1953                 .late_enable = &si_dpm_late_enable,
1954                 .disable = &si_dpm_disable,
1955                 .pre_set_power_state = &si_dpm_pre_set_power_state,
1956                 .set_power_state = &si_dpm_set_power_state,
1957                 .post_set_power_state = &si_dpm_post_set_power_state,
1958                 .display_configuration_changed = &si_dpm_display_configuration_changed,
1959                 .fini = &si_dpm_fini,
1960                 .get_sclk = &ni_dpm_get_sclk,
1961                 .get_mclk = &ni_dpm_get_mclk,
1962                 .print_power_state = &ni_dpm_print_power_state,
1963                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1964                 .force_performance_level = &si_dpm_force_performance_level,
1965                 .vblank_too_short = &ni_dpm_vblank_too_short,
1966                 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
1967                 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
1968                 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
1969                 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
1970         },
1971         .pflip = {
1972                 .page_flip = &evergreen_page_flip,
1973                 .page_flip_pending = &evergreen_page_flip_pending,
1974         },
1975 };
1976
1977 static struct radeon_asic_ring ci_gfx_ring = {
1978         .ib_execute = &cik_ring_ib_execute,
1979         .ib_parse = &cik_ib_parse,
1980         .emit_fence = &cik_fence_gfx_ring_emit,
1981         .emit_semaphore = &cik_semaphore_ring_emit,
1982         .cs_parse = NULL,
1983         .ring_test = &cik_ring_test,
1984         .ib_test = &cik_ib_test,
1985         .is_lockup = &cik_gfx_is_lockup,
1986         .vm_flush = &cik_vm_flush,
1987         .get_rptr = &cik_gfx_get_rptr,
1988         .get_wptr = &cik_gfx_get_wptr,
1989         .set_wptr = &cik_gfx_set_wptr,
1990 };
1991
1992 static struct radeon_asic_ring ci_cp_ring = {
1993         .ib_execute = &cik_ring_ib_execute,
1994         .ib_parse = &cik_ib_parse,
1995         .emit_fence = &cik_fence_compute_ring_emit,
1996         .emit_semaphore = &cik_semaphore_ring_emit,
1997         .cs_parse = NULL,
1998         .ring_test = &cik_ring_test,
1999         .ib_test = &cik_ib_test,
2000         .is_lockup = &cik_gfx_is_lockup,
2001         .vm_flush = &cik_vm_flush,
2002         .get_rptr = &cik_compute_get_rptr,
2003         .get_wptr = &cik_compute_get_wptr,
2004         .set_wptr = &cik_compute_set_wptr,
2005 };
2006
2007 static struct radeon_asic_ring ci_dma_ring = {
2008         .ib_execute = &cik_sdma_ring_ib_execute,
2009         .ib_parse = &cik_ib_parse,
2010         .emit_fence = &cik_sdma_fence_ring_emit,
2011         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2012         .cs_parse = NULL,
2013         .ring_test = &cik_sdma_ring_test,
2014         .ib_test = &cik_sdma_ib_test,
2015         .is_lockup = &cik_sdma_is_lockup,
2016         .vm_flush = &cik_dma_vm_flush,
2017         .get_rptr = &cik_sdma_get_rptr,
2018         .get_wptr = &cik_sdma_get_wptr,
2019         .set_wptr = &cik_sdma_set_wptr,
2020 };
2021
2022 static struct radeon_asic_ring ci_vce_ring = {
2023         .ib_execute = &radeon_vce_ib_execute,
2024         .emit_fence = &radeon_vce_fence_emit,
2025         .emit_semaphore = &radeon_vce_semaphore_emit,
2026         .cs_parse = &radeon_vce_cs_parse,
2027         .ring_test = &radeon_vce_ring_test,
2028         .ib_test = &radeon_vce_ib_test,
2029         .is_lockup = &radeon_ring_test_lockup,
2030         .get_rptr = &vce_v1_0_get_rptr,
2031         .get_wptr = &vce_v1_0_get_wptr,
2032         .set_wptr = &vce_v1_0_set_wptr,
2033 };
2034
2035 static struct radeon_asic ci_asic = {
2036         .init = &cik_init,
2037         .fini = &cik_fini,
2038         .suspend = &cik_suspend,
2039         .resume = &cik_resume,
2040         .asic_reset = &cik_asic_reset,
2041         .vga_set_state = &r600_vga_set_state,
2042         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2043         .gui_idle = &r600_gui_idle,
2044         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2045         .get_xclk = &cik_get_xclk,
2046         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2047         .gart = {
2048                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2049                 .get_page_entry = &rs600_gart_get_page_entry,
2050                 .set_page = &rs600_gart_set_page,
2051         },
2052         .vm = {
2053                 .init = &cik_vm_init,
2054                 .fini = &cik_vm_fini,
2055                 .copy_pages = &cik_sdma_vm_copy_pages,
2056                 .write_pages = &cik_sdma_vm_write_pages,
2057                 .set_pages = &cik_sdma_vm_set_pages,
2058                 .pad_ib = &cik_sdma_vm_pad_ib,
2059         },
2060         .ring = {
2061                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2062                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2063                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2064                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2065                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2066                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2067                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2068                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2069         },
2070         .irq = {
2071                 .set = &cik_irq_set,
2072                 .process = &cik_irq_process,
2073         },
2074         .display = {
2075                 .bandwidth_update = &dce8_bandwidth_update,
2076                 .get_vblank_counter = &evergreen_get_vblank_counter,
2077                 .wait_for_vblank = &dce4_wait_for_vblank,
2078                 .set_backlight_level = &atombios_set_backlight_level,
2079                 .get_backlight_level = &atombios_get_backlight_level,
2080         },
2081         .copy = {
2082                 .blit = &cik_copy_cpdma,
2083                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2084                 .dma = &cik_copy_dma,
2085                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2086                 .copy = &cik_copy_dma,
2087                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2088         },
2089         .surface = {
2090                 .set_reg = r600_set_surface_reg,
2091                 .clear_reg = r600_clear_surface_reg,
2092         },
2093         .hpd = {
2094                 .init = &evergreen_hpd_init,
2095                 .fini = &evergreen_hpd_fini,
2096                 .sense = &evergreen_hpd_sense,
2097                 .set_polarity = &evergreen_hpd_set_polarity,
2098         },
2099         .pm = {
2100                 .misc = &evergreen_pm_misc,
2101                 .prepare = &evergreen_pm_prepare,
2102                 .finish = &evergreen_pm_finish,
2103                 .init_profile = &sumo_pm_init_profile,
2104                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2105                 .get_engine_clock = &radeon_atom_get_engine_clock,
2106                 .set_engine_clock = &radeon_atom_set_engine_clock,
2107                 .get_memory_clock = &radeon_atom_get_memory_clock,
2108                 .set_memory_clock = &radeon_atom_set_memory_clock,
2109                 .get_pcie_lanes = NULL,
2110                 .set_pcie_lanes = NULL,
2111                 .set_clock_gating = NULL,
2112                 .set_uvd_clocks = &cik_set_uvd_clocks,
2113                 .set_vce_clocks = &cik_set_vce_clocks,
2114                 .get_temperature = &ci_get_temp,
2115         },
2116         .dpm = {
2117                 .init = &ci_dpm_init,
2118                 .setup_asic = &ci_dpm_setup_asic,
2119                 .enable = &ci_dpm_enable,
2120                 .late_enable = &ci_dpm_late_enable,
2121                 .disable = &ci_dpm_disable,
2122                 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2123                 .set_power_state = &ci_dpm_set_power_state,
2124                 .post_set_power_state = &ci_dpm_post_set_power_state,
2125                 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2126                 .fini = &ci_dpm_fini,
2127                 .get_sclk = &ci_dpm_get_sclk,
2128                 .get_mclk = &ci_dpm_get_mclk,
2129                 .print_power_state = &ci_dpm_print_power_state,
2130                 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2131                 .force_performance_level = &ci_dpm_force_performance_level,
2132                 .vblank_too_short = &ci_dpm_vblank_too_short,
2133                 .powergate_uvd = &ci_dpm_powergate_uvd,
2134                 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2135                 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2136                 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2137                 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
2138         },
2139         .pflip = {
2140                 .page_flip = &evergreen_page_flip,
2141                 .page_flip_pending = &evergreen_page_flip_pending,
2142         },
2143 };
2144
2145 static struct radeon_asic kv_asic = {
2146         .init = &cik_init,
2147         .fini = &cik_fini,
2148         .suspend = &cik_suspend,
2149         .resume = &cik_resume,
2150         .asic_reset = &cik_asic_reset,
2151         .vga_set_state = &r600_vga_set_state,
2152         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2153         .gui_idle = &r600_gui_idle,
2154         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2155         .get_xclk = &cik_get_xclk,
2156         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2157         .gart = {
2158                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2159                 .get_page_entry = &rs600_gart_get_page_entry,
2160                 .set_page = &rs600_gart_set_page,
2161         },
2162         .vm = {
2163                 .init = &cik_vm_init,
2164                 .fini = &cik_vm_fini,
2165                 .copy_pages = &cik_sdma_vm_copy_pages,
2166                 .write_pages = &cik_sdma_vm_write_pages,
2167                 .set_pages = &cik_sdma_vm_set_pages,
2168                 .pad_ib = &cik_sdma_vm_pad_ib,
2169         },
2170         .ring = {
2171                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2172                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2173                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2174                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2175                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2176                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2177                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2178                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2179         },
2180         .irq = {
2181                 .set = &cik_irq_set,
2182                 .process = &cik_irq_process,
2183         },
2184         .display = {
2185                 .bandwidth_update = &dce8_bandwidth_update,
2186                 .get_vblank_counter = &evergreen_get_vblank_counter,
2187                 .wait_for_vblank = &dce4_wait_for_vblank,
2188                 .set_backlight_level = &atombios_set_backlight_level,
2189                 .get_backlight_level = &atombios_get_backlight_level,
2190         },
2191         .copy = {
2192                 .blit = &cik_copy_cpdma,
2193                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2194                 .dma = &cik_copy_dma,
2195                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2196                 .copy = &cik_copy_dma,
2197                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2198         },
2199         .surface = {
2200                 .set_reg = r600_set_surface_reg,
2201                 .clear_reg = r600_clear_surface_reg,
2202         },
2203         .hpd = {
2204                 .init = &evergreen_hpd_init,
2205                 .fini = &evergreen_hpd_fini,
2206                 .sense = &evergreen_hpd_sense,
2207                 .set_polarity = &evergreen_hpd_set_polarity,
2208         },
2209         .pm = {
2210                 .misc = &evergreen_pm_misc,
2211                 .prepare = &evergreen_pm_prepare,
2212                 .finish = &evergreen_pm_finish,
2213                 .init_profile = &sumo_pm_init_profile,
2214                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2215                 .get_engine_clock = &radeon_atom_get_engine_clock,
2216                 .set_engine_clock = &radeon_atom_set_engine_clock,
2217                 .get_memory_clock = &radeon_atom_get_memory_clock,
2218                 .set_memory_clock = &radeon_atom_set_memory_clock,
2219                 .get_pcie_lanes = NULL,
2220                 .set_pcie_lanes = NULL,
2221                 .set_clock_gating = NULL,
2222                 .set_uvd_clocks = &cik_set_uvd_clocks,
2223                 .set_vce_clocks = &cik_set_vce_clocks,
2224                 .get_temperature = &kv_get_temp,
2225         },
2226         .dpm = {
2227                 .init = &kv_dpm_init,
2228                 .setup_asic = &kv_dpm_setup_asic,
2229                 .enable = &kv_dpm_enable,
2230                 .late_enable = &kv_dpm_late_enable,
2231                 .disable = &kv_dpm_disable,
2232                 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2233                 .set_power_state = &kv_dpm_set_power_state,
2234                 .post_set_power_state = &kv_dpm_post_set_power_state,
2235                 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2236                 .fini = &kv_dpm_fini,
2237                 .get_sclk = &kv_dpm_get_sclk,
2238                 .get_mclk = &kv_dpm_get_mclk,
2239                 .print_power_state = &kv_dpm_print_power_state,
2240                 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2241                 .force_performance_level = &kv_dpm_force_performance_level,
2242                 .powergate_uvd = &kv_dpm_powergate_uvd,
2243                 .enable_bapm = &kv_dpm_enable_bapm,
2244         },
2245         .pflip = {
2246                 .page_flip = &evergreen_page_flip,
2247                 .page_flip_pending = &evergreen_page_flip_pending,
2248         },
2249 };
2250
2251 /**
2252  * radeon_asic_init - register asic specific callbacks
2253  *
2254  * @rdev: radeon device pointer
2255  *
2256  * Registers the appropriate asic specific callbacks for each
2257  * chip family.  Also sets other asics specific info like the number
2258  * of crtcs and the register aperture accessors (all asics).
2259  * Returns 0 for success.
2260  */
2261 int radeon_asic_init(struct radeon_device *rdev)
2262 {
2263         radeon_register_accessor_init(rdev);
2264
2265         /* set the number of crtcs */
2266         if (rdev->flags & RADEON_SINGLE_CRTC)
2267                 rdev->num_crtc = 1;
2268         else
2269                 rdev->num_crtc = 2;
2270
2271         rdev->has_uvd = false;
2272
2273         switch (rdev->family) {
2274         case CHIP_R100:
2275         case CHIP_RV100:
2276         case CHIP_RS100:
2277         case CHIP_RV200:
2278         case CHIP_RS200:
2279                 rdev->asic = &r100_asic;
2280                 break;
2281         case CHIP_R200:
2282         case CHIP_RV250:
2283         case CHIP_RS300:
2284         case CHIP_RV280:
2285                 rdev->asic = &r200_asic;
2286                 break;
2287         case CHIP_R300:
2288         case CHIP_R350:
2289         case CHIP_RV350:
2290         case CHIP_RV380:
2291                 if (rdev->flags & RADEON_IS_PCIE)
2292                         rdev->asic = &r300_asic_pcie;
2293                 else
2294                         rdev->asic = &r300_asic;
2295                 break;
2296         case CHIP_R420:
2297         case CHIP_R423:
2298         case CHIP_RV410:
2299                 rdev->asic = &r420_asic;
2300                 /* handle macs */
2301                 if (rdev->bios == NULL) {
2302                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2303                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2304                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2305                         rdev->asic->pm.set_memory_clock = NULL;
2306                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2307                 }
2308                 break;
2309         case CHIP_RS400:
2310         case CHIP_RS480:
2311                 rdev->asic = &rs400_asic;
2312                 break;
2313         case CHIP_RS600:
2314                 rdev->asic = &rs600_asic;
2315                 break;
2316         case CHIP_RS690:
2317         case CHIP_RS740:
2318                 rdev->asic = &rs690_asic;
2319                 break;
2320         case CHIP_RV515:
2321                 rdev->asic = &rv515_asic;
2322                 break;
2323         case CHIP_R520:
2324         case CHIP_RV530:
2325         case CHIP_RV560:
2326         case CHIP_RV570:
2327         case CHIP_R580:
2328                 rdev->asic = &r520_asic;
2329                 break;
2330         case CHIP_R600:
2331                 rdev->asic = &r600_asic;
2332                 break;
2333         case CHIP_RV610:
2334         case CHIP_RV630:
2335         case CHIP_RV620:
2336         case CHIP_RV635:
2337         case CHIP_RV670:
2338                 rdev->asic = &rv6xx_asic;
2339                 rdev->has_uvd = true;
2340                 break;
2341         case CHIP_RS780:
2342         case CHIP_RS880:
2343                 rdev->asic = &rs780_asic;
2344                 /* 760G/780V/880V don't have UVD */
2345                 if ((rdev->pdev->device == 0x9616)||
2346                     (rdev->pdev->device == 0x9611)||
2347                     (rdev->pdev->device == 0x9613)||
2348                     (rdev->pdev->device == 0x9711)||
2349                     (rdev->pdev->device == 0x9713))
2350                         rdev->has_uvd = false;
2351                 else
2352                         rdev->has_uvd = true;
2353                 break;
2354         case CHIP_RV770:
2355         case CHIP_RV730:
2356         case CHIP_RV710:
2357         case CHIP_RV740:
2358                 rdev->asic = &rv770_asic;
2359                 rdev->has_uvd = true;
2360                 break;
2361         case CHIP_CEDAR:
2362         case CHIP_REDWOOD:
2363         case CHIP_JUNIPER:
2364         case CHIP_CYPRESS:
2365         case CHIP_HEMLOCK:
2366                 /* set num crtcs */
2367                 if (rdev->family == CHIP_CEDAR)
2368                         rdev->num_crtc = 4;
2369                 else
2370                         rdev->num_crtc = 6;
2371                 rdev->asic = &evergreen_asic;
2372                 rdev->has_uvd = true;
2373                 break;
2374         case CHIP_PALM:
2375         case CHIP_SUMO:
2376         case CHIP_SUMO2:
2377                 rdev->asic = &sumo_asic;
2378                 rdev->has_uvd = true;
2379                 break;
2380         case CHIP_BARTS:
2381         case CHIP_TURKS:
2382         case CHIP_CAICOS:
2383                 /* set num crtcs */
2384                 if (rdev->family == CHIP_CAICOS)
2385                         rdev->num_crtc = 4;
2386                 else
2387                         rdev->num_crtc = 6;
2388                 rdev->asic = &btc_asic;
2389                 rdev->has_uvd = true;
2390                 break;
2391         case CHIP_CAYMAN:
2392                 rdev->asic = &cayman_asic;
2393                 /* set num crtcs */
2394                 rdev->num_crtc = 6;
2395                 rdev->has_uvd = true;
2396                 break;
2397         case CHIP_ARUBA:
2398                 rdev->asic = &trinity_asic;
2399                 /* set num crtcs */
2400                 rdev->num_crtc = 4;
2401                 rdev->has_uvd = true;
2402                 break;
2403         case CHIP_TAHITI:
2404         case CHIP_PITCAIRN:
2405         case CHIP_VERDE:
2406         case CHIP_OLAND:
2407         case CHIP_HAINAN:
2408                 rdev->asic = &si_asic;
2409                 /* set num crtcs */
2410                 if (rdev->family == CHIP_HAINAN)
2411                         rdev->num_crtc = 0;
2412                 else if (rdev->family == CHIP_OLAND)
2413                         rdev->num_crtc = 2;
2414                 else
2415                         rdev->num_crtc = 6;
2416                 if (rdev->family == CHIP_HAINAN)
2417                         rdev->has_uvd = false;
2418                 else
2419                         rdev->has_uvd = true;
2420                 switch (rdev->family) {
2421                 case CHIP_TAHITI:
2422                         rdev->cg_flags =
2423                                 RADEON_CG_SUPPORT_GFX_MGCG |
2424                                 RADEON_CG_SUPPORT_GFX_MGLS |
2425                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2426                                 RADEON_CG_SUPPORT_GFX_CGLS |
2427                                 RADEON_CG_SUPPORT_GFX_CGTS |
2428                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2429                                 RADEON_CG_SUPPORT_MC_MGCG |
2430                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2431                                 RADEON_CG_SUPPORT_BIF_LS |
2432                                 RADEON_CG_SUPPORT_VCE_MGCG |
2433                                 RADEON_CG_SUPPORT_UVD_MGCG |
2434                                 RADEON_CG_SUPPORT_HDP_LS |
2435                                 RADEON_CG_SUPPORT_HDP_MGCG;
2436                         rdev->pg_flags = 0;
2437                         break;
2438                 case CHIP_PITCAIRN:
2439                         rdev->cg_flags =
2440                                 RADEON_CG_SUPPORT_GFX_MGCG |
2441                                 RADEON_CG_SUPPORT_GFX_MGLS |
2442                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2443                                 RADEON_CG_SUPPORT_GFX_CGLS |
2444                                 RADEON_CG_SUPPORT_GFX_CGTS |
2445                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2446                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2447                                 RADEON_CG_SUPPORT_MC_LS |
2448                                 RADEON_CG_SUPPORT_MC_MGCG |
2449                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2450                                 RADEON_CG_SUPPORT_BIF_LS |
2451                                 RADEON_CG_SUPPORT_VCE_MGCG |
2452                                 RADEON_CG_SUPPORT_UVD_MGCG |
2453                                 RADEON_CG_SUPPORT_HDP_LS |
2454                                 RADEON_CG_SUPPORT_HDP_MGCG;
2455                         rdev->pg_flags = 0;
2456                         break;
2457                 case CHIP_VERDE:
2458                         rdev->cg_flags =
2459                                 RADEON_CG_SUPPORT_GFX_MGCG |
2460                                 RADEON_CG_SUPPORT_GFX_MGLS |
2461                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2462                                 RADEON_CG_SUPPORT_GFX_CGLS |
2463                                 RADEON_CG_SUPPORT_GFX_CGTS |
2464                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2465                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2466                                 RADEON_CG_SUPPORT_MC_LS |
2467                                 RADEON_CG_SUPPORT_MC_MGCG |
2468                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2469                                 RADEON_CG_SUPPORT_BIF_LS |
2470                                 RADEON_CG_SUPPORT_VCE_MGCG |
2471                                 RADEON_CG_SUPPORT_UVD_MGCG |
2472                                 RADEON_CG_SUPPORT_HDP_LS |
2473                                 RADEON_CG_SUPPORT_HDP_MGCG;
2474                         rdev->pg_flags = 0 |
2475                                 /*RADEON_PG_SUPPORT_GFX_PG | */
2476                                 RADEON_PG_SUPPORT_SDMA;
2477                         break;
2478                 case CHIP_OLAND:
2479                         rdev->cg_flags =
2480                                 RADEON_CG_SUPPORT_GFX_MGCG |
2481                                 RADEON_CG_SUPPORT_GFX_MGLS |
2482                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2483                                 RADEON_CG_SUPPORT_GFX_CGLS |
2484                                 RADEON_CG_SUPPORT_GFX_CGTS |
2485                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2486                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2487                                 RADEON_CG_SUPPORT_MC_LS |
2488                                 RADEON_CG_SUPPORT_MC_MGCG |
2489                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2490                                 RADEON_CG_SUPPORT_BIF_LS |
2491                                 RADEON_CG_SUPPORT_UVD_MGCG |
2492                                 RADEON_CG_SUPPORT_HDP_LS |
2493                                 RADEON_CG_SUPPORT_HDP_MGCG;
2494                         rdev->pg_flags = 0;
2495                         break;
2496                 case CHIP_HAINAN:
2497                         rdev->cg_flags =
2498                                 RADEON_CG_SUPPORT_GFX_MGCG |
2499                                 RADEON_CG_SUPPORT_GFX_MGLS |
2500                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2501                                 RADEON_CG_SUPPORT_GFX_CGLS |
2502                                 RADEON_CG_SUPPORT_GFX_CGTS |
2503                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2504                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2505                                 RADEON_CG_SUPPORT_MC_LS |
2506                                 RADEON_CG_SUPPORT_MC_MGCG |
2507                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2508                                 RADEON_CG_SUPPORT_BIF_LS |
2509                                 RADEON_CG_SUPPORT_HDP_LS |
2510                                 RADEON_CG_SUPPORT_HDP_MGCG;
2511                         rdev->pg_flags = 0;
2512                         break;
2513                 default:
2514                         rdev->cg_flags = 0;
2515                         rdev->pg_flags = 0;
2516                         break;
2517                 }
2518                 break;
2519         case CHIP_BONAIRE:
2520         case CHIP_HAWAII:
2521                 rdev->asic = &ci_asic;
2522                 rdev->num_crtc = 6;
2523                 rdev->has_uvd = true;
2524                 if (rdev->family == CHIP_BONAIRE) {
2525                         rdev->cg_flags =
2526                                 RADEON_CG_SUPPORT_GFX_MGCG |
2527                                 RADEON_CG_SUPPORT_GFX_MGLS |
2528                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2529                                 RADEON_CG_SUPPORT_GFX_CGLS |
2530                                 RADEON_CG_SUPPORT_GFX_CGTS |
2531                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2532                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2533                                 RADEON_CG_SUPPORT_MC_LS |
2534                                 RADEON_CG_SUPPORT_MC_MGCG |
2535                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2536                                 RADEON_CG_SUPPORT_SDMA_LS |
2537                                 RADEON_CG_SUPPORT_BIF_LS |
2538                                 RADEON_CG_SUPPORT_VCE_MGCG |
2539                                 RADEON_CG_SUPPORT_UVD_MGCG |
2540                                 RADEON_CG_SUPPORT_HDP_LS |
2541                                 RADEON_CG_SUPPORT_HDP_MGCG;
2542                         rdev->pg_flags = 0;
2543                 } else {
2544                         rdev->cg_flags =
2545                                 RADEON_CG_SUPPORT_GFX_MGCG |
2546                                 RADEON_CG_SUPPORT_GFX_MGLS |
2547                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2548                                 RADEON_CG_SUPPORT_GFX_CGLS |
2549                                 RADEON_CG_SUPPORT_GFX_CGTS |
2550                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2551                                 RADEON_CG_SUPPORT_MC_LS |
2552                                 RADEON_CG_SUPPORT_MC_MGCG |
2553                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2554                                 RADEON_CG_SUPPORT_SDMA_LS |
2555                                 RADEON_CG_SUPPORT_BIF_LS |
2556                                 RADEON_CG_SUPPORT_VCE_MGCG |
2557                                 RADEON_CG_SUPPORT_UVD_MGCG |
2558                                 RADEON_CG_SUPPORT_HDP_LS |
2559                                 RADEON_CG_SUPPORT_HDP_MGCG;
2560                         rdev->pg_flags = 0;
2561                 }
2562                 break;
2563         case CHIP_KAVERI:
2564         case CHIP_KABINI:
2565         case CHIP_MULLINS:
2566                 rdev->asic = &kv_asic;
2567                 /* set num crtcs */
2568                 if (rdev->family == CHIP_KAVERI) {
2569                         rdev->num_crtc = 4;
2570                         rdev->cg_flags =
2571                                 RADEON_CG_SUPPORT_GFX_MGCG |
2572                                 RADEON_CG_SUPPORT_GFX_MGLS |
2573                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2574                                 RADEON_CG_SUPPORT_GFX_CGLS |
2575                                 RADEON_CG_SUPPORT_GFX_CGTS |
2576                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2577                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2578                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2579                                 RADEON_CG_SUPPORT_SDMA_LS |
2580                                 RADEON_CG_SUPPORT_BIF_LS |
2581                                 RADEON_CG_SUPPORT_VCE_MGCG |
2582                                 RADEON_CG_SUPPORT_UVD_MGCG |
2583                                 RADEON_CG_SUPPORT_HDP_LS |
2584                                 RADEON_CG_SUPPORT_HDP_MGCG;
2585                         rdev->pg_flags = 0;
2586                                 /*RADEON_PG_SUPPORT_GFX_PG |
2587                                 RADEON_PG_SUPPORT_GFX_SMG |
2588                                 RADEON_PG_SUPPORT_GFX_DMG |
2589                                 RADEON_PG_SUPPORT_UVD |
2590                                 RADEON_PG_SUPPORT_VCE |
2591                                 RADEON_PG_SUPPORT_CP |
2592                                 RADEON_PG_SUPPORT_GDS |
2593                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2594                                 RADEON_PG_SUPPORT_ACP |
2595                                 RADEON_PG_SUPPORT_SAMU;*/
2596                 } else {
2597                         rdev->num_crtc = 2;
2598                         rdev->cg_flags =
2599                                 RADEON_CG_SUPPORT_GFX_MGCG |
2600                                 RADEON_CG_SUPPORT_GFX_MGLS |
2601                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2602                                 RADEON_CG_SUPPORT_GFX_CGLS |
2603                                 RADEON_CG_SUPPORT_GFX_CGTS |
2604                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2605                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2606                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2607                                 RADEON_CG_SUPPORT_SDMA_LS |
2608                                 RADEON_CG_SUPPORT_BIF_LS |
2609                                 RADEON_CG_SUPPORT_VCE_MGCG |
2610                                 RADEON_CG_SUPPORT_UVD_MGCG |
2611                                 RADEON_CG_SUPPORT_HDP_LS |
2612                                 RADEON_CG_SUPPORT_HDP_MGCG;
2613                         rdev->pg_flags = 0;
2614                                 /*RADEON_PG_SUPPORT_GFX_PG |
2615                                 RADEON_PG_SUPPORT_GFX_SMG |
2616                                 RADEON_PG_SUPPORT_UVD |
2617                                 RADEON_PG_SUPPORT_VCE |
2618                                 RADEON_PG_SUPPORT_CP |
2619                                 RADEON_PG_SUPPORT_GDS |
2620                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2621                                 RADEON_PG_SUPPORT_SAMU;*/
2622                 }
2623                 rdev->has_uvd = true;
2624                 break;
2625         default:
2626                 /* FIXME: not supported yet */
2627                 return -EINVAL;
2628         }
2629
2630         if (rdev->flags & RADEON_IS_IGP) {
2631                 rdev->asic->pm.get_memory_clock = NULL;
2632                 rdev->asic->pm.set_memory_clock = NULL;
2633         }
2634
2635         return 0;
2636 }
2637