2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #ifndef __RADEON_ASIC_H__
29 #define __RADEON_ASIC_H__
34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
51 * r100,rv100,rs100,rv200,rs200
61 int r100_init(struct radeon_device *rdev);
62 void r100_fini(struct radeon_device *rdev);
63 int r100_suspend(struct radeon_device *rdev);
64 int r100_resume(struct radeon_device *rdev);
65 void r100_vga_set_state(struct radeon_device *rdev, bool state);
66 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
67 int r100_asic_reset(struct radeon_device *rdev);
68 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
69 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
70 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
71 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
72 int r100_irq_set(struct radeon_device *rdev);
73 int r100_irq_process(struct radeon_device *rdev);
74 void r100_fence_ring_emit(struct radeon_device *rdev,
75 struct radeon_fence *fence);
76 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
77 struct radeon_ring *cp,
78 struct radeon_semaphore *semaphore,
80 int r100_cs_parse(struct radeon_cs_parser *p);
81 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
82 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
83 int r100_copy_blit(struct radeon_device *rdev,
86 unsigned num_gpu_pages,
87 struct radeon_fence **fence);
88 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
89 uint32_t tiling_flags, uint32_t pitch,
90 uint32_t offset, uint32_t obj_size);
91 void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
92 void r100_bandwidth_update(struct radeon_device *rdev);
93 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
94 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
95 void r100_hpd_init(struct radeon_device *rdev);
96 void r100_hpd_fini(struct radeon_device *rdev);
97 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
98 void r100_hpd_set_polarity(struct radeon_device *rdev,
99 enum radeon_hpd_id hpd);
100 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
101 int r100_debugfs_cp_init(struct radeon_device *rdev);
102 void r100_cp_disable(struct radeon_device *rdev);
103 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
104 void r100_cp_fini(struct radeon_device *rdev);
105 int r100_pci_gart_init(struct radeon_device *rdev);
106 void r100_pci_gart_fini(struct radeon_device *rdev);
107 int r100_pci_gart_enable(struct radeon_device *rdev);
108 void r100_pci_gart_disable(struct radeon_device *rdev);
109 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
110 int r100_gui_wait_for_idle(struct radeon_device *rdev);
111 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
112 void r100_irq_disable(struct radeon_device *rdev);
113 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
114 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
115 void r100_vram_init_sizes(struct radeon_device *rdev);
116 int r100_cp_reset(struct radeon_device *rdev);
117 void r100_vga_render_disable(struct radeon_device *rdev);
118 void r100_restore_sanity(struct radeon_device *rdev);
119 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
120 struct radeon_cs_packet *pkt,
121 struct radeon_bo *robj);
122 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
123 struct radeon_cs_packet *pkt,
124 const unsigned *auth, unsigned n,
125 radeon_packet0_check_t check);
126 int r100_cs_packet_parse(struct radeon_cs_parser *p,
127 struct radeon_cs_packet *pkt,
129 void r100_enable_bm(struct radeon_device *rdev);
130 void r100_set_common_regs(struct radeon_device *rdev);
131 void r100_bm_disable(struct radeon_device *rdev);
132 extern bool r100_gui_idle(struct radeon_device *rdev);
133 extern void r100_pm_misc(struct radeon_device *rdev);
134 extern void r100_pm_prepare(struct radeon_device *rdev);
135 extern void r100_pm_finish(struct radeon_device *rdev);
136 extern void r100_pm_init_profile(struct radeon_device *rdev);
137 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
138 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
139 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
140 extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
142 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
143 struct radeon_ring *ring);
144 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
145 struct radeon_ring *ring);
146 void r100_gfx_set_wptr(struct radeon_device *rdev,
147 struct radeon_ring *ring);
150 * r200,rv250,rs300,rv280
152 extern int r200_copy_dma(struct radeon_device *rdev,
155 unsigned num_gpu_pages,
156 struct radeon_fence **fence);
157 void r200_set_safe_registers(struct radeon_device *rdev);
160 * r300,r350,rv350,rv380
162 extern int r300_init(struct radeon_device *rdev);
163 extern void r300_fini(struct radeon_device *rdev);
164 extern int r300_suspend(struct radeon_device *rdev);
165 extern int r300_resume(struct radeon_device *rdev);
166 extern int r300_asic_reset(struct radeon_device *rdev);
167 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
168 extern void r300_fence_ring_emit(struct radeon_device *rdev,
169 struct radeon_fence *fence);
170 extern int r300_cs_parse(struct radeon_cs_parser *p);
171 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
172 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
173 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
174 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
175 extern void r300_set_reg_safe(struct radeon_device *rdev);
176 extern void r300_mc_program(struct radeon_device *rdev);
177 extern void r300_mc_init(struct radeon_device *rdev);
178 extern void r300_clock_startup(struct radeon_device *rdev);
179 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
180 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
181 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
182 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
183 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
184 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
189 extern int r420_init(struct radeon_device *rdev);
190 extern void r420_fini(struct radeon_device *rdev);
191 extern int r420_suspend(struct radeon_device *rdev);
192 extern int r420_resume(struct radeon_device *rdev);
193 extern void r420_pm_init_profile(struct radeon_device *rdev);
194 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
195 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
196 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
197 extern void r420_pipes_init(struct radeon_device *rdev);
202 extern int rs400_init(struct radeon_device *rdev);
203 extern void rs400_fini(struct radeon_device *rdev);
204 extern int rs400_suspend(struct radeon_device *rdev);
205 extern int rs400_resume(struct radeon_device *rdev);
206 void rs400_gart_tlb_flush(struct radeon_device *rdev);
207 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
208 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
209 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
210 int rs400_gart_init(struct radeon_device *rdev);
211 int rs400_gart_enable(struct radeon_device *rdev);
212 void rs400_gart_adjust_size(struct radeon_device *rdev);
213 void rs400_gart_disable(struct radeon_device *rdev);
214 void rs400_gart_fini(struct radeon_device *rdev);
215 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
220 extern int rs600_asic_reset(struct radeon_device *rdev);
221 extern int rs600_init(struct radeon_device *rdev);
222 extern void rs600_fini(struct radeon_device *rdev);
223 extern int rs600_suspend(struct radeon_device *rdev);
224 extern int rs600_resume(struct radeon_device *rdev);
225 int rs600_irq_set(struct radeon_device *rdev);
226 int rs600_irq_process(struct radeon_device *rdev);
227 void rs600_irq_disable(struct radeon_device *rdev);
228 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
229 void rs600_gart_tlb_flush(struct radeon_device *rdev);
230 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
231 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
232 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
233 void rs600_bandwidth_update(struct radeon_device *rdev);
234 void rs600_hpd_init(struct radeon_device *rdev);
235 void rs600_hpd_fini(struct radeon_device *rdev);
236 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
237 void rs600_hpd_set_polarity(struct radeon_device *rdev,
238 enum radeon_hpd_id hpd);
239 extern void rs600_pm_misc(struct radeon_device *rdev);
240 extern void rs600_pm_prepare(struct radeon_device *rdev);
241 extern void rs600_pm_finish(struct radeon_device *rdev);
242 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
243 void rs600_set_safe_registers(struct radeon_device *rdev);
244 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
245 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
250 int rs690_init(struct radeon_device *rdev);
251 void rs690_fini(struct radeon_device *rdev);
252 int rs690_resume(struct radeon_device *rdev);
253 int rs690_suspend(struct radeon_device *rdev);
254 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
255 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
256 void rs690_bandwidth_update(struct radeon_device *rdev);
257 void rs690_line_buffer_adjust(struct radeon_device *rdev,
258 struct drm_display_mode *mode1,
259 struct drm_display_mode *mode2);
260 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
265 struct rv515_mc_save {
266 u32 vga_render_control;
268 bool crtc_enabled[2];
271 int rv515_init(struct radeon_device *rdev);
272 void rv515_fini(struct radeon_device *rdev);
273 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
274 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
275 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
276 void rv515_bandwidth_update(struct radeon_device *rdev);
277 int rv515_resume(struct radeon_device *rdev);
278 int rv515_suspend(struct radeon_device *rdev);
279 void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
280 void rv515_vga_render_disable(struct radeon_device *rdev);
281 void rv515_set_safe_registers(struct radeon_device *rdev);
282 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
283 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
284 void rv515_clock_startup(struct radeon_device *rdev);
285 void rv515_debugfs(struct radeon_device *rdev);
286 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
289 * r520,rv530,rv560,rv570,r580
291 int r520_init(struct radeon_device *rdev);
292 int r520_resume(struct radeon_device *rdev);
293 int r520_mc_wait_for_idle(struct radeon_device *rdev);
296 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
298 int r600_init(struct radeon_device *rdev);
299 void r600_fini(struct radeon_device *rdev);
300 int r600_suspend(struct radeon_device *rdev);
301 int r600_resume(struct radeon_device *rdev);
302 void r600_vga_set_state(struct radeon_device *rdev, bool state);
303 int r600_wb_init(struct radeon_device *rdev);
304 void r600_wb_fini(struct radeon_device *rdev);
305 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
306 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
307 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
308 int r600_cs_parse(struct radeon_cs_parser *p);
309 int r600_dma_cs_parse(struct radeon_cs_parser *p);
310 void r600_fence_ring_emit(struct radeon_device *rdev,
311 struct radeon_fence *fence);
312 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
313 struct radeon_ring *cp,
314 struct radeon_semaphore *semaphore,
316 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
317 struct radeon_fence *fence);
318 bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
319 struct radeon_ring *ring,
320 struct radeon_semaphore *semaphore,
322 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
323 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
324 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
325 int r600_asic_reset(struct radeon_device *rdev);
326 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
327 uint32_t tiling_flags, uint32_t pitch,
328 uint32_t offset, uint32_t obj_size);
329 void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
330 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
331 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
332 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
333 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
334 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
335 int r600_copy_cpdma(struct radeon_device *rdev,
336 uint64_t src_offset, uint64_t dst_offset,
337 unsigned num_gpu_pages, struct radeon_fence **fence);
338 int r600_copy_dma(struct radeon_device *rdev,
339 uint64_t src_offset, uint64_t dst_offset,
340 unsigned num_gpu_pages, struct radeon_fence **fence);
341 void r600_hpd_init(struct radeon_device *rdev);
342 void r600_hpd_fini(struct radeon_device *rdev);
343 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
344 void r600_hpd_set_polarity(struct radeon_device *rdev,
345 enum radeon_hpd_id hpd);
346 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
347 extern bool r600_gui_idle(struct radeon_device *rdev);
348 extern void r600_pm_misc(struct radeon_device *rdev);
349 extern void r600_pm_init_profile(struct radeon_device *rdev);
350 extern void rs780_pm_init_profile(struct radeon_device *rdev);
351 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
352 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
353 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
354 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
355 extern int r600_get_pcie_lanes(struct radeon_device *rdev);
356 bool r600_card_posted(struct radeon_device *rdev);
357 void r600_cp_stop(struct radeon_device *rdev);
358 int r600_cp_start(struct radeon_device *rdev);
359 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
360 int r600_cp_resume(struct radeon_device *rdev);
361 void r600_cp_fini(struct radeon_device *rdev);
362 int r600_count_pipe_bits(uint32_t val);
363 int r600_mc_wait_for_idle(struct radeon_device *rdev);
364 int r600_pcie_gart_init(struct radeon_device *rdev);
365 void r600_scratch_init(struct radeon_device *rdev);
366 int r600_init_microcode(struct radeon_device *rdev);
367 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
368 struct radeon_ring *ring);
369 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
370 struct radeon_ring *ring);
371 void r600_gfx_set_wptr(struct radeon_device *rdev,
372 struct radeon_ring *ring);
374 int r600_irq_process(struct radeon_device *rdev);
375 int r600_irq_init(struct radeon_device *rdev);
376 void r600_irq_fini(struct radeon_device *rdev);
377 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
378 int r600_irq_set(struct radeon_device *rdev);
379 void r600_irq_suspend(struct radeon_device *rdev);
380 void r600_disable_interrupts(struct radeon_device *rdev);
381 void r600_rlc_stop(struct radeon_device *rdev);
383 int r600_audio_init(struct radeon_device *rdev);
384 struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
385 void r600_audio_fini(struct radeon_device *rdev);
386 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
387 void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
389 void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
390 void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
391 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
392 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
393 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
394 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
395 int r600_mc_wait_for_idle(struct radeon_device *rdev);
396 u32 r600_get_xclk(struct radeon_device *rdev);
397 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
398 int rv6xx_get_temp(struct radeon_device *rdev);
399 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
400 int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
401 void r600_dpm_post_set_power_state(struct radeon_device *rdev);
402 int r600_dpm_late_enable(struct radeon_device *rdev);
404 uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
405 struct radeon_ring *ring);
406 uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
407 struct radeon_ring *ring);
408 void r600_dma_set_wptr(struct radeon_device *rdev,
409 struct radeon_ring *ring);
411 int rv6xx_dpm_init(struct radeon_device *rdev);
412 int rv6xx_dpm_enable(struct radeon_device *rdev);
413 void rv6xx_dpm_disable(struct radeon_device *rdev);
414 int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
415 void rv6xx_setup_asic(struct radeon_device *rdev);
416 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
417 void rv6xx_dpm_fini(struct radeon_device *rdev);
418 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
419 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
420 void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
421 struct radeon_ps *ps);
422 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
424 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
425 enum radeon_dpm_forced_level level);
427 int rs780_dpm_init(struct radeon_device *rdev);
428 int rs780_dpm_enable(struct radeon_device *rdev);
429 void rs780_dpm_disable(struct radeon_device *rdev);
430 int rs780_dpm_set_power_state(struct radeon_device *rdev);
431 void rs780_dpm_setup_asic(struct radeon_device *rdev);
432 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
433 void rs780_dpm_fini(struct radeon_device *rdev);
434 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
435 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
436 void rs780_dpm_print_power_state(struct radeon_device *rdev,
437 struct radeon_ps *ps);
438 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
440 int rs780_dpm_force_performance_level(struct radeon_device *rdev,
441 enum radeon_dpm_forced_level level);
444 * rv770,rv730,rv710,rv740
446 int rv770_init(struct radeon_device *rdev);
447 void rv770_fini(struct radeon_device *rdev);
448 int rv770_suspend(struct radeon_device *rdev);
449 int rv770_resume(struct radeon_device *rdev);
450 void rv770_pm_misc(struct radeon_device *rdev);
451 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
452 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
453 void r700_cp_stop(struct radeon_device *rdev);
454 void r700_cp_fini(struct radeon_device *rdev);
455 int rv770_copy_dma(struct radeon_device *rdev,
456 uint64_t src_offset, uint64_t dst_offset,
457 unsigned num_gpu_pages,
458 struct radeon_fence **fence);
459 u32 rv770_get_xclk(struct radeon_device *rdev);
460 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
461 int rv770_get_temp(struct radeon_device *rdev);
463 void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
465 int rv770_dpm_init(struct radeon_device *rdev);
466 int rv770_dpm_enable(struct radeon_device *rdev);
467 int rv770_dpm_late_enable(struct radeon_device *rdev);
468 void rv770_dpm_disable(struct radeon_device *rdev);
469 int rv770_dpm_set_power_state(struct radeon_device *rdev);
470 void rv770_dpm_setup_asic(struct radeon_device *rdev);
471 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
472 void rv770_dpm_fini(struct radeon_device *rdev);
473 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
474 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
475 void rv770_dpm_print_power_state(struct radeon_device *rdev,
476 struct radeon_ps *ps);
477 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
479 int rv770_dpm_force_performance_level(struct radeon_device *rdev,
480 enum radeon_dpm_forced_level level);
481 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
486 struct evergreen_mc_save {
487 u32 vga_render_control;
489 bool crtc_enabled[RADEON_MAX_CRTCS];
492 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
493 int evergreen_init(struct radeon_device *rdev);
494 void evergreen_fini(struct radeon_device *rdev);
495 int evergreen_suspend(struct radeon_device *rdev);
496 int evergreen_resume(struct radeon_device *rdev);
497 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
498 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
499 int evergreen_asic_reset(struct radeon_device *rdev);
500 void evergreen_bandwidth_update(struct radeon_device *rdev);
501 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
502 void evergreen_hpd_init(struct radeon_device *rdev);
503 void evergreen_hpd_fini(struct radeon_device *rdev);
504 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
505 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
506 enum radeon_hpd_id hpd);
507 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
508 int evergreen_irq_set(struct radeon_device *rdev);
509 int evergreen_irq_process(struct radeon_device *rdev);
510 extern int evergreen_cs_parse(struct radeon_cs_parser *p);
511 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
512 extern void evergreen_pm_misc(struct radeon_device *rdev);
513 extern void evergreen_pm_prepare(struct radeon_device *rdev);
514 extern void evergreen_pm_finish(struct radeon_device *rdev);
515 extern void sumo_pm_init_profile(struct radeon_device *rdev);
516 extern void btc_pm_init_profile(struct radeon_device *rdev);
517 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
518 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
519 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
520 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
521 void evergreen_disable_interrupt_state(struct radeon_device *rdev);
522 int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
523 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
524 struct radeon_fence *fence);
525 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
526 struct radeon_ib *ib);
527 int evergreen_copy_dma(struct radeon_device *rdev,
528 uint64_t src_offset, uint64_t dst_offset,
529 unsigned num_gpu_pages,
530 struct radeon_fence **fence);
531 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
532 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
533 int evergreen_get_temp(struct radeon_device *rdev);
534 int sumo_get_temp(struct radeon_device *rdev);
535 int tn_get_temp(struct radeon_device *rdev);
536 int cypress_dpm_init(struct radeon_device *rdev);
537 void cypress_dpm_setup_asic(struct radeon_device *rdev);
538 int cypress_dpm_enable(struct radeon_device *rdev);
539 void cypress_dpm_disable(struct radeon_device *rdev);
540 int cypress_dpm_set_power_state(struct radeon_device *rdev);
541 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
542 void cypress_dpm_fini(struct radeon_device *rdev);
543 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
544 int btc_dpm_init(struct radeon_device *rdev);
545 void btc_dpm_setup_asic(struct radeon_device *rdev);
546 int btc_dpm_enable(struct radeon_device *rdev);
547 void btc_dpm_disable(struct radeon_device *rdev);
548 int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
549 int btc_dpm_set_power_state(struct radeon_device *rdev);
550 void btc_dpm_post_set_power_state(struct radeon_device *rdev);
551 void btc_dpm_fini(struct radeon_device *rdev);
552 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
553 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
554 bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
555 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
557 int sumo_dpm_init(struct radeon_device *rdev);
558 int sumo_dpm_enable(struct radeon_device *rdev);
559 int sumo_dpm_late_enable(struct radeon_device *rdev);
560 void sumo_dpm_disable(struct radeon_device *rdev);
561 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
562 int sumo_dpm_set_power_state(struct radeon_device *rdev);
563 void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
564 void sumo_dpm_setup_asic(struct radeon_device *rdev);
565 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
566 void sumo_dpm_fini(struct radeon_device *rdev);
567 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
568 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
569 void sumo_dpm_print_power_state(struct radeon_device *rdev,
570 struct radeon_ps *ps);
571 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
573 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
574 enum radeon_dpm_forced_level level);
579 void cayman_fence_ring_emit(struct radeon_device *rdev,
580 struct radeon_fence *fence);
581 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
582 int cayman_init(struct radeon_device *rdev);
583 void cayman_fini(struct radeon_device *rdev);
584 int cayman_suspend(struct radeon_device *rdev);
585 int cayman_resume(struct radeon_device *rdev);
586 int cayman_asic_reset(struct radeon_device *rdev);
587 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
588 int cayman_vm_init(struct radeon_device *rdev);
589 void cayman_vm_fini(struct radeon_device *rdev);
590 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
591 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
592 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
593 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
594 void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
595 struct radeon_ib *ib);
596 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
597 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
598 void cayman_dma_vm_set_page(struct radeon_device *rdev,
599 struct radeon_ib *ib,
601 uint64_t addr, unsigned count,
602 uint32_t incr, uint32_t flags);
604 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
606 u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
607 struct radeon_ring *ring);
608 u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
609 struct radeon_ring *ring);
610 void cayman_gfx_set_wptr(struct radeon_device *rdev,
611 struct radeon_ring *ring);
612 uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
613 struct radeon_ring *ring);
614 uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
615 struct radeon_ring *ring);
616 void cayman_dma_set_wptr(struct radeon_device *rdev,
617 struct radeon_ring *ring);
619 int ni_dpm_init(struct radeon_device *rdev);
620 void ni_dpm_setup_asic(struct radeon_device *rdev);
621 int ni_dpm_enable(struct radeon_device *rdev);
622 void ni_dpm_disable(struct radeon_device *rdev);
623 int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
624 int ni_dpm_set_power_state(struct radeon_device *rdev);
625 void ni_dpm_post_set_power_state(struct radeon_device *rdev);
626 void ni_dpm_fini(struct radeon_device *rdev);
627 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
628 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
629 void ni_dpm_print_power_state(struct radeon_device *rdev,
630 struct radeon_ps *ps);
631 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
633 int ni_dpm_force_performance_level(struct radeon_device *rdev,
634 enum radeon_dpm_forced_level level);
635 bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
636 int trinity_dpm_init(struct radeon_device *rdev);
637 int trinity_dpm_enable(struct radeon_device *rdev);
638 int trinity_dpm_late_enable(struct radeon_device *rdev);
639 void trinity_dpm_disable(struct radeon_device *rdev);
640 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
641 int trinity_dpm_set_power_state(struct radeon_device *rdev);
642 void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
643 void trinity_dpm_setup_asic(struct radeon_device *rdev);
644 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
645 void trinity_dpm_fini(struct radeon_device *rdev);
646 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
647 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
648 void trinity_dpm_print_power_state(struct radeon_device *rdev,
649 struct radeon_ps *ps);
650 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
652 int trinity_dpm_force_performance_level(struct radeon_device *rdev,
653 enum radeon_dpm_forced_level level);
654 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
657 void dce6_bandwidth_update(struct radeon_device *rdev);
658 int dce6_audio_init(struct radeon_device *rdev);
659 void dce6_audio_fini(struct radeon_device *rdev);
664 void si_fence_ring_emit(struct radeon_device *rdev,
665 struct radeon_fence *fence);
666 void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
667 int si_init(struct radeon_device *rdev);
668 void si_fini(struct radeon_device *rdev);
669 int si_suspend(struct radeon_device *rdev);
670 int si_resume(struct radeon_device *rdev);
671 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
672 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
673 int si_asic_reset(struct radeon_device *rdev);
674 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
675 int si_irq_set(struct radeon_device *rdev);
676 int si_irq_process(struct radeon_device *rdev);
677 int si_vm_init(struct radeon_device *rdev);
678 void si_vm_fini(struct radeon_device *rdev);
679 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
680 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
681 int si_copy_dma(struct radeon_device *rdev,
682 uint64_t src_offset, uint64_t dst_offset,
683 unsigned num_gpu_pages,
684 struct radeon_fence **fence);
685 void si_dma_vm_set_page(struct radeon_device *rdev,
686 struct radeon_ib *ib,
688 uint64_t addr, unsigned count,
689 uint32_t incr, uint32_t flags);
690 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
691 u32 si_get_xclk(struct radeon_device *rdev);
692 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
693 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
694 int si_get_temp(struct radeon_device *rdev);
695 int si_dpm_init(struct radeon_device *rdev);
696 void si_dpm_setup_asic(struct radeon_device *rdev);
697 int si_dpm_enable(struct radeon_device *rdev);
698 int si_dpm_late_enable(struct radeon_device *rdev);
699 void si_dpm_disable(struct radeon_device *rdev);
700 int si_dpm_pre_set_power_state(struct radeon_device *rdev);
701 int si_dpm_set_power_state(struct radeon_device *rdev);
702 void si_dpm_post_set_power_state(struct radeon_device *rdev);
703 void si_dpm_fini(struct radeon_device *rdev);
704 void si_dpm_display_configuration_changed(struct radeon_device *rdev);
705 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
707 int si_dpm_force_performance_level(struct radeon_device *rdev,
708 enum radeon_dpm_forced_level level);
711 void dce8_bandwidth_update(struct radeon_device *rdev);
716 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
717 u32 cik_get_xclk(struct radeon_device *rdev);
718 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
719 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
720 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
721 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
722 void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
723 struct radeon_fence *fence);
724 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
725 struct radeon_ring *ring,
726 struct radeon_semaphore *semaphore,
728 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
729 int cik_copy_dma(struct radeon_device *rdev,
730 uint64_t src_offset, uint64_t dst_offset,
731 unsigned num_gpu_pages,
732 struct radeon_fence **fence);
733 int cik_copy_cpdma(struct radeon_device *rdev,
734 uint64_t src_offset, uint64_t dst_offset,
735 unsigned num_gpu_pages,
736 struct radeon_fence **fence);
737 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
738 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
739 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
740 void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
741 struct radeon_fence *fence);
742 void cik_fence_compute_ring_emit(struct radeon_device *rdev,
743 struct radeon_fence *fence);
744 bool cik_semaphore_ring_emit(struct radeon_device *rdev,
745 struct radeon_ring *cp,
746 struct radeon_semaphore *semaphore,
748 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
749 int cik_init(struct radeon_device *rdev);
750 void cik_fini(struct radeon_device *rdev);
751 int cik_suspend(struct radeon_device *rdev);
752 int cik_resume(struct radeon_device *rdev);
753 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
754 int cik_asic_reset(struct radeon_device *rdev);
755 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
756 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
757 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
758 int cik_irq_set(struct radeon_device *rdev);
759 int cik_irq_process(struct radeon_device *rdev);
760 int cik_vm_init(struct radeon_device *rdev);
761 void cik_vm_fini(struct radeon_device *rdev);
762 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
763 void cik_sdma_vm_set_page(struct radeon_device *rdev,
764 struct radeon_ib *ib,
766 uint64_t addr, unsigned count,
767 uint32_t incr, uint32_t flags);
768 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
769 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
770 u32 cik_gfx_get_rptr(struct radeon_device *rdev,
771 struct radeon_ring *ring);
772 u32 cik_gfx_get_wptr(struct radeon_device *rdev,
773 struct radeon_ring *ring);
774 void cik_gfx_set_wptr(struct radeon_device *rdev,
775 struct radeon_ring *ring);
776 u32 cik_compute_get_rptr(struct radeon_device *rdev,
777 struct radeon_ring *ring);
778 u32 cik_compute_get_wptr(struct radeon_device *rdev,
779 struct radeon_ring *ring);
780 void cik_compute_set_wptr(struct radeon_device *rdev,
781 struct radeon_ring *ring);
782 u32 cik_sdma_get_rptr(struct radeon_device *rdev,
783 struct radeon_ring *ring);
784 u32 cik_sdma_get_wptr(struct radeon_device *rdev,
785 struct radeon_ring *ring);
786 void cik_sdma_set_wptr(struct radeon_device *rdev,
787 struct radeon_ring *ring);
788 int ci_get_temp(struct radeon_device *rdev);
789 int kv_get_temp(struct radeon_device *rdev);
791 int ci_dpm_init(struct radeon_device *rdev);
792 int ci_dpm_enable(struct radeon_device *rdev);
793 int ci_dpm_late_enable(struct radeon_device *rdev);
794 void ci_dpm_disable(struct radeon_device *rdev);
795 int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
796 int ci_dpm_set_power_state(struct radeon_device *rdev);
797 void ci_dpm_post_set_power_state(struct radeon_device *rdev);
798 void ci_dpm_setup_asic(struct radeon_device *rdev);
799 void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
800 void ci_dpm_fini(struct radeon_device *rdev);
801 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
802 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
803 void ci_dpm_print_power_state(struct radeon_device *rdev,
804 struct radeon_ps *ps);
805 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
807 int ci_dpm_force_performance_level(struct radeon_device *rdev,
808 enum radeon_dpm_forced_level level);
809 bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
810 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
812 int kv_dpm_init(struct radeon_device *rdev);
813 int kv_dpm_enable(struct radeon_device *rdev);
814 int kv_dpm_late_enable(struct radeon_device *rdev);
815 void kv_dpm_disable(struct radeon_device *rdev);
816 int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
817 int kv_dpm_set_power_state(struct radeon_device *rdev);
818 void kv_dpm_post_set_power_state(struct radeon_device *rdev);
819 void kv_dpm_setup_asic(struct radeon_device *rdev);
820 void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
821 void kv_dpm_fini(struct radeon_device *rdev);
822 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
823 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
824 void kv_dpm_print_power_state(struct radeon_device *rdev,
825 struct radeon_ps *ps);
826 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
828 int kv_dpm_force_performance_level(struct radeon_device *rdev,
829 enum radeon_dpm_forced_level level);
830 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
831 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
834 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
835 struct radeon_ring *ring);
836 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
837 struct radeon_ring *ring);
838 void uvd_v1_0_set_wptr(struct radeon_device *rdev,
839 struct radeon_ring *ring);
841 int uvd_v1_0_init(struct radeon_device *rdev);
842 void uvd_v1_0_fini(struct radeon_device *rdev);
843 int uvd_v1_0_start(struct radeon_device *rdev);
844 void uvd_v1_0_stop(struct radeon_device *rdev);
846 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
847 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
848 bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
849 struct radeon_ring *ring,
850 struct radeon_semaphore *semaphore,
852 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
855 int uvd_v2_2_resume(struct radeon_device *rdev);
856 void uvd_v2_2_fence_emit(struct radeon_device *rdev,
857 struct radeon_fence *fence);
860 bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
861 struct radeon_ring *ring,
862 struct radeon_semaphore *semaphore,
866 int uvd_v4_2_resume(struct radeon_device *rdev);
869 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
870 struct radeon_ring *ring);
871 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
872 struct radeon_ring *ring);
873 void vce_v1_0_set_wptr(struct radeon_device *rdev,
874 struct radeon_ring *ring);
875 int vce_v1_0_init(struct radeon_device *rdev);
876 int vce_v1_0_start(struct radeon_device *rdev);
879 int vce_v2_0_resume(struct radeon_device *rdev);