drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  66                                                                uint8_t id)
  67 {
  68         struct atom_context *ctx = rdev->mode_info.atom_context;
  69         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  70         struct radeon_i2c_bus_rec i2c;
  71         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  72         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  73         uint16_t data_offset, size;
  74         int i, num_indices;
  75
  76         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  77         i2c.valid = false;
  78
  79         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  80                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  83                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  84
  85                 for (i = 0; i < num_indices; i++) {
  86                         gpio = &i2c_info->asGPIO_Info[i];
  87
  88                         /* some evergreen boards have bad data for this entry */
  89                         if (ASIC_IS_DCE4(rdev)) {
  90                                 if ((i == 7) &&
  91                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
  92                                     (gpio->sucI2cId.ucAccess == 0)) {
  93                                         gpio->sucI2cId.ucAccess = 0x97;
  94                                         gpio->ucDataMaskShift = 8;
  95                                         gpio->ucDataEnShift = 8;
  96                                         gpio->ucDataY_Shift = 8;
  97                                         gpio->ucDataA_Shift = 8;
  98                                 }
  99                         }
 100
 101                         if (gpio->sucI2cId.ucAccess == id) {
 102                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 103                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 104                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 105                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 106                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 107                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 108                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 109                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 110                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 111                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 112                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 113                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 114                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 115                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 116                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 117                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 118
 119                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 120                                         i2c.hw_capable = true;
 121                                 else
 122                                         i2c.hw_capable = false;
 123
 124                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 125                                         i2c.mm_i2c = true;
 126                                 else
 127                                         i2c.mm_i2c = false;
 128
 129                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 130
 131                                 if (i2c.mask_clk_reg)
 132                                         i2c.valid = true;
 133                                 break;
 134                         }
 135                 }
 136         }
 137
 138         return i2c;
 139 }
 140
 141 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 142 {
 143         struct atom_context *ctx = rdev->mode_info.atom_context;
 144         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 145         struct radeon_i2c_bus_rec i2c;
 146         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 147         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 148         uint16_t data_offset, size;
 149         int i, num_indices;
 150         char stmp[32];
 151
 152         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 153
 154         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 155                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 156
 157                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 158                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 159
 160                 for (i = 0; i < num_indices; i++) {
 161                         gpio = &i2c_info->asGPIO_Info[i];
 162                         i2c.valid = false;
 163
 164                         /* some evergreen boards have bad data for this entry */
 165                         if (ASIC_IS_DCE4(rdev)) {
 166                                 if ((i == 7) &&
 167                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
 168                                     (gpio->sucI2cId.ucAccess == 0)) {
 169                                         gpio->sucI2cId.ucAccess = 0x97;
 170                                         gpio->ucDataMaskShift = 8;
 171                                         gpio->ucDataEnShift = 8;
 172                                         gpio->ucDataY_Shift = 8;
 173                                         gpio->ucDataA_Shift = 8;
 174                                 }
 175                         }
 176
 177                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 178                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 179                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 180                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 181                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 182                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 183                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 184                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 185                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 186                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 187                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 188                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 189                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 190                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 191                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 192                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 193
 194                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 195                                 i2c.hw_capable = true;
 196                         else
 197                                 i2c.hw_capable = false;
 198
 199                         if (gpio->sucI2cId.ucAccess == 0xa0)
 200                                 i2c.mm_i2c = true;
 201                         else
 202                                 i2c.mm_i2c = false;
 203
 204                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 205
 206                         if (i2c.mask_clk_reg) {
 207                                 i2c.valid = true;
 208                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 209                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 210                         }
 211                 }
 212         }
 213 }
 214
 215 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 216                                                         u8 id)
 217 {
 218         struct atom_context *ctx = rdev->mode_info.atom_context;
 219         struct radeon_gpio_rec gpio;
 220         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 221         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 222         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 223         u16 data_offset, size;
 224         int i, num_indices;
 225
 226         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 227         gpio.valid = false;
 228
 229         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 230                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 231
 232                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 233                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 234
 235                 for (i = 0; i < num_indices; i++) {
 236                         pin = &gpio_info->asGPIO_Pin[i];
 237                         if (id == pin->ucGPIO_ID) {
 238                                 gpio.id = pin->ucGPIO_ID;
 239                                 gpio.reg = pin->usGpioPin_AIndex * 4;
 240                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 241                                 gpio.valid = true;
 242                                 break;
 243                         }
 244                 }
 245         }
 246
 247         return gpio;
 248 }
 249
 250 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 251                                                             struct radeon_gpio_rec *gpio)
 252 {
 253         struct radeon_hpd hpd;
 254         u32 reg;
 255
 256         memset(&hpd, 0, sizeof(struct radeon_hpd));
 257
 258         if (ASIC_IS_DCE4(rdev))
 259                 reg = EVERGREEN_DC_GPIO_HPD_A;
 260         else
 261                 reg = AVIVO_DC_GPIO_HPD_A;
 262
 263         hpd.gpio = *gpio;
 264         if (gpio->reg == reg) {
 265                 switch(gpio->mask) {
 266                 case (1 << 0):
 267                         hpd.hpd = RADEON_HPD_1;
 268                         break;
 269                 case (1 << 8):
 270                         hpd.hpd = RADEON_HPD_2;
 271                         break;
 272                 case (1 << 16):
 273                         hpd.hpd = RADEON_HPD_3;
 274                         break;
 275                 case (1 << 24):
 276                         hpd.hpd = RADEON_HPD_4;
 277                         break;
 278                 case (1 << 26):
 279                         hpd.hpd = RADEON_HPD_5;
 280                         break;
 281                 case (1 << 28):
 282                         hpd.hpd = RADEON_HPD_6;
 283                         break;
 284                 default:
 285                         hpd.hpd = RADEON_HPD_NONE;
 286                         break;
 287                 }
 288         } else
 289                 hpd.hpd = RADEON_HPD_NONE;
 290         return hpd;
 291 }
 292
 293 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 294                                      uint32_t supported_device,
 295                                      int *connector_type,
 296                                      struct radeon_i2c_bus_rec *i2c_bus,
 297                                      uint16_t *line_mux,
 298                                      struct radeon_hpd *hpd)
 299 {
 300         struct radeon_device *rdev = dev->dev_private;
 301
 302         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 303         if ((dev->pdev->device == 0x791e) &&
 304             (dev->pdev->subsystem_vendor == 0x1043) &&
 305             (dev->pdev->subsystem_device == 0x826d)) {
 306                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 307                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 308                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 309         }
 310
 311         /* Asrock RS600 board lists the DVI port as HDMI */
 312         if ((dev->pdev->device == 0x7941) &&
 313             (dev->pdev->subsystem_vendor == 0x1849) &&
 314             (dev->pdev->subsystem_device == 0x7941)) {
 315                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 316                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 317                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 318         }
 319
 320         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 321         if ((dev->pdev->device == 0x796e) &&
 322             (dev->pdev->subsystem_vendor == 0x1462) &&
 323             (dev->pdev->subsystem_device == 0x7302)) {
 324                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 325                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 326                         return false;
 327         }
 328
 329         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 330         if ((dev->pdev->device == 0x7941) &&
 331             (dev->pdev->subsystem_vendor == 0x147b) &&
 332             (dev->pdev->subsystem_device == 0x2412)) {
 333                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 334                         return false;
 335         }
 336
 337         /* Falcon NW laptop lists vga ddc line for LVDS */
 338         if ((dev->pdev->device == 0x5653) &&
 339             (dev->pdev->subsystem_vendor == 0x1462) &&
 340             (dev->pdev->subsystem_device == 0x0291)) {
 341                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 342                         i2c_bus->valid = false;
 343                         *line_mux = 53;
 344                 }
 345         }
 346
 347         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 348         if ((dev->pdev->device == 0x7146) &&
 349             (dev->pdev->subsystem_vendor == 0x17af) &&
 350             (dev->pdev->subsystem_device == 0x2058)) {
 351                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 352                         return false;
 353         }
 354
 355         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 356         if ((dev->pdev->device == 0x7142) &&
 357             (dev->pdev->subsystem_vendor == 0x1458) &&
 358             (dev->pdev->subsystem_device == 0x2134)) {
 359                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 360                         return false;
 361         }
 362
 363
 364         /* Funky macbooks */
 365         if ((dev->pdev->device == 0x71C5) &&
 366             (dev->pdev->subsystem_vendor == 0x106b) &&
 367             (dev->pdev->subsystem_device == 0x0080)) {
 368                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 369                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 370                         return false;
 371                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 372                         *line_mux = 0x90;
 373         }
 374
 375         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 376         if ((dev->pdev->device == 0x9598) &&
 377             (dev->pdev->subsystem_vendor == 0x1043) &&
 378             (dev->pdev->subsystem_device == 0x01da)) {
 379                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 380                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 381                 }
 382         }
 383
 384         /* ASUS HD 3600 board lists the DVI port as HDMI */
 385         if ((dev->pdev->device == 0x9598) &&
 386             (dev->pdev->subsystem_vendor == 0x1043) &&
 387             (dev->pdev->subsystem_device == 0x01e4)) {
 388                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 389                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 390                 }
 391         }
 392
 393         /* ASUS HD 3450 board lists the DVI port as HDMI */
 394         if ((dev->pdev->device == 0x95C5) &&
 395             (dev->pdev->subsystem_vendor == 0x1043) &&
 396             (dev->pdev->subsystem_device == 0x01e2)) {
 397                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 398                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 399                 }
 400         }
 401
 402         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 403          * HDMI + VGA reporting as HDMI
 404          */
 405         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 406                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 407                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 408                         *line_mux = 0;
 409                 }
 410         }
 411
 412         /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
 413         if ((dev->pdev->device == 0x95c4) &&
 414             (dev->pdev->subsystem_vendor == 0x1025) &&
 415             (dev->pdev->subsystem_device == 0x013c)) {
 416                 struct radeon_gpio_rec gpio;
 417
 418                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 419                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 420                         gpio = radeon_lookup_gpio(rdev, 6);
 421                         *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 422                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 423                 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 424                            (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 425                         gpio = radeon_lookup_gpio(rdev, 7);
 426                         *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 427                 }
 428         }
 429
 430         /* XFX Pine Group device rv730 reports no VGA DDC lines
 431          * even though they are wired up to record 0x93
 432          */
 433         if ((dev->pdev->device == 0x9498) &&
 434             (dev->pdev->subsystem_vendor == 0x1682) &&
 435             (dev->pdev->subsystem_device == 0x2452)) {
 436                 struct radeon_device *rdev = dev->dev_private;
 437                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 438         }
 439         return true;
 440 }
 441
 442 const int supported_devices_connector_convert[] = {
 443         DRM_MODE_CONNECTOR_Unknown,
 444         DRM_MODE_CONNECTOR_VGA,
 445         DRM_MODE_CONNECTOR_DVII,
 446         DRM_MODE_CONNECTOR_DVID,
 447         DRM_MODE_CONNECTOR_DVIA,
 448         DRM_MODE_CONNECTOR_SVIDEO,
 449         DRM_MODE_CONNECTOR_Composite,
 450         DRM_MODE_CONNECTOR_LVDS,
 451         DRM_MODE_CONNECTOR_Unknown,
 452         DRM_MODE_CONNECTOR_Unknown,
 453         DRM_MODE_CONNECTOR_HDMIA,
 454         DRM_MODE_CONNECTOR_HDMIB,
 455         DRM_MODE_CONNECTOR_Unknown,
 456         DRM_MODE_CONNECTOR_Unknown,
 457         DRM_MODE_CONNECTOR_9PinDIN,
 458         DRM_MODE_CONNECTOR_DisplayPort
 459 };
 460
 461 const uint16_t supported_devices_connector_object_id_convert[] = {
 462         CONNECTOR_OBJECT_ID_NONE,
 463         CONNECTOR_OBJECT_ID_VGA,
 464         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 465         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 466         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 467         CONNECTOR_OBJECT_ID_COMPOSITE,
 468         CONNECTOR_OBJECT_ID_SVIDEO,
 469         CONNECTOR_OBJECT_ID_LVDS,
 470         CONNECTOR_OBJECT_ID_9PIN_DIN,
 471         CONNECTOR_OBJECT_ID_9PIN_DIN,
 472         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 473         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 474         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 475         CONNECTOR_OBJECT_ID_SVIDEO
 476 };
 477
 478 const int object_connector_convert[] = {
 479         DRM_MODE_CONNECTOR_Unknown,
 480         DRM_MODE_CONNECTOR_DVII,
 481         DRM_MODE_CONNECTOR_DVII,
 482         DRM_MODE_CONNECTOR_DVID,
 483         DRM_MODE_CONNECTOR_DVID,
 484         DRM_MODE_CONNECTOR_VGA,
 485         DRM_MODE_CONNECTOR_Composite,
 486         DRM_MODE_CONNECTOR_SVIDEO,
 487         DRM_MODE_CONNECTOR_Unknown,
 488         DRM_MODE_CONNECTOR_Unknown,
 489         DRM_MODE_CONNECTOR_9PinDIN,
 490         DRM_MODE_CONNECTOR_Unknown,
 491         DRM_MODE_CONNECTOR_HDMIA,
 492         DRM_MODE_CONNECTOR_HDMIB,
 493         DRM_MODE_CONNECTOR_LVDS,
 494         DRM_MODE_CONNECTOR_9PinDIN,
 495         DRM_MODE_CONNECTOR_Unknown,
 496         DRM_MODE_CONNECTOR_Unknown,
 497         DRM_MODE_CONNECTOR_Unknown,
 498         DRM_MODE_CONNECTOR_DisplayPort,
 499         DRM_MODE_CONNECTOR_eDP,
 500         DRM_MODE_CONNECTOR_Unknown
 501 };
 502
 503 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 504 {
 505         struct radeon_device *rdev = dev->dev_private;
 506         struct radeon_mode_info *mode_info = &rdev->mode_info;
 507         struct atom_context *ctx = mode_info->atom_context;
 508         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 509         u16 size, data_offset;
 510         u8 frev, crev;
 511         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 512         ATOM_OBJECT_TABLE *router_obj;
 513         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 514         ATOM_OBJECT_HEADER *obj_header;
 515         int i, j, k, path_size, device_support;
 516         int connector_type;
 517         u16 igp_lane_info, conn_id, connector_object_id;
 518         struct radeon_i2c_bus_rec ddc_bus;
 519         struct radeon_router router;
 520         struct radeon_gpio_rec gpio;
 521         struct radeon_hpd hpd;
 522
 523         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 524                 return false;
 525
 526         if (crev < 2)
 527                 return false;
 528
 529         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 530         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 531             (ctx->bios + data_offset +
 532              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 533         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 534             (ctx->bios + data_offset +
 535              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 536         router_obj = (ATOM_OBJECT_TABLE *)
 537                 (ctx->bios + data_offset +
 538                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 539         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 540
 541         path_size = 0;
 542         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 543                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 544                 ATOM_DISPLAY_OBJECT_PATH *path;
 545                 addr += path_size;
 546                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 547                 path_size += le16_to_cpu(path->usSize);
 548
 549                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 550                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 551
 552                         con_obj_id =
 553                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 554                             >> OBJECT_ID_SHIFT;
 555                         con_obj_num =
 556                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 557                             >> ENUM_ID_SHIFT;
 558                         con_obj_type =
 559                             (le16_to_cpu(path->usConnObjectId) &
 560                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 561
 562                         /* TODO CV support */
 563                         if (le16_to_cpu(path->usDeviceTag) ==
 564                                 ATOM_DEVICE_CV_SUPPORT)
 565                                 continue;
 566
 567                         /* IGP chips */
 568                         if ((rdev->flags & RADEON_IS_IGP) &&
 569                             (con_obj_id ==
 570                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 571                                 uint16_t igp_offset = 0;
 572                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 573
 574                                 index =
 575                                     GetIndexIntoMasterTable(DATA,
 576                                                             IntegratedSystemInfo);
 577
 578                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 579                                                            &crev, &igp_offset)) {
 580
 581                                         if (crev >= 2) {
 582                                                 igp_obj =
 583                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 584                                                          *) (ctx->bios + igp_offset);
 585
 586                                                 if (igp_obj) {
 587                                                         uint32_t slot_config, ct;
 588
 589                                                         if (con_obj_num == 1)
 590                                                                 slot_config =
 591                                                                         igp_obj->
 592                                                                         ulDDISlot1Config;
 593                                                         else
 594                                                                 slot_config =
 595                                                                         igp_obj->
 596                                                                         ulDDISlot2Config;
 597
 598                                                         ct = (slot_config >> 16) & 0xff;
 599                                                         connector_type =
 600                                                                 object_connector_convert
 601                                                                 [ct];
 602                                                         connector_object_id = ct;
 603                                                         igp_lane_info =
 604                                                                 slot_config & 0xffff;
 605                                                 } else
 606                                                         continue;
 607                                         } else
 608                                                 continue;
 609                                 } else {
 610                                         igp_lane_info = 0;
 611                                         connector_type =
 612                                                 object_connector_convert[con_obj_id];
 613                                         connector_object_id = con_obj_id;
 614                                 }
 615                         } else {
 616                                 igp_lane_info = 0;
 617                                 connector_type =
 618                                     object_connector_convert[con_obj_id];
 619                                 connector_object_id = con_obj_id;
 620                         }
 621
 622                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 623                                 continue;
 624
 625                         router.ddc_valid = false;
 626                         router.cd_valid = false;
 627                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 628                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 629
 630                                 grph_obj_id =
 631                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 632                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 633                                 grph_obj_num =
 634                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 635                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 636                                 grph_obj_type =
 637                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 638                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 639
 640                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 641                                         u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
 642
 643                                         radeon_add_atom_encoder(dev,
 644                                                                 encoder_obj,
 645                                                                 le16_to_cpu
 646                                                                 (path->
 647                                                                  usDeviceTag));
 648
 649                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 650                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 651                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 652                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 653                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 654                                                                 (ctx->bios + data_offset +
 655                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 656                                                         ATOM_I2C_RECORD *i2c_record;
 657                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 658                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 659                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 660                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 661                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 662                                                                 (ctx->bios + data_offset +
 663                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 664                                                         int enum_id;
 665
 666                                                         router.router_id = router_obj_id;
 667                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 668                                                              enum_id++) {
 669                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 670                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 671                                                                         break;
 672                                                         }
 673
 674                                                         while (record->ucRecordType > 0 &&
 675                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 676                                                                 switch (record->ucRecordType) {
 677                                                                 case ATOM_I2C_RECORD_TYPE:
 678                                                                         i2c_record =
 679                                                                                 (ATOM_I2C_RECORD *)
 680                                                                                 record;
 681                                                                         i2c_config =
 682                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 683                                                                                 &i2c_record->sucI2cId;
 684                                                                         router.i2c_info =
 685                                                                                 radeon_lookup_i2c_gpio(rdev,
 686                                                                                                        i2c_config->
 687                                                                                                        ucAccess);
 688                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 689                                                                         break;
 690                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 691                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 692                                                                                 record;
 693                                                                         router.ddc_valid = true;
 694                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 695                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 696                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 697                                                                         break;
 698                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 699                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 700                                                                                 record;
 701                                                                         router.cd_valid = true;
 702                                                                         router.cd_mux_type = cd_path->ucMuxType;
 703                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 704                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 705                                                                         break;
 706                                                                 }
 707                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 708                                                                         ((char *)record + record->ucRecordSize);
 709                                                         }
 710                                                 }
 711                                         }
 712                                 }
 713                         }
 714
 715                         /* look up gpio for ddc, hpd */
 716                         ddc_bus.valid = false;
 717                         hpd.hpd = RADEON_HPD_NONE;
 718                         if ((le16_to_cpu(path->usDeviceTag) &
 719                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 720                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 721                                         if (le16_to_cpu(path->usConnObjectId) ==
 722                                             le16_to_cpu(con_obj->asObjects[j].
 723                                                         usObjectID)) {
 724                                                 ATOM_COMMON_RECORD_HEADER
 725                                                     *record =
 726                                                     (ATOM_COMMON_RECORD_HEADER
 727                                                      *)
 728                                                     (ctx->bios + data_offset +
 729                                                      le16_to_cpu(con_obj->
 730                                                                  asObjects[j].
 731                                                                  usRecordOffset));
 732                                                 ATOM_I2C_RECORD *i2c_record;
 733                                                 ATOM_HPD_INT_RECORD *hpd_record;
 734                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 735
 736                                                 while (record->ucRecordType > 0
 737                                                        && record->
 738                                                        ucRecordType <=
 739                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 740                                                         switch (record->ucRecordType) {
 741                                                         case ATOM_I2C_RECORD_TYPE:
 742                                                                 i2c_record =
 743                                                                     (ATOM_I2C_RECORD *)
 744                                                                         record;
 745                                                                 i2c_config =
 746                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 747                                                                         &i2c_record->sucI2cId;
 748                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 749                                                                                                  i2c_config->
 750                                                                                                  ucAccess);
 751                                                                 break;
 752                                                         case ATOM_HPD_INT_RECORD_TYPE:
 753                                                                 hpd_record =
 754                                                                         (ATOM_HPD_INT_RECORD *)
 755                                                                         record;
 756                                                                 gpio = radeon_lookup_gpio(rdev,
 757                                                                                           hpd_record->ucHPDIntGPIOID);
 758                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 759                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 760                                                                 break;
 761                                                         }
 762                                                         record =
 763                                                             (ATOM_COMMON_RECORD_HEADER
 764                                                              *) ((char *)record
 765                                                                  +
 766                                                                  record->
 767                                                                  ucRecordSize);
 768                                                 }
 769                                                 break;
 770                                         }
 771                                 }
 772                         }
 773
 774                         /* needed for aux chan transactions */
 775                         ddc_bus.hpd = hpd.hpd;
 776
 777                         conn_id = le16_to_cpu(path->usConnObjectId);
 778
 779                         if (!radeon_atom_apply_quirks
 780                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 781                              &ddc_bus, &conn_id, &hpd))
 782                                 continue;
 783
 784                         radeon_add_atom_connector(dev,
 785                                                   conn_id,
 786                                                   le16_to_cpu(path->
 787                                                               usDeviceTag),
 788                                                   connector_type, &ddc_bus,
 789                                                   igp_lane_info,
 790                                                   connector_object_id,
 791                                                   &hpd,
 792                                                   &router);
 793
 794                 }
 795         }
 796
 797         radeon_link_encoder_connector(dev);
 798
 799         return true;
 800 }
 801
 802 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 803                                                  int connector_type,
 804                                                  uint16_t devices)
 805 {
 806         struct radeon_device *rdev = dev->dev_private;
 807
 808         if (rdev->flags & RADEON_IS_IGP) {
 809                 return supported_devices_connector_object_id_convert
 810                         [connector_type];
 811         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 812                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 813                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 814                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 815                 struct atom_context *ctx = mode_info->atom_context;
 816                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 817                 uint16_t size, data_offset;
 818                 uint8_t frev, crev;
 819                 ATOM_XTMDS_INFO *xtmds;
 820
 821                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 822                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 823
 824                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 825                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 826                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 827                                 else
 828                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 829                         } else {
 830                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 831                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 832                                 else
 833                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 834                         }
 835                 } else
 836                         return supported_devices_connector_object_id_convert
 837                                 [connector_type];
 838         } else {
 839                 return supported_devices_connector_object_id_convert
 840                         [connector_type];
 841         }
 842 }
 843
 844 struct bios_connector {
 845         bool valid;
 846         uint16_t line_mux;
 847         uint16_t devices;
 848         int connector_type;
 849         struct radeon_i2c_bus_rec ddc_bus;
 850         struct radeon_hpd hpd;
 851 };
 852
 853 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 854                                                                  drm_device
 855                                                                  *dev)
 856 {
 857         struct radeon_device *rdev = dev->dev_private;
 858         struct radeon_mode_info *mode_info = &rdev->mode_info;
 859         struct atom_context *ctx = mode_info->atom_context;
 860         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 861         uint16_t size, data_offset;
 862         uint8_t frev, crev;
 863         uint16_t device_support;
 864         uint8_t dac;
 865         union atom_supported_devices *supported_devices;
 866         int i, j, max_device;
 867         struct bios_connector *bios_connectors;
 868         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 869         struct radeon_router router;
 870
 871         router.ddc_valid = false;
 872         router.cd_valid = false;
 873
 874         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 875         if (!bios_connectors)
 876                 return false;
 877
 878         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 879                                     &data_offset)) {
 880                 kfree(bios_connectors);
 881                 return false;
 882         }
 883
 884         supported_devices =
 885             (union atom_supported_devices *)(ctx->bios + data_offset);
 886
 887         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 888
 889         if (frev > 1)
 890                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 891         else
 892                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 893
 894         for (i = 0; i < max_device; i++) {
 895                 ATOM_CONNECTOR_INFO_I2C ci =
 896                     supported_devices->info.asConnInfo[i];
 897
 898                 bios_connectors[i].valid = false;
 899
 900                 if (!(device_support & (1 << i))) {
 901                         continue;
 902                 }
 903
 904                 if (i == ATOM_DEVICE_CV_INDEX) {
 905                         DRM_DEBUG_KMS("Skipping Component Video\n");
 906                         continue;
 907                 }
 908
 909                 bios_connectors[i].connector_type =
 910                     supported_devices_connector_convert[ci.sucConnectorInfo.
 911                                                         sbfAccess.
 912                                                         bfConnectorType];
 913
 914                 if (bios_connectors[i].connector_type ==
 915                     DRM_MODE_CONNECTOR_Unknown)
 916                         continue;
 917
 918                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 919
 920                 bios_connectors[i].line_mux =
 921                         ci.sucI2cId.ucAccess;
 922
 923                 /* give tv unique connector ids */
 924                 if (i == ATOM_DEVICE_TV1_INDEX) {
 925                         bios_connectors[i].ddc_bus.valid = false;
 926                         bios_connectors[i].line_mux = 50;
 927                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 928                         bios_connectors[i].ddc_bus.valid = false;
 929                         bios_connectors[i].line_mux = 51;
 930                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 931                         bios_connectors[i].ddc_bus.valid = false;
 932                         bios_connectors[i].line_mux = 52;
 933                 } else
 934                         bios_connectors[i].ddc_bus =
 935                             radeon_lookup_i2c_gpio(rdev,
 936                                                    bios_connectors[i].line_mux);
 937
 938                 if ((crev > 1) && (frev > 1)) {
 939                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 940                         switch (isb) {
 941                         case 0x4:
 942                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 943                                 break;
 944                         case 0xa:
 945                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 946                                 break;
 947                         default:
 948                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 949                                 break;
 950                         }
 951                 } else {
 952                         if (i == ATOM_DEVICE_DFP1_INDEX)
 953                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 954                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 955                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 956                         else
 957                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 958                 }
 959
 960                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 961                  * shared with a DVI port, we'll pick up the DVI connector when we
 962                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 963                  */
 964                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 965                         bios_connectors[i].connector_type =
 966                             DRM_MODE_CONNECTOR_VGA;
 967
 968                 if (!radeon_atom_apply_quirks
 969                     (dev, (1 << i), &bios_connectors[i].connector_type,
 970                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 971                      &bios_connectors[i].hpd))
 972                         continue;
 973
 974                 bios_connectors[i].valid = true;
 975                 bios_connectors[i].devices = (1 << i);
 976
 977                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 978                         radeon_add_atom_encoder(dev,
 979                                                 radeon_get_encoder_enum(dev,
 980                                                                       (1 << i),
 981                                                                       dac),
 982                                                 (1 << i));
 983                 else
 984                         radeon_add_legacy_encoder(dev,
 985                                                   radeon_get_encoder_enum(dev,
 986                                                                         (1 << i),
 987                                                                         dac),
 988                                                   (1 << i));
 989         }
 990
 991         /* combine shared connectors */
 992         for (i = 0; i < max_device; i++) {
 993                 if (bios_connectors[i].valid) {
 994                         for (j = 0; j < max_device; j++) {
 995                                 if (bios_connectors[j].valid && (i != j)) {
 996                                         if (bios_connectors[i].line_mux ==
 997                                             bios_connectors[j].line_mux) {
 998                                                 /* make sure not to combine LVDS */
 999                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1000                                                         bios_connectors[i].line_mux = 53;
1001                                                         bios_connectors[i].ddc_bus.valid = false;
1002                                                         continue;
1003                                                 }
1004                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1005                                                         bios_connectors[j].line_mux = 53;
1006                                                         bios_connectors[j].ddc_bus.valid = false;
1007                                                         continue;
1008                                                 }
1009                                                 /* combine analog and digital for DVI-I */
1010                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1011                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1012                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1013                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1014                                                         bios_connectors[i].devices |=
1015                                                                 bios_connectors[j].devices;
1016                                                         bios_connectors[i].connector_type =
1017                                                                 DRM_MODE_CONNECTOR_DVII;
1018                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1019                                                                 bios_connectors[i].hpd =
1020                                                                         bios_connectors[j].hpd;
1021                                                         bios_connectors[j].valid = false;
1022                                                 }
1023                                         }
1024                                 }
1025                         }
1026                 }
1027         }
1028
1029         /* add the connectors */
1030         for (i = 0; i < max_device; i++) {
1031                 if (bios_connectors[i].valid) {
1032                         uint16_t connector_object_id =
1033                                 atombios_get_connector_object_id(dev,
1034                                                       bios_connectors[i].connector_type,
1035                                                       bios_connectors[i].devices);
1036                         radeon_add_atom_connector(dev,
1037                                                   bios_connectors[i].line_mux,
1038                                                   bios_connectors[i].devices,
1039                                                   bios_connectors[i].
1040                                                   connector_type,
1041                                                   &bios_connectors[i].ddc_bus,
1042                                                   0,
1043                                                   connector_object_id,
1044                                                   &bios_connectors[i].hpd,
1045                                                   &router);
1046                 }
1047         }
1048
1049         radeon_link_encoder_connector(dev);
1050
1051         kfree(bios_connectors);
1052         return true;
1053 }
1054
1055 union firmware_info {
1056         ATOM_FIRMWARE_INFO info;
1057         ATOM_FIRMWARE_INFO_V1_2 info_12;
1058         ATOM_FIRMWARE_INFO_V1_3 info_13;
1059         ATOM_FIRMWARE_INFO_V1_4 info_14;
1060         ATOM_FIRMWARE_INFO_V2_1 info_21;
1061 };
1062
1063 bool radeon_atom_get_clock_info(struct drm_device *dev)
1064 {
1065         struct radeon_device *rdev = dev->dev_private;
1066         struct radeon_mode_info *mode_info = &rdev->mode_info;
1067         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1068         union firmware_info *firmware_info;
1069         uint8_t frev, crev;
1070         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1071         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1072         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1073         struct radeon_pll *spll = &rdev->clock.spll;
1074         struct radeon_pll *mpll = &rdev->clock.mpll;
1075         uint16_t data_offset;
1076
1077         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1078                                    &frev, &crev, &data_offset)) {
1079                 firmware_info =
1080                         (union firmware_info *)(mode_info->atom_context->bios +
1081                                                 data_offset);
1082                 /* pixel clocks */
1083                 p1pll->reference_freq =
1084                     le16_to_cpu(firmware_info->info.usReferenceClock);
1085                 p1pll->reference_div = 0;
1086
1087                 if (crev < 2)
1088                         p1pll->pll_out_min =
1089                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1090                 else
1091                         p1pll->pll_out_min =
1092                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1093                 p1pll->pll_out_max =
1094                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1095
1096                 if (crev >= 4) {
1097                         p1pll->lcd_pll_out_min =
1098                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1099                         if (p1pll->lcd_pll_out_min == 0)
1100                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1101                         p1pll->lcd_pll_out_max =
1102                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1103                         if (p1pll->lcd_pll_out_max == 0)
1104                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1105                 } else {
1106                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1107                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1108                 }
1109
1110                 if (p1pll->pll_out_min == 0) {
1111                         if (ASIC_IS_AVIVO(rdev))
1112                                 p1pll->pll_out_min = 64800;
1113                         else
1114                                 p1pll->pll_out_min = 20000;
1115                 } else if (p1pll->pll_out_min > 64800) {
1116                         /* Limiting the pll output range is a good thing generally as
1117                          * it limits the number of possible pll combinations for a given
1118                          * frequency presumably to the ones that work best on each card.
1119                          * However, certain duallink DVI monitors seem to like
1120                          * pll combinations that would be limited by this at least on
1121                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
1122                          * family.
1123                          */
1124                         p1pll->pll_out_min = 64800;
1125                 }
1126
1127                 p1pll->pll_in_min =
1128                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1129                 p1pll->pll_in_max =
1130                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1131
1132                 *p2pll = *p1pll;
1133
1134                 /* system clock */
1135                 spll->reference_freq =
1136                     le16_to_cpu(firmware_info->info.usReferenceClock);
1137                 spll->reference_div = 0;
1138
1139                 spll->pll_out_min =
1140                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1141                 spll->pll_out_max =
1142                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1143
1144                 /* ??? */
1145                 if (spll->pll_out_min == 0) {
1146                         if (ASIC_IS_AVIVO(rdev))
1147                                 spll->pll_out_min = 64800;
1148                         else
1149                                 spll->pll_out_min = 20000;
1150                 }
1151
1152                 spll->pll_in_min =
1153                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1154                 spll->pll_in_max =
1155                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1156
1157                 /* memory clock */
1158                 mpll->reference_freq =
1159                     le16_to_cpu(firmware_info->info.usReferenceClock);
1160                 mpll->reference_div = 0;
1161
1162                 mpll->pll_out_min =
1163                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1164                 mpll->pll_out_max =
1165                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1166
1167                 /* ??? */
1168                 if (mpll->pll_out_min == 0) {
1169                         if (ASIC_IS_AVIVO(rdev))
1170                                 mpll->pll_out_min = 64800;
1171                         else
1172                                 mpll->pll_out_min = 20000;
1173                 }
1174
1175                 mpll->pll_in_min =
1176                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1177                 mpll->pll_in_max =
1178                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1179
1180                 rdev->clock.default_sclk =
1181                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1182                 rdev->clock.default_mclk =
1183                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1184
1185                 if (ASIC_IS_DCE4(rdev)) {
1186                         rdev->clock.default_dispclk =
1187                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1188                         if (rdev->clock.default_dispclk == 0)
1189                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1190                         rdev->clock.dp_extclk =
1191                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1192                 }
1193                 *dcpll = *p1pll;
1194
1195                 return true;
1196         }
1197
1198         return false;
1199 }
1200
1201 union igp_info {
1202         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1203         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1204 };
1205
1206 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1207 {
1208         struct radeon_mode_info *mode_info = &rdev->mode_info;
1209         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1210         union igp_info *igp_info;
1211         u8 frev, crev;
1212         u16 data_offset;
1213
1214         /* sideport is AMD only */
1215         if (rdev->family == CHIP_RS600)
1216                 return false;
1217
1218         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1219                                    &frev, &crev, &data_offset)) {
1220                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1221                                       data_offset);
1222                 switch (crev) {
1223                 case 1:
1224                         if (igp_info->info.ulBootUpMemoryClock)
1225                                 return true;
1226                         break;
1227                 case 2:
1228                         if (igp_info->info_2.ulBootUpSidePortClock)
1229                                 return true;
1230                         break;
1231                 default:
1232                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1233                         break;
1234                 }
1235         }
1236         return false;
1237 }
1238
1239 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1240                                    struct radeon_encoder_int_tmds *tmds)
1241 {
1242         struct drm_device *dev = encoder->base.dev;
1243         struct radeon_device *rdev = dev->dev_private;
1244         struct radeon_mode_info *mode_info = &rdev->mode_info;
1245         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1246         uint16_t data_offset;
1247         struct _ATOM_TMDS_INFO *tmds_info;
1248         uint8_t frev, crev;
1249         uint16_t maxfreq;
1250         int i;
1251
1252         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1253                                    &frev, &crev, &data_offset)) {
1254                 tmds_info =
1255                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1256                                                    data_offset);
1257
1258                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1259                 for (i = 0; i < 4; i++) {
1260                         tmds->tmds_pll[i].freq =
1261                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1262                         tmds->tmds_pll[i].value =
1263                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1264                         tmds->tmds_pll[i].value |=
1265                             (tmds_info->asMiscInfo[i].
1266                              ucPLL_VCO_Gain & 0x3f) << 6;
1267                         tmds->tmds_pll[i].value |=
1268                             (tmds_info->asMiscInfo[i].
1269                              ucPLL_DutyCycle & 0xf) << 12;
1270                         tmds->tmds_pll[i].value |=
1271                             (tmds_info->asMiscInfo[i].
1272                              ucPLL_VoltageSwing & 0xf) << 16;
1273
1274                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1275                                   tmds->tmds_pll[i].freq,
1276                                   tmds->tmds_pll[i].value);
1277
1278                         if (maxfreq == tmds->tmds_pll[i].freq) {
1279                                 tmds->tmds_pll[i].freq = 0xffffffff;
1280                                 break;
1281                         }
1282                 }
1283                 return true;
1284         }
1285         return false;
1286 }
1287
1288 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1289                                       struct radeon_atom_ss *ss,
1290                                       int id)
1291 {
1292         struct radeon_mode_info *mode_info = &rdev->mode_info;
1293         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1294         uint16_t data_offset, size;
1295         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1296         uint8_t frev, crev;
1297         int i, num_indices;
1298
1299         memset(ss, 0, sizeof(struct radeon_atom_ss));
1300         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1301                                    &frev, &crev, &data_offset)) {
1302                 ss_info =
1303                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1304
1305                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1306                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1307
1308                 for (i = 0; i < num_indices; i++) {
1309                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1310                                 ss->percentage =
1311                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1312                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1313                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1314                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1315                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1316                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1317                                 return true;
1318                         }
1319                 }
1320         }
1321         return false;
1322 }
1323
1324 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1325                                                  struct radeon_atom_ss *ss,
1326                                                  int id)
1327 {
1328         struct radeon_mode_info *mode_info = &rdev->mode_info;
1329         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1330         u16 data_offset, size;
1331         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1332         u8 frev, crev;
1333         u16 percentage = 0, rate = 0;
1334
1335         /* get any igp specific overrides */
1336         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1337                                    &frev, &crev, &data_offset)) {
1338                 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1339                         (mode_info->atom_context->bios + data_offset);
1340                 switch (id) {
1341                 case ASIC_INTERNAL_SS_ON_TMDS:
1342                         percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1343                         rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1344                         break;
1345                 case ASIC_INTERNAL_SS_ON_HDMI:
1346                         percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1347                         rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1348                         break;
1349                 case ASIC_INTERNAL_SS_ON_LVDS:
1350                         percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1351                         rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1352                         break;
1353                 }
1354                 if (percentage)
1355                         ss->percentage = percentage;
1356                 if (rate)
1357                         ss->rate = rate;
1358         }
1359 }
1360
1361 union asic_ss_info {
1362         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1363         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1364         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1365 };
1366
1367 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1368                                       struct radeon_atom_ss *ss,
1369                                       int id, u32 clock)
1370 {
1371         struct radeon_mode_info *mode_info = &rdev->mode_info;
1372         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1373         uint16_t data_offset, size;
1374         union asic_ss_info *ss_info;
1375         uint8_t frev, crev;
1376         int i, num_indices;
1377
1378         memset(ss, 0, sizeof(struct radeon_atom_ss));
1379         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1380                                    &frev, &crev, &data_offset)) {
1381
1382                 ss_info =
1383                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1384
1385                 switch (frev) {
1386                 case 1:
1387                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1388                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1389
1390                         for (i = 0; i < num_indices; i++) {
1391                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1392                                     (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1393                                         ss->percentage =
1394                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1395                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1396                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1397                                         return true;
1398                                 }
1399                         }
1400                         break;
1401                 case 2:
1402                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1403                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1404                         for (i = 0; i < num_indices; i++) {
1405                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1406                                     (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1407                                         ss->percentage =
1408                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1409                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1410                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1411                                         return true;
1412                                 }
1413                         }
1414                         break;
1415                 case 3:
1416                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1417                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1418                         for (i = 0; i < num_indices; i++) {
1419                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1420                                     (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1421                                         ss->percentage =
1422                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1423                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1424                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1425                                         if (rdev->flags & RADEON_IS_IGP)
1426                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1427                                         return true;
1428                                 }
1429                         }
1430                         break;
1431                 default:
1432                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1433                         break;
1434                 }
1435
1436         }
1437         return false;
1438 }
1439
1440 union lvds_info {
1441         struct _ATOM_LVDS_INFO info;
1442         struct _ATOM_LVDS_INFO_V12 info_12;
1443 };
1444
1445 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1446                                                               radeon_encoder
1447                                                               *encoder)
1448 {
1449         struct drm_device *dev = encoder->base.dev;
1450         struct radeon_device *rdev = dev->dev_private;
1451         struct radeon_mode_info *mode_info = &rdev->mode_info;
1452         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1453         uint16_t data_offset, misc;
1454         union lvds_info *lvds_info;
1455         uint8_t frev, crev;
1456         struct radeon_encoder_atom_dig *lvds = NULL;
1457         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1458
1459         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1460                                    &frev, &crev, &data_offset)) {
1461                 lvds_info =
1462                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1463                 lvds =
1464                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1465
1466                 if (!lvds)
1467                         return NULL;
1468
1469                 lvds->native_mode.clock =
1470                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1471                 lvds->native_mode.hdisplay =
1472                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1473                 lvds->native_mode.vdisplay =
1474                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1475                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1476                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1477                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1478                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1479                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1480                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1481                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1482                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1483                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1484                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1485                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1486                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1487                 lvds->panel_pwr_delay =
1488                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1489                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1490
1491                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1492                 if (misc & ATOM_VSYNC_POLARITY)
1493                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1494                 if (misc & ATOM_HSYNC_POLARITY)
1495                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1496                 if (misc & ATOM_COMPOSITESYNC)
1497                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1498                 if (misc & ATOM_INTERLACE)
1499                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1500                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1501                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1502
1503                 /* set crtc values */
1504                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1505
1506                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1507
1508                 encoder->native_mode = lvds->native_mode;
1509
1510                 if (encoder_enum == 2)
1511                         lvds->linkb = true;
1512                 else
1513                         lvds->linkb = false;
1514
1515         }
1516         return lvds;
1517 }
1518
1519 struct radeon_encoder_primary_dac *
1520 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1521 {
1522         struct drm_device *dev = encoder->base.dev;
1523         struct radeon_device *rdev = dev->dev_private;
1524         struct radeon_mode_info *mode_info = &rdev->mode_info;
1525         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1526         uint16_t data_offset;
1527         struct _COMPASSIONATE_DATA *dac_info;
1528         uint8_t frev, crev;
1529         uint8_t bg, dac;
1530         struct radeon_encoder_primary_dac *p_dac = NULL;
1531
1532         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1533                                    &frev, &crev, &data_offset)) {
1534                 dac_info = (struct _COMPASSIONATE_DATA *)
1535                         (mode_info->atom_context->bios + data_offset);
1536
1537                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1538
1539                 if (!p_dac)
1540                         return NULL;
1541
1542                 bg = dac_info->ucDAC1_BG_Adjustment;
1543                 dac = dac_info->ucDAC1_DAC_Adjustment;
1544                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1545
1546         }
1547         return p_dac;
1548 }
1549
1550 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1551                                 struct drm_display_mode *mode)
1552 {
1553         struct radeon_mode_info *mode_info = &rdev->mode_info;
1554         ATOM_ANALOG_TV_INFO *tv_info;
1555         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1556         ATOM_DTD_FORMAT *dtd_timings;
1557         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1558         u8 frev, crev;
1559         u16 data_offset, misc;
1560
1561         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1562                                     &frev, &crev, &data_offset))
1563                 return false;
1564
1565         switch (crev) {
1566         case 1:
1567                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1568                 if (index >= MAX_SUPPORTED_TV_TIMING)
1569                         return false;
1570
1571                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1572                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1573                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1574                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1575                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1576
1577                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1578                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1579                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1580                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1581                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1582
1583                 mode->flags = 0;
1584                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1585                 if (misc & ATOM_VSYNC_POLARITY)
1586                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1587                 if (misc & ATOM_HSYNC_POLARITY)
1588                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1589                 if (misc & ATOM_COMPOSITESYNC)
1590                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1591                 if (misc & ATOM_INTERLACE)
1592                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1593                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1594                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1595
1596                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1597
1598                 if (index == 1) {
1599                         /* PAL timings appear to have wrong values for totals */
1600                         mode->crtc_htotal -= 1;
1601                         mode->crtc_vtotal -= 1;
1602                 }
1603                 break;
1604         case 2:
1605                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1606                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1607                         return false;
1608
1609                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1610                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1611                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1612                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1613                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1614                         le16_to_cpu(dtd_timings->usHSyncOffset);
1615                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1616                         le16_to_cpu(dtd_timings->usHSyncWidth);
1617
1618                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1619                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1620                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1621                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1622                         le16_to_cpu(dtd_timings->usVSyncOffset);
1623                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1624                         le16_to_cpu(dtd_timings->usVSyncWidth);
1625
1626                 mode->flags = 0;
1627                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1628                 if (misc & ATOM_VSYNC_POLARITY)
1629                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1630                 if (misc & ATOM_HSYNC_POLARITY)
1631                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1632                 if (misc & ATOM_COMPOSITESYNC)
1633                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1634                 if (misc & ATOM_INTERLACE)
1635                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1636                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1637                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1638
1639                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1640                 break;
1641         }
1642         return true;
1643 }
1644
1645 enum radeon_tv_std
1646 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1647 {
1648         struct radeon_mode_info *mode_info = &rdev->mode_info;
1649         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1650         uint16_t data_offset;
1651         uint8_t frev, crev;
1652         struct _ATOM_ANALOG_TV_INFO *tv_info;
1653         enum radeon_tv_std tv_std = TV_STD_NTSC;
1654
1655         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1656                                    &frev, &crev, &data_offset)) {
1657
1658                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1659                         (mode_info->atom_context->bios + data_offset);
1660
1661                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1662                 case ATOM_TV_NTSC:
1663                         tv_std = TV_STD_NTSC;
1664                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1665                         break;
1666                 case ATOM_TV_NTSCJ:
1667                         tv_std = TV_STD_NTSC_J;
1668                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1669                         break;
1670                 case ATOM_TV_PAL:
1671                         tv_std = TV_STD_PAL;
1672                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1673                         break;
1674                 case ATOM_TV_PALM:
1675                         tv_std = TV_STD_PAL_M;
1676                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1677                         break;
1678                 case ATOM_TV_PALN:
1679                         tv_std = TV_STD_PAL_N;
1680                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1681                         break;
1682                 case ATOM_TV_PALCN:
1683                         tv_std = TV_STD_PAL_CN;
1684                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1685                         break;
1686                 case ATOM_TV_PAL60:
1687                         tv_std = TV_STD_PAL_60;
1688                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1689                         break;
1690                 case ATOM_TV_SECAM:
1691                         tv_std = TV_STD_SECAM;
1692                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1693                         break;
1694                 default:
1695                         tv_std = TV_STD_NTSC;
1696                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1697                         break;
1698                 }
1699         }
1700         return tv_std;
1701 }
1702
1703 struct radeon_encoder_tv_dac *
1704 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1705 {
1706         struct drm_device *dev = encoder->base.dev;
1707         struct radeon_device *rdev = dev->dev_private;
1708         struct radeon_mode_info *mode_info = &rdev->mode_info;
1709         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1710         uint16_t data_offset;
1711         struct _COMPASSIONATE_DATA *dac_info;
1712         uint8_t frev, crev;
1713         uint8_t bg, dac;
1714         struct radeon_encoder_tv_dac *tv_dac = NULL;
1715
1716         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1717                                    &frev, &crev, &data_offset)) {
1718
1719                 dac_info = (struct _COMPASSIONATE_DATA *)
1720                         (mode_info->atom_context->bios + data_offset);
1721
1722                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1723
1724                 if (!tv_dac)
1725                         return NULL;
1726
1727                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1728                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1729                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1730
1731                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1732                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1733                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1734
1735                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1736                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1737                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1738
1739                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1740         }
1741         return tv_dac;
1742 }
1743
1744 static const char *thermal_controller_names[] = {
1745         "NONE",
1746         "lm63",
1747         "adm1032",
1748         "adm1030",
1749         "max6649",
1750         "lm64",
1751         "f75375",
1752         "asc7xxx",
1753 };
1754
1755 static const char *pp_lib_thermal_controller_names[] = {
1756         "NONE",
1757         "lm63",
1758         "adm1032",
1759         "adm1030",
1760         "max6649",
1761         "lm64",
1762         "f75375",
1763         "RV6xx",
1764         "RV770",
1765         "adt7473",
1766         "External GPIO",
1767         "Evergreen",
1768         "adt7473 with internal",
1769
1770 };
1771
1772 union power_info {
1773         struct _ATOM_POWERPLAY_INFO info;
1774         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1775         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1776         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1777 };
1778
1779 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1780 {
1781         struct radeon_mode_info *mode_info = &rdev->mode_info;
1782         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1783         u16 data_offset;
1784         u8 frev, crev;
1785         u32 misc, misc2 = 0, sclk, mclk;
1786         union power_info *power_info;
1787         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1788         struct _ATOM_PPLIB_STATE *power_state;
1789         int num_modes = 0, i, j;
1790         int state_index = 0, mode_index = 0;
1791         struct radeon_i2c_bus_rec i2c_bus;
1792
1793         rdev->pm.default_power_state_index = -1;
1794
1795         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1796                                    &frev, &crev, &data_offset)) {
1797                 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1798                 if (frev < 4) {
1799                         /* add the i2c bus for thermal/fan chip */
1800                         if (power_info->info.ucOverdriveThermalController > 0) {
1801                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1802                                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1803                                          power_info->info.ucOverdriveControllerAddress >> 1);
1804                                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1805                                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1806                                 if (rdev->pm.i2c_bus) {
1807                                         struct i2c_board_info info = { };
1808                                         const char *name = thermal_controller_names[power_info->info.
1809                                                                                     ucOverdriveThermalController];
1810                                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1811                                         strlcpy(info.type, name, sizeof(info.type));
1812                                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1813                                 }
1814                         }
1815                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1816                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1817                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1818                         /* last mode is usually default, array is low to high */
1819                         for (i = 0; i < num_modes; i++) {
1820                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1821                                 switch (frev) {
1822                                 case 1:
1823                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1824                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1825                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1826                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1827                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1828                                         /* skip invalid modes */
1829                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1830                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1831                                                 continue;
1832                                         rdev->pm.power_state[state_index].pcie_lanes =
1833                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1834                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1835                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1836                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1837                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1838                                                         VOLTAGE_GPIO;
1839                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1840                                                         radeon_lookup_gpio(rdev,
1841                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1842                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1843                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1844                                                                 true;
1845                                                 else
1846                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1847                                                                 false;
1848                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1849                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1850                                                         VOLTAGE_VDDC;
1851                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1852                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1853                                         }
1854                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1855                                         rdev->pm.power_state[state_index].misc = misc;
1856                                         /* order matters! */
1857                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1858                                                 rdev->pm.power_state[state_index].type =
1859                                                         POWER_STATE_TYPE_POWERSAVE;
1860                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1861                                                 rdev->pm.power_state[state_index].type =
1862                                                         POWER_STATE_TYPE_BATTERY;
1863                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1864                                                 rdev->pm.power_state[state_index].type =
1865                                                         POWER_STATE_TYPE_BATTERY;
1866                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1867                                                 rdev->pm.power_state[state_index].type =
1868                                                         POWER_STATE_TYPE_BALANCED;
1869                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1870                                                 rdev->pm.power_state[state_index].type =
1871                                                         POWER_STATE_TYPE_PERFORMANCE;
1872                                                 rdev->pm.power_state[state_index].flags &=
1873                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1874                                         }
1875                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1876                                                 rdev->pm.power_state[state_index].type =
1877                                                         POWER_STATE_TYPE_DEFAULT;
1878                                                 rdev->pm.default_power_state_index = state_index;
1879                                                 rdev->pm.power_state[state_index].default_clock_mode =
1880                                                         &rdev->pm.power_state[state_index].clock_info[0];
1881                                                 rdev->pm.power_state[state_index].flags &=
1882                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1883                                         } else if (state_index == 0) {
1884                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1885                                                         RADEON_PM_MODE_NO_DISPLAY;
1886                                         }
1887                                         state_index++;
1888                                         break;
1889                                 case 2:
1890                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1891                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1892                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1893                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1894                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1895                                         /* skip invalid modes */
1896                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1897                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1898                                                 continue;
1899                                         rdev->pm.power_state[state_index].pcie_lanes =
1900                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1901                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1902                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1903                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1904                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1905                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1906                                                         VOLTAGE_GPIO;
1907                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1908                                                         radeon_lookup_gpio(rdev,
1909                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1910                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1911                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1912                                                                 true;
1913                                                 else
1914                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1915                                                                 false;
1916                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1917                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1918                                                         VOLTAGE_VDDC;
1919                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1920                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1921                                         }
1922                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1923                                         rdev->pm.power_state[state_index].misc = misc;
1924                                         rdev->pm.power_state[state_index].misc2 = misc2;
1925                                         /* order matters! */
1926                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1927                                                 rdev->pm.power_state[state_index].type =
1928                                                         POWER_STATE_TYPE_POWERSAVE;
1929                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1930                                                 rdev->pm.power_state[state_index].type =
1931                                                         POWER_STATE_TYPE_BATTERY;
1932                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1933                                                 rdev->pm.power_state[state_index].type =
1934                                                         POWER_STATE_TYPE_BATTERY;
1935                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1936                                                 rdev->pm.power_state[state_index].type =
1937                                                         POWER_STATE_TYPE_BALANCED;
1938                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1939                                                 rdev->pm.power_state[state_index].type =
1940                                                         POWER_STATE_TYPE_PERFORMANCE;
1941                                                 rdev->pm.power_state[state_index].flags &=
1942                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1943                                         }
1944                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1945                                                 rdev->pm.power_state[state_index].type =
1946                                                         POWER_STATE_TYPE_BALANCED;
1947                                         if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1948                                                 rdev->pm.power_state[state_index].flags &=
1949                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1950                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1951                                                 rdev->pm.power_state[state_index].type =
1952                                                         POWER_STATE_TYPE_DEFAULT;
1953                                                 rdev->pm.default_power_state_index = state_index;
1954                                                 rdev->pm.power_state[state_index].default_clock_mode =
1955                                                         &rdev->pm.power_state[state_index].clock_info[0];
1956                                                 rdev->pm.power_state[state_index].flags &=
1957                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1958                                         } else if (state_index == 0) {
1959                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1960                                                         RADEON_PM_MODE_NO_DISPLAY;
1961                                         }
1962                                         state_index++;
1963                                         break;
1964                                 case 3:
1965                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1966                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1967                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1968                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1969                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1970                                         /* skip invalid modes */
1971                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1972                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1973                                                 continue;
1974                                         rdev->pm.power_state[state_index].pcie_lanes =
1975                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1976                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1977                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1978                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1979                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1980                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1981                                                         VOLTAGE_GPIO;
1982                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1983                                                         radeon_lookup_gpio(rdev,
1984                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1985                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1986                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1987                                                                 true;
1988                                                 else
1989                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1990                                                                 false;
1991                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1992                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1993                                                         VOLTAGE_VDDC;
1994                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1995                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1996                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1997                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1998                                                                 true;
1999                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2000                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2001                                                 }
2002                                         }
2003                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2004                                         rdev->pm.power_state[state_index].misc = misc;
2005                                         rdev->pm.power_state[state_index].misc2 = misc2;
2006                                         /* order matters! */
2007                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2008                                                 rdev->pm.power_state[state_index].type =
2009                                                         POWER_STATE_TYPE_POWERSAVE;
2010                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2011                                                 rdev->pm.power_state[state_index].type =
2012                                                         POWER_STATE_TYPE_BATTERY;
2013                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2014                                                 rdev->pm.power_state[state_index].type =
2015                                                         POWER_STATE_TYPE_BATTERY;
2016                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2017                                                 rdev->pm.power_state[state_index].type =
2018                                                         POWER_STATE_TYPE_BALANCED;
2019                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2020                                                 rdev->pm.power_state[state_index].type =
2021                                                         POWER_STATE_TYPE_PERFORMANCE;
2022                                                 rdev->pm.power_state[state_index].flags &=
2023                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2024                                         }
2025                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2026                                                 rdev->pm.power_state[state_index].type =
2027                                                         POWER_STATE_TYPE_BALANCED;
2028                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2029                                                 rdev->pm.power_state[state_index].type =
2030                                                         POWER_STATE_TYPE_DEFAULT;
2031                                                 rdev->pm.default_power_state_index = state_index;
2032                                                 rdev->pm.power_state[state_index].default_clock_mode =
2033                                                         &rdev->pm.power_state[state_index].clock_info[0];
2034                                         } else if (state_index == 0) {
2035                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
2036                                                         RADEON_PM_MODE_NO_DISPLAY;
2037                                         }
2038                                         state_index++;
2039                                         break;
2040                                 }
2041                         }
2042                         /* last mode is usually default */
2043                         if (rdev->pm.default_power_state_index == -1) {
2044                                 rdev->pm.power_state[state_index - 1].type =
2045                                         POWER_STATE_TYPE_DEFAULT;
2046                                 rdev->pm.default_power_state_index = state_index - 1;
2047                                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2048                                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2049                                 rdev->pm.power_state[state_index].flags &=
2050                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2051                                 rdev->pm.power_state[state_index].misc = 0;
2052                                 rdev->pm.power_state[state_index].misc2 = 0;
2053                         }
2054                 } else {
2055                         int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2056                         uint8_t fw_frev, fw_crev;
2057                         uint16_t fw_data_offset, vddc = 0;
2058                         union firmware_info *firmware_info;
2059                         ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
2060
2061                         if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
2062                                                    &fw_frev, &fw_crev, &fw_data_offset)) {
2063                                 firmware_info =
2064                                         (union firmware_info *)(mode_info->atom_context->bios +
2065                                                                 fw_data_offset);
2066                                 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2067                         }
2068
2069                         /* add the i2c bus for thermal/fan chip */
2070                         if (controller->ucType > 0) {
2071                                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2072                                         DRM_INFO("Internal thermal controller %s fan control\n",
2073                                                  (controller->ucFanParameters &
2074                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2075                                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2076                                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2077                                         DRM_INFO("Internal thermal controller %s fan control\n",
2078                                                  (controller->ucFanParameters &
2079                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2080                                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2081                                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2082                                         DRM_INFO("Internal thermal controller %s fan control\n",
2083                                                  (controller->ucFanParameters &
2084                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2085                                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2086                                 } else if ((controller->ucType ==
2087                                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2088                                            (controller->ucType ==
2089                                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
2090                                         DRM_INFO("Special thermal controller config\n");
2091                                 } else {
2092                                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2093                                                  pp_lib_thermal_controller_names[controller->ucType],
2094                                                  controller->ucI2cAddress >> 1,
2095                                                  (controller->ucFanParameters &
2096                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2097                                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2098                                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2099                                         if (rdev->pm.i2c_bus) {
2100                                                 struct i2c_board_info info = { };
2101                                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2102                                                 info.addr = controller->ucI2cAddress >> 1;
2103                                                 strlcpy(info.type, name, sizeof(info.type));
2104                                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2105                                         }
2106
2107                                 }
2108                         }
2109                         /* first mode is usually default, followed by low to high */
2110                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
2111                                 mode_index = 0;
2112                                 power_state = (struct _ATOM_PPLIB_STATE *)
2113                                         (mode_info->atom_context->bios +
2114                                          data_offset +
2115                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
2116                                          i * power_info->info_4.ucStateEntrySize);
2117                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2118                                         (mode_info->atom_context->bios +
2119                                          data_offset +
2120                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
2121                                          (power_state->ucNonClockStateIndex *
2122                                           power_info->info_4.ucNonClockSize));
2123                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
2124                                         if (rdev->flags & RADEON_IS_IGP) {
2125                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
2126                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
2127                                                         (mode_info->atom_context->bios +
2128                                                          data_offset +
2129                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2130                                                          (power_state->ucClockStateIndices[j] *
2131                                                           power_info->info_4.ucClockInfoSize));
2132                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
2133                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
2134                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2135                                                 /* skip invalid modes */
2136                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2137                                                         continue;
2138                                                 /* voltage works differently on IGPs */
2139                                                 mode_index++;
2140                                         } else if (ASIC_IS_DCE4(rdev)) {
2141                                                 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
2142                                                         (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
2143                                                         (mode_info->atom_context->bios +
2144                                                          data_offset +
2145                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2146                                                          (power_state->ucClockStateIndices[j] *
2147                                                           power_info->info_4.ucClockInfoSize));
2148                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2149                                                 sclk |= clock_info->ucEngineClockHigh << 16;
2150                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2151                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
2152                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2153                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2154                                                 /* skip invalid modes */
2155                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2156                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2157                                                         continue;
2158                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2159                                                         VOLTAGE_SW;
2160                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2161                                                         clock_info->usVDDC;
2162                                                 /* XXX usVDDCI */
2163                                                 mode_index++;
2164                                         } else {
2165                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2166                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2167                                                         (mode_info->atom_context->bios +
2168                                                          data_offset +
2169                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2170                                                          (power_state->ucClockStateIndices[j] *
2171                                                           power_info->info_4.ucClockInfoSize));
2172                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2173                                                 sclk |= clock_info->ucEngineClockHigh << 16;
2174                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2175                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
2176                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2177                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2178                                                 /* skip invalid modes */
2179                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2180                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2181                                                         continue;
2182                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2183                                                         VOLTAGE_SW;
2184                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2185                                                         clock_info->usVDDC;
2186                                                 mode_index++;
2187                                         }
2188                                 }
2189                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2190                                 if (mode_index) {
2191                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2192                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
2193                                         rdev->pm.power_state[state_index].misc = misc;
2194                                         rdev->pm.power_state[state_index].misc2 = misc2;
2195                                         rdev->pm.power_state[state_index].pcie_lanes =
2196                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2197                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2198                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2199                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2200                                                 rdev->pm.power_state[state_index].type =
2201                                                         POWER_STATE_TYPE_BATTERY;
2202                                                 break;
2203                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2204                                                 rdev->pm.power_state[state_index].type =
2205                                                         POWER_STATE_TYPE_BALANCED;
2206                                                 break;
2207                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2208                                                 rdev->pm.power_state[state_index].type =
2209                                                         POWER_STATE_TYPE_PERFORMANCE;
2210                                                 break;
2211                                         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2212                                                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2213                                                         rdev->pm.power_state[state_index].type =
2214                                                                 POWER_STATE_TYPE_PERFORMANCE;
2215                                                 break;
2216                                         }
2217                                         rdev->pm.power_state[state_index].flags = 0;
2218                                         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2219                                                 rdev->pm.power_state[state_index].flags |=
2220                                                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2221                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2222                                                 rdev->pm.power_state[state_index].type =
2223                                                         POWER_STATE_TYPE_DEFAULT;
2224                                                 rdev->pm.default_power_state_index = state_index;
2225                                                 rdev->pm.power_state[state_index].default_clock_mode =
2226                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2227                                                 /* patch the table values with the default slck/mclk from firmware info */
2228                                                 for (j = 0; j < mode_index; j++) {
2229                                                         rdev->pm.power_state[state_index].clock_info[j].mclk =
2230                                                                 rdev->clock.default_mclk;
2231                                                         rdev->pm.power_state[state_index].clock_info[j].sclk =
2232                                                                 rdev->clock.default_sclk;
2233                                                         if (vddc)
2234                                                                 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2235                                                                         vddc;
2236                                                 }
2237                                         }
2238                                         state_index++;
2239                                 }
2240                         }
2241                         /* if multiple clock modes, mark the lowest as no display */
2242                         for (i = 0; i < state_index; i++) {
2243                                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2244                                         rdev->pm.power_state[i].clock_info[0].flags |=
2245                                                 RADEON_PM_MODE_NO_DISPLAY;
2246                         }
2247                         /* first mode is usually default */
2248                         if (rdev->pm.default_power_state_index == -1) {
2249                                 rdev->pm.power_state[0].type =
2250                                         POWER_STATE_TYPE_DEFAULT;
2251                                 rdev->pm.default_power_state_index = 0;
2252                                 rdev->pm.power_state[0].default_clock_mode =
2253                                         &rdev->pm.power_state[0].clock_info[0];
2254                         }
2255                 }
2256         } else {
2257                 /* add the default mode */
2258                 rdev->pm.power_state[state_index].type =
2259                         POWER_STATE_TYPE_DEFAULT;
2260                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2261                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2262                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2263                 rdev->pm.power_state[state_index].default_clock_mode =
2264                         &rdev->pm.power_state[state_index].clock_info[0];
2265                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2266                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2267                 rdev->pm.default_power_state_index = state_index;
2268                 rdev->pm.power_state[state_index].flags = 0;
2269                 state_index++;
2270         }
2271
2272         rdev->pm.num_power_states = state_index;
2273
2274         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2275         rdev->pm.current_clock_mode_index = 0;
2276         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2277 }
2278
2279 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2280 {
2281         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2282         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2283
2284         args.ucEnable = enable;
2285
2286         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2287 }
2288
2289 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2290 {
2291         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2292         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2293
2294         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2295         return args.ulReturnEngineClock;
2296 }
2297
2298 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2299 {
2300         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2301         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2302
2303         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2304         return args.ulReturnMemoryClock;
2305 }
2306
2307 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2308                                   uint32_t eng_clock)
2309 {
2310         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2311         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2312
2313         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
2314
2315         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2316 }
2317
2318 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2319                                   uint32_t mem_clock)
2320 {
2321         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2322         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2323
2324         if (rdev->flags & RADEON_IS_IGP)
2325                 return;
2326
2327         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
2328
2329         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2330 }
2331
2332 union set_voltage {
2333         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2334         struct _SET_VOLTAGE_PARAMETERS v1;
2335         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2336 };
2337
2338 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2339 {
2340         union set_voltage args;
2341         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2342         u8 frev, crev, volt_index = level;
2343
2344         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2345                 return;
2346
2347         switch (crev) {
2348         case 1:
2349                 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2350                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2351                 args.v1.ucVoltageIndex = volt_index;
2352                 break;
2353         case 2:
2354                 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2355                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2356                 args.v2.usVoltageLevel = cpu_to_le16(level);
2357                 break;
2358         default:
2359                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2360                 return;
2361         }
2362
2363         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2364 }
2365
2366
2367
2368 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2369 {
2370         struct radeon_device *rdev = dev->dev_private;
2371         uint32_t bios_2_scratch, bios_6_scratch;
2372
2373         if (rdev->family >= CHIP_R600) {
2374                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2375                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2376         } else {
2377                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2378                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2379         }
2380
2381         /* let the bios control the backlight */
2382         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2383
2384         /* tell the bios not to handle mode switching */
2385         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2386
2387         if (rdev->family >= CHIP_R600) {
2388                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2389                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2390         } else {
2391                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2392                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2393         }
2394
2395 }
2396
2397 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2398 {
2399         uint32_t scratch_reg;
2400         int i;
2401
2402         if (rdev->family >= CHIP_R600)
2403                 scratch_reg = R600_BIOS_0_SCRATCH;
2404         else
2405                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2406
2407         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2408                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2409 }
2410
2411 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2412 {
2413         uint32_t scratch_reg;
2414         int i;
2415
2416         if (rdev->family >= CHIP_R600)
2417                 scratch_reg = R600_BIOS_0_SCRATCH;
2418         else
2419                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2420
2421         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2422                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2423 }
2424
2425 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2426 {
2427         struct drm_device *dev = encoder->dev;
2428         struct radeon_device *rdev = dev->dev_private;
2429         uint32_t bios_6_scratch;
2430
2431         if (rdev->family >= CHIP_R600)
2432                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2433         else
2434                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2435
2436         if (lock)
2437                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2438         else
2439                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2440
2441         if (rdev->family >= CHIP_R600)
2442                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2443         else
2444                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2445 }
2446
2447 /* at some point we may want to break this out into individual functions */
2448 void
2449 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2450                                        struct drm_encoder *encoder,
2451                                        bool connected)
2452 {
2453         struct drm_device *dev = connector->dev;
2454         struct radeon_device *rdev = dev->dev_private;
2455         struct radeon_connector *radeon_connector =
2456             to_radeon_connector(connector);
2457         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2458         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2459
2460         if (rdev->family >= CHIP_R600) {
2461                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2462                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2463                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2464         } else {
2465                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2466                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2467                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2468         }
2469
2470         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2471             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2472                 if (connected) {
2473                         DRM_DEBUG_KMS("TV1 connected\n");
2474                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2475                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2476                 } else {
2477                         DRM_DEBUG_KMS("TV1 disconnected\n");
2478                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2479                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2480                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2481                 }
2482         }
2483         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2484             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2485                 if (connected) {
2486                         DRM_DEBUG_KMS("CV connected\n");
2487                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2488                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2489                 } else {
2490                         DRM_DEBUG_KMS("CV disconnected\n");
2491                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2492                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2493                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2494                 }
2495         }
2496         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2497             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2498                 if (connected) {
2499                         DRM_DEBUG_KMS("LCD1 connected\n");
2500                         bios_0_scratch |= ATOM_S0_LCD1;
2501                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2502                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2503                 } else {
2504                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2505                         bios_0_scratch &= ~ATOM_S0_LCD1;
2506                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2507                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2508                 }
2509         }
2510         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2511             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2512                 if (connected) {
2513                         DRM_DEBUG_KMS("CRT1 connected\n");
2514                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2515                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2516                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2517                 } else {
2518                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2519                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2520                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2521                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2522                 }
2523         }
2524         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2525             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2526                 if (connected) {
2527                         DRM_DEBUG_KMS("CRT2 connected\n");
2528                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2529                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2530                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2531                 } else {
2532                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2533                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2534                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2535                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2536                 }
2537         }
2538         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2539             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2540                 if (connected) {
2541                         DRM_DEBUG_KMS("DFP1 connected\n");
2542                         bios_0_scratch |= ATOM_S0_DFP1;
2543                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2544                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2545                 } else {
2546                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2547                         bios_0_scratch &= ~ATOM_S0_DFP1;
2548                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2549                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2550                 }
2551         }
2552         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2553             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2554                 if (connected) {
2555                         DRM_DEBUG_KMS("DFP2 connected\n");
2556                         bios_0_scratch |= ATOM_S0_DFP2;
2557                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2558                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2559                 } else {
2560                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2561                         bios_0_scratch &= ~ATOM_S0_DFP2;
2562                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2563                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2564                 }
2565         }
2566         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2567             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2568                 if (connected) {
2569                         DRM_DEBUG_KMS("DFP3 connected\n");
2570                         bios_0_scratch |= ATOM_S0_DFP3;
2571                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2572                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2573                 } else {
2574                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2575                         bios_0_scratch &= ~ATOM_S0_DFP3;
2576                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2577                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2578                 }
2579         }
2580         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2581             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2582                 if (connected) {
2583                         DRM_DEBUG_KMS("DFP4 connected\n");
2584                         bios_0_scratch |= ATOM_S0_DFP4;
2585                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2586                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2587                 } else {
2588                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2589                         bios_0_scratch &= ~ATOM_S0_DFP4;
2590                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2591                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2592                 }
2593         }
2594         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2595             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2596                 if (connected) {
2597                         DRM_DEBUG_KMS("DFP5 connected\n");
2598                         bios_0_scratch |= ATOM_S0_DFP5;
2599                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2600                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2601                 } else {
2602                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2603                         bios_0_scratch &= ~ATOM_S0_DFP5;
2604                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2605                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2606                 }
2607         }
2608
2609         if (rdev->family >= CHIP_R600) {
2610                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2611                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2612                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2613         } else {
2614                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2615                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2616                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2617         }
2618 }
2619
2620 void
2621 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2622 {
2623         struct drm_device *dev = encoder->dev;
2624         struct radeon_device *rdev = dev->dev_private;
2625         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2626         uint32_t bios_3_scratch;
2627
2628         if (rdev->family >= CHIP_R600)
2629                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2630         else
2631                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2632
2633         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2634                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2635                 bios_3_scratch |= (crtc << 18);
2636         }
2637         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2638                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2639                 bios_3_scratch |= (crtc << 24);
2640         }
2641         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2642                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2643                 bios_3_scratch |= (crtc << 16);
2644         }
2645         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2646                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2647                 bios_3_scratch |= (crtc << 20);
2648         }
2649         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2650                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2651                 bios_3_scratch |= (crtc << 17);
2652         }
2653         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2654                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2655                 bios_3_scratch |= (crtc << 19);
2656         }
2657         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2658                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2659                 bios_3_scratch |= (crtc << 23);
2660         }
2661         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2662                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2663                 bios_3_scratch |= (crtc << 25);
2664         }
2665
2666         if (rdev->family >= CHIP_R600)
2667                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2668         else
2669                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2670 }
2671
2672 void
2673 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2674 {
2675         struct drm_device *dev = encoder->dev;
2676         struct radeon_device *rdev = dev->dev_private;
2677         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2678         uint32_t bios_2_scratch;
2679
2680         if (rdev->family >= CHIP_R600)
2681                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2682         else
2683                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2684
2685         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2686                 if (on)
2687                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2688                 else
2689                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2690         }
2691         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2692                 if (on)
2693                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2694                 else
2695                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2696         }
2697         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2698                 if (on)
2699                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2700                 else
2701                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2702         }
2703         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2704                 if (on)
2705                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2706                 else
2707                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2708         }
2709         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2710                 if (on)
2711                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2712                 else
2713                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2714         }
2715         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2716                 if (on)
2717                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2718                 else
2719                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2720         }
2721         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2722                 if (on)
2723                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2724                 else
2725                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2726         }
2727         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2728                 if (on)
2729                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2730                 else
2731                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2732         }
2733         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2734                 if (on)
2735                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2736                 else
2737                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2738         }
2739         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2740                 if (on)
2741                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2742                 else
2743                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2744         }
2745
2746         if (rdev->family >= CHIP_R600)
2747                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2748         else
2749                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2750 }