2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
54 /* from radeon_legacy_encoder.c */
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
68 struct atom_context *ctx = rdev->mode_info.atom_context;
69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 uint16_t data_offset, size;
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i];
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
91 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
104 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
109 if (gpio->sucI2cId.ucAccess == id) {
110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
121 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
128 i2c.hw_capable = true;
130 i2c.hw_capable = false;
132 if (gpio->sucI2cId.ucAccess == 0xa0)
137 i2c.i2c_id = gpio->sucI2cId.ucAccess;
139 if (i2c.mask_clk_reg)
149 void radeon_atombios_i2c_init(struct radeon_device *rdev)
151 struct atom_context *ctx = rdev->mode_info.atom_context;
152 ATOM_GPIO_I2C_ASSIGMENT *gpio;
153 struct radeon_i2c_bus_rec i2c;
154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
155 struct _ATOM_GPIO_I2C_INFO *i2c_info;
156 uint16_t data_offset, size;
160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
168 for (i = 0; i < num_indices; i++) {
169 gpio = &i2c_info->asGPIO_Info[i];
172 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
173 if ((rdev->family == CHIP_R420) ||
174 (rdev->family == CHIP_R423) ||
175 (rdev->family == CHIP_RV410)) {
176 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
177 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
178 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
179 gpio->ucClkMaskShift = 0x19;
180 gpio->ucDataMaskShift = 0x18;
184 /* some evergreen boards have bad data for this entry */
185 if (ASIC_IS_DCE4(rdev)) {
187 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
188 (gpio->sucI2cId.ucAccess == 0)) {
189 gpio->sucI2cId.ucAccess = 0x97;
190 gpio->ucDataMaskShift = 8;
191 gpio->ucDataEnShift = 8;
192 gpio->ucDataY_Shift = 8;
193 gpio->ucDataA_Shift = 8;
197 /* some DCE3 boards have bad data for this entry */
198 if (ASIC_IS_DCE3(rdev)) {
200 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
201 (gpio->sucI2cId.ucAccess == 0x94))
202 gpio->sucI2cId.ucAccess = 0x14;
205 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
206 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
207 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
208 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
209 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
210 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
211 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
212 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
213 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
214 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
215 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
216 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
217 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
218 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
219 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
220 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
222 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
223 i2c.hw_capable = true;
225 i2c.hw_capable = false;
227 if (gpio->sucI2cId.ucAccess == 0xa0)
232 i2c.i2c_id = gpio->sucI2cId.ucAccess;
234 if (i2c.mask_clk_reg) {
236 sprintf(stmp, "0x%x", i2c.i2c_id);
237 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
243 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
246 struct atom_context *ctx = rdev->mode_info.atom_context;
247 struct radeon_gpio_rec gpio;
248 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
249 struct _ATOM_GPIO_PIN_LUT *gpio_info;
250 ATOM_GPIO_PIN_ASSIGNMENT *pin;
251 u16 data_offset, size;
254 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
257 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
258 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
260 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
261 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
263 for (i = 0; i < num_indices; i++) {
264 pin = &gpio_info->asGPIO_Pin[i];
265 if (id == pin->ucGPIO_ID) {
266 gpio.id = pin->ucGPIO_ID;
267 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
268 gpio.mask = (1 << pin->ucGpioPinBitShift);
278 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
279 struct radeon_gpio_rec *gpio)
281 struct radeon_hpd hpd;
284 memset(&hpd, 0, sizeof(struct radeon_hpd));
286 if (ASIC_IS_DCE4(rdev))
287 reg = EVERGREEN_DC_GPIO_HPD_A;
289 reg = AVIVO_DC_GPIO_HPD_A;
292 if (gpio->reg == reg) {
295 hpd.hpd = RADEON_HPD_1;
298 hpd.hpd = RADEON_HPD_2;
301 hpd.hpd = RADEON_HPD_3;
304 hpd.hpd = RADEON_HPD_4;
307 hpd.hpd = RADEON_HPD_5;
310 hpd.hpd = RADEON_HPD_6;
313 hpd.hpd = RADEON_HPD_NONE;
317 hpd.hpd = RADEON_HPD_NONE;
321 static bool radeon_atom_apply_quirks(struct drm_device *dev,
322 uint32_t supported_device,
324 struct radeon_i2c_bus_rec *i2c_bus,
326 struct radeon_hpd *hpd)
329 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
330 if ((dev->pdev->device == 0x791e) &&
331 (dev->pdev->subsystem_vendor == 0x1043) &&
332 (dev->pdev->subsystem_device == 0x826d)) {
333 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
334 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
335 *connector_type = DRM_MODE_CONNECTOR_DVID;
338 /* Asrock RS600 board lists the DVI port as HDMI */
339 if ((dev->pdev->device == 0x7941) &&
340 (dev->pdev->subsystem_vendor == 0x1849) &&
341 (dev->pdev->subsystem_device == 0x7941)) {
342 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
343 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
344 *connector_type = DRM_MODE_CONNECTOR_DVID;
347 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
348 if ((dev->pdev->device == 0x796e) &&
349 (dev->pdev->subsystem_vendor == 0x1462) &&
350 (dev->pdev->subsystem_device == 0x7302)) {
351 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
352 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
356 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
357 if ((dev->pdev->device == 0x7941) &&
358 (dev->pdev->subsystem_vendor == 0x147b) &&
359 (dev->pdev->subsystem_device == 0x2412)) {
360 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
364 /* Falcon NW laptop lists vga ddc line for LVDS */
365 if ((dev->pdev->device == 0x5653) &&
366 (dev->pdev->subsystem_vendor == 0x1462) &&
367 (dev->pdev->subsystem_device == 0x0291)) {
368 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
369 i2c_bus->valid = false;
374 /* HIS X1300 is DVI+VGA, not DVI+DVI */
375 if ((dev->pdev->device == 0x7146) &&
376 (dev->pdev->subsystem_vendor == 0x17af) &&
377 (dev->pdev->subsystem_device == 0x2058)) {
378 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
382 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
383 if ((dev->pdev->device == 0x7142) &&
384 (dev->pdev->subsystem_vendor == 0x1458) &&
385 (dev->pdev->subsystem_device == 0x2134)) {
386 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
392 if ((dev->pdev->device == 0x71C5) &&
393 (dev->pdev->subsystem_vendor == 0x106b) &&
394 (dev->pdev->subsystem_device == 0x0080)) {
395 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
396 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
398 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
402 /* mac rv630, rv730, others */
403 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
404 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
405 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
406 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
409 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
410 if ((dev->pdev->device == 0x9598) &&
411 (dev->pdev->subsystem_vendor == 0x1043) &&
412 (dev->pdev->subsystem_device == 0x01da)) {
413 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
414 *connector_type = DRM_MODE_CONNECTOR_DVII;
418 /* ASUS HD 3600 board lists the DVI port as HDMI */
419 if ((dev->pdev->device == 0x9598) &&
420 (dev->pdev->subsystem_vendor == 0x1043) &&
421 (dev->pdev->subsystem_device == 0x01e4)) {
422 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
423 *connector_type = DRM_MODE_CONNECTOR_DVII;
427 /* ASUS HD 3450 board lists the DVI port as HDMI */
428 if ((dev->pdev->device == 0x95C5) &&
429 (dev->pdev->subsystem_vendor == 0x1043) &&
430 (dev->pdev->subsystem_device == 0x01e2)) {
431 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
432 *connector_type = DRM_MODE_CONNECTOR_DVII;
436 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
437 * HDMI + VGA reporting as HDMI
439 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
440 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
441 *connector_type = DRM_MODE_CONNECTOR_VGA;
446 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
447 * on the laptop and a DVI port on the docking station and
448 * both share the same encoder, hpd pin, and ddc line.
449 * So while the bios table is technically correct,
450 * we drop the DVI port here since xrandr has no concept of
451 * encoders and will try and drive both connectors
452 * with different crtcs which isn't possible on the hardware
453 * side and leaves no crtcs for LVDS or VGA.
455 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
456 (dev->pdev->subsystem_vendor == 0x1025) &&
457 (dev->pdev->subsystem_device == 0x013c)) {
458 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
459 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
460 /* actually it's a DVI-D port not DVI-I */
461 *connector_type = DRM_MODE_CONNECTOR_DVID;
466 /* XFX Pine Group device rv730 reports no VGA DDC lines
467 * even though they are wired up to record 0x93
469 if ((dev->pdev->device == 0x9498) &&
470 (dev->pdev->subsystem_vendor == 0x1682) &&
471 (dev->pdev->subsystem_device == 0x2452)) {
472 struct radeon_device *rdev = dev->dev_private;
473 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
478 const int supported_devices_connector_convert[] = {
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_VGA,
481 DRM_MODE_CONNECTOR_DVII,
482 DRM_MODE_CONNECTOR_DVID,
483 DRM_MODE_CONNECTOR_DVIA,
484 DRM_MODE_CONNECTOR_SVIDEO,
485 DRM_MODE_CONNECTOR_Composite,
486 DRM_MODE_CONNECTOR_LVDS,
487 DRM_MODE_CONNECTOR_Unknown,
488 DRM_MODE_CONNECTOR_Unknown,
489 DRM_MODE_CONNECTOR_HDMIA,
490 DRM_MODE_CONNECTOR_HDMIB,
491 DRM_MODE_CONNECTOR_Unknown,
492 DRM_MODE_CONNECTOR_Unknown,
493 DRM_MODE_CONNECTOR_9PinDIN,
494 DRM_MODE_CONNECTOR_DisplayPort
497 const uint16_t supported_devices_connector_object_id_convert[] = {
498 CONNECTOR_OBJECT_ID_NONE,
499 CONNECTOR_OBJECT_ID_VGA,
500 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
501 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
502 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
503 CONNECTOR_OBJECT_ID_COMPOSITE,
504 CONNECTOR_OBJECT_ID_SVIDEO,
505 CONNECTOR_OBJECT_ID_LVDS,
506 CONNECTOR_OBJECT_ID_9PIN_DIN,
507 CONNECTOR_OBJECT_ID_9PIN_DIN,
508 CONNECTOR_OBJECT_ID_DISPLAYPORT,
509 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
510 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
511 CONNECTOR_OBJECT_ID_SVIDEO
514 const int object_connector_convert[] = {
515 DRM_MODE_CONNECTOR_Unknown,
516 DRM_MODE_CONNECTOR_DVII,
517 DRM_MODE_CONNECTOR_DVII,
518 DRM_MODE_CONNECTOR_DVID,
519 DRM_MODE_CONNECTOR_DVID,
520 DRM_MODE_CONNECTOR_VGA,
521 DRM_MODE_CONNECTOR_Composite,
522 DRM_MODE_CONNECTOR_SVIDEO,
523 DRM_MODE_CONNECTOR_Unknown,
524 DRM_MODE_CONNECTOR_Unknown,
525 DRM_MODE_CONNECTOR_9PinDIN,
526 DRM_MODE_CONNECTOR_Unknown,
527 DRM_MODE_CONNECTOR_HDMIA,
528 DRM_MODE_CONNECTOR_HDMIB,
529 DRM_MODE_CONNECTOR_LVDS,
530 DRM_MODE_CONNECTOR_9PinDIN,
531 DRM_MODE_CONNECTOR_Unknown,
532 DRM_MODE_CONNECTOR_Unknown,
533 DRM_MODE_CONNECTOR_Unknown,
534 DRM_MODE_CONNECTOR_DisplayPort,
535 DRM_MODE_CONNECTOR_eDP,
536 DRM_MODE_CONNECTOR_Unknown
539 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
541 struct radeon_device *rdev = dev->dev_private;
542 struct radeon_mode_info *mode_info = &rdev->mode_info;
543 struct atom_context *ctx = mode_info->atom_context;
544 int index = GetIndexIntoMasterTable(DATA, Object_Header);
545 u16 size, data_offset;
547 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
548 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
549 ATOM_OBJECT_TABLE *router_obj;
550 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
551 ATOM_OBJECT_HEADER *obj_header;
552 int i, j, k, path_size, device_support;
554 u16 igp_lane_info, conn_id, connector_object_id;
555 struct radeon_i2c_bus_rec ddc_bus;
556 struct radeon_router router;
557 struct radeon_gpio_rec gpio;
558 struct radeon_hpd hpd;
560 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
566 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
567 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
568 (ctx->bios + data_offset +
569 le16_to_cpu(obj_header->usDisplayPathTableOffset));
570 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
571 (ctx->bios + data_offset +
572 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
573 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
574 (ctx->bios + data_offset +
575 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
576 router_obj = (ATOM_OBJECT_TABLE *)
577 (ctx->bios + data_offset +
578 le16_to_cpu(obj_header->usRouterObjectTableOffset));
579 device_support = le16_to_cpu(obj_header->usDeviceSupport);
582 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
583 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
584 ATOM_DISPLAY_OBJECT_PATH *path;
586 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
587 path_size += le16_to_cpu(path->usSize);
589 if (device_support & le16_to_cpu(path->usDeviceTag)) {
590 uint8_t con_obj_id, con_obj_num, con_obj_type;
593 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
596 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
599 (le16_to_cpu(path->usConnObjectId) &
600 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
602 /* TODO CV support */
603 if (le16_to_cpu(path->usDeviceTag) ==
604 ATOM_DEVICE_CV_SUPPORT)
608 if ((rdev->flags & RADEON_IS_IGP) &&
610 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
611 uint16_t igp_offset = 0;
612 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
615 GetIndexIntoMasterTable(DATA,
616 IntegratedSystemInfo);
618 if (atom_parse_data_header(ctx, index, &size, &frev,
619 &crev, &igp_offset)) {
623 (ATOM_INTEGRATED_SYSTEM_INFO_V2
624 *) (ctx->bios + igp_offset);
627 uint32_t slot_config, ct;
629 if (con_obj_num == 1)
638 ct = (slot_config >> 16) & 0xff;
640 object_connector_convert
642 connector_object_id = ct;
644 slot_config & 0xffff;
652 object_connector_convert[con_obj_id];
653 connector_object_id = con_obj_id;
658 object_connector_convert[con_obj_id];
659 connector_object_id = con_obj_id;
662 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
665 router.ddc_valid = false;
666 router.cd_valid = false;
667 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
668 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
671 (le16_to_cpu(path->usGraphicObjIds[j]) &
672 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
674 (le16_to_cpu(path->usGraphicObjIds[j]) &
675 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
677 (le16_to_cpu(path->usGraphicObjIds[j]) &
678 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
680 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
681 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
682 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
683 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
684 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
685 (ctx->bios + data_offset +
686 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
687 ATOM_ENCODER_CAP_RECORD *cap_record;
690 while (record->ucRecordSize > 0 &&
691 record->ucRecordType > 0 &&
692 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
693 switch (record->ucRecordType) {
694 case ATOM_ENCODER_CAP_RECORD_TYPE:
695 cap_record =(ATOM_ENCODER_CAP_RECORD *)
697 caps = le16_to_cpu(cap_record->usEncoderCap);
700 record = (ATOM_COMMON_RECORD_HEADER *)
701 ((char *)record + record->ucRecordSize);
703 radeon_add_atom_encoder(dev,
711 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
712 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
713 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
714 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
715 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
716 (ctx->bios + data_offset +
717 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
718 ATOM_I2C_RECORD *i2c_record;
719 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
720 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
721 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
722 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
723 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
724 (ctx->bios + data_offset +
725 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
728 router.router_id = router_obj_id;
729 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
731 if (le16_to_cpu(path->usConnObjectId) ==
732 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
736 while (record->ucRecordSize > 0 &&
737 record->ucRecordType > 0 &&
738 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
739 switch (record->ucRecordType) {
740 case ATOM_I2C_RECORD_TYPE:
745 (ATOM_I2C_ID_CONFIG_ACCESS *)
746 &i2c_record->sucI2cId;
748 radeon_lookup_i2c_gpio(rdev,
751 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
753 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
754 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
756 router.ddc_valid = true;
757 router.ddc_mux_type = ddc_path->ucMuxType;
758 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
759 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
761 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
762 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
764 router.cd_valid = true;
765 router.cd_mux_type = cd_path->ucMuxType;
766 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
767 router.cd_mux_state = cd_path->ucMuxState[enum_id];
770 record = (ATOM_COMMON_RECORD_HEADER *)
771 ((char *)record + record->ucRecordSize);
778 /* look up gpio for ddc, hpd */
779 ddc_bus.valid = false;
780 hpd.hpd = RADEON_HPD_NONE;
781 if ((le16_to_cpu(path->usDeviceTag) &
782 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
783 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
784 if (le16_to_cpu(path->usConnObjectId) ==
785 le16_to_cpu(con_obj->asObjects[j].
787 ATOM_COMMON_RECORD_HEADER
789 (ATOM_COMMON_RECORD_HEADER
791 (ctx->bios + data_offset +
792 le16_to_cpu(con_obj->
795 ATOM_I2C_RECORD *i2c_record;
796 ATOM_HPD_INT_RECORD *hpd_record;
797 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
799 while (record->ucRecordSize > 0 &&
800 record->ucRecordType > 0 &&
801 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
802 switch (record->ucRecordType) {
803 case ATOM_I2C_RECORD_TYPE:
808 (ATOM_I2C_ID_CONFIG_ACCESS *)
809 &i2c_record->sucI2cId;
810 ddc_bus = radeon_lookup_i2c_gpio(rdev,
814 case ATOM_HPD_INT_RECORD_TYPE:
816 (ATOM_HPD_INT_RECORD *)
818 gpio = radeon_lookup_gpio(rdev,
819 hpd_record->ucHPDIntGPIOID);
820 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
821 hpd.plugged_state = hpd_record->ucPlugged_PinState;
825 (ATOM_COMMON_RECORD_HEADER
836 /* needed for aux chan transactions */
837 ddc_bus.hpd = hpd.hpd;
839 conn_id = le16_to_cpu(path->usConnObjectId);
841 if (!radeon_atom_apply_quirks
842 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
843 &ddc_bus, &conn_id, &hpd))
846 radeon_add_atom_connector(dev,
850 connector_type, &ddc_bus,
859 radeon_link_encoder_connector(dev);
864 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
868 struct radeon_device *rdev = dev->dev_private;
870 if (rdev->flags & RADEON_IS_IGP) {
871 return supported_devices_connector_object_id_convert
873 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
874 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
875 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
876 struct radeon_mode_info *mode_info = &rdev->mode_info;
877 struct atom_context *ctx = mode_info->atom_context;
878 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
879 uint16_t size, data_offset;
881 ATOM_XTMDS_INFO *xtmds;
883 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
884 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
886 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
887 if (connector_type == DRM_MODE_CONNECTOR_DVII)
888 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
890 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
892 if (connector_type == DRM_MODE_CONNECTOR_DVII)
893 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
895 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
898 return supported_devices_connector_object_id_convert
901 return supported_devices_connector_object_id_convert
906 struct bios_connector {
911 struct radeon_i2c_bus_rec ddc_bus;
912 struct radeon_hpd hpd;
915 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
919 struct radeon_device *rdev = dev->dev_private;
920 struct radeon_mode_info *mode_info = &rdev->mode_info;
921 struct atom_context *ctx = mode_info->atom_context;
922 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
923 uint16_t size, data_offset;
925 uint16_t device_support;
927 union atom_supported_devices *supported_devices;
928 int i, j, max_device;
929 struct bios_connector *bios_connectors;
930 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
931 struct radeon_router router;
933 router.ddc_valid = false;
934 router.cd_valid = false;
936 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
937 if (!bios_connectors)
940 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
942 kfree(bios_connectors);
947 (union atom_supported_devices *)(ctx->bios + data_offset);
949 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
952 max_device = ATOM_MAX_SUPPORTED_DEVICE;
954 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
956 for (i = 0; i < max_device; i++) {
957 ATOM_CONNECTOR_INFO_I2C ci =
958 supported_devices->info.asConnInfo[i];
960 bios_connectors[i].valid = false;
962 if (!(device_support & (1 << i))) {
966 if (i == ATOM_DEVICE_CV_INDEX) {
967 DRM_DEBUG_KMS("Skipping Component Video\n");
971 bios_connectors[i].connector_type =
972 supported_devices_connector_convert[ci.sucConnectorInfo.
976 if (bios_connectors[i].connector_type ==
977 DRM_MODE_CONNECTOR_Unknown)
980 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
982 bios_connectors[i].line_mux =
983 ci.sucI2cId.ucAccess;
985 /* give tv unique connector ids */
986 if (i == ATOM_DEVICE_TV1_INDEX) {
987 bios_connectors[i].ddc_bus.valid = false;
988 bios_connectors[i].line_mux = 50;
989 } else if (i == ATOM_DEVICE_TV2_INDEX) {
990 bios_connectors[i].ddc_bus.valid = false;
991 bios_connectors[i].line_mux = 51;
992 } else if (i == ATOM_DEVICE_CV_INDEX) {
993 bios_connectors[i].ddc_bus.valid = false;
994 bios_connectors[i].line_mux = 52;
996 bios_connectors[i].ddc_bus =
997 radeon_lookup_i2c_gpio(rdev,
998 bios_connectors[i].line_mux);
1000 if ((crev > 1) && (frev > 1)) {
1001 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
1004 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1010 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1014 if (i == ATOM_DEVICE_DFP1_INDEX)
1015 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1016 else if (i == ATOM_DEVICE_DFP2_INDEX)
1017 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1019 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1022 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1023 * shared with a DVI port, we'll pick up the DVI connector when we
1024 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1026 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1027 bios_connectors[i].connector_type =
1028 DRM_MODE_CONNECTOR_VGA;
1030 if (!radeon_atom_apply_quirks
1031 (dev, (1 << i), &bios_connectors[i].connector_type,
1032 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1033 &bios_connectors[i].hpd))
1036 bios_connectors[i].valid = true;
1037 bios_connectors[i].devices = (1 << i);
1039 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1040 radeon_add_atom_encoder(dev,
1041 radeon_get_encoder_enum(dev,
1047 radeon_add_legacy_encoder(dev,
1048 radeon_get_encoder_enum(dev,
1054 /* combine shared connectors */
1055 for (i = 0; i < max_device; i++) {
1056 if (bios_connectors[i].valid) {
1057 for (j = 0; j < max_device; j++) {
1058 if (bios_connectors[j].valid && (i != j)) {
1059 if (bios_connectors[i].line_mux ==
1060 bios_connectors[j].line_mux) {
1061 /* make sure not to combine LVDS */
1062 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1063 bios_connectors[i].line_mux = 53;
1064 bios_connectors[i].ddc_bus.valid = false;
1067 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1068 bios_connectors[j].line_mux = 53;
1069 bios_connectors[j].ddc_bus.valid = false;
1072 /* combine analog and digital for DVI-I */
1073 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1074 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1075 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1076 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1077 bios_connectors[i].devices |=
1078 bios_connectors[j].devices;
1079 bios_connectors[i].connector_type =
1080 DRM_MODE_CONNECTOR_DVII;
1081 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1082 bios_connectors[i].hpd =
1083 bios_connectors[j].hpd;
1084 bios_connectors[j].valid = false;
1092 /* add the connectors */
1093 for (i = 0; i < max_device; i++) {
1094 if (bios_connectors[i].valid) {
1095 uint16_t connector_object_id =
1096 atombios_get_connector_object_id(dev,
1097 bios_connectors[i].connector_type,
1098 bios_connectors[i].devices);
1099 radeon_add_atom_connector(dev,
1100 bios_connectors[i].line_mux,
1101 bios_connectors[i].devices,
1104 &bios_connectors[i].ddc_bus,
1106 connector_object_id,
1107 &bios_connectors[i].hpd,
1112 radeon_link_encoder_connector(dev);
1114 kfree(bios_connectors);
1118 union firmware_info {
1119 ATOM_FIRMWARE_INFO info;
1120 ATOM_FIRMWARE_INFO_V1_2 info_12;
1121 ATOM_FIRMWARE_INFO_V1_3 info_13;
1122 ATOM_FIRMWARE_INFO_V1_4 info_14;
1123 ATOM_FIRMWARE_INFO_V2_1 info_21;
1124 ATOM_FIRMWARE_INFO_V2_2 info_22;
1127 bool radeon_atom_get_clock_info(struct drm_device *dev)
1129 struct radeon_device *rdev = dev->dev_private;
1130 struct radeon_mode_info *mode_info = &rdev->mode_info;
1131 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1132 union firmware_info *firmware_info;
1134 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1135 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1136 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1137 struct radeon_pll *spll = &rdev->clock.spll;
1138 struct radeon_pll *mpll = &rdev->clock.mpll;
1139 uint16_t data_offset;
1141 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1142 &frev, &crev, &data_offset)) {
1144 (union firmware_info *)(mode_info->atom_context->bios +
1147 p1pll->reference_freq =
1148 le16_to_cpu(firmware_info->info.usReferenceClock);
1149 p1pll->reference_div = 0;
1152 p1pll->pll_out_min =
1153 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1155 p1pll->pll_out_min =
1156 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1157 p1pll->pll_out_max =
1158 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1161 p1pll->lcd_pll_out_min =
1162 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1163 if (p1pll->lcd_pll_out_min == 0)
1164 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1165 p1pll->lcd_pll_out_max =
1166 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1167 if (p1pll->lcd_pll_out_max == 0)
1168 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1170 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1171 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1174 if (p1pll->pll_out_min == 0) {
1175 if (ASIC_IS_AVIVO(rdev))
1176 p1pll->pll_out_min = 64800;
1178 p1pll->pll_out_min = 20000;
1182 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1184 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1189 if (ASIC_IS_DCE4(rdev))
1190 spll->reference_freq =
1191 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1193 spll->reference_freq =
1194 le16_to_cpu(firmware_info->info.usReferenceClock);
1195 spll->reference_div = 0;
1198 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1200 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1203 if (spll->pll_out_min == 0) {
1204 if (ASIC_IS_AVIVO(rdev))
1205 spll->pll_out_min = 64800;
1207 spll->pll_out_min = 20000;
1211 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1213 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1216 if (ASIC_IS_DCE4(rdev))
1217 mpll->reference_freq =
1218 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1220 mpll->reference_freq =
1221 le16_to_cpu(firmware_info->info.usReferenceClock);
1222 mpll->reference_div = 0;
1225 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1227 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1230 if (mpll->pll_out_min == 0) {
1231 if (ASIC_IS_AVIVO(rdev))
1232 mpll->pll_out_min = 64800;
1234 mpll->pll_out_min = 20000;
1238 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1240 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1242 rdev->clock.default_sclk =
1243 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1244 rdev->clock.default_mclk =
1245 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1247 if (ASIC_IS_DCE4(rdev)) {
1248 rdev->clock.default_dispclk =
1249 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1250 if (rdev->clock.default_dispclk == 0) {
1251 if (ASIC_IS_DCE5(rdev))
1252 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1254 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1256 rdev->clock.dp_extclk =
1257 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1261 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1262 if (rdev->clock.max_pixel_clock == 0)
1263 rdev->clock.max_pixel_clock = 40000;
1272 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1273 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1276 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1278 struct radeon_mode_info *mode_info = &rdev->mode_info;
1279 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1280 union igp_info *igp_info;
1284 /* sideport is AMD only */
1285 if (rdev->family == CHIP_RS600)
1288 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1289 &frev, &crev, &data_offset)) {
1290 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1294 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1298 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1302 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1309 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1310 struct radeon_encoder_int_tmds *tmds)
1312 struct drm_device *dev = encoder->base.dev;
1313 struct radeon_device *rdev = dev->dev_private;
1314 struct radeon_mode_info *mode_info = &rdev->mode_info;
1315 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1316 uint16_t data_offset;
1317 struct _ATOM_TMDS_INFO *tmds_info;
1322 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1323 &frev, &crev, &data_offset)) {
1325 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1328 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1329 for (i = 0; i < 4; i++) {
1330 tmds->tmds_pll[i].freq =
1331 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1332 tmds->tmds_pll[i].value =
1333 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1334 tmds->tmds_pll[i].value |=
1335 (tmds_info->asMiscInfo[i].
1336 ucPLL_VCO_Gain & 0x3f) << 6;
1337 tmds->tmds_pll[i].value |=
1338 (tmds_info->asMiscInfo[i].
1339 ucPLL_DutyCycle & 0xf) << 12;
1340 tmds->tmds_pll[i].value |=
1341 (tmds_info->asMiscInfo[i].
1342 ucPLL_VoltageSwing & 0xf) << 16;
1344 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1345 tmds->tmds_pll[i].freq,
1346 tmds->tmds_pll[i].value);
1348 if (maxfreq == tmds->tmds_pll[i].freq) {
1349 tmds->tmds_pll[i].freq = 0xffffffff;
1358 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1359 struct radeon_atom_ss *ss,
1362 struct radeon_mode_info *mode_info = &rdev->mode_info;
1363 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1364 uint16_t data_offset, size;
1365 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1369 memset(ss, 0, sizeof(struct radeon_atom_ss));
1370 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1371 &frev, &crev, &data_offset)) {
1373 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1375 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1376 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1378 for (i = 0; i < num_indices; i++) {
1379 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1381 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1382 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1383 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1384 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1385 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1386 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1394 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1395 struct radeon_atom_ss *ss,
1398 struct radeon_mode_info *mode_info = &rdev->mode_info;
1399 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1400 u16 data_offset, size;
1401 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1403 u16 percentage = 0, rate = 0;
1405 /* get any igp specific overrides */
1406 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1407 &frev, &crev, &data_offset)) {
1408 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1409 (mode_info->atom_context->bios + data_offset);
1411 case ASIC_INTERNAL_SS_ON_TMDS:
1412 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1413 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1415 case ASIC_INTERNAL_SS_ON_HDMI:
1416 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1417 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1419 case ASIC_INTERNAL_SS_ON_LVDS:
1420 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1421 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1425 ss->percentage = percentage;
1431 union asic_ss_info {
1432 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1433 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1434 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1437 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1438 struct radeon_atom_ss *ss,
1441 struct radeon_mode_info *mode_info = &rdev->mode_info;
1442 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1443 uint16_t data_offset, size;
1444 union asic_ss_info *ss_info;
1448 memset(ss, 0, sizeof(struct radeon_atom_ss));
1449 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1450 &frev, &crev, &data_offset)) {
1453 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1457 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1458 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1460 for (i = 0; i < num_indices; i++) {
1461 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1462 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1464 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1465 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1466 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1472 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1473 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1474 for (i = 0; i < num_indices; i++) {
1475 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1476 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1478 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1479 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1480 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1486 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1487 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1488 for (i = 0; i < num_indices; i++) {
1489 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1490 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1492 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1493 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1494 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1495 if (rdev->flags & RADEON_IS_IGP)
1496 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1502 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1511 struct _ATOM_LVDS_INFO info;
1512 struct _ATOM_LVDS_INFO_V12 info_12;
1515 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1519 struct drm_device *dev = encoder->base.dev;
1520 struct radeon_device *rdev = dev->dev_private;
1521 struct radeon_mode_info *mode_info = &rdev->mode_info;
1522 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1523 uint16_t data_offset, misc;
1524 union lvds_info *lvds_info;
1526 struct radeon_encoder_atom_dig *lvds = NULL;
1527 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1529 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1530 &frev, &crev, &data_offset)) {
1532 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1534 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1539 lvds->native_mode.clock =
1540 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1541 lvds->native_mode.hdisplay =
1542 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1543 lvds->native_mode.vdisplay =
1544 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1545 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1546 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1547 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1548 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1549 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1550 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1551 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1552 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1553 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1554 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1555 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1556 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1557 lvds->panel_pwr_delay =
1558 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1559 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1561 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1562 if (misc & ATOM_VSYNC_POLARITY)
1563 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1564 if (misc & ATOM_HSYNC_POLARITY)
1565 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1566 if (misc & ATOM_COMPOSITESYNC)
1567 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1568 if (misc & ATOM_INTERLACE)
1569 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1570 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1571 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1573 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1574 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1576 /* set crtc values */
1577 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1579 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1581 encoder->native_mode = lvds->native_mode;
1583 if (encoder_enum == 2)
1586 lvds->linkb = false;
1588 /* parse the lcd record table */
1589 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1590 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1591 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1592 bool bad_record = false;
1595 if ((frev == 1) && (crev < 2))
1597 record = (u8 *)(mode_info->atom_context->bios +
1598 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1601 record = (u8 *)(mode_info->atom_context->bios +
1603 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1604 while (*record != ATOM_RECORD_END_TYPE) {
1606 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1607 record += sizeof(ATOM_PATCH_RECORD_MODE);
1609 case LCD_RTS_RECORD_TYPE:
1610 record += sizeof(ATOM_LCD_RTS_RECORD);
1612 case LCD_CAP_RECORD_TYPE:
1613 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1615 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1616 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1617 if (fake_edid_record->ucFakeEDIDLength) {
1620 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1621 edid = kmalloc(edid_size, GFP_KERNEL);
1623 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1624 fake_edid_record->ucFakeEDIDLength);
1626 if (drm_edid_is_valid(edid)) {
1627 rdev->mode_info.bios_hardcoded_edid = edid;
1628 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1633 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1635 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1636 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1637 lvds->native_mode.width_mm = panel_res_record->usHSize;
1638 lvds->native_mode.height_mm = panel_res_record->usVSize;
1639 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1642 DRM_ERROR("Bad LCD record %d\n", *record);
1654 struct radeon_encoder_primary_dac *
1655 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1657 struct drm_device *dev = encoder->base.dev;
1658 struct radeon_device *rdev = dev->dev_private;
1659 struct radeon_mode_info *mode_info = &rdev->mode_info;
1660 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1661 uint16_t data_offset;
1662 struct _COMPASSIONATE_DATA *dac_info;
1665 struct radeon_encoder_primary_dac *p_dac = NULL;
1667 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1668 &frev, &crev, &data_offset)) {
1669 dac_info = (struct _COMPASSIONATE_DATA *)
1670 (mode_info->atom_context->bios + data_offset);
1672 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1677 bg = dac_info->ucDAC1_BG_Adjustment;
1678 dac = dac_info->ucDAC1_DAC_Adjustment;
1679 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1685 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1686 struct drm_display_mode *mode)
1688 struct radeon_mode_info *mode_info = &rdev->mode_info;
1689 ATOM_ANALOG_TV_INFO *tv_info;
1690 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1691 ATOM_DTD_FORMAT *dtd_timings;
1692 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1694 u16 data_offset, misc;
1696 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1697 &frev, &crev, &data_offset))
1702 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1703 if (index >= MAX_SUPPORTED_TV_TIMING)
1706 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1707 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1708 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1709 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1710 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1712 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1713 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1714 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1715 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1716 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1719 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1720 if (misc & ATOM_VSYNC_POLARITY)
1721 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1722 if (misc & ATOM_HSYNC_POLARITY)
1723 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1724 if (misc & ATOM_COMPOSITESYNC)
1725 mode->flags |= DRM_MODE_FLAG_CSYNC;
1726 if (misc & ATOM_INTERLACE)
1727 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1728 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1729 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1731 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1734 /* PAL timings appear to have wrong values for totals */
1735 mode->crtc_htotal -= 1;
1736 mode->crtc_vtotal -= 1;
1740 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1741 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1744 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1745 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1746 le16_to_cpu(dtd_timings->usHBlanking_Time);
1747 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1748 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1749 le16_to_cpu(dtd_timings->usHSyncOffset);
1750 mode->crtc_hsync_end = mode->crtc_hsync_start +
1751 le16_to_cpu(dtd_timings->usHSyncWidth);
1753 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1754 le16_to_cpu(dtd_timings->usVBlanking_Time);
1755 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1756 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1757 le16_to_cpu(dtd_timings->usVSyncOffset);
1758 mode->crtc_vsync_end = mode->crtc_vsync_start +
1759 le16_to_cpu(dtd_timings->usVSyncWidth);
1762 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1763 if (misc & ATOM_VSYNC_POLARITY)
1764 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1765 if (misc & ATOM_HSYNC_POLARITY)
1766 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1767 if (misc & ATOM_COMPOSITESYNC)
1768 mode->flags |= DRM_MODE_FLAG_CSYNC;
1769 if (misc & ATOM_INTERLACE)
1770 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1771 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1772 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1774 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1781 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1783 struct radeon_mode_info *mode_info = &rdev->mode_info;
1784 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1785 uint16_t data_offset;
1787 struct _ATOM_ANALOG_TV_INFO *tv_info;
1788 enum radeon_tv_std tv_std = TV_STD_NTSC;
1790 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1791 &frev, &crev, &data_offset)) {
1793 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1794 (mode_info->atom_context->bios + data_offset);
1796 switch (tv_info->ucTV_BootUpDefaultStandard) {
1798 tv_std = TV_STD_NTSC;
1799 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1802 tv_std = TV_STD_NTSC_J;
1803 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1806 tv_std = TV_STD_PAL;
1807 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1810 tv_std = TV_STD_PAL_M;
1811 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1814 tv_std = TV_STD_PAL_N;
1815 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1818 tv_std = TV_STD_PAL_CN;
1819 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1822 tv_std = TV_STD_PAL_60;
1823 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1826 tv_std = TV_STD_SECAM;
1827 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1830 tv_std = TV_STD_NTSC;
1831 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1838 struct radeon_encoder_tv_dac *
1839 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1841 struct drm_device *dev = encoder->base.dev;
1842 struct radeon_device *rdev = dev->dev_private;
1843 struct radeon_mode_info *mode_info = &rdev->mode_info;
1844 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1845 uint16_t data_offset;
1846 struct _COMPASSIONATE_DATA *dac_info;
1849 struct radeon_encoder_tv_dac *tv_dac = NULL;
1851 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1852 &frev, &crev, &data_offset)) {
1854 dac_info = (struct _COMPASSIONATE_DATA *)
1855 (mode_info->atom_context->bios + data_offset);
1857 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1862 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1863 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1864 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1866 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1867 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1868 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1870 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1871 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1872 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1874 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1879 static const char *thermal_controller_names[] = {
1890 static const char *pp_lib_thermal_controller_names[] = {
1910 struct _ATOM_POWERPLAY_INFO info;
1911 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1912 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1913 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1914 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1915 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1918 union pplib_clock_info {
1919 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1920 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1921 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1922 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1925 union pplib_power_state {
1926 struct _ATOM_PPLIB_STATE v1;
1927 struct _ATOM_PPLIB_STATE_V2 v2;
1930 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1932 u32 misc, u32 misc2)
1934 rdev->pm.power_state[state_index].misc = misc;
1935 rdev->pm.power_state[state_index].misc2 = misc2;
1936 /* order matters! */
1937 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1938 rdev->pm.power_state[state_index].type =
1939 POWER_STATE_TYPE_POWERSAVE;
1940 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1941 rdev->pm.power_state[state_index].type =
1942 POWER_STATE_TYPE_BATTERY;
1943 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1944 rdev->pm.power_state[state_index].type =
1945 POWER_STATE_TYPE_BATTERY;
1946 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1947 rdev->pm.power_state[state_index].type =
1948 POWER_STATE_TYPE_BALANCED;
1949 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1950 rdev->pm.power_state[state_index].type =
1951 POWER_STATE_TYPE_PERFORMANCE;
1952 rdev->pm.power_state[state_index].flags &=
1953 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1955 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1956 rdev->pm.power_state[state_index].type =
1957 POWER_STATE_TYPE_BALANCED;
1958 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1959 rdev->pm.power_state[state_index].type =
1960 POWER_STATE_TYPE_DEFAULT;
1961 rdev->pm.default_power_state_index = state_index;
1962 rdev->pm.power_state[state_index].default_clock_mode =
1963 &rdev->pm.power_state[state_index].clock_info[0];
1964 } else if (state_index == 0) {
1965 rdev->pm.power_state[state_index].clock_info[0].flags |=
1966 RADEON_PM_MODE_NO_DISPLAY;
1970 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1972 struct radeon_mode_info *mode_info = &rdev->mode_info;
1973 u32 misc, misc2 = 0;
1974 int num_modes = 0, i;
1975 int state_index = 0;
1976 struct radeon_i2c_bus_rec i2c_bus;
1977 union power_info *power_info;
1978 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1982 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1983 &frev, &crev, &data_offset))
1985 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1987 /* add the i2c bus for thermal/fan chip */
1988 if (power_info->info.ucOverdriveThermalController > 0) {
1989 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1990 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1991 power_info->info.ucOverdriveControllerAddress >> 1);
1992 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1993 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1994 if (rdev->pm.i2c_bus) {
1995 struct i2c_board_info info = { };
1996 const char *name = thermal_controller_names[power_info->info.
1997 ucOverdriveThermalController];
1998 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1999 strlcpy(info.type, name, sizeof(info.type));
2000 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2003 num_modes = power_info->info.ucNumOfPowerModeEntries;
2004 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2005 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2006 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2007 if (!rdev->pm.power_state)
2009 /* last mode is usually default, array is low to high */
2010 for (i = 0; i < num_modes; i++) {
2011 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2014 rdev->pm.power_state[state_index].num_clock_modes = 1;
2015 rdev->pm.power_state[state_index].clock_info[0].mclk =
2016 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2017 rdev->pm.power_state[state_index].clock_info[0].sclk =
2018 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2019 /* skip invalid modes */
2020 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2021 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2023 rdev->pm.power_state[state_index].pcie_lanes =
2024 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2025 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2026 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2027 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2028 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2030 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2031 radeon_lookup_gpio(rdev,
2032 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2033 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2034 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2037 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2039 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2040 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2042 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2043 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2045 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2046 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2050 rdev->pm.power_state[state_index].num_clock_modes = 1;
2051 rdev->pm.power_state[state_index].clock_info[0].mclk =
2052 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2053 rdev->pm.power_state[state_index].clock_info[0].sclk =
2054 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2055 /* skip invalid modes */
2056 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2057 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2059 rdev->pm.power_state[state_index].pcie_lanes =
2060 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2061 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2062 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2063 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2064 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2065 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2067 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2068 radeon_lookup_gpio(rdev,
2069 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2070 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2071 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2074 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2076 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2077 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2079 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2080 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2082 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2083 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2087 rdev->pm.power_state[state_index].num_clock_modes = 1;
2088 rdev->pm.power_state[state_index].clock_info[0].mclk =
2089 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2090 rdev->pm.power_state[state_index].clock_info[0].sclk =
2091 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2092 /* skip invalid modes */
2093 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2094 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2096 rdev->pm.power_state[state_index].pcie_lanes =
2097 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2098 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2099 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2100 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2101 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2102 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2104 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2105 radeon_lookup_gpio(rdev,
2106 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2107 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2108 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2111 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2113 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2114 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2116 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2117 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2118 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2119 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2121 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2122 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2125 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2126 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2131 /* last mode is usually default */
2132 if (rdev->pm.default_power_state_index == -1) {
2133 rdev->pm.power_state[state_index - 1].type =
2134 POWER_STATE_TYPE_DEFAULT;
2135 rdev->pm.default_power_state_index = state_index - 1;
2136 rdev->pm.power_state[state_index - 1].default_clock_mode =
2137 &rdev->pm.power_state[state_index - 1].clock_info[0];
2138 rdev->pm.power_state[state_index].flags &=
2139 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2140 rdev->pm.power_state[state_index].misc = 0;
2141 rdev->pm.power_state[state_index].misc2 = 0;
2146 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2147 ATOM_PPLIB_THERMALCONTROLLER *controller)
2149 struct radeon_i2c_bus_rec i2c_bus;
2151 /* add the i2c bus for thermal/fan chip */
2152 if (controller->ucType > 0) {
2153 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2154 DRM_INFO("Internal thermal controller %s fan control\n",
2155 (controller->ucFanParameters &
2156 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2157 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2158 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2159 DRM_INFO("Internal thermal controller %s fan control\n",
2160 (controller->ucFanParameters &
2161 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2162 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2163 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2164 DRM_INFO("Internal thermal controller %s fan control\n",
2165 (controller->ucFanParameters &
2166 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2167 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2168 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2169 DRM_INFO("Internal thermal controller %s fan control\n",
2170 (controller->ucFanParameters &
2171 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2172 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2173 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2174 DRM_INFO("Internal thermal controller %s fan control\n",
2175 (controller->ucFanParameters &
2176 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2177 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2178 } else if ((controller->ucType ==
2179 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2180 (controller->ucType ==
2181 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2182 (controller->ucType ==
2183 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2184 DRM_INFO("Special thermal controller config\n");
2186 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2187 pp_lib_thermal_controller_names[controller->ucType],
2188 controller->ucI2cAddress >> 1,
2189 (controller->ucFanParameters &
2190 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2191 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2192 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2193 if (rdev->pm.i2c_bus) {
2194 struct i2c_board_info info = { };
2195 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2196 info.addr = controller->ucI2cAddress >> 1;
2197 strlcpy(info.type, name, sizeof(info.type));
2198 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2204 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2205 u16 *vddc, u16 *vddci)
2207 struct radeon_mode_info *mode_info = &rdev->mode_info;
2208 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2211 union firmware_info *firmware_info;
2216 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2217 &frev, &crev, &data_offset)) {
2219 (union firmware_info *)(mode_info->atom_context->bios +
2221 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2222 if ((frev == 2) && (crev >= 2))
2223 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2227 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2228 int state_index, int mode_index,
2229 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2232 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2233 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2236 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2238 rdev->pm.power_state[state_index].misc = misc;
2239 rdev->pm.power_state[state_index].misc2 = misc2;
2240 rdev->pm.power_state[state_index].pcie_lanes =
2241 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2242 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2243 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2244 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2245 rdev->pm.power_state[state_index].type =
2246 POWER_STATE_TYPE_BATTERY;
2248 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2249 rdev->pm.power_state[state_index].type =
2250 POWER_STATE_TYPE_BALANCED;
2252 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2253 rdev->pm.power_state[state_index].type =
2254 POWER_STATE_TYPE_PERFORMANCE;
2256 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2257 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2258 rdev->pm.power_state[state_index].type =
2259 POWER_STATE_TYPE_PERFORMANCE;
2262 rdev->pm.power_state[state_index].flags = 0;
2263 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2264 rdev->pm.power_state[state_index].flags |=
2265 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2266 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2267 rdev->pm.power_state[state_index].type =
2268 POWER_STATE_TYPE_DEFAULT;
2269 rdev->pm.default_power_state_index = state_index;
2270 rdev->pm.power_state[state_index].default_clock_mode =
2271 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2272 if (ASIC_IS_DCE5(rdev)) {
2273 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2274 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2275 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2276 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2277 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2279 /* patch the table values with the default slck/mclk from firmware info */
2280 for (j = 0; j < mode_index; j++) {
2281 rdev->pm.power_state[state_index].clock_info[j].mclk =
2282 rdev->clock.default_mclk;
2283 rdev->pm.power_state[state_index].clock_info[j].sclk =
2284 rdev->clock.default_sclk;
2286 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2293 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2294 int state_index, int mode_index,
2295 union pplib_clock_info *clock_info)
2299 if (rdev->flags & RADEON_IS_IGP) {
2300 if (rdev->family >= CHIP_PALM) {
2301 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2302 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2303 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2305 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2306 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2307 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2309 } else if (ASIC_IS_DCE4(rdev)) {
2310 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2311 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2312 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2313 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2314 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2315 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2316 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2318 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2319 le16_to_cpu(clock_info->evergreen.usVDDC);
2320 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2321 le16_to_cpu(clock_info->evergreen.usVDDCI);
2323 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2324 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2325 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2326 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2327 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2328 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2329 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2331 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2332 le16_to_cpu(clock_info->r600.usVDDC);
2335 /* patch up vddc if necessary */
2336 if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2339 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2340 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2343 if (rdev->flags & RADEON_IS_IGP) {
2344 /* skip invalid modes */
2345 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2348 /* skip invalid modes */
2349 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2350 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2356 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2358 struct radeon_mode_info *mode_info = &rdev->mode_info;
2359 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2360 union pplib_power_state *power_state;
2362 int state_index = 0, mode_index = 0;
2363 union pplib_clock_info *clock_info;
2365 union power_info *power_info;
2366 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2370 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2371 &frev, &crev, &data_offset))
2373 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2375 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2376 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2377 power_info->pplib.ucNumStates, GFP_KERNEL);
2378 if (!rdev->pm.power_state)
2380 /* first mode is usually default, followed by low to high */
2381 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2383 power_state = (union pplib_power_state *)
2384 (mode_info->atom_context->bios + data_offset +
2385 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2386 i * power_info->pplib.ucStateEntrySize);
2387 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2388 (mode_info->atom_context->bios + data_offset +
2389 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2390 (power_state->v1.ucNonClockStateIndex *
2391 power_info->pplib.ucNonClockSize));
2392 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2393 clock_info = (union pplib_clock_info *)
2394 (mode_info->atom_context->bios + data_offset +
2395 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2396 (power_state->v1.ucClockStateIndices[j] *
2397 power_info->pplib.ucClockInfoSize));
2398 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2399 state_index, mode_index,
2404 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2406 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2411 /* if multiple clock modes, mark the lowest as no display */
2412 for (i = 0; i < state_index; i++) {
2413 if (rdev->pm.power_state[i].num_clock_modes > 1)
2414 rdev->pm.power_state[i].clock_info[0].flags |=
2415 RADEON_PM_MODE_NO_DISPLAY;
2417 /* first mode is usually default */
2418 if (rdev->pm.default_power_state_index == -1) {
2419 rdev->pm.power_state[0].type =
2420 POWER_STATE_TYPE_DEFAULT;
2421 rdev->pm.default_power_state_index = 0;
2422 rdev->pm.power_state[0].default_clock_mode =
2423 &rdev->pm.power_state[0].clock_info[0];
2428 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2430 struct radeon_mode_info *mode_info = &rdev->mode_info;
2431 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2432 union pplib_power_state *power_state;
2433 int i, j, non_clock_array_index, clock_array_index;
2434 int state_index = 0, mode_index = 0;
2435 union pplib_clock_info *clock_info;
2436 struct StateArray *state_array;
2437 struct ClockInfoArray *clock_info_array;
2438 struct NonClockInfoArray *non_clock_info_array;
2440 union power_info *power_info;
2441 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2445 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2446 &frev, &crev, &data_offset))
2448 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2450 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2451 state_array = (struct StateArray *)
2452 (mode_info->atom_context->bios + data_offset +
2453 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2454 clock_info_array = (struct ClockInfoArray *)
2455 (mode_info->atom_context->bios + data_offset +
2456 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2457 non_clock_info_array = (struct NonClockInfoArray *)
2458 (mode_info->atom_context->bios + data_offset +
2459 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2460 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2461 state_array->ucNumEntries, GFP_KERNEL);
2462 if (!rdev->pm.power_state)
2464 for (i = 0; i < state_array->ucNumEntries; i++) {
2466 power_state = (union pplib_power_state *)&state_array->states[i];
2467 /* XXX this might be an inagua bug... */
2468 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2469 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2470 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2471 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2472 clock_array_index = power_state->v2.clockInfoIndex[j];
2473 /* XXX this might be an inagua bug... */
2474 if (clock_array_index >= clock_info_array->ucNumEntries)
2476 clock_info = (union pplib_clock_info *)
2477 &clock_info_array->clockInfo[clock_array_index];
2478 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2479 state_index, mode_index,
2484 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2486 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2491 /* if multiple clock modes, mark the lowest as no display */
2492 for (i = 0; i < state_index; i++) {
2493 if (rdev->pm.power_state[i].num_clock_modes > 1)
2494 rdev->pm.power_state[i].clock_info[0].flags |=
2495 RADEON_PM_MODE_NO_DISPLAY;
2497 /* first mode is usually default */
2498 if (rdev->pm.default_power_state_index == -1) {
2499 rdev->pm.power_state[0].type =
2500 POWER_STATE_TYPE_DEFAULT;
2501 rdev->pm.default_power_state_index = 0;
2502 rdev->pm.power_state[0].default_clock_mode =
2503 &rdev->pm.power_state[0].clock_info[0];
2508 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2510 struct radeon_mode_info *mode_info = &rdev->mode_info;
2511 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2514 int state_index = 0;
2516 rdev->pm.default_power_state_index = -1;
2518 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2519 &frev, &crev, &data_offset)) {
2524 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2528 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2531 state_index = radeon_atombios_parse_power_table_6(rdev);
2537 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2538 if (rdev->pm.power_state) {
2539 /* add the default mode */
2540 rdev->pm.power_state[state_index].type =
2541 POWER_STATE_TYPE_DEFAULT;
2542 rdev->pm.power_state[state_index].num_clock_modes = 1;
2543 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2544 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2545 rdev->pm.power_state[state_index].default_clock_mode =
2546 &rdev->pm.power_state[state_index].clock_info[0];
2547 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2548 rdev->pm.power_state[state_index].pcie_lanes = 16;
2549 rdev->pm.default_power_state_index = state_index;
2550 rdev->pm.power_state[state_index].flags = 0;
2555 rdev->pm.num_power_states = state_index;
2557 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2558 rdev->pm.current_clock_mode_index = 0;
2559 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2562 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2564 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2565 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2567 args.ucEnable = enable;
2569 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2572 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2574 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2575 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2577 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2578 return le32_to_cpu(args.ulReturnEngineClock);
2581 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2583 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2584 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2586 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2587 return le32_to_cpu(args.ulReturnMemoryClock);
2590 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2593 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2594 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2596 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2598 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2601 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2604 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2605 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2607 if (rdev->flags & RADEON_IS_IGP)
2610 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2612 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2616 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2617 struct _SET_VOLTAGE_PARAMETERS v1;
2618 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2621 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2623 union set_voltage args;
2624 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2625 u8 frev, crev, volt_index = voltage_level;
2627 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2630 /* 0xff01 is a flag rather then an actual voltage */
2631 if (voltage_level == 0xff01)
2636 args.v1.ucVoltageType = voltage_type;
2637 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2638 args.v1.ucVoltageIndex = volt_index;
2641 args.v2.ucVoltageType = voltage_type;
2642 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2643 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2646 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2650 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2653 int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2656 union set_voltage args;
2657 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2660 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2667 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2668 args.v2.ucVoltageMode = 0;
2669 args.v2.usVoltageLevel = 0;
2671 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2673 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2676 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2683 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2685 struct radeon_device *rdev = dev->dev_private;
2686 uint32_t bios_2_scratch, bios_6_scratch;
2688 if (rdev->family >= CHIP_R600) {
2689 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2690 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2692 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2693 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2696 /* let the bios control the backlight */
2697 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2699 /* tell the bios not to handle mode switching */
2700 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2702 if (rdev->family >= CHIP_R600) {
2703 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2704 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2706 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2707 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2712 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2714 uint32_t scratch_reg;
2717 if (rdev->family >= CHIP_R600)
2718 scratch_reg = R600_BIOS_0_SCRATCH;
2720 scratch_reg = RADEON_BIOS_0_SCRATCH;
2722 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2723 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2726 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2728 uint32_t scratch_reg;
2731 if (rdev->family >= CHIP_R600)
2732 scratch_reg = R600_BIOS_0_SCRATCH;
2734 scratch_reg = RADEON_BIOS_0_SCRATCH;
2736 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2737 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2740 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2742 struct drm_device *dev = encoder->dev;
2743 struct radeon_device *rdev = dev->dev_private;
2744 uint32_t bios_6_scratch;
2746 if (rdev->family >= CHIP_R600)
2747 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2749 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2752 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2753 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2755 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2756 bios_6_scratch |= ATOM_S6_ACC_MODE;
2759 if (rdev->family >= CHIP_R600)
2760 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2762 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2765 /* at some point we may want to break this out into individual functions */
2767 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2768 struct drm_encoder *encoder,
2771 struct drm_device *dev = connector->dev;
2772 struct radeon_device *rdev = dev->dev_private;
2773 struct radeon_connector *radeon_connector =
2774 to_radeon_connector(connector);
2775 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2776 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2778 if (rdev->family >= CHIP_R600) {
2779 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2780 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2781 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2783 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2784 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2785 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2788 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2789 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2791 DRM_DEBUG_KMS("TV1 connected\n");
2792 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2793 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2795 DRM_DEBUG_KMS("TV1 disconnected\n");
2796 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2797 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2798 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2801 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2802 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2804 DRM_DEBUG_KMS("CV connected\n");
2805 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2806 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2808 DRM_DEBUG_KMS("CV disconnected\n");
2809 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2810 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2811 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2814 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2815 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2817 DRM_DEBUG_KMS("LCD1 connected\n");
2818 bios_0_scratch |= ATOM_S0_LCD1;
2819 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2820 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2822 DRM_DEBUG_KMS("LCD1 disconnected\n");
2823 bios_0_scratch &= ~ATOM_S0_LCD1;
2824 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2825 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2828 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2829 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2831 DRM_DEBUG_KMS("CRT1 connected\n");
2832 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2833 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2834 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2836 DRM_DEBUG_KMS("CRT1 disconnected\n");
2837 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2838 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2839 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2842 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2843 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2845 DRM_DEBUG_KMS("CRT2 connected\n");
2846 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2847 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2848 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2850 DRM_DEBUG_KMS("CRT2 disconnected\n");
2851 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2852 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2853 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2856 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2857 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2859 DRM_DEBUG_KMS("DFP1 connected\n");
2860 bios_0_scratch |= ATOM_S0_DFP1;
2861 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2862 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2864 DRM_DEBUG_KMS("DFP1 disconnected\n");
2865 bios_0_scratch &= ~ATOM_S0_DFP1;
2866 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2867 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2870 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2871 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2873 DRM_DEBUG_KMS("DFP2 connected\n");
2874 bios_0_scratch |= ATOM_S0_DFP2;
2875 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2876 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2878 DRM_DEBUG_KMS("DFP2 disconnected\n");
2879 bios_0_scratch &= ~ATOM_S0_DFP2;
2880 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2881 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2884 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2885 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2887 DRM_DEBUG_KMS("DFP3 connected\n");
2888 bios_0_scratch |= ATOM_S0_DFP3;
2889 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2890 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2892 DRM_DEBUG_KMS("DFP3 disconnected\n");
2893 bios_0_scratch &= ~ATOM_S0_DFP3;
2894 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2895 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2898 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2899 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2901 DRM_DEBUG_KMS("DFP4 connected\n");
2902 bios_0_scratch |= ATOM_S0_DFP4;
2903 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2904 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2906 DRM_DEBUG_KMS("DFP4 disconnected\n");
2907 bios_0_scratch &= ~ATOM_S0_DFP4;
2908 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2909 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2912 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2913 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2915 DRM_DEBUG_KMS("DFP5 connected\n");
2916 bios_0_scratch |= ATOM_S0_DFP5;
2917 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2918 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2920 DRM_DEBUG_KMS("DFP5 disconnected\n");
2921 bios_0_scratch &= ~ATOM_S0_DFP5;
2922 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2923 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2927 if (rdev->family >= CHIP_R600) {
2928 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2929 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2930 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2932 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2933 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2934 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2939 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2941 struct drm_device *dev = encoder->dev;
2942 struct radeon_device *rdev = dev->dev_private;
2943 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2944 uint32_t bios_3_scratch;
2946 if (rdev->family >= CHIP_R600)
2947 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2949 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2951 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2952 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2953 bios_3_scratch |= (crtc << 18);
2955 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2956 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2957 bios_3_scratch |= (crtc << 24);
2959 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2960 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2961 bios_3_scratch |= (crtc << 16);
2963 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2964 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2965 bios_3_scratch |= (crtc << 20);
2967 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2968 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2969 bios_3_scratch |= (crtc << 17);
2971 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2972 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2973 bios_3_scratch |= (crtc << 19);
2975 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2976 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2977 bios_3_scratch |= (crtc << 23);
2979 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2980 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2981 bios_3_scratch |= (crtc << 25);
2984 if (rdev->family >= CHIP_R600)
2985 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2987 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2991 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2993 struct drm_device *dev = encoder->dev;
2994 struct radeon_device *rdev = dev->dev_private;
2995 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2996 uint32_t bios_2_scratch;
2998 if (rdev->family >= CHIP_R600)
2999 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3001 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3003 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3005 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3007 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3009 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3011 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3013 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3015 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3017 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3019 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3021 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3023 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3025 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3027 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3029 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3031 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3033 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3035 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3037 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3039 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3041 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3043 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3045 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3047 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3049 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3051 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3053 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3055 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3057 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3059 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3061 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3064 if (rdev->family >= CHIP_R600)
3065 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3067 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);