2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "radeon_reg.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
35 #include <linux/acpi.h>
40 /* If you boot an IGP board with a discrete card as the primary,
41 * the IGP rom is not accessible via the rom bar as the IGP rom is
42 * part of the system bios. On boot, the system bios puts a
43 * copy of the igp rom at the start of vram if a discrete card is
46 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
48 uint8_t __iomem *bios;
49 resource_size_t vram_base;
50 resource_size_t size = 256 * 1024; /* ??? */
52 if (!(rdev->flags & RADEON_IS_IGP))
53 if (!radeon_card_posted(rdev))
57 vram_base = pci_resource_start(rdev->pdev, 0);
58 bios = ioremap(vram_base, size);
63 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
67 rdev->bios = kmalloc(size, GFP_KERNEL);
68 if (rdev->bios == NULL) {
72 memcpy_fromio(rdev->bios, bios, size);
77 static bool radeon_read_bios(struct radeon_device *rdev)
79 uint8_t __iomem *bios;
83 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
84 bios = pci_map_rom(rdev->pdev, &size);
89 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
90 pci_unmap_rom(rdev->pdev, bios);
93 rdev->bios = kmemdup(bios, size, GFP_KERNEL);
94 if (rdev->bios == NULL) {
95 pci_unmap_rom(rdev->pdev, bios);
98 pci_unmap_rom(rdev->pdev, bios);
103 /* ATRM is used to get the BIOS on the discrete cards in
106 /* retrieve the ROM in 4k blocks */
107 #define ATRM_BIOS_PAGE 4096
109 * radeon_atrm_call - fetch a chunk of the vbios
111 * @atrm_handle: acpi ATRM handle
112 * @bios: vbios image pointer
113 * @offset: offset of vbios image data to fetch
114 * @len: length of vbios image data to fetch
116 * Executes ATRM to fetch a chunk of the discrete
117 * vbios image on PX systems (all asics).
118 * Returns the length of the buffer fetched.
120 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
124 union acpi_object atrm_arg_elements[2], *obj;
125 struct acpi_object_list atrm_arg;
126 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
129 atrm_arg.pointer = &atrm_arg_elements[0];
131 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
132 atrm_arg_elements[0].integer.value = offset;
134 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
135 atrm_arg_elements[1].integer.value = len;
137 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
138 if (ACPI_FAILURE(status)) {
139 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
143 obj = (union acpi_object *)buffer.pointer;
144 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
145 len = obj->buffer.length;
146 kfree(buffer.pointer);
150 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
153 int size = 256 * 1024;
155 struct pci_dev *pdev = NULL;
156 acpi_handle dhandle, atrm_handle;
160 /* ATRM is for the discrete card only */
161 if (rdev->flags & RADEON_IS_IGP)
164 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
165 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
169 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
170 if (!ACPI_FAILURE(status)) {
179 rdev->bios = kmalloc(size, GFP_KERNEL);
181 DRM_ERROR("Unable to allocate bios\n");
185 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
186 ret = radeon_atrm_call(atrm_handle,
188 (i * ATRM_BIOS_PAGE),
190 if (ret < ATRM_BIOS_PAGE)
194 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
201 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
207 static bool ni_read_disabled_bios(struct radeon_device *rdev)
212 u32 vga_render_control;
216 bus_cntl = RREG32(R600_BUS_CNTL);
217 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
218 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
219 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
220 rom_cntl = RREG32(R600_ROM_CNTL);
223 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
224 if (!ASIC_IS_NODCE(rdev)) {
225 /* Disable VGA mode */
226 WREG32(AVIVO_D1VGA_CONTROL,
227 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
228 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
229 WREG32(AVIVO_D2VGA_CONTROL,
230 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
231 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
232 WREG32(AVIVO_VGA_RENDER_CONTROL,
233 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
235 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
237 r = radeon_read_bios(rdev);
240 WREG32(R600_BUS_CNTL, bus_cntl);
241 if (!ASIC_IS_NODCE(rdev)) {
242 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
243 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
244 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
246 WREG32(R600_ROM_CNTL, rom_cntl);
250 static bool r700_read_disabled_bios(struct radeon_device *rdev)
252 uint32_t viph_control;
254 uint32_t d1vga_control;
255 uint32_t d2vga_control;
256 uint32_t vga_render_control;
258 uint32_t cg_spll_func_cntl = 0;
259 uint32_t cg_spll_status;
262 viph_control = RREG32(RADEON_VIPH_CONTROL);
263 bus_cntl = RREG32(R600_BUS_CNTL);
264 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
265 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
266 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
267 rom_cntl = RREG32(R600_ROM_CNTL);
270 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
272 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
273 /* Disable VGA mode */
274 WREG32(AVIVO_D1VGA_CONTROL,
275 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
276 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
277 WREG32(AVIVO_D2VGA_CONTROL,
278 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
279 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
280 WREG32(AVIVO_VGA_RENDER_CONTROL,
281 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
283 if (rdev->family == CHIP_RV730) {
284 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
286 /* enable bypass mode */
287 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
288 R600_SPLL_BYPASS_EN));
290 /* wait for SPLL_CHG_STATUS to change to 1 */
292 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
293 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
295 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
297 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
299 r = radeon_read_bios(rdev);
302 if (rdev->family == CHIP_RV730) {
303 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
305 /* wait for SPLL_CHG_STATUS to change to 1 */
307 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
308 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
310 WREG32(RADEON_VIPH_CONTROL, viph_control);
311 WREG32(R600_BUS_CNTL, bus_cntl);
312 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
313 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
314 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
315 WREG32(R600_ROM_CNTL, rom_cntl);
319 static bool r600_read_disabled_bios(struct radeon_device *rdev)
321 uint32_t viph_control;
323 uint32_t d1vga_control;
324 uint32_t d2vga_control;
325 uint32_t vga_render_control;
327 uint32_t general_pwrmgt;
328 uint32_t low_vid_lower_gpio_cntl;
329 uint32_t medium_vid_lower_gpio_cntl;
330 uint32_t high_vid_lower_gpio_cntl;
331 uint32_t ctxsw_vid_lower_gpio_cntl;
332 uint32_t lower_gpio_enable;
335 viph_control = RREG32(RADEON_VIPH_CONTROL);
336 bus_cntl = RREG32(R600_BUS_CNTL);
337 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
338 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
339 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
340 rom_cntl = RREG32(R600_ROM_CNTL);
341 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
342 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
343 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
344 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
345 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
346 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
349 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
351 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
352 /* Disable VGA mode */
353 WREG32(AVIVO_D1VGA_CONTROL,
354 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
355 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
356 WREG32(AVIVO_D2VGA_CONTROL,
357 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
358 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
359 WREG32(AVIVO_VGA_RENDER_CONTROL,
360 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
362 WREG32(R600_ROM_CNTL,
363 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
364 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
365 R600_SCK_OVERWRITE));
367 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
368 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
369 (low_vid_lower_gpio_cntl & ~0x400));
370 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
371 (medium_vid_lower_gpio_cntl & ~0x400));
372 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
373 (high_vid_lower_gpio_cntl & ~0x400));
374 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
375 (ctxsw_vid_lower_gpio_cntl & ~0x400));
376 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
378 r = radeon_read_bios(rdev);
381 WREG32(RADEON_VIPH_CONTROL, viph_control);
382 WREG32(R600_BUS_CNTL, bus_cntl);
383 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
384 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
385 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
386 WREG32(R600_ROM_CNTL, rom_cntl);
387 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
388 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
389 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
390 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
391 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
392 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
396 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
398 uint32_t seprom_cntl1;
399 uint32_t viph_control;
401 uint32_t d1vga_control;
402 uint32_t d2vga_control;
403 uint32_t vga_render_control;
406 uint32_t gpiopad_mask;
409 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
410 viph_control = RREG32(RADEON_VIPH_CONTROL);
411 bus_cntl = RREG32(RV370_BUS_CNTL);
412 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
413 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
414 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
415 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
416 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
417 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
419 WREG32(RADEON_SEPROM_CNTL1,
420 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
421 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
422 WREG32(RADEON_GPIOPAD_A, 0);
423 WREG32(RADEON_GPIOPAD_EN, 0);
424 WREG32(RADEON_GPIOPAD_MASK, 0);
427 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
430 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
432 /* Disable VGA mode */
433 WREG32(AVIVO_D1VGA_CONTROL,
434 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
435 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
436 WREG32(AVIVO_D2VGA_CONTROL,
437 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
438 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
439 WREG32(AVIVO_VGA_RENDER_CONTROL,
440 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
442 r = radeon_read_bios(rdev);
445 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
446 WREG32(RADEON_VIPH_CONTROL, viph_control);
447 WREG32(RV370_BUS_CNTL, bus_cntl);
448 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
449 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
450 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
451 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
452 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
453 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
457 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
459 uint32_t seprom_cntl1;
460 uint32_t viph_control;
462 uint32_t crtc_gen_cntl;
463 uint32_t crtc2_gen_cntl;
464 uint32_t crtc_ext_cntl;
465 uint32_t fp2_gen_cntl;
468 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
469 viph_control = RREG32(RADEON_VIPH_CONTROL);
470 if (rdev->flags & RADEON_IS_PCIE)
471 bus_cntl = RREG32(RV370_BUS_CNTL);
473 bus_cntl = RREG32(RADEON_BUS_CNTL);
474 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
476 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
479 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
480 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
483 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
484 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
487 WREG32(RADEON_SEPROM_CNTL1,
488 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
489 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
492 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
495 if (rdev->flags & RADEON_IS_PCIE)
496 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
498 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
500 /* Turn off mem requests and CRTC for both controllers */
501 WREG32(RADEON_CRTC_GEN_CNTL,
502 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
503 (RADEON_CRTC_DISP_REQ_EN_B |
504 RADEON_CRTC_EXT_DISP_EN)));
505 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
506 WREG32(RADEON_CRTC2_GEN_CNTL,
507 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
508 RADEON_CRTC2_DISP_REQ_EN_B));
511 WREG32(RADEON_CRTC_EXT_CNTL,
512 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
513 (RADEON_CRTC_SYNC_TRISTAT |
514 RADEON_CRTC_DISPLAY_DIS)));
516 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
517 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
520 r = radeon_read_bios(rdev);
523 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
524 WREG32(RADEON_VIPH_CONTROL, viph_control);
525 if (rdev->flags & RADEON_IS_PCIE)
526 WREG32(RV370_BUS_CNTL, bus_cntl);
528 WREG32(RADEON_BUS_CNTL, bus_cntl);
529 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
530 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
531 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
533 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
534 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
535 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
540 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
542 if (rdev->flags & RADEON_IS_IGP)
543 return igp_read_bios_from_vram(rdev);
544 else if (rdev->family >= CHIP_BARTS)
545 return ni_read_disabled_bios(rdev);
546 else if (rdev->family >= CHIP_RV770)
547 return r700_read_disabled_bios(rdev);
548 else if (rdev->family >= CHIP_R600)
549 return r600_read_disabled_bios(rdev);
550 else if (rdev->family >= CHIP_RS600)
551 return avivo_read_disabled_bios(rdev);
553 return legacy_read_disabled_bios(rdev);
557 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
560 struct acpi_table_header *hdr;
562 UEFI_ACPI_VFCT *vfct;
563 GOP_VBIOS_CONTENT *vbios;
564 VFCT_IMAGE_HEADER *vhdr;
566 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
568 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
569 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
573 vfct = (UEFI_ACPI_VFCT *)hdr;
574 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
575 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
579 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
580 vhdr = &vbios->VbiosHeader;
581 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
582 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
583 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
585 if (vhdr->PCIBus != rdev->pdev->bus->number ||
586 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
587 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
588 vhdr->VendorID != rdev->pdev->vendor ||
589 vhdr->DeviceID != rdev->pdev->device) {
590 DRM_INFO("ACPI VFCT table is not for this card\n");
594 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
595 DRM_ERROR("ACPI VFCT image truncated\n");
599 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
606 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
612 bool radeon_get_bios(struct radeon_device *rdev)
617 r = radeon_atrm_get_bios(rdev);
619 r = radeon_acpi_vfct_bios(rdev);
621 r = igp_read_bios_from_vram(rdev);
623 r = radeon_read_bios(rdev);
625 r = radeon_read_disabled_bios(rdev);
627 if (r == false || rdev->bios == NULL) {
628 DRM_ERROR("Unable to locate a BIOS ROM\n");
632 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
633 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
638 if (RBIOS8(tmp + 0x14) != 0x0) {
639 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
643 rdev->bios_header_start = RBIOS16(0x48);
644 if (!rdev->bios_header_start) {
647 tmp = rdev->bios_header_start + 4;
648 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
649 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
650 rdev->is_atom_bios = true;
652 rdev->is_atom_bios = false;
655 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");