2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
114 enum radeon_combios_ddc {
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
149 struct radeon_device *rdev = dev->dev_private;
151 uint16_t offset = 0, check_offset;
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
161 offset = check_offset;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
166 offset = check_offset;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
171 offset = check_offset;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
176 offset = check_offset;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
181 offset = check_offset;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
186 offset = check_offset;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
191 offset = check_offset;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
196 offset = check_offset;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
201 offset = check_offset;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
206 offset = check_offset;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
211 offset = check_offset;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
216 offset = check_offset;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
221 offset = check_offset;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
226 offset = check_offset;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
231 offset = check_offset;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
236 offset = check_offset;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
241 offset = check_offset;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
246 offset = check_offset;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
251 offset = check_offset;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
256 offset = check_offset;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
261 offset = check_offset;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
266 offset = check_offset;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
271 offset = check_offset;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
276 offset = check_offset;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
281 offset = check_offset;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
286 offset = check_offset;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
291 offset = check_offset;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
296 offset = check_offset;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
301 offset = check_offset;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
306 offset = check_offset;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
311 offset = check_offset;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
316 offset = check_offset;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
321 offset = check_offset;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
326 offset = check_offset;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
333 rev = RBIOS8(check_offset);
335 check_offset = RBIOS16(check_offset + 0x3);
337 offset = check_offset;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
345 rev = RBIOS8(check_offset);
347 check_offset = RBIOS16(check_offset + 0x5);
349 offset = check_offset;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
357 rev = RBIOS8(check_offset);
359 check_offset = RBIOS16(check_offset + 0x7);
361 offset = check_offset;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
369 rev = RBIOS8(check_offset);
371 check_offset = RBIOS16(check_offset + 0x9);
373 offset = check_offset;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
381 while (RBIOS8(check_offset++));
384 offset = check_offset;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
391 check_offset = RBIOS16(check_offset + 0x11);
393 offset = check_offset;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
400 check_offset = RBIOS16(check_offset + 0x13);
402 offset = check_offset;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
409 check_offset = RBIOS16(check_offset + 0x15);
411 offset = check_offset;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
418 check_offset = RBIOS16(check_offset + 0x17);
420 offset = check_offset;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
427 check_offset = RBIOS16(check_offset + 0x2);
429 offset = check_offset;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
436 check_offset = RBIOS16(check_offset + 0x4);
438 offset = check_offset;
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
458 raw = rdev->bios + edid_info;
459 edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
463 memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
465 if (!drm_edid_is_valid(edid)) {
470 rdev->mode_info.bios_hardcoded_edid = edid;
474 /* this is used for atom LCDs as well */
476 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
478 if (rdev->mode_info.bios_hardcoded_edid)
479 return rdev->mode_info.bios_hardcoded_edid;
483 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
484 enum radeon_combios_ddc ddc,
488 struct radeon_i2c_bus_rec i2c;
492 * DDC_NONE_DETECTED = none
493 * DDC_DVI = RADEON_GPIO_DVI_DDC
494 * DDC_VGA = RADEON_GPIO_VGA_DDC
495 * DDC_LCD = RADEON_GPIOPAD_MASK
496 * DDC_GPIO = RADEON_MDGPIO_MASK
498 * DDC_MONID = RADEON_GPIO_MONID
499 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
501 * DDC_MONID = RADEON_GPIO_MONID
502 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
504 * DDC_MONID = RADEON_GPIOPAD_MASK
505 * DDC_CRT2 = RADEON_GPIO_MONID
508 case DDC_NONE_DETECTED:
513 ddc_line = RADEON_GPIO_DVI_DDC;
516 ddc_line = RADEON_GPIO_VGA_DDC;
519 ddc_line = RADEON_GPIOPAD_MASK;
522 ddc_line = RADEON_MDGPIO_MASK;
525 if (rdev->family == CHIP_RS300 ||
526 rdev->family == CHIP_RS400 ||
527 rdev->family == CHIP_RS480)
528 ddc_line = RADEON_GPIOPAD_MASK;
530 ddc_line = RADEON_GPIO_MONID;
533 if (rdev->family == CHIP_RS300 ||
534 rdev->family == CHIP_RS400 ||
535 rdev->family == CHIP_RS480)
536 ddc_line = RADEON_GPIO_MONID;
537 else if (rdev->family >= CHIP_R300) {
538 ddc_line = RADEON_GPIO_DVI_DDC;
541 ddc_line = RADEON_GPIO_CRT2_DDC;
545 if (ddc_line == RADEON_GPIOPAD_MASK) {
546 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
547 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
548 i2c.a_clk_reg = RADEON_GPIOPAD_A;
549 i2c.a_data_reg = RADEON_GPIOPAD_A;
550 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
551 i2c.en_data_reg = RADEON_GPIOPAD_EN;
552 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
553 i2c.y_data_reg = RADEON_GPIOPAD_Y;
554 } else if (ddc_line == RADEON_MDGPIO_MASK) {
555 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
556 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
557 i2c.a_clk_reg = RADEON_MDGPIO_A;
558 i2c.a_data_reg = RADEON_MDGPIO_A;
559 i2c.en_clk_reg = RADEON_MDGPIO_EN;
560 i2c.en_data_reg = RADEON_MDGPIO_EN;
561 i2c.y_clk_reg = RADEON_MDGPIO_Y;
562 i2c.y_data_reg = RADEON_MDGPIO_Y;
564 i2c.mask_clk_reg = ddc_line;
565 i2c.mask_data_reg = ddc_line;
566 i2c.a_clk_reg = ddc_line;
567 i2c.a_data_reg = ddc_line;
568 i2c.en_clk_reg = ddc_line;
569 i2c.en_data_reg = ddc_line;
570 i2c.y_clk_reg = ddc_line;
571 i2c.y_data_reg = ddc_line;
574 if (clk_mask && data_mask) {
575 /* system specific masks */
576 i2c.mask_clk_mask = clk_mask;
577 i2c.mask_data_mask = data_mask;
578 i2c.a_clk_mask = clk_mask;
579 i2c.a_data_mask = data_mask;
580 i2c.en_clk_mask = clk_mask;
581 i2c.en_data_mask = data_mask;
582 i2c.y_clk_mask = clk_mask;
583 i2c.y_data_mask = data_mask;
584 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
585 (ddc_line == RADEON_MDGPIO_MASK)) {
586 /* default gpiopad masks */
587 i2c.mask_clk_mask = (0x20 << 8);
588 i2c.mask_data_mask = 0x80;
589 i2c.a_clk_mask = (0x20 << 8);
590 i2c.a_data_mask = 0x80;
591 i2c.en_clk_mask = (0x20 << 8);
592 i2c.en_data_mask = 0x80;
593 i2c.y_clk_mask = (0x20 << 8);
594 i2c.y_data_mask = 0x80;
596 /* default masks for ddc pads */
597 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
598 i2c.mask_data_mask = RADEON_GPIO_EN_0;
599 i2c.a_clk_mask = RADEON_GPIO_A_1;
600 i2c.a_data_mask = RADEON_GPIO_A_0;
601 i2c.en_clk_mask = RADEON_GPIO_EN_1;
602 i2c.en_data_mask = RADEON_GPIO_EN_0;
603 i2c.y_clk_mask = RADEON_GPIO_Y_1;
604 i2c.y_data_mask = RADEON_GPIO_Y_0;
607 switch (rdev->family) {
615 case RADEON_GPIO_DVI_DDC:
616 i2c.hw_capable = true;
619 i2c.hw_capable = false;
625 case RADEON_GPIO_DVI_DDC:
626 case RADEON_GPIO_MONID:
627 i2c.hw_capable = true;
630 i2c.hw_capable = false;
637 case RADEON_GPIO_VGA_DDC:
638 case RADEON_GPIO_DVI_DDC:
639 case RADEON_GPIO_CRT2_DDC:
640 i2c.hw_capable = true;
643 i2c.hw_capable = false;
650 case RADEON_GPIO_VGA_DDC:
651 case RADEON_GPIO_DVI_DDC:
652 i2c.hw_capable = true;
655 i2c.hw_capable = false;
664 case RADEON_GPIO_VGA_DDC:
665 case RADEON_GPIO_DVI_DDC:
666 i2c.hw_capable = true;
668 case RADEON_GPIO_MONID:
669 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
670 * reliably on some pre-r4xx hardware; not sure why.
672 i2c.hw_capable = false;
675 i2c.hw_capable = false;
680 i2c.hw_capable = false;
686 i2c.hpd = RADEON_HPD_NONE;
696 void radeon_combios_i2c_init(struct radeon_device *rdev)
698 struct drm_device *dev = rdev->ddev;
699 struct radeon_i2c_bus_rec i2c;
702 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
703 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
705 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
706 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
709 i2c.hw_capable = true;
712 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
714 if (rdev->family == CHIP_RS300 ||
715 rdev->family == CHIP_RS400 ||
716 rdev->family == CHIP_RS480) {
718 u8 id, blocks, clk, data;
721 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
722 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
724 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
726 blocks = RBIOS8(offset + 2);
727 for (i = 0; i < blocks; i++) {
728 id = RBIOS8(offset + 3 + (i * 5) + 0);
730 clk = RBIOS8(offset + 3 + (i * 5) + 3);
731 data = RBIOS8(offset + 3 + (i * 5) + 4);
732 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
733 (1 << clk), (1 << data));
734 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
740 } else if (rdev->family >= CHIP_R300) {
741 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
742 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
744 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
745 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
747 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
748 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
752 bool radeon_combios_get_clock_info(struct drm_device *dev)
754 struct radeon_device *rdev = dev->dev_private;
756 struct radeon_pll *p1pll = &rdev->clock.p1pll;
757 struct radeon_pll *p2pll = &rdev->clock.p2pll;
758 struct radeon_pll *spll = &rdev->clock.spll;
759 struct radeon_pll *mpll = &rdev->clock.mpll;
763 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
765 rev = RBIOS8(pll_info);
768 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
769 p1pll->reference_div = RBIOS16(pll_info + 0x10);
770 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
771 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
772 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
773 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
776 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
777 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
779 p1pll->pll_in_min = 40;
780 p1pll->pll_in_max = 500;
785 spll->reference_freq = RBIOS16(pll_info + 0x1a);
786 spll->reference_div = RBIOS16(pll_info + 0x1c);
787 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
788 spll->pll_out_max = RBIOS32(pll_info + 0x22);
791 spll->pll_in_min = RBIOS32(pll_info + 0x48);
792 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
795 spll->pll_in_min = 40;
796 spll->pll_in_max = 500;
800 mpll->reference_freq = RBIOS16(pll_info + 0x26);
801 mpll->reference_div = RBIOS16(pll_info + 0x28);
802 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
803 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
806 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
807 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
810 mpll->pll_in_min = 40;
811 mpll->pll_in_max = 500;
814 /* default sclk/mclk */
815 sclk = RBIOS16(pll_info + 0xa);
816 mclk = RBIOS16(pll_info + 0x8);
822 rdev->clock.default_sclk = sclk;
823 rdev->clock.default_mclk = mclk;
830 bool radeon_combios_sideport_present(struct radeon_device *rdev)
832 struct drm_device *dev = rdev->ddev;
835 /* sideport is AMD only */
836 if (rdev->family == CHIP_RS400)
839 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
842 if (RBIOS16(igp_info + 0x4))
848 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
849 0x00000808, /* r100 */
850 0x00000808, /* rv100 */
851 0x00000808, /* rs100 */
852 0x00000808, /* rv200 */
853 0x00000808, /* rs200 */
854 0x00000808, /* r200 */
855 0x00000808, /* rv250 */
856 0x00000000, /* rs300 */
857 0x00000808, /* rv280 */
858 0x00000808, /* r300 */
859 0x00000808, /* r350 */
860 0x00000808, /* rv350 */
861 0x00000808, /* rv380 */
862 0x00000808, /* r420 */
863 0x00000808, /* r423 */
864 0x00000808, /* rv410 */
865 0x00000000, /* rs400 */
866 0x00000000, /* rs480 */
869 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
870 struct radeon_encoder_primary_dac *p_dac)
872 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
876 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
880 struct drm_device *dev = encoder->base.dev;
881 struct radeon_device *rdev = dev->dev_private;
883 uint8_t rev, bg, dac;
884 struct radeon_encoder_primary_dac *p_dac = NULL;
887 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
893 /* check CRT table */
894 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
896 rev = RBIOS8(dac_info) & 0x3;
898 bg = RBIOS8(dac_info + 0x2) & 0xf;
899 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
900 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
902 bg = RBIOS8(dac_info + 0x2) & 0xf;
903 dac = RBIOS8(dac_info + 0x3) & 0xf;
904 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
906 /* if the values are all zeros, use the table */
907 if (p_dac->ps2_pdac_adj)
911 if (!found) /* fallback to defaults */
912 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
918 radeon_combios_get_tv_info(struct radeon_device *rdev)
920 struct drm_device *dev = rdev->ddev;
922 enum radeon_tv_std tv_std = TV_STD_NTSC;
924 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
926 if (RBIOS8(tv_info + 6) == 'T') {
927 switch (RBIOS8(tv_info + 7) & 0xf) {
929 tv_std = TV_STD_NTSC;
930 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
934 DRM_DEBUG_KMS("Default TV standard: PAL\n");
937 tv_std = TV_STD_PAL_M;
938 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
941 tv_std = TV_STD_PAL_60;
942 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
945 tv_std = TV_STD_NTSC_J;
946 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
949 tv_std = TV_STD_SCART_PAL;
950 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
953 tv_std = TV_STD_NTSC;
955 ("Unknown TV standard; defaulting to NTSC\n");
959 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
961 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
964 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
967 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
970 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
980 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
981 0x00000000, /* r100 */
982 0x00280000, /* rv100 */
983 0x00000000, /* rs100 */
984 0x00880000, /* rv200 */
985 0x00000000, /* rs200 */
986 0x00000000, /* r200 */
987 0x00770000, /* rv250 */
988 0x00290000, /* rs300 */
989 0x00560000, /* rv280 */
990 0x00780000, /* r300 */
991 0x00770000, /* r350 */
992 0x00780000, /* rv350 */
993 0x00780000, /* rv380 */
994 0x01080000, /* r420 */
995 0x01080000, /* r423 */
996 0x01080000, /* rv410 */
997 0x00780000, /* rs400 */
998 0x00780000, /* rs480 */
1001 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1002 struct radeon_encoder_tv_dac *tv_dac)
1004 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1005 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1006 tv_dac->ps2_tvdac_adj = 0x00880000;
1007 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1008 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1012 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1016 struct drm_device *dev = encoder->base.dev;
1017 struct radeon_device *rdev = dev->dev_private;
1019 uint8_t rev, bg, dac;
1020 struct radeon_encoder_tv_dac *tv_dac = NULL;
1023 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1027 /* first check TV table */
1028 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1030 rev = RBIOS8(dac_info + 0x3);
1032 bg = RBIOS8(dac_info + 0xc) & 0xf;
1033 dac = RBIOS8(dac_info + 0xd) & 0xf;
1034 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1036 bg = RBIOS8(dac_info + 0xe) & 0xf;
1037 dac = RBIOS8(dac_info + 0xf) & 0xf;
1038 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1040 bg = RBIOS8(dac_info + 0x10) & 0xf;
1041 dac = RBIOS8(dac_info + 0x11) & 0xf;
1042 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1043 /* if the values are all zeros, use the table */
1044 if (tv_dac->ps2_tvdac_adj)
1046 } else if (rev > 1) {
1047 bg = RBIOS8(dac_info + 0xc) & 0xf;
1048 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1049 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1051 bg = RBIOS8(dac_info + 0xd) & 0xf;
1052 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1053 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1055 bg = RBIOS8(dac_info + 0xe) & 0xf;
1056 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1057 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1058 /* if the values are all zeros, use the table */
1059 if (tv_dac->ps2_tvdac_adj)
1062 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1065 /* then check CRT table */
1067 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1069 rev = RBIOS8(dac_info) & 0x3;
1071 bg = RBIOS8(dac_info + 0x3) & 0xf;
1072 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1073 tv_dac->ps2_tvdac_adj =
1074 (bg << 16) | (dac << 20);
1075 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1076 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1077 /* if the values are all zeros, use the table */
1078 if (tv_dac->ps2_tvdac_adj)
1081 bg = RBIOS8(dac_info + 0x4) & 0xf;
1082 dac = RBIOS8(dac_info + 0x5) & 0xf;
1083 tv_dac->ps2_tvdac_adj =
1084 (bg << 16) | (dac << 20);
1085 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1086 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1087 /* if the values are all zeros, use the table */
1088 if (tv_dac->ps2_tvdac_adj)
1092 DRM_INFO("No TV DAC info found in BIOS\n");
1096 if (!found) /* fallback to defaults */
1097 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1102 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1106 struct radeon_encoder_lvds *lvds = NULL;
1107 uint32_t fp_vert_stretch, fp_horz_stretch;
1108 uint32_t ppll_div_sel, ppll_val;
1109 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1111 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1116 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1117 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1119 /* These should be fail-safe defaults, fingers crossed */
1120 lvds->panel_pwr_delay = 200;
1121 lvds->panel_vcc_delay = 2000;
1123 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1124 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1125 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1127 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1128 lvds->native_mode.vdisplay =
1129 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1130 RADEON_VERT_PANEL_SHIFT) + 1;
1132 lvds->native_mode.vdisplay =
1133 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1135 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1136 lvds->native_mode.hdisplay =
1137 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1138 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1140 lvds->native_mode.hdisplay =
1141 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1143 if ((lvds->native_mode.hdisplay < 640) ||
1144 (lvds->native_mode.vdisplay < 480)) {
1145 lvds->native_mode.hdisplay = 640;
1146 lvds->native_mode.vdisplay = 480;
1149 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1150 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1151 if ((ppll_val & 0x000707ff) == 0x1bb)
1152 lvds->use_bios_dividers = false;
1154 lvds->panel_ref_divider =
1155 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1156 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1157 lvds->panel_fb_divider = ppll_val & 0x7ff;
1159 if ((lvds->panel_ref_divider != 0) &&
1160 (lvds->panel_fb_divider > 3))
1161 lvds->use_bios_dividers = true;
1163 lvds->panel_vcc_delay = 200;
1165 DRM_INFO("Panel info derived from registers\n");
1166 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1167 lvds->native_mode.vdisplay);
1172 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1175 struct drm_device *dev = encoder->base.dev;
1176 struct radeon_device *rdev = dev->dev_private;
1178 uint32_t panel_setup;
1181 struct radeon_encoder_lvds *lvds = NULL;
1183 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1186 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1191 for (i = 0; i < 24; i++)
1192 stmp[i] = RBIOS8(lcd_info + i + 1);
1195 DRM_INFO("Panel ID String: %s\n", stmp);
1197 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1198 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1200 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1201 lvds->native_mode.vdisplay);
1203 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1204 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1206 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1207 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1208 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1210 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1211 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1212 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1213 if ((lvds->panel_ref_divider != 0) &&
1214 (lvds->panel_fb_divider > 3))
1215 lvds->use_bios_dividers = true;
1217 panel_setup = RBIOS32(lcd_info + 0x39);
1218 lvds->lvds_gen_cntl = 0xff00;
1219 if (panel_setup & 0x1)
1220 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1222 if ((panel_setup >> 4) & 0x1)
1223 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1225 switch ((panel_setup >> 8) & 0x7) {
1227 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1230 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1233 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1239 if ((panel_setup >> 16) & 0x1)
1240 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1242 if ((panel_setup >> 17) & 0x1)
1243 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1245 if ((panel_setup >> 18) & 0x1)
1246 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1248 if ((panel_setup >> 23) & 0x1)
1249 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1251 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1253 for (i = 0; i < 32; i++) {
1254 tmp = RBIOS16(lcd_info + 64 + i * 2);
1258 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1259 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1260 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1261 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1262 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1263 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1264 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1265 (RBIOS8(tmp + 23) * 8);
1267 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1268 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1269 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1270 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1271 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1272 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1274 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1275 lvds->native_mode.flags = 0;
1276 /* set crtc values */
1277 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1282 DRM_INFO("No panel info found in BIOS\n");
1283 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1287 encoder->native_mode = lvds->native_mode;
1291 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1292 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1293 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1294 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1295 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1296 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1297 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1298 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1299 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1300 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1301 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1302 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1303 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1304 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1305 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1306 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1307 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1308 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1309 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1312 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1313 struct radeon_encoder_int_tmds *tmds)
1315 struct drm_device *dev = encoder->base.dev;
1316 struct radeon_device *rdev = dev->dev_private;
1319 for (i = 0; i < 4; i++) {
1320 tmds->tmds_pll[i].value =
1321 default_tmds_pll[rdev->family][i].value;
1322 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1328 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1329 struct radeon_encoder_int_tmds *tmds)
1331 struct drm_device *dev = encoder->base.dev;
1332 struct radeon_device *rdev = dev->dev_private;
1337 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1340 ver = RBIOS8(tmds_info);
1341 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1343 n = RBIOS8(tmds_info + 5) + 1;
1346 for (i = 0; i < n; i++) {
1347 tmds->tmds_pll[i].value =
1348 RBIOS32(tmds_info + i * 10 + 0x08);
1349 tmds->tmds_pll[i].freq =
1350 RBIOS16(tmds_info + i * 10 + 0x10);
1351 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1352 tmds->tmds_pll[i].freq,
1353 tmds->tmds_pll[i].value);
1355 } else if (ver == 4) {
1357 n = RBIOS8(tmds_info + 5) + 1;
1360 for (i = 0; i < n; i++) {
1361 tmds->tmds_pll[i].value =
1362 RBIOS32(tmds_info + stride + 0x08);
1363 tmds->tmds_pll[i].freq =
1364 RBIOS16(tmds_info + stride + 0x10);
1369 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1370 tmds->tmds_pll[i].freq,
1371 tmds->tmds_pll[i].value);
1375 DRM_INFO("No TMDS info found in BIOS\n");
1381 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1382 struct radeon_encoder_ext_tmds *tmds)
1384 struct drm_device *dev = encoder->base.dev;
1385 struct radeon_device *rdev = dev->dev_private;
1386 struct radeon_i2c_bus_rec i2c_bus;
1388 /* default for macs */
1389 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1390 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1392 /* XXX some macs have duallink chips */
1393 switch (rdev->mode_info.connector_table) {
1394 case CT_POWERBOOK_EXTERNAL:
1395 case CT_MINI_EXTERNAL:
1397 tmds->dvo_chip = DVO_SIL164;
1398 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1405 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1406 struct radeon_encoder_ext_tmds *tmds)
1408 struct drm_device *dev = encoder->base.dev;
1409 struct radeon_device *rdev = dev->dev_private;
1412 enum radeon_combios_ddc gpio;
1413 struct radeon_i2c_bus_rec i2c_bus;
1415 tmds->i2c_bus = NULL;
1416 if (rdev->flags & RADEON_IS_IGP) {
1417 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1418 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1419 tmds->dvo_chip = DVO_SIL164;
1420 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1422 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1424 ver = RBIOS8(offset);
1425 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1426 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1427 tmds->slave_addr >>= 1; /* 7 bit addressing */
1428 gpio = RBIOS8(offset + 4 + 3);
1429 if (gpio == DDC_LCD) {
1431 i2c_bus.valid = true;
1432 i2c_bus.hw_capable = true;
1433 i2c_bus.mm_i2c = true;
1434 i2c_bus.i2c_id = 0xa0;
1436 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1437 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1441 if (!tmds->i2c_bus) {
1442 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1449 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1451 struct radeon_device *rdev = dev->dev_private;
1452 struct radeon_i2c_bus_rec ddc_i2c;
1453 struct radeon_hpd hpd;
1455 rdev->mode_info.connector_table = radeon_connector_table;
1456 if (rdev->mode_info.connector_table == CT_NONE) {
1457 #ifdef CONFIG_PPC_PMAC
1458 if (of_machine_is_compatible("PowerBook3,3")) {
1459 /* powerbook with VGA */
1460 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1461 } else if (of_machine_is_compatible("PowerBook3,4") ||
1462 of_machine_is_compatible("PowerBook3,5")) {
1463 /* powerbook with internal tmds */
1464 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1465 } else if (of_machine_is_compatible("PowerBook5,1") ||
1466 of_machine_is_compatible("PowerBook5,2") ||
1467 of_machine_is_compatible("PowerBook5,3") ||
1468 of_machine_is_compatible("PowerBook5,4") ||
1469 of_machine_is_compatible("PowerBook5,5")) {
1470 /* powerbook with external single link tmds (sil164) */
1471 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1472 } else if (of_machine_is_compatible("PowerBook5,6")) {
1473 /* powerbook with external dual or single link tmds */
1474 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1475 } else if (of_machine_is_compatible("PowerBook5,7") ||
1476 of_machine_is_compatible("PowerBook5,8") ||
1477 of_machine_is_compatible("PowerBook5,9")) {
1478 /* PowerBook6,2 ? */
1479 /* powerbook with external dual link tmds (sil1178?) */
1480 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1481 } else if (of_machine_is_compatible("PowerBook4,1") ||
1482 of_machine_is_compatible("PowerBook4,2") ||
1483 of_machine_is_compatible("PowerBook4,3") ||
1484 of_machine_is_compatible("PowerBook6,3") ||
1485 of_machine_is_compatible("PowerBook6,5") ||
1486 of_machine_is_compatible("PowerBook6,7")) {
1488 rdev->mode_info.connector_table = CT_IBOOK;
1489 } else if (of_machine_is_compatible("PowerMac4,4")) {
1491 rdev->mode_info.connector_table = CT_EMAC;
1492 } else if (of_machine_is_compatible("PowerMac10,1")) {
1493 /* mini with internal tmds */
1494 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1495 } else if (of_machine_is_compatible("PowerMac10,2")) {
1496 /* mini with external tmds */
1497 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1498 } else if (of_machine_is_compatible("PowerMac12,1")) {
1500 /* imac g5 isight */
1501 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1502 } else if ((rdev->pdev->device == 0x4a48) &&
1503 (rdev->pdev->subsystem_vendor == 0x1002) &&
1504 (rdev->pdev->subsystem_device == 0x4a48)) {
1506 rdev->mode_info.connector_table = CT_MAC_X800;
1507 } else if ((rdev->pdev->device == 0x4150) &&
1508 (rdev->pdev->subsystem_vendor == 0x1002) &&
1509 (rdev->pdev->subsystem_device == 0x4150)) {
1511 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1513 #endif /* CONFIG_PPC_PMAC */
1515 if (ASIC_IS_RN50(rdev))
1516 rdev->mode_info.connector_table = CT_RN50_POWER;
1519 rdev->mode_info.connector_table = CT_GENERIC;
1522 switch (rdev->mode_info.connector_table) {
1524 DRM_INFO("Connector Table: %d (generic)\n",
1525 rdev->mode_info.connector_table);
1526 /* these are the most common settings */
1527 if (rdev->flags & RADEON_SINGLE_CRTC) {
1528 /* VGA - primary dac */
1529 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1530 hpd.hpd = RADEON_HPD_NONE;
1531 radeon_add_legacy_encoder(dev,
1532 radeon_get_encoder_enum(dev,
1533 ATOM_DEVICE_CRT1_SUPPORT,
1535 ATOM_DEVICE_CRT1_SUPPORT);
1536 radeon_add_legacy_connector(dev, 0,
1537 ATOM_DEVICE_CRT1_SUPPORT,
1538 DRM_MODE_CONNECTOR_VGA,
1540 CONNECTOR_OBJECT_ID_VGA,
1542 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1544 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1545 hpd.hpd = RADEON_HPD_NONE;
1546 radeon_add_legacy_encoder(dev,
1547 radeon_get_encoder_enum(dev,
1548 ATOM_DEVICE_LCD1_SUPPORT,
1550 ATOM_DEVICE_LCD1_SUPPORT);
1551 radeon_add_legacy_connector(dev, 0,
1552 ATOM_DEVICE_LCD1_SUPPORT,
1553 DRM_MODE_CONNECTOR_LVDS,
1555 CONNECTOR_OBJECT_ID_LVDS,
1558 /* VGA - primary dac */
1559 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1560 hpd.hpd = RADEON_HPD_NONE;
1561 radeon_add_legacy_encoder(dev,
1562 radeon_get_encoder_enum(dev,
1563 ATOM_DEVICE_CRT1_SUPPORT,
1565 ATOM_DEVICE_CRT1_SUPPORT);
1566 radeon_add_legacy_connector(dev, 1,
1567 ATOM_DEVICE_CRT1_SUPPORT,
1568 DRM_MODE_CONNECTOR_VGA,
1570 CONNECTOR_OBJECT_ID_VGA,
1573 /* DVI-I - tv dac, int tmds */
1574 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1575 hpd.hpd = RADEON_HPD_1;
1576 radeon_add_legacy_encoder(dev,
1577 radeon_get_encoder_enum(dev,
1578 ATOM_DEVICE_DFP1_SUPPORT,
1580 ATOM_DEVICE_DFP1_SUPPORT);
1581 radeon_add_legacy_encoder(dev,
1582 radeon_get_encoder_enum(dev,
1583 ATOM_DEVICE_CRT2_SUPPORT,
1585 ATOM_DEVICE_CRT2_SUPPORT);
1586 radeon_add_legacy_connector(dev, 0,
1587 ATOM_DEVICE_DFP1_SUPPORT |
1588 ATOM_DEVICE_CRT2_SUPPORT,
1589 DRM_MODE_CONNECTOR_DVII,
1591 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1594 /* VGA - primary dac */
1595 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1596 hpd.hpd = RADEON_HPD_NONE;
1597 radeon_add_legacy_encoder(dev,
1598 radeon_get_encoder_enum(dev,
1599 ATOM_DEVICE_CRT1_SUPPORT,
1601 ATOM_DEVICE_CRT1_SUPPORT);
1602 radeon_add_legacy_connector(dev, 1,
1603 ATOM_DEVICE_CRT1_SUPPORT,
1604 DRM_MODE_CONNECTOR_VGA,
1606 CONNECTOR_OBJECT_ID_VGA,
1610 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1612 ddc_i2c.valid = false;
1613 hpd.hpd = RADEON_HPD_NONE;
1614 radeon_add_legacy_encoder(dev,
1615 radeon_get_encoder_enum(dev,
1616 ATOM_DEVICE_TV1_SUPPORT,
1618 ATOM_DEVICE_TV1_SUPPORT);
1619 radeon_add_legacy_connector(dev, 2,
1620 ATOM_DEVICE_TV1_SUPPORT,
1621 DRM_MODE_CONNECTOR_SVIDEO,
1623 CONNECTOR_OBJECT_ID_SVIDEO,
1628 DRM_INFO("Connector Table: %d (ibook)\n",
1629 rdev->mode_info.connector_table);
1631 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1632 hpd.hpd = RADEON_HPD_NONE;
1633 radeon_add_legacy_encoder(dev,
1634 radeon_get_encoder_enum(dev,
1635 ATOM_DEVICE_LCD1_SUPPORT,
1637 ATOM_DEVICE_LCD1_SUPPORT);
1638 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1639 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1640 CONNECTOR_OBJECT_ID_LVDS,
1643 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1644 hpd.hpd = RADEON_HPD_NONE;
1645 radeon_add_legacy_encoder(dev,
1646 radeon_get_encoder_enum(dev,
1647 ATOM_DEVICE_CRT2_SUPPORT,
1649 ATOM_DEVICE_CRT2_SUPPORT);
1650 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1651 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1652 CONNECTOR_OBJECT_ID_VGA,
1655 ddc_i2c.valid = false;
1656 hpd.hpd = RADEON_HPD_NONE;
1657 radeon_add_legacy_encoder(dev,
1658 radeon_get_encoder_enum(dev,
1659 ATOM_DEVICE_TV1_SUPPORT,
1661 ATOM_DEVICE_TV1_SUPPORT);
1662 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1663 DRM_MODE_CONNECTOR_SVIDEO,
1665 CONNECTOR_OBJECT_ID_SVIDEO,
1668 case CT_POWERBOOK_EXTERNAL:
1669 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1670 rdev->mode_info.connector_table);
1672 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1673 hpd.hpd = RADEON_HPD_NONE;
1674 radeon_add_legacy_encoder(dev,
1675 radeon_get_encoder_enum(dev,
1676 ATOM_DEVICE_LCD1_SUPPORT,
1678 ATOM_DEVICE_LCD1_SUPPORT);
1679 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1680 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1681 CONNECTOR_OBJECT_ID_LVDS,
1683 /* DVI-I - primary dac, ext tmds */
1684 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1685 hpd.hpd = RADEON_HPD_2; /* ??? */
1686 radeon_add_legacy_encoder(dev,
1687 radeon_get_encoder_enum(dev,
1688 ATOM_DEVICE_DFP2_SUPPORT,
1690 ATOM_DEVICE_DFP2_SUPPORT);
1691 radeon_add_legacy_encoder(dev,
1692 radeon_get_encoder_enum(dev,
1693 ATOM_DEVICE_CRT1_SUPPORT,
1695 ATOM_DEVICE_CRT1_SUPPORT);
1696 /* XXX some are SL */
1697 radeon_add_legacy_connector(dev, 1,
1698 ATOM_DEVICE_DFP2_SUPPORT |
1699 ATOM_DEVICE_CRT1_SUPPORT,
1700 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1701 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1704 ddc_i2c.valid = false;
1705 hpd.hpd = RADEON_HPD_NONE;
1706 radeon_add_legacy_encoder(dev,
1707 radeon_get_encoder_enum(dev,
1708 ATOM_DEVICE_TV1_SUPPORT,
1710 ATOM_DEVICE_TV1_SUPPORT);
1711 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1712 DRM_MODE_CONNECTOR_SVIDEO,
1714 CONNECTOR_OBJECT_ID_SVIDEO,
1717 case CT_POWERBOOK_INTERNAL:
1718 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1719 rdev->mode_info.connector_table);
1721 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1722 hpd.hpd = RADEON_HPD_NONE;
1723 radeon_add_legacy_encoder(dev,
1724 radeon_get_encoder_enum(dev,
1725 ATOM_DEVICE_LCD1_SUPPORT,
1727 ATOM_DEVICE_LCD1_SUPPORT);
1728 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1729 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1730 CONNECTOR_OBJECT_ID_LVDS,
1732 /* DVI-I - primary dac, int tmds */
1733 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1734 hpd.hpd = RADEON_HPD_1; /* ??? */
1735 radeon_add_legacy_encoder(dev,
1736 radeon_get_encoder_enum(dev,
1737 ATOM_DEVICE_DFP1_SUPPORT,
1739 ATOM_DEVICE_DFP1_SUPPORT);
1740 radeon_add_legacy_encoder(dev,
1741 radeon_get_encoder_enum(dev,
1742 ATOM_DEVICE_CRT1_SUPPORT,
1744 ATOM_DEVICE_CRT1_SUPPORT);
1745 radeon_add_legacy_connector(dev, 1,
1746 ATOM_DEVICE_DFP1_SUPPORT |
1747 ATOM_DEVICE_CRT1_SUPPORT,
1748 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1749 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1752 ddc_i2c.valid = false;
1753 hpd.hpd = RADEON_HPD_NONE;
1754 radeon_add_legacy_encoder(dev,
1755 radeon_get_encoder_enum(dev,
1756 ATOM_DEVICE_TV1_SUPPORT,
1758 ATOM_DEVICE_TV1_SUPPORT);
1759 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1760 DRM_MODE_CONNECTOR_SVIDEO,
1762 CONNECTOR_OBJECT_ID_SVIDEO,
1765 case CT_POWERBOOK_VGA:
1766 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1767 rdev->mode_info.connector_table);
1769 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1770 hpd.hpd = RADEON_HPD_NONE;
1771 radeon_add_legacy_encoder(dev,
1772 radeon_get_encoder_enum(dev,
1773 ATOM_DEVICE_LCD1_SUPPORT,
1775 ATOM_DEVICE_LCD1_SUPPORT);
1776 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1777 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1778 CONNECTOR_OBJECT_ID_LVDS,
1780 /* VGA - primary dac */
1781 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1782 hpd.hpd = RADEON_HPD_NONE;
1783 radeon_add_legacy_encoder(dev,
1784 radeon_get_encoder_enum(dev,
1785 ATOM_DEVICE_CRT1_SUPPORT,
1787 ATOM_DEVICE_CRT1_SUPPORT);
1788 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1789 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1790 CONNECTOR_OBJECT_ID_VGA,
1793 ddc_i2c.valid = false;
1794 hpd.hpd = RADEON_HPD_NONE;
1795 radeon_add_legacy_encoder(dev,
1796 radeon_get_encoder_enum(dev,
1797 ATOM_DEVICE_TV1_SUPPORT,
1799 ATOM_DEVICE_TV1_SUPPORT);
1800 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1801 DRM_MODE_CONNECTOR_SVIDEO,
1803 CONNECTOR_OBJECT_ID_SVIDEO,
1806 case CT_MINI_EXTERNAL:
1807 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1808 rdev->mode_info.connector_table);
1809 /* DVI-I - tv dac, ext tmds */
1810 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1811 hpd.hpd = RADEON_HPD_2; /* ??? */
1812 radeon_add_legacy_encoder(dev,
1813 radeon_get_encoder_enum(dev,
1814 ATOM_DEVICE_DFP2_SUPPORT,
1816 ATOM_DEVICE_DFP2_SUPPORT);
1817 radeon_add_legacy_encoder(dev,
1818 radeon_get_encoder_enum(dev,
1819 ATOM_DEVICE_CRT2_SUPPORT,
1821 ATOM_DEVICE_CRT2_SUPPORT);
1822 /* XXX are any DL? */
1823 radeon_add_legacy_connector(dev, 0,
1824 ATOM_DEVICE_DFP2_SUPPORT |
1825 ATOM_DEVICE_CRT2_SUPPORT,
1826 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1827 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1830 ddc_i2c.valid = false;
1831 hpd.hpd = RADEON_HPD_NONE;
1832 radeon_add_legacy_encoder(dev,
1833 radeon_get_encoder_enum(dev,
1834 ATOM_DEVICE_TV1_SUPPORT,
1836 ATOM_DEVICE_TV1_SUPPORT);
1837 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1838 DRM_MODE_CONNECTOR_SVIDEO,
1840 CONNECTOR_OBJECT_ID_SVIDEO,
1843 case CT_MINI_INTERNAL:
1844 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1845 rdev->mode_info.connector_table);
1846 /* DVI-I - tv dac, int tmds */
1847 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1848 hpd.hpd = RADEON_HPD_1; /* ??? */
1849 radeon_add_legacy_encoder(dev,
1850 radeon_get_encoder_enum(dev,
1851 ATOM_DEVICE_DFP1_SUPPORT,
1853 ATOM_DEVICE_DFP1_SUPPORT);
1854 radeon_add_legacy_encoder(dev,
1855 radeon_get_encoder_enum(dev,
1856 ATOM_DEVICE_CRT2_SUPPORT,
1858 ATOM_DEVICE_CRT2_SUPPORT);
1859 radeon_add_legacy_connector(dev, 0,
1860 ATOM_DEVICE_DFP1_SUPPORT |
1861 ATOM_DEVICE_CRT2_SUPPORT,
1862 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1863 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1866 ddc_i2c.valid = false;
1867 hpd.hpd = RADEON_HPD_NONE;
1868 radeon_add_legacy_encoder(dev,
1869 radeon_get_encoder_enum(dev,
1870 ATOM_DEVICE_TV1_SUPPORT,
1872 ATOM_DEVICE_TV1_SUPPORT);
1873 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1874 DRM_MODE_CONNECTOR_SVIDEO,
1876 CONNECTOR_OBJECT_ID_SVIDEO,
1879 case CT_IMAC_G5_ISIGHT:
1880 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1881 rdev->mode_info.connector_table);
1882 /* DVI-D - int tmds */
1883 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1884 hpd.hpd = RADEON_HPD_1; /* ??? */
1885 radeon_add_legacy_encoder(dev,
1886 radeon_get_encoder_enum(dev,
1887 ATOM_DEVICE_DFP1_SUPPORT,
1889 ATOM_DEVICE_DFP1_SUPPORT);
1890 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1891 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1892 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1895 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1896 hpd.hpd = RADEON_HPD_NONE;
1897 radeon_add_legacy_encoder(dev,
1898 radeon_get_encoder_enum(dev,
1899 ATOM_DEVICE_CRT2_SUPPORT,
1901 ATOM_DEVICE_CRT2_SUPPORT);
1902 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1903 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1904 CONNECTOR_OBJECT_ID_VGA,
1907 ddc_i2c.valid = false;
1908 hpd.hpd = RADEON_HPD_NONE;
1909 radeon_add_legacy_encoder(dev,
1910 radeon_get_encoder_enum(dev,
1911 ATOM_DEVICE_TV1_SUPPORT,
1913 ATOM_DEVICE_TV1_SUPPORT);
1914 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1915 DRM_MODE_CONNECTOR_SVIDEO,
1917 CONNECTOR_OBJECT_ID_SVIDEO,
1921 DRM_INFO("Connector Table: %d (emac)\n",
1922 rdev->mode_info.connector_table);
1923 /* VGA - primary dac */
1924 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1925 hpd.hpd = RADEON_HPD_NONE;
1926 radeon_add_legacy_encoder(dev,
1927 radeon_get_encoder_enum(dev,
1928 ATOM_DEVICE_CRT1_SUPPORT,
1930 ATOM_DEVICE_CRT1_SUPPORT);
1931 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1932 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1933 CONNECTOR_OBJECT_ID_VGA,
1936 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1937 hpd.hpd = RADEON_HPD_NONE;
1938 radeon_add_legacy_encoder(dev,
1939 radeon_get_encoder_enum(dev,
1940 ATOM_DEVICE_CRT2_SUPPORT,
1942 ATOM_DEVICE_CRT2_SUPPORT);
1943 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1944 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1945 CONNECTOR_OBJECT_ID_VGA,
1948 ddc_i2c.valid = false;
1949 hpd.hpd = RADEON_HPD_NONE;
1950 radeon_add_legacy_encoder(dev,
1951 radeon_get_encoder_enum(dev,
1952 ATOM_DEVICE_TV1_SUPPORT,
1954 ATOM_DEVICE_TV1_SUPPORT);
1955 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1956 DRM_MODE_CONNECTOR_SVIDEO,
1958 CONNECTOR_OBJECT_ID_SVIDEO,
1962 DRM_INFO("Connector Table: %d (rn50-power)\n",
1963 rdev->mode_info.connector_table);
1964 /* VGA - primary dac */
1965 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1966 hpd.hpd = RADEON_HPD_NONE;
1967 radeon_add_legacy_encoder(dev,
1968 radeon_get_encoder_enum(dev,
1969 ATOM_DEVICE_CRT1_SUPPORT,
1971 ATOM_DEVICE_CRT1_SUPPORT);
1972 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1973 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1974 CONNECTOR_OBJECT_ID_VGA,
1976 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1977 hpd.hpd = RADEON_HPD_NONE;
1978 radeon_add_legacy_encoder(dev,
1979 radeon_get_encoder_enum(dev,
1980 ATOM_DEVICE_CRT2_SUPPORT,
1982 ATOM_DEVICE_CRT2_SUPPORT);
1983 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1984 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1985 CONNECTOR_OBJECT_ID_VGA,
1989 DRM_INFO("Connector Table: %d (mac x800)\n",
1990 rdev->mode_info.connector_table);
1991 /* DVI - primary dac, internal tmds */
1992 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1993 hpd.hpd = RADEON_HPD_1; /* ??? */
1994 radeon_add_legacy_encoder(dev,
1995 radeon_get_encoder_enum(dev,
1996 ATOM_DEVICE_DFP1_SUPPORT,
1998 ATOM_DEVICE_DFP1_SUPPORT);
1999 radeon_add_legacy_encoder(dev,
2000 radeon_get_encoder_enum(dev,
2001 ATOM_DEVICE_CRT1_SUPPORT,
2003 ATOM_DEVICE_CRT1_SUPPORT);
2004 radeon_add_legacy_connector(dev, 0,
2005 ATOM_DEVICE_DFP1_SUPPORT |
2006 ATOM_DEVICE_CRT1_SUPPORT,
2007 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2008 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2010 /* DVI - tv dac, dvo */
2011 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2012 hpd.hpd = RADEON_HPD_2; /* ??? */
2013 radeon_add_legacy_encoder(dev,
2014 radeon_get_encoder_enum(dev,
2015 ATOM_DEVICE_DFP2_SUPPORT,
2017 ATOM_DEVICE_DFP2_SUPPORT);
2018 radeon_add_legacy_encoder(dev,
2019 radeon_get_encoder_enum(dev,
2020 ATOM_DEVICE_CRT2_SUPPORT,
2022 ATOM_DEVICE_CRT2_SUPPORT);
2023 radeon_add_legacy_connector(dev, 1,
2024 ATOM_DEVICE_DFP2_SUPPORT |
2025 ATOM_DEVICE_CRT2_SUPPORT,
2026 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2027 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2030 case CT_MAC_G5_9600:
2031 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2032 rdev->mode_info.connector_table);
2033 /* DVI - tv dac, dvo */
2034 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2035 hpd.hpd = RADEON_HPD_1; /* ??? */
2036 radeon_add_legacy_encoder(dev,
2037 radeon_get_encoder_enum(dev,
2038 ATOM_DEVICE_DFP2_SUPPORT,
2040 ATOM_DEVICE_DFP2_SUPPORT);
2041 radeon_add_legacy_encoder(dev,
2042 radeon_get_encoder_enum(dev,
2043 ATOM_DEVICE_CRT2_SUPPORT,
2045 ATOM_DEVICE_CRT2_SUPPORT);
2046 radeon_add_legacy_connector(dev, 0,
2047 ATOM_DEVICE_DFP2_SUPPORT |
2048 ATOM_DEVICE_CRT2_SUPPORT,
2049 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2050 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2052 /* ADC - primary dac, internal tmds */
2053 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2054 hpd.hpd = RADEON_HPD_2; /* ??? */
2055 radeon_add_legacy_encoder(dev,
2056 radeon_get_encoder_enum(dev,
2057 ATOM_DEVICE_DFP1_SUPPORT,
2059 ATOM_DEVICE_DFP1_SUPPORT);
2060 radeon_add_legacy_encoder(dev,
2061 radeon_get_encoder_enum(dev,
2062 ATOM_DEVICE_CRT1_SUPPORT,
2064 ATOM_DEVICE_CRT1_SUPPORT);
2065 radeon_add_legacy_connector(dev, 1,
2066 ATOM_DEVICE_DFP1_SUPPORT |
2067 ATOM_DEVICE_CRT1_SUPPORT,
2068 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2069 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2073 DRM_INFO("Connector table: %d (invalid)\n",
2074 rdev->mode_info.connector_table);
2078 radeon_link_encoder_connector(dev);
2083 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2085 enum radeon_combios_connector
2087 struct radeon_i2c_bus_rec *ddc_i2c,
2088 struct radeon_hpd *hpd)
2091 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2092 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2093 if (dev->pdev->device == 0x515e &&
2094 dev->pdev->subsystem_vendor == 0x1014) {
2095 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2096 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2100 /* X300 card with extra non-existent DVI port */
2101 if (dev->pdev->device == 0x5B60 &&
2102 dev->pdev->subsystem_vendor == 0x17af &&
2103 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2104 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2111 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2113 /* Acer 5102 has non-existent TV port */
2114 if (dev->pdev->device == 0x5975 &&
2115 dev->pdev->subsystem_vendor == 0x1025 &&
2116 dev->pdev->subsystem_device == 0x009f)
2119 /* HP dc5750 has non-existent TV port */
2120 if (dev->pdev->device == 0x5974 &&
2121 dev->pdev->subsystem_vendor == 0x103c &&
2122 dev->pdev->subsystem_device == 0x280a)
2125 /* MSI S270 has non-existent TV port */
2126 if (dev->pdev->device == 0x5955 &&
2127 dev->pdev->subsystem_vendor == 0x1462 &&
2128 dev->pdev->subsystem_device == 0x0131)
2134 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2136 struct radeon_device *rdev = dev->dev_private;
2137 uint32_t ext_tmds_info;
2139 if (rdev->flags & RADEON_IS_IGP) {
2141 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2143 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2145 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2146 if (ext_tmds_info) {
2147 uint8_t rev = RBIOS8(ext_tmds_info);
2148 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2151 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2153 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2157 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2159 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2164 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2166 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2169 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2171 struct radeon_device *rdev = dev->dev_private;
2172 uint32_t conn_info, entry, devices;
2173 uint16_t tmp, connector_object_id;
2174 enum radeon_combios_ddc ddc_type;
2175 enum radeon_combios_connector connector;
2177 struct radeon_i2c_bus_rec ddc_i2c;
2178 struct radeon_hpd hpd;
2180 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2182 for (i = 0; i < 4; i++) {
2183 entry = conn_info + 2 + i * 2;
2185 if (!RBIOS16(entry))
2188 tmp = RBIOS16(entry);
2190 connector = (tmp >> 12) & 0xf;
2192 ddc_type = (tmp >> 8) & 0xf;
2193 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2195 switch (connector) {
2196 case CONNECTOR_PROPRIETARY_LEGACY:
2197 case CONNECTOR_DVI_I_LEGACY:
2198 case CONNECTOR_DVI_D_LEGACY:
2199 if ((tmp >> 4) & 0x1)
2200 hpd.hpd = RADEON_HPD_2;
2202 hpd.hpd = RADEON_HPD_1;
2205 hpd.hpd = RADEON_HPD_NONE;
2209 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2213 switch (connector) {
2214 case CONNECTOR_PROPRIETARY_LEGACY:
2215 if ((tmp >> 4) & 0x1)
2216 devices = ATOM_DEVICE_DFP2_SUPPORT;
2218 devices = ATOM_DEVICE_DFP1_SUPPORT;
2219 radeon_add_legacy_encoder(dev,
2220 radeon_get_encoder_enum
2223 radeon_add_legacy_connector(dev, i, devices,
2224 legacy_connector_convert
2227 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2230 case CONNECTOR_CRT_LEGACY:
2232 devices = ATOM_DEVICE_CRT2_SUPPORT;
2233 radeon_add_legacy_encoder(dev,
2234 radeon_get_encoder_enum
2236 ATOM_DEVICE_CRT2_SUPPORT,
2238 ATOM_DEVICE_CRT2_SUPPORT);
2240 devices = ATOM_DEVICE_CRT1_SUPPORT;
2241 radeon_add_legacy_encoder(dev,
2242 radeon_get_encoder_enum
2244 ATOM_DEVICE_CRT1_SUPPORT,
2246 ATOM_DEVICE_CRT1_SUPPORT);
2248 radeon_add_legacy_connector(dev,
2251 legacy_connector_convert
2254 CONNECTOR_OBJECT_ID_VGA,
2257 case CONNECTOR_DVI_I_LEGACY:
2260 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2261 radeon_add_legacy_encoder(dev,
2262 radeon_get_encoder_enum
2264 ATOM_DEVICE_CRT2_SUPPORT,
2266 ATOM_DEVICE_CRT2_SUPPORT);
2268 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2269 radeon_add_legacy_encoder(dev,
2270 radeon_get_encoder_enum
2272 ATOM_DEVICE_CRT1_SUPPORT,
2274 ATOM_DEVICE_CRT1_SUPPORT);
2276 if ((tmp >> 4) & 0x1) {
2277 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2278 radeon_add_legacy_encoder(dev,
2279 radeon_get_encoder_enum
2281 ATOM_DEVICE_DFP2_SUPPORT,
2283 ATOM_DEVICE_DFP2_SUPPORT);
2284 connector_object_id = combios_check_dl_dvi(dev, 0);
2286 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2287 radeon_add_legacy_encoder(dev,
2288 radeon_get_encoder_enum
2290 ATOM_DEVICE_DFP1_SUPPORT,
2292 ATOM_DEVICE_DFP1_SUPPORT);
2293 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2295 radeon_add_legacy_connector(dev,
2298 legacy_connector_convert
2301 connector_object_id,
2304 case CONNECTOR_DVI_D_LEGACY:
2305 if ((tmp >> 4) & 0x1) {
2306 devices = ATOM_DEVICE_DFP2_SUPPORT;
2307 connector_object_id = combios_check_dl_dvi(dev, 1);
2309 devices = ATOM_DEVICE_DFP1_SUPPORT;
2310 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2312 radeon_add_legacy_encoder(dev,
2313 radeon_get_encoder_enum
2316 radeon_add_legacy_connector(dev, i, devices,
2317 legacy_connector_convert
2320 connector_object_id,
2323 case CONNECTOR_CTV_LEGACY:
2324 case CONNECTOR_STV_LEGACY:
2325 radeon_add_legacy_encoder(dev,
2326 radeon_get_encoder_enum
2328 ATOM_DEVICE_TV1_SUPPORT,
2330 ATOM_DEVICE_TV1_SUPPORT);
2331 radeon_add_legacy_connector(dev, i,
2332 ATOM_DEVICE_TV1_SUPPORT,
2333 legacy_connector_convert
2336 CONNECTOR_OBJECT_ID_SVIDEO,
2340 DRM_ERROR("Unknown connector type: %d\n",
2347 uint16_t tmds_info =
2348 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2350 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2352 radeon_add_legacy_encoder(dev,
2353 radeon_get_encoder_enum(dev,
2354 ATOM_DEVICE_CRT1_SUPPORT,
2356 ATOM_DEVICE_CRT1_SUPPORT);
2357 radeon_add_legacy_encoder(dev,
2358 radeon_get_encoder_enum(dev,
2359 ATOM_DEVICE_DFP1_SUPPORT,
2361 ATOM_DEVICE_DFP1_SUPPORT);
2363 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2364 hpd.hpd = RADEON_HPD_1;
2365 radeon_add_legacy_connector(dev,
2367 ATOM_DEVICE_CRT1_SUPPORT |
2368 ATOM_DEVICE_DFP1_SUPPORT,
2369 DRM_MODE_CONNECTOR_DVII,
2371 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2375 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2376 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2378 radeon_add_legacy_encoder(dev,
2379 radeon_get_encoder_enum(dev,
2380 ATOM_DEVICE_CRT1_SUPPORT,
2382 ATOM_DEVICE_CRT1_SUPPORT);
2383 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2384 hpd.hpd = RADEON_HPD_NONE;
2385 radeon_add_legacy_connector(dev,
2387 ATOM_DEVICE_CRT1_SUPPORT,
2388 DRM_MODE_CONNECTOR_VGA,
2390 CONNECTOR_OBJECT_ID_VGA,
2393 DRM_DEBUG_KMS("No connector info found\n");
2399 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2401 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2403 uint16_t lcd_ddc_info =
2404 combios_get_table_offset(dev,
2405 COMBIOS_LCD_DDC_INFO_TABLE);
2407 radeon_add_legacy_encoder(dev,
2408 radeon_get_encoder_enum(dev,
2409 ATOM_DEVICE_LCD1_SUPPORT,
2411 ATOM_DEVICE_LCD1_SUPPORT);
2414 ddc_type = RBIOS8(lcd_ddc_info + 2);
2418 combios_setup_i2c_bus(rdev,
2420 RBIOS32(lcd_ddc_info + 3),
2421 RBIOS32(lcd_ddc_info + 7));
2422 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2426 combios_setup_i2c_bus(rdev,
2428 RBIOS32(lcd_ddc_info + 3),
2429 RBIOS32(lcd_ddc_info + 7));
2430 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2434 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2437 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2439 ddc_i2c.valid = false;
2441 hpd.hpd = RADEON_HPD_NONE;
2442 radeon_add_legacy_connector(dev,
2444 ATOM_DEVICE_LCD1_SUPPORT,
2445 DRM_MODE_CONNECTOR_LVDS,
2447 CONNECTOR_OBJECT_ID_LVDS,
2452 /* check TV table */
2453 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2455 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2457 if (RBIOS8(tv_info + 6) == 'T') {
2458 if (radeon_apply_legacy_tv_quirks(dev)) {
2459 hpd.hpd = RADEON_HPD_NONE;
2460 ddc_i2c.valid = false;
2461 radeon_add_legacy_encoder(dev,
2462 radeon_get_encoder_enum
2464 ATOM_DEVICE_TV1_SUPPORT,
2466 ATOM_DEVICE_TV1_SUPPORT);
2467 radeon_add_legacy_connector(dev, 6,
2468 ATOM_DEVICE_TV1_SUPPORT,
2469 DRM_MODE_CONNECTOR_SVIDEO,
2471 CONNECTOR_OBJECT_ID_SVIDEO,
2478 radeon_link_encoder_connector(dev);
2483 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2485 struct drm_device *dev = rdev->ddev;
2486 u16 offset, misc, misc2 = 0;
2487 u8 rev, blocks, tmp;
2488 int state_index = 0;
2490 rdev->pm.default_power_state_index = -1;
2492 /* allocate 2 power states */
2493 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2494 if (!rdev->pm.power_state) {
2495 rdev->pm.default_power_state_index = state_index;
2496 rdev->pm.num_power_states = 0;
2498 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2499 rdev->pm.current_clock_mode_index = 0;
2503 if (rdev->flags & RADEON_IS_MOBILITY) {
2504 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2506 rev = RBIOS8(offset);
2507 blocks = RBIOS8(offset + 0x2);
2508 /* power mode 0 tends to be the only valid one */
2509 rdev->pm.power_state[state_index].num_clock_modes = 1;
2510 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2511 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2512 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2513 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2515 rdev->pm.power_state[state_index].type =
2516 POWER_STATE_TYPE_BATTERY;
2517 misc = RBIOS16(offset + 0x5 + 0x0);
2519 misc2 = RBIOS16(offset + 0x5 + 0xe);
2520 rdev->pm.power_state[state_index].misc = misc;
2521 rdev->pm.power_state[state_index].misc2 = misc2;
2523 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2525 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2528 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2530 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2532 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2533 RBIOS16(offset + 0x5 + 0xb) * 4;
2534 tmp = RBIOS8(offset + 0x5 + 0xd);
2535 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2537 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2538 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2539 if (entries && voltage_table_offset) {
2540 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2541 RBIOS16(voltage_table_offset) * 4;
2542 tmp = RBIOS8(voltage_table_offset + 0x2);
2543 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2545 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2547 switch ((misc2 & 0x700) >> 8) {
2550 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2553 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2556 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2559 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2562 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2566 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2568 rdev->pm.power_state[state_index].pcie_lanes =
2569 RBIOS8(offset + 0x5 + 0x10);
2570 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2573 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2576 /* XXX figure out some good default low power mode for desktop cards */
2580 /* add the default mode */
2581 rdev->pm.power_state[state_index].type =
2582 POWER_STATE_TYPE_DEFAULT;
2583 rdev->pm.power_state[state_index].num_clock_modes = 1;
2584 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2585 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2586 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2587 if ((state_index > 0) &&
2588 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2589 rdev->pm.power_state[state_index].clock_info[0].voltage =
2590 rdev->pm.power_state[0].clock_info[0].voltage;
2592 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2593 rdev->pm.power_state[state_index].pcie_lanes = 16;
2594 rdev->pm.power_state[state_index].flags = 0;
2595 rdev->pm.default_power_state_index = state_index;
2596 rdev->pm.num_power_states = state_index + 1;
2598 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2599 rdev->pm.current_clock_mode_index = 0;
2602 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2604 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2605 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2610 switch (tmds->dvo_chip) {
2613 radeon_i2c_put_byte(tmds->i2c_bus,
2616 radeon_i2c_put_byte(tmds->i2c_bus,
2619 radeon_i2c_put_byte(tmds->i2c_bus,
2622 radeon_i2c_put_byte(tmds->i2c_bus,
2625 radeon_i2c_put_byte(tmds->i2c_bus,
2630 /* sil 1178 - untested */
2649 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2651 struct drm_device *dev = encoder->dev;
2652 struct radeon_device *rdev = dev->dev_private;
2653 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2655 uint8_t blocks, slave_addr, rev;
2657 uint32_t reg, val, and_mask, or_mask;
2658 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2663 if (rdev->flags & RADEON_IS_IGP) {
2664 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2665 rev = RBIOS8(offset);
2667 rev = RBIOS8(offset);
2669 blocks = RBIOS8(offset + 3);
2671 while (blocks > 0) {
2672 id = RBIOS16(index);
2676 reg = (id & 0x1fff) * 4;
2677 val = RBIOS32(index);
2682 reg = (id & 0x1fff) * 4;
2683 and_mask = RBIOS32(index);
2685 or_mask = RBIOS32(index);
2688 val = (val & and_mask) | or_mask;
2692 val = RBIOS16(index);
2697 val = RBIOS16(index);
2702 slave_addr = id & 0xff;
2703 slave_addr >>= 1; /* 7 bit addressing */
2705 reg = RBIOS8(index);
2707 val = RBIOS8(index);
2709 radeon_i2c_put_byte(tmds->i2c_bus,
2714 DRM_ERROR("Unknown id %d\n", id >> 13);
2723 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2725 index = offset + 10;
2726 id = RBIOS16(index);
2727 while (id != 0xffff) {
2731 reg = (id & 0x1fff) * 4;
2732 val = RBIOS32(index);
2736 reg = (id & 0x1fff) * 4;
2737 and_mask = RBIOS32(index);
2739 or_mask = RBIOS32(index);
2742 val = (val & and_mask) | or_mask;
2746 val = RBIOS16(index);
2752 and_mask = RBIOS32(index);
2754 or_mask = RBIOS32(index);
2756 val = RREG32_PLL(reg);
2757 val = (val & and_mask) | or_mask;
2758 WREG32_PLL(reg, val);
2762 val = RBIOS8(index);
2764 radeon_i2c_put_byte(tmds->i2c_bus,
2769 DRM_ERROR("Unknown id %d\n", id >> 13);
2772 id = RBIOS16(index);
2780 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2782 struct radeon_device *rdev = dev->dev_private;
2785 while (RBIOS16(offset)) {
2786 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2787 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2788 uint32_t val, and_mask, or_mask;
2794 val = RBIOS32(offset);
2799 val = RBIOS32(offset);
2804 and_mask = RBIOS32(offset);
2806 or_mask = RBIOS32(offset);
2814 and_mask = RBIOS32(offset);
2816 or_mask = RBIOS32(offset);
2824 val = RBIOS16(offset);
2829 val = RBIOS16(offset);
2836 (RADEON_CLK_PWRMGT_CNTL) &
2843 if ((RREG32(RADEON_MC_STATUS) &
2859 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2861 struct radeon_device *rdev = dev->dev_private;
2864 while (RBIOS8(offset)) {
2865 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2866 uint8_t addr = (RBIOS8(offset) & 0x3f);
2867 uint32_t val, shift, tmp;
2868 uint32_t and_mask, or_mask;
2873 val = RBIOS32(offset);
2875 WREG32_PLL(addr, val);
2878 shift = RBIOS8(offset) * 8;
2880 and_mask = RBIOS8(offset) << shift;
2881 and_mask |= ~(0xff << shift);
2883 or_mask = RBIOS8(offset) << shift;
2885 tmp = RREG32_PLL(addr);
2888 WREG32_PLL(addr, tmp);
2904 (RADEON_CLK_PWRMGT_CNTL) &
2912 (RADEON_CLK_PWRMGT_CNTL) &
2919 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2920 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2922 uint32_t mclk_cntl =
2925 mclk_cntl &= 0xffff0000;
2926 /*mclk_cntl |= 0x00001111;*//* ??? */
2927 WREG32_PLL(RADEON_MCLK_CNTL,
2932 (RADEON_CLK_PWRMGT_CNTL,
2934 ~RADEON_CG_NO1_DEBUG_0);
2949 static void combios_parse_ram_reset_table(struct drm_device *dev,
2952 struct radeon_device *rdev = dev->dev_private;
2956 uint8_t val = RBIOS8(offset);
2957 while (val != 0xff) {
2961 uint32_t channel_complete_mask;
2963 if (ASIC_IS_R300(rdev))
2964 channel_complete_mask =
2965 R300_MEM_PWRUP_COMPLETE;
2967 channel_complete_mask =
2968 RADEON_MEM_PWRUP_COMPLETE;
2971 if ((RREG32(RADEON_MEM_STR_CNTL) &
2972 channel_complete_mask) ==
2973 channel_complete_mask)
2977 uint32_t or_mask = RBIOS16(offset);
2980 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2981 tmp &= RADEON_SDRAM_MODE_MASK;
2983 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2985 or_mask = val << 24;
2986 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2987 tmp &= RADEON_B3MEM_RESET_MASK;
2989 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2991 val = RBIOS8(offset);
2996 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2997 int mem_addr_mapping)
2999 struct radeon_device *rdev = dev->dev_private;
3004 mem_cntl = RREG32(RADEON_MEM_CNTL);
3005 if (mem_cntl & RV100_HALF_MODE)
3008 mem_cntl &= ~(0xff << 8);
3009 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3010 WREG32(RADEON_MEM_CNTL, mem_cntl);
3011 RREG32(RADEON_MEM_CNTL);
3015 /* something like this???? */
3017 addr = ram * 1024 * 1024;
3018 /* write to each page */
3019 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3020 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3021 /* read back and verify */
3022 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3023 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3030 static void combios_write_ram_size(struct drm_device *dev)
3032 struct radeon_device *rdev = dev->dev_private;
3035 uint32_t mem_size = 0;
3036 uint32_t mem_cntl = 0;
3038 /* should do something smarter here I guess... */
3039 if (rdev->flags & RADEON_IS_IGP)
3042 /* first check detected mem table */
3043 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3045 rev = RBIOS8(offset);
3047 mem_cntl = RBIOS32(offset + 1);
3048 mem_size = RBIOS16(offset + 5);
3049 if ((rdev->family < CHIP_R200) &&
3050 !ASIC_IS_RN50(rdev))
3051 WREG32(RADEON_MEM_CNTL, mem_cntl);
3057 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3059 rev = RBIOS8(offset - 1);
3061 if ((rdev->family < CHIP_R200)
3062 && !ASIC_IS_RN50(rdev)) {
3064 int mem_addr_mapping = 0;
3066 while (RBIOS8(offset)) {
3067 ram = RBIOS8(offset);
3070 if (mem_addr_mapping != 0x25)
3073 combios_detect_ram(dev, ram,
3080 mem_size = RBIOS8(offset);
3082 mem_size = RBIOS8(offset);
3083 mem_size *= 2; /* convert to MB */
3088 mem_size *= (1024 * 1024); /* convert to bytes */
3089 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3092 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3094 uint16_t dyn_clk_info =
3095 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3098 combios_parse_pll_table(dev, dyn_clk_info);
3101 void radeon_combios_asic_init(struct drm_device *dev)
3103 struct radeon_device *rdev = dev->dev_private;
3106 /* port hardcoded mac stuff from radeonfb */
3107 if (rdev->bios == NULL)
3111 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3113 combios_parse_mmio_table(dev, table);
3116 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3118 combios_parse_pll_table(dev, table);
3121 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3123 combios_parse_mmio_table(dev, table);
3125 if (!(rdev->flags & RADEON_IS_IGP)) {
3128 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3130 combios_parse_mmio_table(dev, table);
3133 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3135 combios_parse_ram_reset_table(dev, table);
3139 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3141 combios_parse_mmio_table(dev, table);
3143 /* write CONFIG_MEMSIZE */
3144 combios_write_ram_size(dev);
3147 /* quirk for rs4xx HP nx6125 laptop to make it resume
3148 * - it hangs on resume inside the dynclk 1 table.
3150 if (rdev->family == CHIP_RS480 &&
3151 rdev->pdev->subsystem_vendor == 0x103c &&
3152 rdev->pdev->subsystem_device == 0x308b)
3155 /* quirk for rs4xx HP dv5000 laptop to make it resume
3156 * - it hangs on resume inside the dynclk 1 table.
3158 if (rdev->family == CHIP_RS480 &&
3159 rdev->pdev->subsystem_vendor == 0x103c &&
3160 rdev->pdev->subsystem_device == 0x30a4)
3164 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3166 combios_parse_pll_table(dev, table);
3170 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3172 struct radeon_device *rdev = dev->dev_private;
3173 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3175 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3176 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3177 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3179 /* let the bios control the backlight */
3180 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3182 /* tell the bios not to handle mode switching */
3183 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3184 RADEON_ACC_MODE_CHANGE);
3186 /* tell the bios a driver is loaded */
3187 bios_7_scratch |= RADEON_DRV_LOADED;
3189 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3190 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3191 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3194 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3196 struct drm_device *dev = encoder->dev;
3197 struct radeon_device *rdev = dev->dev_private;
3198 uint32_t bios_6_scratch;
3200 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3203 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3205 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3207 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3211 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3212 struct drm_encoder *encoder,
3215 struct drm_device *dev = connector->dev;
3216 struct radeon_device *rdev = dev->dev_private;
3217 struct radeon_connector *radeon_connector =
3218 to_radeon_connector(connector);
3219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3220 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3221 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3223 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3224 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3226 DRM_DEBUG_KMS("TV1 connected\n");
3228 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3229 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3230 bios_5_scratch |= RADEON_TV1_ON;
3231 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3233 DRM_DEBUG_KMS("TV1 disconnected\n");
3234 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3235 bios_5_scratch &= ~RADEON_TV1_ON;
3236 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3239 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3240 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3242 DRM_DEBUG_KMS("LCD1 connected\n");
3243 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3244 bios_5_scratch |= RADEON_LCD1_ON;
3245 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3247 DRM_DEBUG_KMS("LCD1 disconnected\n");
3248 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3249 bios_5_scratch &= ~RADEON_LCD1_ON;
3250 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3253 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3254 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3256 DRM_DEBUG_KMS("CRT1 connected\n");
3257 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3258 bios_5_scratch |= RADEON_CRT1_ON;
3259 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3261 DRM_DEBUG_KMS("CRT1 disconnected\n");
3262 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3263 bios_5_scratch &= ~RADEON_CRT1_ON;
3264 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3267 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3268 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3270 DRM_DEBUG_KMS("CRT2 connected\n");
3271 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3272 bios_5_scratch |= RADEON_CRT2_ON;
3273 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3275 DRM_DEBUG_KMS("CRT2 disconnected\n");
3276 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3277 bios_5_scratch &= ~RADEON_CRT2_ON;
3278 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3281 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3282 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3284 DRM_DEBUG_KMS("DFP1 connected\n");
3285 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3286 bios_5_scratch |= RADEON_DFP1_ON;
3287 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3289 DRM_DEBUG_KMS("DFP1 disconnected\n");
3290 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3291 bios_5_scratch &= ~RADEON_DFP1_ON;
3292 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3295 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3296 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3298 DRM_DEBUG_KMS("DFP2 connected\n");
3299 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3300 bios_5_scratch |= RADEON_DFP2_ON;
3301 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3303 DRM_DEBUG_KMS("DFP2 disconnected\n");
3304 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3305 bios_5_scratch &= ~RADEON_DFP2_ON;
3306 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3309 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3310 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3314 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3316 struct drm_device *dev = encoder->dev;
3317 struct radeon_device *rdev = dev->dev_private;
3318 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3319 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3321 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3322 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3323 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3325 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3326 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3327 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3329 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3330 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3331 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3333 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3334 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3335 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3337 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3338 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3339 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3341 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3342 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3343 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3345 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3349 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3351 struct drm_device *dev = encoder->dev;
3352 struct radeon_device *rdev = dev->dev_private;
3353 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3354 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3356 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3358 bios_6_scratch |= RADEON_TV_DPMS_ON;
3360 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3362 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3364 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3366 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3368 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3370 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3372 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3374 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3376 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3378 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3380 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);