2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
114 enum radeon_combios_ddc {
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
149 struct radeon_device *rdev = dev->dev_private;
151 uint16_t offset = 0, check_offset;
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
161 offset = check_offset;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
166 offset = check_offset;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
171 offset = check_offset;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
176 offset = check_offset;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
181 offset = check_offset;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
186 offset = check_offset;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
191 offset = check_offset;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
196 offset = check_offset;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
201 offset = check_offset;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
206 offset = check_offset;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
211 offset = check_offset;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
216 offset = check_offset;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
221 offset = check_offset;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
226 offset = check_offset;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
231 offset = check_offset;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
236 offset = check_offset;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
241 offset = check_offset;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
246 offset = check_offset;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
251 offset = check_offset;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
256 offset = check_offset;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
261 offset = check_offset;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
266 offset = check_offset;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
271 offset = check_offset;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
276 offset = check_offset;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
281 offset = check_offset;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
286 offset = check_offset;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
291 offset = check_offset;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
296 offset = check_offset;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
301 offset = check_offset;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
306 offset = check_offset;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
311 offset = check_offset;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
316 offset = check_offset;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
321 offset = check_offset;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
326 offset = check_offset;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
333 rev = RBIOS8(check_offset);
335 check_offset = RBIOS16(check_offset + 0x3);
337 offset = check_offset;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
345 rev = RBIOS8(check_offset);
347 check_offset = RBIOS16(check_offset + 0x5);
349 offset = check_offset;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
357 rev = RBIOS8(check_offset);
359 check_offset = RBIOS16(check_offset + 0x7);
361 offset = check_offset;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
369 rev = RBIOS8(check_offset);
371 check_offset = RBIOS16(check_offset + 0x9);
373 offset = check_offset;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
381 while (RBIOS8(check_offset++));
384 offset = check_offset;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
391 check_offset = RBIOS16(check_offset + 0x11);
393 offset = check_offset;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
400 check_offset = RBIOS16(check_offset + 0x13);
402 offset = check_offset;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
409 check_offset = RBIOS16(check_offset + 0x15);
411 offset = check_offset;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
418 check_offset = RBIOS16(check_offset + 0x17);
420 offset = check_offset;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
427 check_offset = RBIOS16(check_offset + 0x2);
429 offset = check_offset;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
436 check_offset = RBIOS16(check_offset + 0x4);
438 offset = check_offset;
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
458 raw = rdev->bios + edid_info;
459 edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
463 memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
465 if (!drm_edid_is_valid(edid)) {
470 rdev->mode_info.bios_hardcoded_edid = edid;
475 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
477 if (rdev->mode_info.bios_hardcoded_edid)
478 return rdev->mode_info.bios_hardcoded_edid;
482 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
483 enum radeon_combios_ddc ddc,
487 struct radeon_i2c_bus_rec i2c;
491 * DDC_NONE_DETECTED = none
492 * DDC_DVI = RADEON_GPIO_DVI_DDC
493 * DDC_VGA = RADEON_GPIO_VGA_DDC
494 * DDC_LCD = RADEON_GPIOPAD_MASK
495 * DDC_GPIO = RADEON_MDGPIO_MASK
497 * DDC_MONID = RADEON_GPIO_MONID
498 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
500 * DDC_MONID = RADEON_GPIO_MONID
501 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
503 * DDC_MONID = RADEON_GPIOPAD_MASK
504 * DDC_CRT2 = RADEON_GPIO_MONID
507 case DDC_NONE_DETECTED:
512 ddc_line = RADEON_GPIO_DVI_DDC;
515 ddc_line = RADEON_GPIO_VGA_DDC;
518 ddc_line = RADEON_GPIOPAD_MASK;
521 ddc_line = RADEON_MDGPIO_MASK;
524 if (rdev->family == CHIP_RS300 ||
525 rdev->family == CHIP_RS400 ||
526 rdev->family == CHIP_RS480)
527 ddc_line = RADEON_GPIOPAD_MASK;
529 ddc_line = RADEON_GPIO_MONID;
532 if (rdev->family == CHIP_RS300 ||
533 rdev->family == CHIP_RS400 ||
534 rdev->family == CHIP_RS480)
535 ddc_line = RADEON_GPIO_MONID;
536 else if (rdev->family >= CHIP_R300) {
537 ddc_line = RADEON_GPIO_DVI_DDC;
540 ddc_line = RADEON_GPIO_CRT2_DDC;
544 if (ddc_line == RADEON_GPIOPAD_MASK) {
545 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
546 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
547 i2c.a_clk_reg = RADEON_GPIOPAD_A;
548 i2c.a_data_reg = RADEON_GPIOPAD_A;
549 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
550 i2c.en_data_reg = RADEON_GPIOPAD_EN;
551 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
552 i2c.y_data_reg = RADEON_GPIOPAD_Y;
553 } else if (ddc_line == RADEON_MDGPIO_MASK) {
554 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
555 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
556 i2c.a_clk_reg = RADEON_MDGPIO_A;
557 i2c.a_data_reg = RADEON_MDGPIO_A;
558 i2c.en_clk_reg = RADEON_MDGPIO_EN;
559 i2c.en_data_reg = RADEON_MDGPIO_EN;
560 i2c.y_clk_reg = RADEON_MDGPIO_Y;
561 i2c.y_data_reg = RADEON_MDGPIO_Y;
563 i2c.mask_clk_reg = ddc_line;
564 i2c.mask_data_reg = ddc_line;
565 i2c.a_clk_reg = ddc_line;
566 i2c.a_data_reg = ddc_line;
567 i2c.en_clk_reg = ddc_line;
568 i2c.en_data_reg = ddc_line;
569 i2c.y_clk_reg = ddc_line;
570 i2c.y_data_reg = ddc_line;
573 if (clk_mask && data_mask) {
574 i2c.mask_clk_mask = clk_mask;
575 i2c.mask_data_mask = data_mask;
576 i2c.a_clk_mask = clk_mask;
577 i2c.a_data_mask = data_mask;
578 i2c.en_clk_mask = clk_mask;
579 i2c.en_data_mask = data_mask;
580 i2c.y_clk_mask = clk_mask;
581 i2c.y_data_mask = data_mask;
583 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
584 i2c.mask_data_mask = RADEON_GPIO_EN_0;
585 i2c.a_clk_mask = RADEON_GPIO_A_1;
586 i2c.a_data_mask = RADEON_GPIO_A_0;
587 i2c.en_clk_mask = RADEON_GPIO_EN_1;
588 i2c.en_data_mask = RADEON_GPIO_EN_0;
589 i2c.y_clk_mask = RADEON_GPIO_Y_1;
590 i2c.y_data_mask = RADEON_GPIO_Y_0;
593 switch (rdev->family) {
601 case RADEON_GPIO_DVI_DDC:
602 i2c.hw_capable = true;
605 i2c.hw_capable = false;
611 case RADEON_GPIO_DVI_DDC:
612 case RADEON_GPIO_MONID:
613 i2c.hw_capable = true;
616 i2c.hw_capable = false;
623 case RADEON_GPIO_VGA_DDC:
624 case RADEON_GPIO_DVI_DDC:
625 case RADEON_GPIO_CRT2_DDC:
626 i2c.hw_capable = true;
629 i2c.hw_capable = false;
636 case RADEON_GPIO_VGA_DDC:
637 case RADEON_GPIO_DVI_DDC:
638 i2c.hw_capable = true;
641 i2c.hw_capable = false;
650 case RADEON_GPIO_VGA_DDC:
651 case RADEON_GPIO_DVI_DDC:
652 i2c.hw_capable = true;
654 case RADEON_GPIO_MONID:
655 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
656 * reliably on some pre-r4xx hardware; not sure why.
658 i2c.hw_capable = false;
661 i2c.hw_capable = false;
666 i2c.hw_capable = false;
672 i2c.hpd = RADEON_HPD_NONE;
682 void radeon_combios_i2c_init(struct radeon_device *rdev)
684 struct drm_device *dev = rdev->ddev;
685 struct radeon_i2c_bus_rec i2c;
688 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
689 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
691 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
692 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
695 i2c.hw_capable = true;
698 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
700 if (rdev->family == CHIP_RS300 ||
701 rdev->family == CHIP_RS400 ||
702 rdev->family == CHIP_RS480) {
704 u8 id, blocks, clk, data;
707 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
708 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
710 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
712 blocks = RBIOS8(offset + 2);
713 for (i = 0; i < blocks; i++) {
714 id = RBIOS8(offset + 3 + (i * 5) + 0);
716 clk = RBIOS8(offset + 3 + (i * 5) + 3);
717 data = RBIOS8(offset + 3 + (i * 5) + 4);
718 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
720 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
726 } else if (rdev->family >= CHIP_R300) {
727 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
728 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
730 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
731 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
733 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
734 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
738 bool radeon_combios_get_clock_info(struct drm_device *dev)
740 struct radeon_device *rdev = dev->dev_private;
742 struct radeon_pll *p1pll = &rdev->clock.p1pll;
743 struct radeon_pll *p2pll = &rdev->clock.p2pll;
744 struct radeon_pll *spll = &rdev->clock.spll;
745 struct radeon_pll *mpll = &rdev->clock.mpll;
749 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
751 rev = RBIOS8(pll_info);
754 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
755 p1pll->reference_div = RBIOS16(pll_info + 0x10);
756 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
757 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
758 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
759 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
762 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
763 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
765 p1pll->pll_in_min = 40;
766 p1pll->pll_in_max = 500;
771 spll->reference_freq = RBIOS16(pll_info + 0x1a);
772 spll->reference_div = RBIOS16(pll_info + 0x1c);
773 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
774 spll->pll_out_max = RBIOS32(pll_info + 0x22);
777 spll->pll_in_min = RBIOS32(pll_info + 0x48);
778 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
781 spll->pll_in_min = 40;
782 spll->pll_in_max = 500;
786 mpll->reference_freq = RBIOS16(pll_info + 0x26);
787 mpll->reference_div = RBIOS16(pll_info + 0x28);
788 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
789 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
792 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
793 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
796 mpll->pll_in_min = 40;
797 mpll->pll_in_max = 500;
800 /* default sclk/mclk */
801 sclk = RBIOS16(pll_info + 0xa);
802 mclk = RBIOS16(pll_info + 0x8);
808 rdev->clock.default_sclk = sclk;
809 rdev->clock.default_mclk = mclk;
816 bool radeon_combios_sideport_present(struct radeon_device *rdev)
818 struct drm_device *dev = rdev->ddev;
821 /* sideport is AMD only */
822 if (rdev->family == CHIP_RS400)
825 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
828 if (RBIOS16(igp_info + 0x4))
834 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
835 0x00000808, /* r100 */
836 0x00000808, /* rv100 */
837 0x00000808, /* rs100 */
838 0x00000808, /* rv200 */
839 0x00000808, /* rs200 */
840 0x00000808, /* r200 */
841 0x00000808, /* rv250 */
842 0x00000000, /* rs300 */
843 0x00000808, /* rv280 */
844 0x00000808, /* r300 */
845 0x00000808, /* r350 */
846 0x00000808, /* rv350 */
847 0x00000808, /* rv380 */
848 0x00000808, /* r420 */
849 0x00000808, /* r423 */
850 0x00000808, /* rv410 */
851 0x00000000, /* rs400 */
852 0x00000000, /* rs480 */
855 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
856 struct radeon_encoder_primary_dac *p_dac)
858 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
862 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
866 struct drm_device *dev = encoder->base.dev;
867 struct radeon_device *rdev = dev->dev_private;
869 uint8_t rev, bg, dac;
870 struct radeon_encoder_primary_dac *p_dac = NULL;
873 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
879 /* check CRT table */
880 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
882 rev = RBIOS8(dac_info) & 0x3;
884 bg = RBIOS8(dac_info + 0x2) & 0xf;
885 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
886 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
888 bg = RBIOS8(dac_info + 0x2) & 0xf;
889 dac = RBIOS8(dac_info + 0x3) & 0xf;
890 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
892 /* if the values are all zeros, use the table */
893 if (p_dac->ps2_pdac_adj)
897 if (!found) /* fallback to defaults */
898 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
904 radeon_combios_get_tv_info(struct radeon_device *rdev)
906 struct drm_device *dev = rdev->ddev;
908 enum radeon_tv_std tv_std = TV_STD_NTSC;
910 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
912 if (RBIOS8(tv_info + 6) == 'T') {
913 switch (RBIOS8(tv_info + 7) & 0xf) {
915 tv_std = TV_STD_NTSC;
916 DRM_INFO("Default TV standard: NTSC\n");
920 DRM_INFO("Default TV standard: PAL\n");
923 tv_std = TV_STD_PAL_M;
924 DRM_INFO("Default TV standard: PAL-M\n");
927 tv_std = TV_STD_PAL_60;
928 DRM_INFO("Default TV standard: PAL-60\n");
931 tv_std = TV_STD_NTSC_J;
932 DRM_INFO("Default TV standard: NTSC-J\n");
935 tv_std = TV_STD_SCART_PAL;
936 DRM_INFO("Default TV standard: SCART-PAL\n");
939 tv_std = TV_STD_NTSC;
941 ("Unknown TV standard; defaulting to NTSC\n");
945 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
947 DRM_INFO("29.498928713 MHz TV ref clk\n");
950 DRM_INFO("28.636360000 MHz TV ref clk\n");
953 DRM_INFO("14.318180000 MHz TV ref clk\n");
956 DRM_INFO("27.000000000 MHz TV ref clk\n");
966 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
967 0x00000000, /* r100 */
968 0x00280000, /* rv100 */
969 0x00000000, /* rs100 */
970 0x00880000, /* rv200 */
971 0x00000000, /* rs200 */
972 0x00000000, /* r200 */
973 0x00770000, /* rv250 */
974 0x00290000, /* rs300 */
975 0x00560000, /* rv280 */
976 0x00780000, /* r300 */
977 0x00770000, /* r350 */
978 0x00780000, /* rv350 */
979 0x00780000, /* rv380 */
980 0x01080000, /* r420 */
981 0x01080000, /* r423 */
982 0x01080000, /* rv410 */
983 0x00780000, /* rs400 */
984 0x00780000, /* rs480 */
987 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
988 struct radeon_encoder_tv_dac *tv_dac)
990 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
991 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
992 tv_dac->ps2_tvdac_adj = 0x00880000;
993 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
994 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
998 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1002 struct drm_device *dev = encoder->base.dev;
1003 struct radeon_device *rdev = dev->dev_private;
1005 uint8_t rev, bg, dac;
1006 struct radeon_encoder_tv_dac *tv_dac = NULL;
1009 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1013 /* first check TV table */
1014 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1016 rev = RBIOS8(dac_info + 0x3);
1018 bg = RBIOS8(dac_info + 0xc) & 0xf;
1019 dac = RBIOS8(dac_info + 0xd) & 0xf;
1020 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1022 bg = RBIOS8(dac_info + 0xe) & 0xf;
1023 dac = RBIOS8(dac_info + 0xf) & 0xf;
1024 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1026 bg = RBIOS8(dac_info + 0x10) & 0xf;
1027 dac = RBIOS8(dac_info + 0x11) & 0xf;
1028 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1029 /* if the values are all zeros, use the table */
1030 if (tv_dac->ps2_tvdac_adj)
1032 } else if (rev > 1) {
1033 bg = RBIOS8(dac_info + 0xc) & 0xf;
1034 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1035 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1037 bg = RBIOS8(dac_info + 0xd) & 0xf;
1038 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1039 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1041 bg = RBIOS8(dac_info + 0xe) & 0xf;
1042 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1043 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1044 /* if the values are all zeros, use the table */
1045 if (tv_dac->ps2_tvdac_adj)
1048 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1051 /* then check CRT table */
1053 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1055 rev = RBIOS8(dac_info) & 0x3;
1057 bg = RBIOS8(dac_info + 0x3) & 0xf;
1058 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1059 tv_dac->ps2_tvdac_adj =
1060 (bg << 16) | (dac << 20);
1061 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1062 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1063 /* if the values are all zeros, use the table */
1064 if (tv_dac->ps2_tvdac_adj)
1067 bg = RBIOS8(dac_info + 0x4) & 0xf;
1068 dac = RBIOS8(dac_info + 0x5) & 0xf;
1069 tv_dac->ps2_tvdac_adj =
1070 (bg << 16) | (dac << 20);
1071 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1072 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1073 /* if the values are all zeros, use the table */
1074 if (tv_dac->ps2_tvdac_adj)
1078 DRM_INFO("No TV DAC info found in BIOS\n");
1082 if (!found) /* fallback to defaults */
1083 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1088 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1092 struct radeon_encoder_lvds *lvds = NULL;
1093 uint32_t fp_vert_stretch, fp_horz_stretch;
1094 uint32_t ppll_div_sel, ppll_val;
1095 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1097 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1102 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1103 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1105 /* These should be fail-safe defaults, fingers crossed */
1106 lvds->panel_pwr_delay = 200;
1107 lvds->panel_vcc_delay = 2000;
1109 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1110 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1111 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1113 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1114 lvds->native_mode.vdisplay =
1115 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1116 RADEON_VERT_PANEL_SHIFT) + 1;
1118 lvds->native_mode.vdisplay =
1119 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1121 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1122 lvds->native_mode.hdisplay =
1123 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1124 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1126 lvds->native_mode.hdisplay =
1127 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1129 if ((lvds->native_mode.hdisplay < 640) ||
1130 (lvds->native_mode.vdisplay < 480)) {
1131 lvds->native_mode.hdisplay = 640;
1132 lvds->native_mode.vdisplay = 480;
1135 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1136 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1137 if ((ppll_val & 0x000707ff) == 0x1bb)
1138 lvds->use_bios_dividers = false;
1140 lvds->panel_ref_divider =
1141 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1142 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1143 lvds->panel_fb_divider = ppll_val & 0x7ff;
1145 if ((lvds->panel_ref_divider != 0) &&
1146 (lvds->panel_fb_divider > 3))
1147 lvds->use_bios_dividers = true;
1149 lvds->panel_vcc_delay = 200;
1151 DRM_INFO("Panel info derived from registers\n");
1152 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1153 lvds->native_mode.vdisplay);
1158 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1161 struct drm_device *dev = encoder->base.dev;
1162 struct radeon_device *rdev = dev->dev_private;
1164 uint32_t panel_setup;
1167 struct radeon_encoder_lvds *lvds = NULL;
1169 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1172 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1177 for (i = 0; i < 24; i++)
1178 stmp[i] = RBIOS8(lcd_info + i + 1);
1181 DRM_INFO("Panel ID String: %s\n", stmp);
1183 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1184 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1186 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1187 lvds->native_mode.vdisplay);
1189 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1190 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1192 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1193 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1194 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1196 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1197 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1198 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1199 if ((lvds->panel_ref_divider != 0) &&
1200 (lvds->panel_fb_divider > 3))
1201 lvds->use_bios_dividers = true;
1203 panel_setup = RBIOS32(lcd_info + 0x39);
1204 lvds->lvds_gen_cntl = 0xff00;
1205 if (panel_setup & 0x1)
1206 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1208 if ((panel_setup >> 4) & 0x1)
1209 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1211 switch ((panel_setup >> 8) & 0x7) {
1213 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1216 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1219 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1225 if ((panel_setup >> 16) & 0x1)
1226 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1228 if ((panel_setup >> 17) & 0x1)
1229 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1231 if ((panel_setup >> 18) & 0x1)
1232 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1234 if ((panel_setup >> 23) & 0x1)
1235 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1237 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1239 for (i = 0; i < 32; i++) {
1240 tmp = RBIOS16(lcd_info + 64 + i * 2);
1244 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1245 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1246 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1247 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1248 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1249 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1250 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1251 (RBIOS8(tmp + 23) * 8);
1253 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1254 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1255 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1256 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1257 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1258 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1260 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1261 lvds->native_mode.flags = 0;
1262 /* set crtc values */
1263 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1268 DRM_INFO("No panel info found in BIOS\n");
1269 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1273 encoder->native_mode = lvds->native_mode;
1277 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1278 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1279 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1280 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1281 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1282 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1283 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1284 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1285 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1286 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1287 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1288 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1289 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1290 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1291 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1292 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1293 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1294 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1295 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1298 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1299 struct radeon_encoder_int_tmds *tmds)
1301 struct drm_device *dev = encoder->base.dev;
1302 struct radeon_device *rdev = dev->dev_private;
1305 for (i = 0; i < 4; i++) {
1306 tmds->tmds_pll[i].value =
1307 default_tmds_pll[rdev->family][i].value;
1308 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1314 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1315 struct radeon_encoder_int_tmds *tmds)
1317 struct drm_device *dev = encoder->base.dev;
1318 struct radeon_device *rdev = dev->dev_private;
1323 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1326 ver = RBIOS8(tmds_info);
1327 DRM_INFO("DFP table revision: %d\n", ver);
1329 n = RBIOS8(tmds_info + 5) + 1;
1332 for (i = 0; i < n; i++) {
1333 tmds->tmds_pll[i].value =
1334 RBIOS32(tmds_info + i * 10 + 0x08);
1335 tmds->tmds_pll[i].freq =
1336 RBIOS16(tmds_info + i * 10 + 0x10);
1337 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1338 tmds->tmds_pll[i].freq,
1339 tmds->tmds_pll[i].value);
1341 } else if (ver == 4) {
1343 n = RBIOS8(tmds_info + 5) + 1;
1346 for (i = 0; i < n; i++) {
1347 tmds->tmds_pll[i].value =
1348 RBIOS32(tmds_info + stride + 0x08);
1349 tmds->tmds_pll[i].freq =
1350 RBIOS16(tmds_info + stride + 0x10);
1355 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1356 tmds->tmds_pll[i].freq,
1357 tmds->tmds_pll[i].value);
1361 DRM_INFO("No TMDS info found in BIOS\n");
1367 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1368 struct radeon_encoder_ext_tmds *tmds)
1370 struct drm_device *dev = encoder->base.dev;
1371 struct radeon_device *rdev = dev->dev_private;
1372 struct radeon_i2c_bus_rec i2c_bus;
1374 /* default for macs */
1375 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1376 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1378 /* XXX some macs have duallink chips */
1379 switch (rdev->mode_info.connector_table) {
1380 case CT_POWERBOOK_EXTERNAL:
1381 case CT_MINI_EXTERNAL:
1383 tmds->dvo_chip = DVO_SIL164;
1384 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1391 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1392 struct radeon_encoder_ext_tmds *tmds)
1394 struct drm_device *dev = encoder->base.dev;
1395 struct radeon_device *rdev = dev->dev_private;
1398 enum radeon_combios_ddc gpio;
1399 struct radeon_i2c_bus_rec i2c_bus;
1401 tmds->i2c_bus = NULL;
1402 if (rdev->flags & RADEON_IS_IGP) {
1403 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1404 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1405 tmds->dvo_chip = DVO_SIL164;
1406 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1410 ver = RBIOS8(offset);
1411 DRM_INFO("External TMDS Table revision: %d\n", ver);
1412 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1413 tmds->slave_addr >>= 1; /* 7 bit addressing */
1414 gpio = RBIOS8(offset + 4 + 3);
1415 if (gpio == DDC_LCD) {
1417 i2c_bus.valid = true;
1418 i2c_bus.hw_capable = true;
1419 i2c_bus.mm_i2c = true;
1420 i2c_bus.i2c_id = 0xa0;
1422 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1423 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1427 if (!tmds->i2c_bus) {
1428 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1435 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1437 struct radeon_device *rdev = dev->dev_private;
1438 struct radeon_i2c_bus_rec ddc_i2c;
1439 struct radeon_hpd hpd;
1441 rdev->mode_info.connector_table = radeon_connector_table;
1442 if (rdev->mode_info.connector_table == CT_NONE) {
1443 #ifdef CONFIG_PPC_PMAC
1444 if (of_machine_is_compatible("PowerBook3,3")) {
1445 /* powerbook with VGA */
1446 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1447 } else if (of_machine_is_compatible("PowerBook3,4") ||
1448 of_machine_is_compatible("PowerBook3,5")) {
1449 /* powerbook with internal tmds */
1450 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1451 } else if (of_machine_is_compatible("PowerBook5,1") ||
1452 of_machine_is_compatible("PowerBook5,2") ||
1453 of_machine_is_compatible("PowerBook5,3") ||
1454 of_machine_is_compatible("PowerBook5,4") ||
1455 of_machine_is_compatible("PowerBook5,5")) {
1456 /* powerbook with external single link tmds (sil164) */
1457 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1458 } else if (of_machine_is_compatible("PowerBook5,6")) {
1459 /* powerbook with external dual or single link tmds */
1460 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1461 } else if (of_machine_is_compatible("PowerBook5,7") ||
1462 of_machine_is_compatible("PowerBook5,8") ||
1463 of_machine_is_compatible("PowerBook5,9")) {
1464 /* PowerBook6,2 ? */
1465 /* powerbook with external dual link tmds (sil1178?) */
1466 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1467 } else if (of_machine_is_compatible("PowerBook4,1") ||
1468 of_machine_is_compatible("PowerBook4,2") ||
1469 of_machine_is_compatible("PowerBook4,3") ||
1470 of_machine_is_compatible("PowerBook6,3") ||
1471 of_machine_is_compatible("PowerBook6,5") ||
1472 of_machine_is_compatible("PowerBook6,7")) {
1474 rdev->mode_info.connector_table = CT_IBOOK;
1475 } else if (of_machine_is_compatible("PowerMac4,4")) {
1477 rdev->mode_info.connector_table = CT_EMAC;
1478 } else if (of_machine_is_compatible("PowerMac10,1")) {
1479 /* mini with internal tmds */
1480 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1481 } else if (of_machine_is_compatible("PowerMac10,2")) {
1482 /* mini with external tmds */
1483 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1484 } else if (of_machine_is_compatible("PowerMac12,1")) {
1486 /* imac g5 isight */
1487 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1489 #endif /* CONFIG_PPC_PMAC */
1491 if (ASIC_IS_RN50(rdev))
1492 rdev->mode_info.connector_table = CT_RN50_POWER;
1495 rdev->mode_info.connector_table = CT_GENERIC;
1498 switch (rdev->mode_info.connector_table) {
1500 DRM_INFO("Connector Table: %d (generic)\n",
1501 rdev->mode_info.connector_table);
1502 /* these are the most common settings */
1503 if (rdev->flags & RADEON_SINGLE_CRTC) {
1504 /* VGA - primary dac */
1505 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1506 hpd.hpd = RADEON_HPD_NONE;
1507 radeon_add_legacy_encoder(dev,
1508 radeon_get_encoder_enum(dev,
1509 ATOM_DEVICE_CRT1_SUPPORT,
1511 ATOM_DEVICE_CRT1_SUPPORT);
1512 radeon_add_legacy_connector(dev, 0,
1513 ATOM_DEVICE_CRT1_SUPPORT,
1514 DRM_MODE_CONNECTOR_VGA,
1516 CONNECTOR_OBJECT_ID_VGA,
1518 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1520 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1521 hpd.hpd = RADEON_HPD_NONE;
1522 radeon_add_legacy_encoder(dev,
1523 radeon_get_encoder_enum(dev,
1524 ATOM_DEVICE_LCD1_SUPPORT,
1526 ATOM_DEVICE_LCD1_SUPPORT);
1527 radeon_add_legacy_connector(dev, 0,
1528 ATOM_DEVICE_LCD1_SUPPORT,
1529 DRM_MODE_CONNECTOR_LVDS,
1531 CONNECTOR_OBJECT_ID_LVDS,
1534 /* VGA - primary dac */
1535 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1536 hpd.hpd = RADEON_HPD_NONE;
1537 radeon_add_legacy_encoder(dev,
1538 radeon_get_encoder_enum(dev,
1539 ATOM_DEVICE_CRT1_SUPPORT,
1541 ATOM_DEVICE_CRT1_SUPPORT);
1542 radeon_add_legacy_connector(dev, 1,
1543 ATOM_DEVICE_CRT1_SUPPORT,
1544 DRM_MODE_CONNECTOR_VGA,
1546 CONNECTOR_OBJECT_ID_VGA,
1549 /* DVI-I - tv dac, int tmds */
1550 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1551 hpd.hpd = RADEON_HPD_1;
1552 radeon_add_legacy_encoder(dev,
1553 radeon_get_encoder_enum(dev,
1554 ATOM_DEVICE_DFP1_SUPPORT,
1556 ATOM_DEVICE_DFP1_SUPPORT);
1557 radeon_add_legacy_encoder(dev,
1558 radeon_get_encoder_enum(dev,
1559 ATOM_DEVICE_CRT2_SUPPORT,
1561 ATOM_DEVICE_CRT2_SUPPORT);
1562 radeon_add_legacy_connector(dev, 0,
1563 ATOM_DEVICE_DFP1_SUPPORT |
1564 ATOM_DEVICE_CRT2_SUPPORT,
1565 DRM_MODE_CONNECTOR_DVII,
1567 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1570 /* VGA - primary dac */
1571 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1572 hpd.hpd = RADEON_HPD_NONE;
1573 radeon_add_legacy_encoder(dev,
1574 radeon_get_encoder_enum(dev,
1575 ATOM_DEVICE_CRT1_SUPPORT,
1577 ATOM_DEVICE_CRT1_SUPPORT);
1578 radeon_add_legacy_connector(dev, 1,
1579 ATOM_DEVICE_CRT1_SUPPORT,
1580 DRM_MODE_CONNECTOR_VGA,
1582 CONNECTOR_OBJECT_ID_VGA,
1586 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1588 ddc_i2c.valid = false;
1589 hpd.hpd = RADEON_HPD_NONE;
1590 radeon_add_legacy_encoder(dev,
1591 radeon_get_encoder_enum(dev,
1592 ATOM_DEVICE_TV1_SUPPORT,
1594 ATOM_DEVICE_TV1_SUPPORT);
1595 radeon_add_legacy_connector(dev, 2,
1596 ATOM_DEVICE_TV1_SUPPORT,
1597 DRM_MODE_CONNECTOR_SVIDEO,
1599 CONNECTOR_OBJECT_ID_SVIDEO,
1604 DRM_INFO("Connector Table: %d (ibook)\n",
1605 rdev->mode_info.connector_table);
1607 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1608 hpd.hpd = RADEON_HPD_NONE;
1609 radeon_add_legacy_encoder(dev,
1610 radeon_get_encoder_enum(dev,
1611 ATOM_DEVICE_LCD1_SUPPORT,
1613 ATOM_DEVICE_LCD1_SUPPORT);
1614 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1615 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1616 CONNECTOR_OBJECT_ID_LVDS,
1619 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1620 hpd.hpd = RADEON_HPD_NONE;
1621 radeon_add_legacy_encoder(dev,
1622 radeon_get_encoder_enum(dev,
1623 ATOM_DEVICE_CRT2_SUPPORT,
1625 ATOM_DEVICE_CRT2_SUPPORT);
1626 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1627 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1628 CONNECTOR_OBJECT_ID_VGA,
1631 ddc_i2c.valid = false;
1632 hpd.hpd = RADEON_HPD_NONE;
1633 radeon_add_legacy_encoder(dev,
1634 radeon_get_encoder_enum(dev,
1635 ATOM_DEVICE_TV1_SUPPORT,
1637 ATOM_DEVICE_TV1_SUPPORT);
1638 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1639 DRM_MODE_CONNECTOR_SVIDEO,
1641 CONNECTOR_OBJECT_ID_SVIDEO,
1644 case CT_POWERBOOK_EXTERNAL:
1645 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1646 rdev->mode_info.connector_table);
1648 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1649 hpd.hpd = RADEON_HPD_NONE;
1650 radeon_add_legacy_encoder(dev,
1651 radeon_get_encoder_enum(dev,
1652 ATOM_DEVICE_LCD1_SUPPORT,
1654 ATOM_DEVICE_LCD1_SUPPORT);
1655 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1656 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1657 CONNECTOR_OBJECT_ID_LVDS,
1659 /* DVI-I - primary dac, ext tmds */
1660 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1661 hpd.hpd = RADEON_HPD_2; /* ??? */
1662 radeon_add_legacy_encoder(dev,
1663 radeon_get_encoder_enum(dev,
1664 ATOM_DEVICE_DFP2_SUPPORT,
1666 ATOM_DEVICE_DFP2_SUPPORT);
1667 radeon_add_legacy_encoder(dev,
1668 radeon_get_encoder_enum(dev,
1669 ATOM_DEVICE_CRT1_SUPPORT,
1671 ATOM_DEVICE_CRT1_SUPPORT);
1672 /* XXX some are SL */
1673 radeon_add_legacy_connector(dev, 1,
1674 ATOM_DEVICE_DFP2_SUPPORT |
1675 ATOM_DEVICE_CRT1_SUPPORT,
1676 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1677 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1680 ddc_i2c.valid = false;
1681 hpd.hpd = RADEON_HPD_NONE;
1682 radeon_add_legacy_encoder(dev,
1683 radeon_get_encoder_enum(dev,
1684 ATOM_DEVICE_TV1_SUPPORT,
1686 ATOM_DEVICE_TV1_SUPPORT);
1687 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1688 DRM_MODE_CONNECTOR_SVIDEO,
1690 CONNECTOR_OBJECT_ID_SVIDEO,
1693 case CT_POWERBOOK_INTERNAL:
1694 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1695 rdev->mode_info.connector_table);
1697 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1698 hpd.hpd = RADEON_HPD_NONE;
1699 radeon_add_legacy_encoder(dev,
1700 radeon_get_encoder_enum(dev,
1701 ATOM_DEVICE_LCD1_SUPPORT,
1703 ATOM_DEVICE_LCD1_SUPPORT);
1704 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1705 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1706 CONNECTOR_OBJECT_ID_LVDS,
1708 /* DVI-I - primary dac, int tmds */
1709 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1710 hpd.hpd = RADEON_HPD_1; /* ??? */
1711 radeon_add_legacy_encoder(dev,
1712 radeon_get_encoder_enum(dev,
1713 ATOM_DEVICE_DFP1_SUPPORT,
1715 ATOM_DEVICE_DFP1_SUPPORT);
1716 radeon_add_legacy_encoder(dev,
1717 radeon_get_encoder_enum(dev,
1718 ATOM_DEVICE_CRT1_SUPPORT,
1720 ATOM_DEVICE_CRT1_SUPPORT);
1721 radeon_add_legacy_connector(dev, 1,
1722 ATOM_DEVICE_DFP1_SUPPORT |
1723 ATOM_DEVICE_CRT1_SUPPORT,
1724 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1725 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1728 ddc_i2c.valid = false;
1729 hpd.hpd = RADEON_HPD_NONE;
1730 radeon_add_legacy_encoder(dev,
1731 radeon_get_encoder_enum(dev,
1732 ATOM_DEVICE_TV1_SUPPORT,
1734 ATOM_DEVICE_TV1_SUPPORT);
1735 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1736 DRM_MODE_CONNECTOR_SVIDEO,
1738 CONNECTOR_OBJECT_ID_SVIDEO,
1741 case CT_POWERBOOK_VGA:
1742 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1743 rdev->mode_info.connector_table);
1745 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1746 hpd.hpd = RADEON_HPD_NONE;
1747 radeon_add_legacy_encoder(dev,
1748 radeon_get_encoder_enum(dev,
1749 ATOM_DEVICE_LCD1_SUPPORT,
1751 ATOM_DEVICE_LCD1_SUPPORT);
1752 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1753 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1754 CONNECTOR_OBJECT_ID_LVDS,
1756 /* VGA - primary dac */
1757 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1758 hpd.hpd = RADEON_HPD_NONE;
1759 radeon_add_legacy_encoder(dev,
1760 radeon_get_encoder_enum(dev,
1761 ATOM_DEVICE_CRT1_SUPPORT,
1763 ATOM_DEVICE_CRT1_SUPPORT);
1764 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1765 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1766 CONNECTOR_OBJECT_ID_VGA,
1769 ddc_i2c.valid = false;
1770 hpd.hpd = RADEON_HPD_NONE;
1771 radeon_add_legacy_encoder(dev,
1772 radeon_get_encoder_enum(dev,
1773 ATOM_DEVICE_TV1_SUPPORT,
1775 ATOM_DEVICE_TV1_SUPPORT);
1776 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1777 DRM_MODE_CONNECTOR_SVIDEO,
1779 CONNECTOR_OBJECT_ID_SVIDEO,
1782 case CT_MINI_EXTERNAL:
1783 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1784 rdev->mode_info.connector_table);
1785 /* DVI-I - tv dac, ext tmds */
1786 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1787 hpd.hpd = RADEON_HPD_2; /* ??? */
1788 radeon_add_legacy_encoder(dev,
1789 radeon_get_encoder_enum(dev,
1790 ATOM_DEVICE_DFP2_SUPPORT,
1792 ATOM_DEVICE_DFP2_SUPPORT);
1793 radeon_add_legacy_encoder(dev,
1794 radeon_get_encoder_enum(dev,
1795 ATOM_DEVICE_CRT2_SUPPORT,
1797 ATOM_DEVICE_CRT2_SUPPORT);
1798 /* XXX are any DL? */
1799 radeon_add_legacy_connector(dev, 0,
1800 ATOM_DEVICE_DFP2_SUPPORT |
1801 ATOM_DEVICE_CRT2_SUPPORT,
1802 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1803 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1806 ddc_i2c.valid = false;
1807 hpd.hpd = RADEON_HPD_NONE;
1808 radeon_add_legacy_encoder(dev,
1809 radeon_get_encoder_enum(dev,
1810 ATOM_DEVICE_TV1_SUPPORT,
1812 ATOM_DEVICE_TV1_SUPPORT);
1813 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1814 DRM_MODE_CONNECTOR_SVIDEO,
1816 CONNECTOR_OBJECT_ID_SVIDEO,
1819 case CT_MINI_INTERNAL:
1820 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1821 rdev->mode_info.connector_table);
1822 /* DVI-I - tv dac, int tmds */
1823 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1824 hpd.hpd = RADEON_HPD_1; /* ??? */
1825 radeon_add_legacy_encoder(dev,
1826 radeon_get_encoder_enum(dev,
1827 ATOM_DEVICE_DFP1_SUPPORT,
1829 ATOM_DEVICE_DFP1_SUPPORT);
1830 radeon_add_legacy_encoder(dev,
1831 radeon_get_encoder_enum(dev,
1832 ATOM_DEVICE_CRT2_SUPPORT,
1834 ATOM_DEVICE_CRT2_SUPPORT);
1835 radeon_add_legacy_connector(dev, 0,
1836 ATOM_DEVICE_DFP1_SUPPORT |
1837 ATOM_DEVICE_CRT2_SUPPORT,
1838 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1839 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1842 ddc_i2c.valid = false;
1843 hpd.hpd = RADEON_HPD_NONE;
1844 radeon_add_legacy_encoder(dev,
1845 radeon_get_encoder_enum(dev,
1846 ATOM_DEVICE_TV1_SUPPORT,
1848 ATOM_DEVICE_TV1_SUPPORT);
1849 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1850 DRM_MODE_CONNECTOR_SVIDEO,
1852 CONNECTOR_OBJECT_ID_SVIDEO,
1855 case CT_IMAC_G5_ISIGHT:
1856 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1857 rdev->mode_info.connector_table);
1858 /* DVI-D - int tmds */
1859 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1860 hpd.hpd = RADEON_HPD_1; /* ??? */
1861 radeon_add_legacy_encoder(dev,
1862 radeon_get_encoder_enum(dev,
1863 ATOM_DEVICE_DFP1_SUPPORT,
1865 ATOM_DEVICE_DFP1_SUPPORT);
1866 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1867 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1868 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1871 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1872 hpd.hpd = RADEON_HPD_NONE;
1873 radeon_add_legacy_encoder(dev,
1874 radeon_get_encoder_enum(dev,
1875 ATOM_DEVICE_CRT2_SUPPORT,
1877 ATOM_DEVICE_CRT2_SUPPORT);
1878 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1879 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1880 CONNECTOR_OBJECT_ID_VGA,
1883 ddc_i2c.valid = false;
1884 hpd.hpd = RADEON_HPD_NONE;
1885 radeon_add_legacy_encoder(dev,
1886 radeon_get_encoder_enum(dev,
1887 ATOM_DEVICE_TV1_SUPPORT,
1889 ATOM_DEVICE_TV1_SUPPORT);
1890 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1891 DRM_MODE_CONNECTOR_SVIDEO,
1893 CONNECTOR_OBJECT_ID_SVIDEO,
1897 DRM_INFO("Connector Table: %d (emac)\n",
1898 rdev->mode_info.connector_table);
1899 /* VGA - primary dac */
1900 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1901 hpd.hpd = RADEON_HPD_NONE;
1902 radeon_add_legacy_encoder(dev,
1903 radeon_get_encoder_enum(dev,
1904 ATOM_DEVICE_CRT1_SUPPORT,
1906 ATOM_DEVICE_CRT1_SUPPORT);
1907 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1908 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1909 CONNECTOR_OBJECT_ID_VGA,
1912 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1913 hpd.hpd = RADEON_HPD_NONE;
1914 radeon_add_legacy_encoder(dev,
1915 radeon_get_encoder_enum(dev,
1916 ATOM_DEVICE_CRT2_SUPPORT,
1918 ATOM_DEVICE_CRT2_SUPPORT);
1919 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1920 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1921 CONNECTOR_OBJECT_ID_VGA,
1924 ddc_i2c.valid = false;
1925 hpd.hpd = RADEON_HPD_NONE;
1926 radeon_add_legacy_encoder(dev,
1927 radeon_get_encoder_enum(dev,
1928 ATOM_DEVICE_TV1_SUPPORT,
1930 ATOM_DEVICE_TV1_SUPPORT);
1931 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1932 DRM_MODE_CONNECTOR_SVIDEO,
1934 CONNECTOR_OBJECT_ID_SVIDEO,
1938 DRM_INFO("Connector Table: %d (rn50-power)\n",
1939 rdev->mode_info.connector_table);
1940 /* VGA - primary dac */
1941 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1942 hpd.hpd = RADEON_HPD_NONE;
1943 radeon_add_legacy_encoder(dev,
1944 radeon_get_encoder_enum(dev,
1945 ATOM_DEVICE_CRT1_SUPPORT,
1947 ATOM_DEVICE_CRT1_SUPPORT);
1948 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1949 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1950 CONNECTOR_OBJECT_ID_VGA,
1952 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1953 hpd.hpd = RADEON_HPD_NONE;
1954 radeon_add_legacy_encoder(dev,
1955 radeon_get_encoder_enum(dev,
1956 ATOM_DEVICE_CRT2_SUPPORT,
1958 ATOM_DEVICE_CRT2_SUPPORT);
1959 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1960 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1961 CONNECTOR_OBJECT_ID_VGA,
1965 DRM_INFO("Connector table: %d (invalid)\n",
1966 rdev->mode_info.connector_table);
1970 radeon_link_encoder_connector(dev);
1975 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1977 enum radeon_combios_connector
1979 struct radeon_i2c_bus_rec *ddc_i2c,
1980 struct radeon_hpd *hpd)
1983 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1984 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1985 if (dev->pdev->device == 0x515e &&
1986 dev->pdev->subsystem_vendor == 0x1014) {
1987 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1988 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1992 /* X300 card with extra non-existent DVI port */
1993 if (dev->pdev->device == 0x5B60 &&
1994 dev->pdev->subsystem_vendor == 0x17af &&
1995 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1996 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2003 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2005 /* Acer 5102 has non-existent TV port */
2006 if (dev->pdev->device == 0x5975 &&
2007 dev->pdev->subsystem_vendor == 0x1025 &&
2008 dev->pdev->subsystem_device == 0x009f)
2011 /* HP dc5750 has non-existent TV port */
2012 if (dev->pdev->device == 0x5974 &&
2013 dev->pdev->subsystem_vendor == 0x103c &&
2014 dev->pdev->subsystem_device == 0x280a)
2017 /* MSI S270 has non-existent TV port */
2018 if (dev->pdev->device == 0x5955 &&
2019 dev->pdev->subsystem_vendor == 0x1462 &&
2020 dev->pdev->subsystem_device == 0x0131)
2026 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2028 struct radeon_device *rdev = dev->dev_private;
2029 uint32_t ext_tmds_info;
2031 if (rdev->flags & RADEON_IS_IGP) {
2033 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2035 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2037 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2038 if (ext_tmds_info) {
2039 uint8_t rev = RBIOS8(ext_tmds_info);
2040 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2043 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2045 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2049 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2051 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2056 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2058 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2061 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2063 struct radeon_device *rdev = dev->dev_private;
2064 uint32_t conn_info, entry, devices;
2065 uint16_t tmp, connector_object_id;
2066 enum radeon_combios_ddc ddc_type;
2067 enum radeon_combios_connector connector;
2069 struct radeon_i2c_bus_rec ddc_i2c;
2070 struct radeon_hpd hpd;
2072 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2074 for (i = 0; i < 4; i++) {
2075 entry = conn_info + 2 + i * 2;
2077 if (!RBIOS16(entry))
2080 tmp = RBIOS16(entry);
2082 connector = (tmp >> 12) & 0xf;
2084 ddc_type = (tmp >> 8) & 0xf;
2085 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2087 switch (connector) {
2088 case CONNECTOR_PROPRIETARY_LEGACY:
2089 case CONNECTOR_DVI_I_LEGACY:
2090 case CONNECTOR_DVI_D_LEGACY:
2091 if ((tmp >> 4) & 0x1)
2092 hpd.hpd = RADEON_HPD_2;
2094 hpd.hpd = RADEON_HPD_1;
2097 hpd.hpd = RADEON_HPD_NONE;
2101 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2105 switch (connector) {
2106 case CONNECTOR_PROPRIETARY_LEGACY:
2107 if ((tmp >> 4) & 0x1)
2108 devices = ATOM_DEVICE_DFP2_SUPPORT;
2110 devices = ATOM_DEVICE_DFP1_SUPPORT;
2111 radeon_add_legacy_encoder(dev,
2112 radeon_get_encoder_enum
2115 radeon_add_legacy_connector(dev, i, devices,
2116 legacy_connector_convert
2119 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2122 case CONNECTOR_CRT_LEGACY:
2124 devices = ATOM_DEVICE_CRT2_SUPPORT;
2125 radeon_add_legacy_encoder(dev,
2126 radeon_get_encoder_enum
2128 ATOM_DEVICE_CRT2_SUPPORT,
2130 ATOM_DEVICE_CRT2_SUPPORT);
2132 devices = ATOM_DEVICE_CRT1_SUPPORT;
2133 radeon_add_legacy_encoder(dev,
2134 radeon_get_encoder_enum
2136 ATOM_DEVICE_CRT1_SUPPORT,
2138 ATOM_DEVICE_CRT1_SUPPORT);
2140 radeon_add_legacy_connector(dev,
2143 legacy_connector_convert
2146 CONNECTOR_OBJECT_ID_VGA,
2149 case CONNECTOR_DVI_I_LEGACY:
2152 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2153 radeon_add_legacy_encoder(dev,
2154 radeon_get_encoder_enum
2156 ATOM_DEVICE_CRT2_SUPPORT,
2158 ATOM_DEVICE_CRT2_SUPPORT);
2160 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2161 radeon_add_legacy_encoder(dev,
2162 radeon_get_encoder_enum
2164 ATOM_DEVICE_CRT1_SUPPORT,
2166 ATOM_DEVICE_CRT1_SUPPORT);
2168 if ((tmp >> 4) & 0x1) {
2169 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2170 radeon_add_legacy_encoder(dev,
2171 radeon_get_encoder_enum
2173 ATOM_DEVICE_DFP2_SUPPORT,
2175 ATOM_DEVICE_DFP2_SUPPORT);
2176 connector_object_id = combios_check_dl_dvi(dev, 0);
2178 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2179 radeon_add_legacy_encoder(dev,
2180 radeon_get_encoder_enum
2182 ATOM_DEVICE_DFP1_SUPPORT,
2184 ATOM_DEVICE_DFP1_SUPPORT);
2185 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2187 radeon_add_legacy_connector(dev,
2190 legacy_connector_convert
2193 connector_object_id,
2196 case CONNECTOR_DVI_D_LEGACY:
2197 if ((tmp >> 4) & 0x1) {
2198 devices = ATOM_DEVICE_DFP2_SUPPORT;
2199 connector_object_id = combios_check_dl_dvi(dev, 1);
2201 devices = ATOM_DEVICE_DFP1_SUPPORT;
2202 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2204 radeon_add_legacy_encoder(dev,
2205 radeon_get_encoder_enum
2208 radeon_add_legacy_connector(dev, i, devices,
2209 legacy_connector_convert
2212 connector_object_id,
2215 case CONNECTOR_CTV_LEGACY:
2216 case CONNECTOR_STV_LEGACY:
2217 radeon_add_legacy_encoder(dev,
2218 radeon_get_encoder_enum
2220 ATOM_DEVICE_TV1_SUPPORT,
2222 ATOM_DEVICE_TV1_SUPPORT);
2223 radeon_add_legacy_connector(dev, i,
2224 ATOM_DEVICE_TV1_SUPPORT,
2225 legacy_connector_convert
2228 CONNECTOR_OBJECT_ID_SVIDEO,
2232 DRM_ERROR("Unknown connector type: %d\n",
2239 uint16_t tmds_info =
2240 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2242 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2244 radeon_add_legacy_encoder(dev,
2245 radeon_get_encoder_enum(dev,
2246 ATOM_DEVICE_CRT1_SUPPORT,
2248 ATOM_DEVICE_CRT1_SUPPORT);
2249 radeon_add_legacy_encoder(dev,
2250 radeon_get_encoder_enum(dev,
2251 ATOM_DEVICE_DFP1_SUPPORT,
2253 ATOM_DEVICE_DFP1_SUPPORT);
2255 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2256 hpd.hpd = RADEON_HPD_1;
2257 radeon_add_legacy_connector(dev,
2259 ATOM_DEVICE_CRT1_SUPPORT |
2260 ATOM_DEVICE_DFP1_SUPPORT,
2261 DRM_MODE_CONNECTOR_DVII,
2263 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2267 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2268 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2270 radeon_add_legacy_encoder(dev,
2271 radeon_get_encoder_enum(dev,
2272 ATOM_DEVICE_CRT1_SUPPORT,
2274 ATOM_DEVICE_CRT1_SUPPORT);
2275 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2276 hpd.hpd = RADEON_HPD_NONE;
2277 radeon_add_legacy_connector(dev,
2279 ATOM_DEVICE_CRT1_SUPPORT,
2280 DRM_MODE_CONNECTOR_VGA,
2282 CONNECTOR_OBJECT_ID_VGA,
2285 DRM_DEBUG_KMS("No connector info found\n");
2291 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2293 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2295 uint16_t lcd_ddc_info =
2296 combios_get_table_offset(dev,
2297 COMBIOS_LCD_DDC_INFO_TABLE);
2299 radeon_add_legacy_encoder(dev,
2300 radeon_get_encoder_enum(dev,
2301 ATOM_DEVICE_LCD1_SUPPORT,
2303 ATOM_DEVICE_LCD1_SUPPORT);
2306 ddc_type = RBIOS8(lcd_ddc_info + 2);
2310 combios_setup_i2c_bus(rdev,
2312 RBIOS32(lcd_ddc_info + 3),
2313 RBIOS32(lcd_ddc_info + 7));
2314 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2318 combios_setup_i2c_bus(rdev,
2320 RBIOS32(lcd_ddc_info + 3),
2321 RBIOS32(lcd_ddc_info + 7));
2322 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2326 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2329 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2331 ddc_i2c.valid = false;
2333 hpd.hpd = RADEON_HPD_NONE;
2334 radeon_add_legacy_connector(dev,
2336 ATOM_DEVICE_LCD1_SUPPORT,
2337 DRM_MODE_CONNECTOR_LVDS,
2339 CONNECTOR_OBJECT_ID_LVDS,
2344 /* check TV table */
2345 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2347 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2349 if (RBIOS8(tv_info + 6) == 'T') {
2350 if (radeon_apply_legacy_tv_quirks(dev)) {
2351 hpd.hpd = RADEON_HPD_NONE;
2352 ddc_i2c.valid = false;
2353 radeon_add_legacy_encoder(dev,
2354 radeon_get_encoder_enum
2356 ATOM_DEVICE_TV1_SUPPORT,
2358 ATOM_DEVICE_TV1_SUPPORT);
2359 radeon_add_legacy_connector(dev, 6,
2360 ATOM_DEVICE_TV1_SUPPORT,
2361 DRM_MODE_CONNECTOR_SVIDEO,
2363 CONNECTOR_OBJECT_ID_SVIDEO,
2370 radeon_link_encoder_connector(dev);
2375 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2377 struct drm_device *dev = rdev->ddev;
2378 u16 offset, misc, misc2 = 0;
2379 u8 rev, blocks, tmp;
2380 int state_index = 0;
2382 rdev->pm.default_power_state_index = -1;
2384 if (rdev->flags & RADEON_IS_MOBILITY) {
2385 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2387 rev = RBIOS8(offset);
2388 blocks = RBIOS8(offset + 0x2);
2389 /* power mode 0 tends to be the only valid one */
2390 rdev->pm.power_state[state_index].num_clock_modes = 1;
2391 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2392 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2393 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2394 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2396 rdev->pm.power_state[state_index].type =
2397 POWER_STATE_TYPE_BATTERY;
2398 misc = RBIOS16(offset + 0x5 + 0x0);
2400 misc2 = RBIOS16(offset + 0x5 + 0xe);
2401 rdev->pm.power_state[state_index].misc = misc;
2402 rdev->pm.power_state[state_index].misc2 = misc2;
2404 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2406 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2409 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2411 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2413 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2414 RBIOS16(offset + 0x5 + 0xb) * 4;
2415 tmp = RBIOS8(offset + 0x5 + 0xd);
2416 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2418 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2419 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2420 if (entries && voltage_table_offset) {
2421 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2422 RBIOS16(voltage_table_offset) * 4;
2423 tmp = RBIOS8(voltage_table_offset + 0x2);
2424 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2426 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2428 switch ((misc2 & 0x700) >> 8) {
2431 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2434 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2437 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2440 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2443 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2447 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2449 rdev->pm.power_state[state_index].pcie_lanes =
2450 RBIOS8(offset + 0x5 + 0x10);
2451 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2454 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2457 /* XXX figure out some good default low power mode for desktop cards */
2461 /* add the default mode */
2462 rdev->pm.power_state[state_index].type =
2463 POWER_STATE_TYPE_DEFAULT;
2464 rdev->pm.power_state[state_index].num_clock_modes = 1;
2465 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2466 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2467 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2468 if ((state_index > 0) &&
2469 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2470 rdev->pm.power_state[state_index].clock_info[0].voltage =
2471 rdev->pm.power_state[0].clock_info[0].voltage;
2473 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2474 rdev->pm.power_state[state_index].pcie_lanes = 16;
2475 rdev->pm.power_state[state_index].flags = 0;
2476 rdev->pm.default_power_state_index = state_index;
2477 rdev->pm.num_power_states = state_index + 1;
2479 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2480 rdev->pm.current_clock_mode_index = 0;
2483 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2485 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2486 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2491 switch (tmds->dvo_chip) {
2494 radeon_i2c_put_byte(tmds->i2c_bus,
2497 radeon_i2c_put_byte(tmds->i2c_bus,
2500 radeon_i2c_put_byte(tmds->i2c_bus,
2503 radeon_i2c_put_byte(tmds->i2c_bus,
2506 radeon_i2c_put_byte(tmds->i2c_bus,
2511 /* sil 1178 - untested */
2530 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2532 struct drm_device *dev = encoder->dev;
2533 struct radeon_device *rdev = dev->dev_private;
2534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2536 uint8_t blocks, slave_addr, rev;
2538 uint32_t reg, val, and_mask, or_mask;
2539 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2544 if (rdev->flags & RADEON_IS_IGP) {
2545 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2546 rev = RBIOS8(offset);
2548 rev = RBIOS8(offset);
2550 blocks = RBIOS8(offset + 3);
2552 while (blocks > 0) {
2553 id = RBIOS16(index);
2557 reg = (id & 0x1fff) * 4;
2558 val = RBIOS32(index);
2563 reg = (id & 0x1fff) * 4;
2564 and_mask = RBIOS32(index);
2566 or_mask = RBIOS32(index);
2569 val = (val & and_mask) | or_mask;
2573 val = RBIOS16(index);
2578 val = RBIOS16(index);
2583 slave_addr = id & 0xff;
2584 slave_addr >>= 1; /* 7 bit addressing */
2586 reg = RBIOS8(index);
2588 val = RBIOS8(index);
2590 radeon_i2c_put_byte(tmds->i2c_bus,
2595 DRM_ERROR("Unknown id %d\n", id >> 13);
2604 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2606 index = offset + 10;
2607 id = RBIOS16(index);
2608 while (id != 0xffff) {
2612 reg = (id & 0x1fff) * 4;
2613 val = RBIOS32(index);
2617 reg = (id & 0x1fff) * 4;
2618 and_mask = RBIOS32(index);
2620 or_mask = RBIOS32(index);
2623 val = (val & and_mask) | or_mask;
2627 val = RBIOS16(index);
2633 and_mask = RBIOS32(index);
2635 or_mask = RBIOS32(index);
2637 val = RREG32_PLL(reg);
2638 val = (val & and_mask) | or_mask;
2639 WREG32_PLL(reg, val);
2643 val = RBIOS8(index);
2645 radeon_i2c_put_byte(tmds->i2c_bus,
2650 DRM_ERROR("Unknown id %d\n", id >> 13);
2653 id = RBIOS16(index);
2661 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2663 struct radeon_device *rdev = dev->dev_private;
2666 while (RBIOS16(offset)) {
2667 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2668 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2669 uint32_t val, and_mask, or_mask;
2675 val = RBIOS32(offset);
2680 val = RBIOS32(offset);
2685 and_mask = RBIOS32(offset);
2687 or_mask = RBIOS32(offset);
2695 and_mask = RBIOS32(offset);
2697 or_mask = RBIOS32(offset);
2705 val = RBIOS16(offset);
2710 val = RBIOS16(offset);
2717 (RADEON_CLK_PWRMGT_CNTL) &
2724 if ((RREG32(RADEON_MC_STATUS) &
2740 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2742 struct radeon_device *rdev = dev->dev_private;
2745 while (RBIOS8(offset)) {
2746 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2747 uint8_t addr = (RBIOS8(offset) & 0x3f);
2748 uint32_t val, shift, tmp;
2749 uint32_t and_mask, or_mask;
2754 val = RBIOS32(offset);
2756 WREG32_PLL(addr, val);
2759 shift = RBIOS8(offset) * 8;
2761 and_mask = RBIOS8(offset) << shift;
2762 and_mask |= ~(0xff << shift);
2764 or_mask = RBIOS8(offset) << shift;
2766 tmp = RREG32_PLL(addr);
2769 WREG32_PLL(addr, tmp);
2785 (RADEON_CLK_PWRMGT_CNTL) &
2793 (RADEON_CLK_PWRMGT_CNTL) &
2800 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2801 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2803 uint32_t mclk_cntl =
2806 mclk_cntl &= 0xffff0000;
2807 /*mclk_cntl |= 0x00001111;*//* ??? */
2808 WREG32_PLL(RADEON_MCLK_CNTL,
2813 (RADEON_CLK_PWRMGT_CNTL,
2815 ~RADEON_CG_NO1_DEBUG_0);
2830 static void combios_parse_ram_reset_table(struct drm_device *dev,
2833 struct radeon_device *rdev = dev->dev_private;
2837 uint8_t val = RBIOS8(offset);
2838 while (val != 0xff) {
2842 uint32_t channel_complete_mask;
2844 if (ASIC_IS_R300(rdev))
2845 channel_complete_mask =
2846 R300_MEM_PWRUP_COMPLETE;
2848 channel_complete_mask =
2849 RADEON_MEM_PWRUP_COMPLETE;
2852 if ((RREG32(RADEON_MEM_STR_CNTL) &
2853 channel_complete_mask) ==
2854 channel_complete_mask)
2858 uint32_t or_mask = RBIOS16(offset);
2861 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2862 tmp &= RADEON_SDRAM_MODE_MASK;
2864 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2866 or_mask = val << 24;
2867 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2868 tmp &= RADEON_B3MEM_RESET_MASK;
2870 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2872 val = RBIOS8(offset);
2877 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2878 int mem_addr_mapping)
2880 struct radeon_device *rdev = dev->dev_private;
2885 mem_cntl = RREG32(RADEON_MEM_CNTL);
2886 if (mem_cntl & RV100_HALF_MODE)
2889 mem_cntl &= ~(0xff << 8);
2890 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2891 WREG32(RADEON_MEM_CNTL, mem_cntl);
2892 RREG32(RADEON_MEM_CNTL);
2896 /* something like this???? */
2898 addr = ram * 1024 * 1024;
2899 /* write to each page */
2900 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2901 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2902 /* read back and verify */
2903 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2904 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2911 static void combios_write_ram_size(struct drm_device *dev)
2913 struct radeon_device *rdev = dev->dev_private;
2916 uint32_t mem_size = 0;
2917 uint32_t mem_cntl = 0;
2919 /* should do something smarter here I guess... */
2920 if (rdev->flags & RADEON_IS_IGP)
2923 /* first check detected mem table */
2924 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2926 rev = RBIOS8(offset);
2928 mem_cntl = RBIOS32(offset + 1);
2929 mem_size = RBIOS16(offset + 5);
2930 if ((rdev->family < CHIP_R200) &&
2931 !ASIC_IS_RN50(rdev))
2932 WREG32(RADEON_MEM_CNTL, mem_cntl);
2938 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2940 rev = RBIOS8(offset - 1);
2942 if ((rdev->family < CHIP_R200)
2943 && !ASIC_IS_RN50(rdev)) {
2945 int mem_addr_mapping = 0;
2947 while (RBIOS8(offset)) {
2948 ram = RBIOS8(offset);
2951 if (mem_addr_mapping != 0x25)
2954 combios_detect_ram(dev, ram,
2961 mem_size = RBIOS8(offset);
2963 mem_size = RBIOS8(offset);
2964 mem_size *= 2; /* convert to MB */
2969 mem_size *= (1024 * 1024); /* convert to bytes */
2970 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2973 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2975 uint16_t dyn_clk_info =
2976 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2979 combios_parse_pll_table(dev, dyn_clk_info);
2982 void radeon_combios_asic_init(struct drm_device *dev)
2984 struct radeon_device *rdev = dev->dev_private;
2987 /* port hardcoded mac stuff from radeonfb */
2988 if (rdev->bios == NULL)
2992 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2994 combios_parse_mmio_table(dev, table);
2997 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2999 combios_parse_pll_table(dev, table);
3002 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3004 combios_parse_mmio_table(dev, table);
3006 if (!(rdev->flags & RADEON_IS_IGP)) {
3009 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3011 combios_parse_mmio_table(dev, table);
3014 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3016 combios_parse_ram_reset_table(dev, table);
3020 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3022 combios_parse_mmio_table(dev, table);
3024 /* write CONFIG_MEMSIZE */
3025 combios_write_ram_size(dev);
3028 /* quirk for rs4xx HP nx6125 laptop to make it resume
3029 * - it hangs on resume inside the dynclk 1 table.
3031 if (rdev->family == CHIP_RS480 &&
3032 rdev->pdev->subsystem_vendor == 0x103c &&
3033 rdev->pdev->subsystem_device == 0x308b)
3036 /* quirk for rs4xx HP dv5000 laptop to make it resume
3037 * - it hangs on resume inside the dynclk 1 table.
3039 if (rdev->family == CHIP_RS480 &&
3040 rdev->pdev->subsystem_vendor == 0x103c &&
3041 rdev->pdev->subsystem_device == 0x30a4)
3045 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3047 combios_parse_pll_table(dev, table);
3051 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3053 struct radeon_device *rdev = dev->dev_private;
3054 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3056 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3057 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3058 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3060 /* let the bios control the backlight */
3061 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3063 /* tell the bios not to handle mode switching */
3064 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3065 RADEON_ACC_MODE_CHANGE);
3067 /* tell the bios a driver is loaded */
3068 bios_7_scratch |= RADEON_DRV_LOADED;
3070 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3071 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3072 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3075 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3077 struct drm_device *dev = encoder->dev;
3078 struct radeon_device *rdev = dev->dev_private;
3079 uint32_t bios_6_scratch;
3081 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3084 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3086 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3088 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3092 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3093 struct drm_encoder *encoder,
3096 struct drm_device *dev = connector->dev;
3097 struct radeon_device *rdev = dev->dev_private;
3098 struct radeon_connector *radeon_connector =
3099 to_radeon_connector(connector);
3100 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3101 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3102 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3104 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3105 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3107 DRM_DEBUG_KMS("TV1 connected\n");
3109 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3110 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3111 bios_5_scratch |= RADEON_TV1_ON;
3112 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3114 DRM_DEBUG_KMS("TV1 disconnected\n");
3115 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3116 bios_5_scratch &= ~RADEON_TV1_ON;
3117 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3120 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3121 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3123 DRM_DEBUG_KMS("LCD1 connected\n");
3124 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3125 bios_5_scratch |= RADEON_LCD1_ON;
3126 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3128 DRM_DEBUG_KMS("LCD1 disconnected\n");
3129 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3130 bios_5_scratch &= ~RADEON_LCD1_ON;
3131 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3134 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3135 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3137 DRM_DEBUG_KMS("CRT1 connected\n");
3138 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3139 bios_5_scratch |= RADEON_CRT1_ON;
3140 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3142 DRM_DEBUG_KMS("CRT1 disconnected\n");
3143 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3144 bios_5_scratch &= ~RADEON_CRT1_ON;
3145 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3148 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3149 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3151 DRM_DEBUG_KMS("CRT2 connected\n");
3152 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3153 bios_5_scratch |= RADEON_CRT2_ON;
3154 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3156 DRM_DEBUG_KMS("CRT2 disconnected\n");
3157 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3158 bios_5_scratch &= ~RADEON_CRT2_ON;
3159 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3162 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3163 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3165 DRM_DEBUG_KMS("DFP1 connected\n");
3166 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3167 bios_5_scratch |= RADEON_DFP1_ON;
3168 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3170 DRM_DEBUG_KMS("DFP1 disconnected\n");
3171 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3172 bios_5_scratch &= ~RADEON_DFP1_ON;
3173 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3176 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3177 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3179 DRM_DEBUG_KMS("DFP2 connected\n");
3180 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3181 bios_5_scratch |= RADEON_DFP2_ON;
3182 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3184 DRM_DEBUG_KMS("DFP2 disconnected\n");
3185 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3186 bios_5_scratch &= ~RADEON_DFP2_ON;
3187 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3190 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3191 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3195 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3197 struct drm_device *dev = encoder->dev;
3198 struct radeon_device *rdev = dev->dev_private;
3199 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3200 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3202 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3203 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3204 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3206 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3207 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3208 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3210 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3211 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3212 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3214 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3215 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3216 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3218 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3219 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3220 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3222 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3223 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3224 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3226 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3230 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3232 struct drm_device *dev = encoder->dev;
3233 struct radeon_device *rdev = dev->dev_private;
3234 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3235 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3237 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3239 bios_6_scratch |= RADEON_TV_DPMS_ON;
3241 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3243 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3245 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3247 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3249 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3251 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3253 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3255 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3257 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3259 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3261 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);