2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include <drm/radeon_drm.h>
29 #include "radeon_reg.h"
32 void r100_cs_dump_packet(struct radeon_cs_parser *p,
33 struct radeon_cs_packet *pkt);
35 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
37 struct drm_device *ddev = p->rdev->ddev;
38 struct radeon_cs_chunk *chunk;
42 if (p->chunk_relocs_idx == -1) {
45 chunk = &p->chunks[p->chunk_relocs_idx];
47 /* FIXME: we assume that each relocs use 4 dwords */
48 p->nrelocs = chunk->length_dw / 4;
49 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
50 if (p->relocs_ptr == NULL) {
53 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
54 if (p->relocs == NULL) {
57 for (i = 0; i < p->nrelocs; i++) {
58 struct drm_radeon_cs_reloc *r;
61 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
62 for (j = 0; j < i; j++) {
63 if (r->handle == p->relocs[j].handle) {
64 p->relocs_ptr[i] = &p->relocs[j];
70 p->relocs[i].gobj = drm_gem_object_lookup(ddev,
73 if (p->relocs[i].gobj == NULL) {
74 DRM_ERROR("gem object lookup failed 0x%x\n",
78 p->relocs_ptr[i] = &p->relocs[i];
79 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
80 p->relocs[i].lobj.bo = p->relocs[i].robj;
81 p->relocs[i].lobj.wdomain = r->write_domain;
82 p->relocs[i].lobj.rdomain = r->read_domains;
83 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
84 p->relocs[i].handle = r->handle;
85 p->relocs[i].flags = r->flags;
86 radeon_bo_list_add_object(&p->relocs[i].lobj,
90 p->relocs[i].handle = 0;
92 return radeon_bo_list_validate(&p->validated);
95 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
97 p->priority = priority;
101 DRM_ERROR("unknown ring id: %d\n", ring);
103 case RADEON_CS_RING_GFX:
104 p->ring = RADEON_RING_TYPE_GFX_INDEX;
106 case RADEON_CS_RING_COMPUTE:
107 if (p->rdev->family >= CHIP_TAHITI) {
109 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
111 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
113 p->ring = RADEON_RING_TYPE_GFX_INDEX;
119 static void radeon_cs_sync_to(struct radeon_cs_parser *p,
120 struct radeon_fence *fence)
122 struct radeon_fence *other;
127 other = p->ib.sync_to[fence->ring];
128 p->ib.sync_to[fence->ring] = radeon_fence_later(fence, other);
131 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
135 for (i = 0; i < p->nrelocs; i++) {
136 if (!p->relocs[i].robj)
139 radeon_cs_sync_to(p, p->relocs[i].robj->tbo.sync_obj);
143 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
144 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
146 struct drm_radeon_cs *cs = data;
147 uint64_t *chunk_array_ptr;
149 u32 ring = RADEON_CS_RING_GFX;
152 if (!cs->num_chunks) {
156 INIT_LIST_HEAD(&p->validated);
159 p->ib.semaphore = NULL;
160 p->const_ib.sa_bo = NULL;
161 p->const_ib.semaphore = NULL;
162 p->chunk_ib_idx = -1;
163 p->chunk_relocs_idx = -1;
164 p->chunk_flags_idx = -1;
165 p->chunk_const_ib_idx = -1;
166 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
167 if (p->chunks_array == NULL) {
170 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
171 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
172 sizeof(uint64_t)*cs->num_chunks)) {
176 p->nchunks = cs->num_chunks;
177 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
178 if (p->chunks == NULL) {
181 for (i = 0; i < p->nchunks; i++) {
182 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
183 struct drm_radeon_cs_chunk user_chunk;
184 uint32_t __user *cdata;
186 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
187 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
188 sizeof(struct drm_radeon_cs_chunk))) {
191 p->chunks[i].length_dw = user_chunk.length_dw;
192 p->chunks[i].kdata = NULL;
193 p->chunks[i].chunk_id = user_chunk.chunk_id;
195 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
196 p->chunk_relocs_idx = i;
198 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
200 /* zero length IB isn't useful */
201 if (p->chunks[i].length_dw == 0)
204 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
205 p->chunk_const_ib_idx = i;
206 /* zero length CONST IB isn't useful */
207 if (p->chunks[i].length_dw == 0)
210 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
211 p->chunk_flags_idx = i;
212 /* zero length flags aren't useful */
213 if (p->chunks[i].length_dw == 0)
217 p->chunks[i].length_dw = user_chunk.length_dw;
218 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
220 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
221 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
222 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
223 size = p->chunks[i].length_dw * sizeof(uint32_t);
224 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
225 if (p->chunks[i].kdata == NULL) {
228 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
229 p->chunks[i].user_ptr, size)) {
232 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
233 p->cs_flags = p->chunks[i].kdata[0];
234 if (p->chunks[i].length_dw > 1)
235 ring = p->chunks[i].kdata[1];
236 if (p->chunks[i].length_dw > 2)
237 priority = (s32)p->chunks[i].kdata[2];
242 /* these are KMS only */
244 if ((p->cs_flags & RADEON_CS_USE_VM) &&
245 !p->rdev->vm_manager.enabled) {
246 DRM_ERROR("VM not active on asic!\n");
250 /* we only support VM on SI+ */
251 if ((p->rdev->family >= CHIP_TAHITI) &&
252 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
253 DRM_ERROR("VM required on SI+!\n");
257 if (radeon_cs_get_ring(p, ring, priority))
261 /* deal with non-vm */
262 if ((p->chunk_ib_idx != -1) &&
263 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
264 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
265 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
266 DRM_ERROR("cs IB too big: %d\n",
267 p->chunks[p->chunk_ib_idx].length_dw);
270 if ((p->rdev->flags & RADEON_IS_AGP)) {
271 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
272 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
273 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
274 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
275 kfree(p->chunks[i].kpage[0]);
276 kfree(p->chunks[i].kpage[1]);
280 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
281 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
282 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
283 p->chunks[p->chunk_ib_idx].last_page_index =
284 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
291 * cs_parser_fini() - clean parser states
292 * @parser: parser structure holding parsing context.
293 * @error: error number
295 * If error is set than unvalidate buffer, otherwise just free memory
296 * used by parsing context.
298 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
303 ttm_eu_fence_buffer_objects(&parser->validated,
306 ttm_eu_backoff_reservation(&parser->validated);
309 if (parser->relocs != NULL) {
310 for (i = 0; i < parser->nrelocs; i++) {
311 if (parser->relocs[i].gobj)
312 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
315 kfree(parser->track);
316 kfree(parser->relocs);
317 kfree(parser->relocs_ptr);
318 for (i = 0; i < parser->nchunks; i++) {
319 kfree(parser->chunks[i].kdata);
320 if ((parser->rdev->flags & RADEON_IS_AGP)) {
321 kfree(parser->chunks[i].kpage[0]);
322 kfree(parser->chunks[i].kpage[1]);
325 kfree(parser->chunks);
326 kfree(parser->chunks_array);
327 radeon_ib_free(parser->rdev, &parser->ib);
328 radeon_ib_free(parser->rdev, &parser->const_ib);
331 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
332 struct radeon_cs_parser *parser)
334 struct radeon_cs_chunk *ib_chunk;
337 if (parser->chunk_ib_idx == -1)
340 if (parser->cs_flags & RADEON_CS_USE_VM)
343 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
344 /* Copy the packet into the IB, the parser will read from the
345 * input memory (cached) and write to the IB (which can be
348 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
349 NULL, ib_chunk->length_dw * 4);
351 DRM_ERROR("Failed to get ib !\n");
354 parser->ib.length_dw = ib_chunk->length_dw;
355 r = radeon_cs_parse(rdev, parser->ring, parser);
356 if (r || parser->parser_error) {
357 DRM_ERROR("Invalid command stream !\n");
360 r = radeon_cs_finish_pages(parser);
362 DRM_ERROR("Invalid command stream !\n");
365 radeon_cs_sync_rings(parser);
366 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
368 DRM_ERROR("Failed to schedule IB !\n");
373 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
374 struct radeon_vm *vm)
376 struct radeon_device *rdev = parser->rdev;
377 struct radeon_bo_list *lobj;
378 struct radeon_bo *bo;
381 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
385 list_for_each_entry(lobj, &parser->validated, tv.head) {
387 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
395 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
396 struct radeon_cs_parser *parser)
398 struct radeon_cs_chunk *ib_chunk;
399 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
400 struct radeon_vm *vm = &fpriv->vm;
403 if (parser->chunk_ib_idx == -1)
405 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
408 if ((rdev->family >= CHIP_TAHITI) &&
409 (parser->chunk_const_ib_idx != -1)) {
410 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
411 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
412 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
415 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
416 vm, ib_chunk->length_dw * 4);
418 DRM_ERROR("Failed to get const ib !\n");
421 parser->const_ib.is_const_ib = true;
422 parser->const_ib.length_dw = ib_chunk->length_dw;
423 /* Copy the packet into the IB */
424 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
425 ib_chunk->length_dw * 4)) {
428 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
434 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
435 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
436 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
439 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
440 vm, ib_chunk->length_dw * 4);
442 DRM_ERROR("Failed to get ib !\n");
445 parser->ib.length_dw = ib_chunk->length_dw;
446 /* Copy the packet into the IB */
447 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
448 ib_chunk->length_dw * 4)) {
451 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
456 mutex_lock(&rdev->vm_manager.lock);
457 mutex_lock(&vm->mutex);
458 r = radeon_vm_alloc_pt(rdev, vm);
462 r = radeon_bo_vm_update_pte(parser, vm);
466 radeon_cs_sync_rings(parser);
467 radeon_cs_sync_to(parser, vm->fence);
468 radeon_cs_sync_to(parser, radeon_vm_grab_id(rdev, vm, parser->ring));
470 if ((rdev->family >= CHIP_TAHITI) &&
471 (parser->chunk_const_ib_idx != -1)) {
472 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
474 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
478 radeon_vm_fence(rdev, vm, parser->ib.fence);
482 radeon_vm_add_to_lru(rdev, vm);
483 mutex_unlock(&vm->mutex);
484 mutex_unlock(&rdev->vm_manager.lock);
488 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
491 r = radeon_gpu_reset(rdev);
498 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
500 struct radeon_device *rdev = dev->dev_private;
501 struct radeon_cs_parser parser;
504 down_read(&rdev->exclusive_lock);
505 if (!rdev->accel_working) {
506 up_read(&rdev->exclusive_lock);
509 /* initialize parser */
510 memset(&parser, 0, sizeof(struct radeon_cs_parser));
513 parser.dev = rdev->dev;
514 parser.family = rdev->family;
515 r = radeon_cs_parser_init(&parser, data);
517 DRM_ERROR("Failed to initialize parser !\n");
518 radeon_cs_parser_fini(&parser, r);
519 up_read(&rdev->exclusive_lock);
520 r = radeon_cs_handle_lockup(rdev, r);
523 r = radeon_cs_parser_relocs(&parser);
525 if (r != -ERESTARTSYS)
526 DRM_ERROR("Failed to parse relocation %d!\n", r);
527 radeon_cs_parser_fini(&parser, r);
528 up_read(&rdev->exclusive_lock);
529 r = radeon_cs_handle_lockup(rdev, r);
532 r = radeon_cs_ib_chunk(rdev, &parser);
536 r = radeon_cs_ib_vm_chunk(rdev, &parser);
541 radeon_cs_parser_fini(&parser, r);
542 up_read(&rdev->exclusive_lock);
543 r = radeon_cs_handle_lockup(rdev, r);
547 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
549 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
551 int size = PAGE_SIZE;
553 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
554 if (i == ibc->last_page_index) {
555 size = (ibc->length_dw * 4) % PAGE_SIZE;
560 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
561 ibc->user_ptr + (i * PAGE_SIZE),
568 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
571 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
573 int size = PAGE_SIZE;
574 bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
576 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
577 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
578 ibc->user_ptr + (i * PAGE_SIZE),
580 p->parser_error = -EFAULT;
585 if (pg_idx == ibc->last_page_index) {
586 size = (ibc->length_dw * 4) % PAGE_SIZE;
591 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
593 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
595 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
596 ibc->user_ptr + (pg_idx * PAGE_SIZE),
598 p->parser_error = -EFAULT;
602 /* copy to IB for non single case */
604 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
606 ibc->last_copied_page = pg_idx;
607 ibc->kpage_idx[new_page] = pg_idx;
612 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
614 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
615 u32 pg_idx, pg_offset;
619 pg_idx = (idx * 4) / PAGE_SIZE;
620 pg_offset = (idx * 4) % PAGE_SIZE;
622 if (ibc->kpage_idx[0] == pg_idx)
623 return ibc->kpage[0][pg_offset/4];
624 if (ibc->kpage_idx[1] == pg_idx)
625 return ibc->kpage[1][pg_offset/4];
627 new_page = radeon_cs_update_pages(p, pg_idx);
629 p->parser_error = new_page;
633 idx_value = ibc->kpage[new_page][pg_offset/4];