2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 #include <linux/list_sort.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon_reg.h"
32 #include "radeon_trace.h"
34 #define RADEON_CS_MAX_PRIORITY 32u
35 #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1)
37 /* This is based on the bucket sort with O(n) time complexity.
38 * An item with priority "i" is added to bucket[i]. The lists are then
39 * concatenated in descending order.
41 struct radeon_cs_buckets {
42 struct list_head bucket[RADEON_CS_NUM_BUCKETS];
45 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
49 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
50 INIT_LIST_HEAD(&b->bucket[i]);
53 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
54 struct list_head *item, unsigned priority)
56 /* Since buffers which appear sooner in the relocation list are
57 * likely to be used more often than buffers which appear later
58 * in the list, the sort mustn't change the ordering of buffers
59 * with the same priority, i.e. it must be stable.
61 list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
64 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
65 struct list_head *out_list)
69 /* Connect the sorted buckets in the output list. */
70 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
71 list_splice(&b->bucket[i], out_list);
75 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
77 struct drm_device *ddev = p->rdev->ddev;
78 struct radeon_cs_chunk *chunk;
79 struct radeon_cs_buckets buckets;
81 bool duplicate, need_mmap_lock = false;
84 if (p->chunk_relocs_idx == -1) {
87 chunk = &p->chunks[p->chunk_relocs_idx];
89 /* FIXME: we assume that each relocs use 4 dwords */
90 p->nrelocs = chunk->length_dw / 4;
91 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
92 if (p->relocs_ptr == NULL) {
95 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
96 if (p->relocs == NULL) {
100 radeon_cs_buckets_init(&buckets);
102 for (i = 0; i < p->nrelocs; i++) {
103 struct drm_radeon_cs_reloc *r;
107 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
108 for (j = 0; j < i; j++) {
109 if (r->handle == p->relocs[j].handle) {
110 p->relocs_ptr[i] = &p->relocs[j];
116 p->relocs[i].handle = 0;
120 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
122 if (p->relocs[i].gobj == NULL) {
123 DRM_ERROR("gem object lookup failed 0x%x\n",
127 p->relocs_ptr[i] = &p->relocs[i];
128 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
130 /* The userspace buffer priorities are from 0 to 15. A higher
131 * number means the buffer is more important.
132 * Also, the buffers used for write have a higher priority than
133 * the buffers used for read only, which doubles the range
134 * to 0 to 31. 32 is reserved for the kernel driver.
136 priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
139 /* the first reloc of an UVD job is the msg and that must be in
140 VRAM, also but everything into VRAM on AGP cards and older
141 IGP chips to avoid image corruptions */
142 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
143 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev) ||
144 p->rdev->family == CHIP_RS780 ||
145 p->rdev->family == CHIP_RS880)) {
147 /* TODO: is this still needed for NI+ ? */
148 p->relocs[i].prefered_domains =
149 RADEON_GEM_DOMAIN_VRAM;
151 p->relocs[i].allowed_domains =
152 RADEON_GEM_DOMAIN_VRAM;
154 /* prioritize this over any other relocation */
155 priority = RADEON_CS_MAX_PRIORITY;
157 uint32_t domain = r->write_domain ?
158 r->write_domain : r->read_domains;
160 if (domain & RADEON_GEM_DOMAIN_CPU) {
161 DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
162 "for command submission\n");
166 p->relocs[i].prefered_domains = domain;
167 if (domain == RADEON_GEM_DOMAIN_VRAM)
168 domain |= RADEON_GEM_DOMAIN_GTT;
169 p->relocs[i].allowed_domains = domain;
172 if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) {
173 uint32_t domain = p->relocs[i].prefered_domains;
174 if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
175 DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
176 "allowed for userptr BOs\n");
179 need_mmap_lock = true;
180 domain = RADEON_GEM_DOMAIN_GTT;
181 p->relocs[i].prefered_domains = domain;
182 p->relocs[i].allowed_domains = domain;
185 p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
186 p->relocs[i].tv.shared = false;
187 p->relocs[i].handle = r->handle;
189 radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head,
193 radeon_cs_buckets_get_list(&buckets, &p->validated);
195 if (p->cs_flags & RADEON_CS_USE_VM)
196 p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
199 down_read(¤t->mm->mmap_sem);
201 r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);
204 up_read(¤t->mm->mmap_sem);
209 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
211 p->priority = priority;
215 DRM_ERROR("unknown ring id: %d\n", ring);
217 case RADEON_CS_RING_GFX:
218 p->ring = RADEON_RING_TYPE_GFX_INDEX;
220 case RADEON_CS_RING_COMPUTE:
221 if (p->rdev->family >= CHIP_TAHITI) {
223 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
225 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
227 p->ring = RADEON_RING_TYPE_GFX_INDEX;
229 case RADEON_CS_RING_DMA:
230 if (p->rdev->family >= CHIP_CAYMAN) {
232 p->ring = R600_RING_TYPE_DMA_INDEX;
234 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
235 } else if (p->rdev->family >= CHIP_RV770) {
236 p->ring = R600_RING_TYPE_DMA_INDEX;
241 case RADEON_CS_RING_UVD:
242 p->ring = R600_RING_TYPE_UVD_INDEX;
244 case RADEON_CS_RING_VCE:
245 /* TODO: only use the low priority ring for now */
246 p->ring = TN_RING_TYPE_VCE1_INDEX;
252 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
256 for (i = 0; i < p->nrelocs; i++) {
257 struct reservation_object *resv;
259 if (!p->relocs[i].robj)
262 resv = p->relocs[i].robj->tbo.resv;
263 radeon_semaphore_sync_resv(p->ib.semaphore, resv, false);
267 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
268 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
270 struct drm_radeon_cs *cs = data;
271 uint64_t *chunk_array_ptr;
273 u32 ring = RADEON_CS_RING_GFX;
276 if (!cs->num_chunks) {
280 INIT_LIST_HEAD(&p->validated);
283 p->ib.semaphore = NULL;
284 p->const_ib.sa_bo = NULL;
285 p->const_ib.semaphore = NULL;
286 p->chunk_ib_idx = -1;
287 p->chunk_relocs_idx = -1;
288 p->chunk_flags_idx = -1;
289 p->chunk_const_ib_idx = -1;
290 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
291 if (p->chunks_array == NULL) {
294 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
295 if (copy_from_user(p->chunks_array, chunk_array_ptr,
296 sizeof(uint64_t)*cs->num_chunks)) {
300 p->nchunks = cs->num_chunks;
301 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
302 if (p->chunks == NULL) {
305 for (i = 0; i < p->nchunks; i++) {
306 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
307 struct drm_radeon_cs_chunk user_chunk;
308 uint32_t __user *cdata;
310 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
311 if (copy_from_user(&user_chunk, chunk_ptr,
312 sizeof(struct drm_radeon_cs_chunk))) {
315 p->chunks[i].length_dw = user_chunk.length_dw;
316 p->chunks[i].chunk_id = user_chunk.chunk_id;
317 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
318 p->chunk_relocs_idx = i;
320 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
322 /* zero length IB isn't useful */
323 if (p->chunks[i].length_dw == 0)
326 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
327 p->chunk_const_ib_idx = i;
328 /* zero length CONST IB isn't useful */
329 if (p->chunks[i].length_dw == 0)
332 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
333 p->chunk_flags_idx = i;
334 /* zero length flags aren't useful */
335 if (p->chunks[i].length_dw == 0)
339 size = p->chunks[i].length_dw;
340 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
341 p->chunks[i].user_ptr = cdata;
342 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB)
345 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
346 if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
350 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
351 size *= sizeof(uint32_t);
352 if (p->chunks[i].kdata == NULL) {
355 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
358 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
359 p->cs_flags = p->chunks[i].kdata[0];
360 if (p->chunks[i].length_dw > 1)
361 ring = p->chunks[i].kdata[1];
362 if (p->chunks[i].length_dw > 2)
363 priority = (s32)p->chunks[i].kdata[2];
367 /* these are KMS only */
369 if ((p->cs_flags & RADEON_CS_USE_VM) &&
370 !p->rdev->vm_manager.enabled) {
371 DRM_ERROR("VM not active on asic!\n");
375 if (radeon_cs_get_ring(p, ring, priority))
378 /* we only support VM on some SI+ rings */
379 if ((p->cs_flags & RADEON_CS_USE_VM) == 0) {
380 if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) {
381 DRM_ERROR("Ring %d requires VM!\n", p->ring);
385 if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) {
386 DRM_ERROR("VM not supported on ring %d!\n",
396 static int cmp_size_smaller_first(void *priv, struct list_head *a,
399 struct radeon_cs_reloc *la = list_entry(a, struct radeon_cs_reloc, tv.head);
400 struct radeon_cs_reloc *lb = list_entry(b, struct radeon_cs_reloc, tv.head);
402 /* Sort A before B if A is smaller. */
403 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
407 * cs_parser_fini() - clean parser states
408 * @parser: parser structure holding parsing context.
409 * @error: error number
411 * If error is set than unvalidate buffer, otherwise just free memory
412 * used by parsing context.
414 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
419 /* Sort the buffer list from the smallest to largest buffer,
420 * which affects the order of buffers in the LRU list.
421 * This assures that the smallest buffers are added first
422 * to the LRU list, so they are likely to be later evicted
423 * first, instead of large buffers whose eviction is more
426 * This slightly lowers the number of bytes moved by TTM
427 * per frame under memory pressure.
429 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
431 ttm_eu_fence_buffer_objects(&parser->ticket,
433 &parser->ib.fence->base);
434 } else if (backoff) {
435 ttm_eu_backoff_reservation(&parser->ticket,
439 if (parser->relocs != NULL) {
440 for (i = 0; i < parser->nrelocs; i++) {
441 if (parser->relocs[i].gobj)
442 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
445 kfree(parser->track);
446 kfree(parser->relocs);
447 kfree(parser->relocs_ptr);
448 kfree(parser->vm_bos);
449 for (i = 0; i < parser->nchunks; i++)
450 drm_free_large(parser->chunks[i].kdata);
451 kfree(parser->chunks);
452 kfree(parser->chunks_array);
453 radeon_ib_free(parser->rdev, &parser->ib);
454 radeon_ib_free(parser->rdev, &parser->const_ib);
457 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
458 struct radeon_cs_parser *parser)
462 if (parser->chunk_ib_idx == -1)
465 if (parser->cs_flags & RADEON_CS_USE_VM)
468 r = radeon_cs_parse(rdev, parser->ring, parser);
469 if (r || parser->parser_error) {
470 DRM_ERROR("Invalid command stream !\n");
474 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
475 radeon_uvd_note_usage(rdev);
476 else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
477 (parser->ring == TN_RING_TYPE_VCE2_INDEX))
478 radeon_vce_note_usage(rdev);
480 radeon_cs_sync_rings(parser);
481 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
483 DRM_ERROR("Failed to schedule IB !\n");
488 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
489 struct radeon_vm *vm)
491 struct radeon_device *rdev = p->rdev;
492 struct radeon_bo_va *bo_va;
495 r = radeon_vm_update_page_directory(rdev, vm);
499 r = radeon_vm_clear_freed(rdev, vm);
503 if (vm->ib_bo_va == NULL) {
504 DRM_ERROR("Tmp BO not in VM!\n");
508 r = radeon_vm_bo_update(rdev, vm->ib_bo_va,
509 &rdev->ring_tmp_bo.bo->tbo.mem);
513 for (i = 0; i < p->nrelocs; i++) {
514 struct radeon_bo *bo;
516 /* ignore duplicates */
517 if (p->relocs_ptr[i] != &p->relocs[i])
520 bo = p->relocs[i].robj;
521 bo_va = radeon_vm_bo_find(vm, bo);
523 dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
527 r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem);
532 return radeon_vm_clear_invalids(rdev, vm);
535 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
536 struct radeon_cs_parser *parser)
538 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
539 struct radeon_vm *vm = &fpriv->vm;
542 if (parser->chunk_ib_idx == -1)
544 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
547 if (parser->const_ib.length_dw) {
548 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
554 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
559 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
560 radeon_uvd_note_usage(rdev);
562 mutex_lock(&vm->mutex);
563 r = radeon_bo_vm_update_pte(parser, vm);
567 radeon_cs_sync_rings(parser);
568 radeon_semaphore_sync_fence(parser->ib.semaphore, vm->fence);
570 if ((rdev->family >= CHIP_TAHITI) &&
571 (parser->chunk_const_ib_idx != -1)) {
572 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
574 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
578 mutex_unlock(&vm->mutex);
582 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
585 r = radeon_gpu_reset(rdev);
592 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
594 struct radeon_cs_chunk *ib_chunk;
595 struct radeon_vm *vm = NULL;
598 if (parser->chunk_ib_idx == -1)
601 if (parser->cs_flags & RADEON_CS_USE_VM) {
602 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
605 if ((rdev->family >= CHIP_TAHITI) &&
606 (parser->chunk_const_ib_idx != -1)) {
607 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
608 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
609 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
612 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
613 vm, ib_chunk->length_dw * 4);
615 DRM_ERROR("Failed to get const ib !\n");
618 parser->const_ib.is_const_ib = true;
619 parser->const_ib.length_dw = ib_chunk->length_dw;
620 if (copy_from_user(parser->const_ib.ptr,
622 ib_chunk->length_dw * 4))
626 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
627 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
628 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
632 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
634 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
635 vm, ib_chunk->length_dw * 4);
637 DRM_ERROR("Failed to get ib !\n");
640 parser->ib.length_dw = ib_chunk->length_dw;
642 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
643 else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
648 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
650 struct radeon_device *rdev = dev->dev_private;
651 struct radeon_cs_parser parser;
654 down_read(&rdev->exclusive_lock);
655 if (!rdev->accel_working) {
656 up_read(&rdev->exclusive_lock);
659 if (rdev->in_reset) {
660 up_read(&rdev->exclusive_lock);
661 r = radeon_gpu_reset(rdev);
666 /* initialize parser */
667 memset(&parser, 0, sizeof(struct radeon_cs_parser));
670 parser.dev = rdev->dev;
671 parser.family = rdev->family;
672 r = radeon_cs_parser_init(&parser, data);
674 DRM_ERROR("Failed to initialize parser !\n");
675 radeon_cs_parser_fini(&parser, r, false);
676 up_read(&rdev->exclusive_lock);
677 r = radeon_cs_handle_lockup(rdev, r);
681 r = radeon_cs_ib_fill(rdev, &parser);
683 r = radeon_cs_parser_relocs(&parser);
684 if (r && r != -ERESTARTSYS)
685 DRM_ERROR("Failed to parse relocation %d!\n", r);
689 radeon_cs_parser_fini(&parser, r, false);
690 up_read(&rdev->exclusive_lock);
691 r = radeon_cs_handle_lockup(rdev, r);
695 trace_radeon_cs(&parser);
697 r = radeon_cs_ib_chunk(rdev, &parser);
701 r = radeon_cs_ib_vm_chunk(rdev, &parser);
706 radeon_cs_parser_fini(&parser, r, true);
707 up_read(&rdev->exclusive_lock);
708 r = radeon_cs_handle_lockup(rdev, r);
713 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
714 * @parser: parser structure holding parsing context.
715 * @pkt: where to store packet information
717 * Assume that chunk_ib_index is properly set. Will return -EINVAL
718 * if packet is bigger than remaining ib size. or if packets is unknown.
720 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
721 struct radeon_cs_packet *pkt,
724 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
725 struct radeon_device *rdev = p->rdev;
728 if (idx >= ib_chunk->length_dw) {
729 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
730 idx, ib_chunk->length_dw);
733 header = radeon_get_ib_value(p, idx);
735 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
736 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
739 case RADEON_PACKET_TYPE0:
740 if (rdev->family < CHIP_R600) {
741 pkt->reg = R100_CP_PACKET0_GET_REG(header);
743 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
745 pkt->reg = R600_CP_PACKET0_GET_REG(header);
747 case RADEON_PACKET_TYPE3:
748 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
750 case RADEON_PACKET_TYPE2:
754 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
757 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
758 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
759 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
766 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
767 * @p: structure holding the parser context.
769 * Check if the next packet is NOP relocation packet3.
771 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
773 struct radeon_cs_packet p3reloc;
776 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
779 if (p3reloc.type != RADEON_PACKET_TYPE3)
781 if (p3reloc.opcode != RADEON_PACKET3_NOP)
787 * radeon_cs_dump_packet() - dump raw packet context
788 * @p: structure holding the parser context.
789 * @pkt: structure holding the packet.
791 * Used mostly for debugging and error reporting.
793 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
794 struct radeon_cs_packet *pkt)
796 volatile uint32_t *ib;
802 for (i = 0; i <= (pkt->count + 1); i++, idx++)
803 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
807 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
808 * @parser: parser structure holding parsing context.
809 * @data: pointer to relocation data
810 * @offset_start: starting offset
811 * @offset_mask: offset mask (to align start offset on)
812 * @reloc: reloc informations
814 * Check if next packet is relocation packet3, do bo validation and compute
815 * GPU offset using the provided start.
817 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
818 struct radeon_cs_reloc **cs_reloc,
821 struct radeon_cs_chunk *relocs_chunk;
822 struct radeon_cs_packet p3reloc;
826 if (p->chunk_relocs_idx == -1) {
827 DRM_ERROR("No relocation chunk !\n");
831 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
832 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
835 p->idx += p3reloc.count + 2;
836 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
837 p3reloc.opcode != RADEON_PACKET3_NOP) {
838 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
840 radeon_cs_dump_packet(p, &p3reloc);
843 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
844 if (idx >= relocs_chunk->length_dw) {
845 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
846 idx, relocs_chunk->length_dw);
847 radeon_cs_dump_packet(p, &p3reloc);
850 /* FIXME: we assume reloc size is 4 dwords */
852 *cs_reloc = p->relocs;
853 (*cs_reloc)->gpu_offset =
854 (u64)relocs_chunk->kdata[idx + 3] << 32;
855 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
857 *cs_reloc = p->relocs_ptr[(idx / 4)];