2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 #include <linux/list_sort.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon_reg.h"
32 #include "radeon_trace.h"
34 #define RADEON_CS_MAX_PRIORITY 32u
35 #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1)
37 /* This is based on the bucket sort with O(n) time complexity.
38 * An item with priority "i" is added to bucket[i]. The lists are then
39 * concatenated in descending order.
41 struct radeon_cs_buckets {
42 struct list_head bucket[RADEON_CS_NUM_BUCKETS];
45 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
49 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
50 INIT_LIST_HEAD(&b->bucket[i]);
53 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
54 struct list_head *item, unsigned priority)
56 /* Since buffers which appear sooner in the relocation list are
57 * likely to be used more often than buffers which appear later
58 * in the list, the sort mustn't change the ordering of buffers
59 * with the same priority, i.e. it must be stable.
61 list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
64 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
65 struct list_head *out_list)
69 /* Connect the sorted buckets in the output list. */
70 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
71 list_splice(&b->bucket[i], out_list);
75 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
77 struct drm_device *ddev = p->rdev->ddev;
78 struct radeon_cs_chunk *chunk;
79 struct radeon_cs_buckets buckets;
81 bool duplicate, need_mmap_lock = false;
84 if (p->chunk_relocs_idx == -1) {
87 chunk = &p->chunks[p->chunk_relocs_idx];
89 /* FIXME: we assume that each relocs use 4 dwords */
90 p->nrelocs = chunk->length_dw / 4;
91 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
92 if (p->relocs_ptr == NULL) {
95 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
96 if (p->relocs == NULL) {
100 radeon_cs_buckets_init(&buckets);
102 for (i = 0; i < p->nrelocs; i++) {
103 struct drm_radeon_cs_reloc *r;
107 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
108 for (j = 0; j < i; j++) {
109 if (r->handle == p->relocs[j].handle) {
110 p->relocs_ptr[i] = &p->relocs[j];
116 p->relocs[i].handle = 0;
120 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
122 if (p->relocs[i].gobj == NULL) {
123 DRM_ERROR("gem object lookup failed 0x%x\n",
127 p->relocs_ptr[i] = &p->relocs[i];
128 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
130 /* The userspace buffer priorities are from 0 to 15. A higher
131 * number means the buffer is more important.
132 * Also, the buffers used for write have a higher priority than
133 * the buffers used for read only, which doubles the range
134 * to 0 to 31. 32 is reserved for the kernel driver.
136 priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
139 /* the first reloc of an UVD job is the msg and that must be in
140 VRAM, also but everything into VRAM on AGP cards and older
141 IGP chips to avoid image corruptions */
142 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
143 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev) ||
144 p->rdev->family == CHIP_RS780 ||
145 p->rdev->family == CHIP_RS880)) {
147 /* TODO: is this still needed for NI+ ? */
148 p->relocs[i].prefered_domains =
149 RADEON_GEM_DOMAIN_VRAM;
151 p->relocs[i].allowed_domains =
152 RADEON_GEM_DOMAIN_VRAM;
154 /* prioritize this over any other relocation */
155 priority = RADEON_CS_MAX_PRIORITY;
157 uint32_t domain = r->write_domain ?
158 r->write_domain : r->read_domains;
160 if (domain & RADEON_GEM_DOMAIN_CPU) {
161 DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
162 "for command submission\n");
166 p->relocs[i].prefered_domains = domain;
167 if (domain == RADEON_GEM_DOMAIN_VRAM)
168 domain |= RADEON_GEM_DOMAIN_GTT;
169 p->relocs[i].allowed_domains = domain;
172 if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) {
173 uint32_t domain = p->relocs[i].prefered_domains;
174 if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
175 DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
176 "allowed for userptr BOs\n");
179 need_mmap_lock = true;
180 domain = RADEON_GEM_DOMAIN_GTT;
181 p->relocs[i].prefered_domains = domain;
182 p->relocs[i].allowed_domains = domain;
185 p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
186 p->relocs[i].tv.shared = !r->write_domain;
187 p->relocs[i].handle = r->handle;
189 radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head,
193 radeon_cs_buckets_get_list(&buckets, &p->validated);
195 if (p->cs_flags & RADEON_CS_USE_VM)
196 p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
199 down_read(¤t->mm->mmap_sem);
201 r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);
204 up_read(¤t->mm->mmap_sem);
209 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
211 p->priority = priority;
215 DRM_ERROR("unknown ring id: %d\n", ring);
217 case RADEON_CS_RING_GFX:
218 p->ring = RADEON_RING_TYPE_GFX_INDEX;
220 case RADEON_CS_RING_COMPUTE:
221 if (p->rdev->family >= CHIP_TAHITI) {
223 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
225 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
227 p->ring = RADEON_RING_TYPE_GFX_INDEX;
229 case RADEON_CS_RING_DMA:
230 if (p->rdev->family >= CHIP_CAYMAN) {
232 p->ring = R600_RING_TYPE_DMA_INDEX;
234 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
235 } else if (p->rdev->family >= CHIP_RV770) {
236 p->ring = R600_RING_TYPE_DMA_INDEX;
241 case RADEON_CS_RING_UVD:
242 p->ring = R600_RING_TYPE_UVD_INDEX;
244 case RADEON_CS_RING_VCE:
245 /* TODO: only use the low priority ring for now */
246 p->ring = TN_RING_TYPE_VCE1_INDEX;
252 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
256 for (i = 0; i < p->nrelocs; i++) {
257 struct reservation_object *resv;
259 if (!p->relocs[i].robj)
262 resv = p->relocs[i].robj->tbo.resv;
263 radeon_semaphore_sync_resv(p->ib.semaphore, resv,
264 p->relocs[i].tv.shared);
268 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
269 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
271 struct drm_radeon_cs *cs = data;
272 uint64_t *chunk_array_ptr;
274 u32 ring = RADEON_CS_RING_GFX;
277 if (!cs->num_chunks) {
281 INIT_LIST_HEAD(&p->validated);
284 p->ib.semaphore = NULL;
285 p->const_ib.sa_bo = NULL;
286 p->const_ib.semaphore = NULL;
287 p->chunk_ib_idx = -1;
288 p->chunk_relocs_idx = -1;
289 p->chunk_flags_idx = -1;
290 p->chunk_const_ib_idx = -1;
291 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
292 if (p->chunks_array == NULL) {
295 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
296 if (copy_from_user(p->chunks_array, chunk_array_ptr,
297 sizeof(uint64_t)*cs->num_chunks)) {
301 p->nchunks = cs->num_chunks;
302 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
303 if (p->chunks == NULL) {
306 for (i = 0; i < p->nchunks; i++) {
307 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
308 struct drm_radeon_cs_chunk user_chunk;
309 uint32_t __user *cdata;
311 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
312 if (copy_from_user(&user_chunk, chunk_ptr,
313 sizeof(struct drm_radeon_cs_chunk))) {
316 p->chunks[i].length_dw = user_chunk.length_dw;
317 p->chunks[i].chunk_id = user_chunk.chunk_id;
318 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
319 p->chunk_relocs_idx = i;
321 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
323 /* zero length IB isn't useful */
324 if (p->chunks[i].length_dw == 0)
327 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
328 p->chunk_const_ib_idx = i;
329 /* zero length CONST IB isn't useful */
330 if (p->chunks[i].length_dw == 0)
333 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
334 p->chunk_flags_idx = i;
335 /* zero length flags aren't useful */
336 if (p->chunks[i].length_dw == 0)
340 size = p->chunks[i].length_dw;
341 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
342 p->chunks[i].user_ptr = cdata;
343 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB)
346 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
347 if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
351 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
352 size *= sizeof(uint32_t);
353 if (p->chunks[i].kdata == NULL) {
356 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
359 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
360 p->cs_flags = p->chunks[i].kdata[0];
361 if (p->chunks[i].length_dw > 1)
362 ring = p->chunks[i].kdata[1];
363 if (p->chunks[i].length_dw > 2)
364 priority = (s32)p->chunks[i].kdata[2];
368 /* these are KMS only */
370 if ((p->cs_flags & RADEON_CS_USE_VM) &&
371 !p->rdev->vm_manager.enabled) {
372 DRM_ERROR("VM not active on asic!\n");
376 if (radeon_cs_get_ring(p, ring, priority))
379 /* we only support VM on some SI+ rings */
380 if ((p->cs_flags & RADEON_CS_USE_VM) == 0) {
381 if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) {
382 DRM_ERROR("Ring %d requires VM!\n", p->ring);
386 if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) {
387 DRM_ERROR("VM not supported on ring %d!\n",
397 static int cmp_size_smaller_first(void *priv, struct list_head *a,
400 struct radeon_cs_reloc *la = list_entry(a, struct radeon_cs_reloc, tv.head);
401 struct radeon_cs_reloc *lb = list_entry(b, struct radeon_cs_reloc, tv.head);
403 /* Sort A before B if A is smaller. */
404 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
408 * cs_parser_fini() - clean parser states
409 * @parser: parser structure holding parsing context.
410 * @error: error number
412 * If error is set than unvalidate buffer, otherwise just free memory
413 * used by parsing context.
415 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
420 /* Sort the buffer list from the smallest to largest buffer,
421 * which affects the order of buffers in the LRU list.
422 * This assures that the smallest buffers are added first
423 * to the LRU list, so they are likely to be later evicted
424 * first, instead of large buffers whose eviction is more
427 * This slightly lowers the number of bytes moved by TTM
428 * per frame under memory pressure.
430 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
432 ttm_eu_fence_buffer_objects(&parser->ticket,
434 &parser->ib.fence->base);
435 } else if (backoff) {
436 ttm_eu_backoff_reservation(&parser->ticket,
440 if (parser->relocs != NULL) {
441 for (i = 0; i < parser->nrelocs; i++) {
442 if (parser->relocs[i].gobj)
443 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
446 kfree(parser->track);
447 kfree(parser->relocs);
448 kfree(parser->relocs_ptr);
449 kfree(parser->vm_bos);
450 for (i = 0; i < parser->nchunks; i++)
451 drm_free_large(parser->chunks[i].kdata);
452 kfree(parser->chunks);
453 kfree(parser->chunks_array);
454 radeon_ib_free(parser->rdev, &parser->ib);
455 radeon_ib_free(parser->rdev, &parser->const_ib);
458 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
459 struct radeon_cs_parser *parser)
463 if (parser->chunk_ib_idx == -1)
466 if (parser->cs_flags & RADEON_CS_USE_VM)
469 r = radeon_cs_parse(rdev, parser->ring, parser);
470 if (r || parser->parser_error) {
471 DRM_ERROR("Invalid command stream !\n");
475 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
476 radeon_uvd_note_usage(rdev);
477 else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
478 (parser->ring == TN_RING_TYPE_VCE2_INDEX))
479 radeon_vce_note_usage(rdev);
481 radeon_cs_sync_rings(parser);
482 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
484 DRM_ERROR("Failed to schedule IB !\n");
489 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
490 struct radeon_vm *vm)
492 struct radeon_device *rdev = p->rdev;
493 struct radeon_bo_va *bo_va;
496 r = radeon_vm_update_page_directory(rdev, vm);
500 r = radeon_vm_clear_freed(rdev, vm);
504 if (vm->ib_bo_va == NULL) {
505 DRM_ERROR("Tmp BO not in VM!\n");
509 r = radeon_vm_bo_update(rdev, vm->ib_bo_va,
510 &rdev->ring_tmp_bo.bo->tbo.mem);
514 for (i = 0; i < p->nrelocs; i++) {
515 struct radeon_bo *bo;
517 /* ignore duplicates */
518 if (p->relocs_ptr[i] != &p->relocs[i])
521 bo = p->relocs[i].robj;
522 bo_va = radeon_vm_bo_find(vm, bo);
524 dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
528 r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem);
533 return radeon_vm_clear_invalids(rdev, vm);
536 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
537 struct radeon_cs_parser *parser)
539 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
540 struct radeon_vm *vm = &fpriv->vm;
543 if (parser->chunk_ib_idx == -1)
545 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
548 if (parser->const_ib.length_dw) {
549 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
555 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
560 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
561 radeon_uvd_note_usage(rdev);
563 mutex_lock(&vm->mutex);
564 r = radeon_bo_vm_update_pte(parser, vm);
568 radeon_cs_sync_rings(parser);
569 radeon_semaphore_sync_fence(parser->ib.semaphore, vm->fence);
571 if ((rdev->family >= CHIP_TAHITI) &&
572 (parser->chunk_const_ib_idx != -1)) {
573 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
575 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
579 mutex_unlock(&vm->mutex);
583 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
586 r = radeon_gpu_reset(rdev);
593 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
595 struct radeon_cs_chunk *ib_chunk;
596 struct radeon_vm *vm = NULL;
599 if (parser->chunk_ib_idx == -1)
602 if (parser->cs_flags & RADEON_CS_USE_VM) {
603 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
606 if ((rdev->family >= CHIP_TAHITI) &&
607 (parser->chunk_const_ib_idx != -1)) {
608 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
609 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
610 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
613 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
614 vm, ib_chunk->length_dw * 4);
616 DRM_ERROR("Failed to get const ib !\n");
619 parser->const_ib.is_const_ib = true;
620 parser->const_ib.length_dw = ib_chunk->length_dw;
621 if (copy_from_user(parser->const_ib.ptr,
623 ib_chunk->length_dw * 4))
627 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
628 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
629 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
633 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
635 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
636 vm, ib_chunk->length_dw * 4);
638 DRM_ERROR("Failed to get ib !\n");
641 parser->ib.length_dw = ib_chunk->length_dw;
643 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
644 else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
649 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
651 struct radeon_device *rdev = dev->dev_private;
652 struct radeon_cs_parser parser;
655 down_read(&rdev->exclusive_lock);
656 if (!rdev->accel_working) {
657 up_read(&rdev->exclusive_lock);
660 if (rdev->in_reset) {
661 up_read(&rdev->exclusive_lock);
662 r = radeon_gpu_reset(rdev);
667 /* initialize parser */
668 memset(&parser, 0, sizeof(struct radeon_cs_parser));
671 parser.dev = rdev->dev;
672 parser.family = rdev->family;
673 r = radeon_cs_parser_init(&parser, data);
675 DRM_ERROR("Failed to initialize parser !\n");
676 radeon_cs_parser_fini(&parser, r, false);
677 up_read(&rdev->exclusive_lock);
678 r = radeon_cs_handle_lockup(rdev, r);
682 r = radeon_cs_ib_fill(rdev, &parser);
684 r = radeon_cs_parser_relocs(&parser);
685 if (r && r != -ERESTARTSYS)
686 DRM_ERROR("Failed to parse relocation %d!\n", r);
690 radeon_cs_parser_fini(&parser, r, false);
691 up_read(&rdev->exclusive_lock);
692 r = radeon_cs_handle_lockup(rdev, r);
696 trace_radeon_cs(&parser);
698 r = radeon_cs_ib_chunk(rdev, &parser);
702 r = radeon_cs_ib_vm_chunk(rdev, &parser);
707 radeon_cs_parser_fini(&parser, r, true);
708 up_read(&rdev->exclusive_lock);
709 r = radeon_cs_handle_lockup(rdev, r);
714 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
715 * @parser: parser structure holding parsing context.
716 * @pkt: where to store packet information
718 * Assume that chunk_ib_index is properly set. Will return -EINVAL
719 * if packet is bigger than remaining ib size. or if packets is unknown.
721 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
722 struct radeon_cs_packet *pkt,
725 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
726 struct radeon_device *rdev = p->rdev;
729 if (idx >= ib_chunk->length_dw) {
730 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
731 idx, ib_chunk->length_dw);
734 header = radeon_get_ib_value(p, idx);
736 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
737 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
740 case RADEON_PACKET_TYPE0:
741 if (rdev->family < CHIP_R600) {
742 pkt->reg = R100_CP_PACKET0_GET_REG(header);
744 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
746 pkt->reg = R600_CP_PACKET0_GET_REG(header);
748 case RADEON_PACKET_TYPE3:
749 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
751 case RADEON_PACKET_TYPE2:
755 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
758 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
759 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
760 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
767 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
768 * @p: structure holding the parser context.
770 * Check if the next packet is NOP relocation packet3.
772 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
774 struct radeon_cs_packet p3reloc;
777 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
780 if (p3reloc.type != RADEON_PACKET_TYPE3)
782 if (p3reloc.opcode != RADEON_PACKET3_NOP)
788 * radeon_cs_dump_packet() - dump raw packet context
789 * @p: structure holding the parser context.
790 * @pkt: structure holding the packet.
792 * Used mostly for debugging and error reporting.
794 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
795 struct radeon_cs_packet *pkt)
797 volatile uint32_t *ib;
803 for (i = 0; i <= (pkt->count + 1); i++, idx++)
804 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
808 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
809 * @parser: parser structure holding parsing context.
810 * @data: pointer to relocation data
811 * @offset_start: starting offset
812 * @offset_mask: offset mask (to align start offset on)
813 * @reloc: reloc informations
815 * Check if next packet is relocation packet3, do bo validation and compute
816 * GPU offset using the provided start.
818 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
819 struct radeon_cs_reloc **cs_reloc,
822 struct radeon_cs_chunk *relocs_chunk;
823 struct radeon_cs_packet p3reloc;
827 if (p->chunk_relocs_idx == -1) {
828 DRM_ERROR("No relocation chunk !\n");
832 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
833 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
836 p->idx += p3reloc.count + 2;
837 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
838 p3reloc.opcode != RADEON_PACKET3_NOP) {
839 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
841 radeon_cs_dump_packet(p, &p3reloc);
844 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
845 if (idx >= relocs_chunk->length_dw) {
846 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
847 idx, relocs_chunk->length_dw);
848 radeon_cs_dump_packet(p, &p3reloc);
851 /* FIXME: we assume reloc size is 4 dwords */
853 *cs_reloc = p->relocs;
854 (*cs_reloc)->gpu_offset =
855 (u64)relocs_chunk->kdata[idx + 3] << 32;
856 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
858 *cs_reloc = p->relocs_ptr[(idx / 4)];