2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 #include <linux/list_sort.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon_reg.h"
32 #include "radeon_trace.h"
34 #define RADEON_CS_MAX_PRIORITY 32u
35 #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1)
37 /* This is based on the bucket sort with O(n) time complexity.
38 * An item with priority "i" is added to bucket[i]. The lists are then
39 * concatenated in descending order.
41 struct radeon_cs_buckets {
42 struct list_head bucket[RADEON_CS_NUM_BUCKETS];
45 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
49 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
50 INIT_LIST_HEAD(&b->bucket[i]);
53 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
54 struct list_head *item, unsigned priority)
56 /* Since buffers which appear sooner in the relocation list are
57 * likely to be used more often than buffers which appear later
58 * in the list, the sort mustn't change the ordering of buffers
59 * with the same priority, i.e. it must be stable.
61 list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
64 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
65 struct list_head *out_list)
69 /* Connect the sorted buckets in the output list. */
70 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
71 list_splice(&b->bucket[i], out_list);
75 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
77 struct drm_device *ddev = p->rdev->ddev;
78 struct radeon_cs_chunk *chunk;
79 struct radeon_cs_buckets buckets;
83 if (p->chunk_relocs_idx == -1) {
86 chunk = &p->chunks[p->chunk_relocs_idx];
88 /* FIXME: we assume that each relocs use 4 dwords */
89 p->nrelocs = chunk->length_dw / 4;
90 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
91 if (p->relocs_ptr == NULL) {
94 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
95 if (p->relocs == NULL) {
99 radeon_cs_buckets_init(&buckets);
101 for (i = 0; i < p->nrelocs; i++) {
102 struct drm_radeon_cs_reloc *r;
106 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
107 for (j = 0; j < i; j++) {
108 if (r->handle == p->relocs[j].handle) {
109 p->relocs_ptr[i] = &p->relocs[j];
115 p->relocs[i].handle = 0;
119 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
121 if (p->relocs[i].gobj == NULL) {
122 DRM_ERROR("gem object lookup failed 0x%x\n",
126 p->relocs_ptr[i] = &p->relocs[i];
127 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
128 p->relocs[i].lobj.bo = p->relocs[i].robj;
130 /* The userspace buffer priorities are from 0 to 15. A higher
131 * number means the buffer is more important.
132 * Also, the buffers used for write have a higher priority than
133 * the buffers used for read only, which doubles the range
134 * to 0 to 31. 32 is reserved for the kernel driver.
136 priority = (r->flags & 0xf) * 2 + !!r->write_domain;
138 /* the first reloc of an UVD job is the msg and that must be in
139 VRAM, also but everything into VRAM on AGP cards to avoid
141 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
142 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
143 /* TODO: is this still needed for NI+ ? */
144 p->relocs[i].lobj.domain =
145 RADEON_GEM_DOMAIN_VRAM;
147 p->relocs[i].lobj.alt_domain =
148 RADEON_GEM_DOMAIN_VRAM;
150 /* prioritize this over any other relocation */
151 priority = RADEON_CS_MAX_PRIORITY;
153 uint32_t domain = r->write_domain ?
154 r->write_domain : r->read_domains;
156 p->relocs[i].lobj.domain = domain;
157 if (domain == RADEON_GEM_DOMAIN_VRAM)
158 domain |= RADEON_GEM_DOMAIN_GTT;
159 p->relocs[i].lobj.alt_domain = domain;
162 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
163 p->relocs[i].handle = r->handle;
165 radeon_cs_buckets_add(&buckets, &p->relocs[i].lobj.tv.head,
169 radeon_cs_buckets_get_list(&buckets, &p->validated);
171 return radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);
174 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
176 p->priority = priority;
180 DRM_ERROR("unknown ring id: %d\n", ring);
182 case RADEON_CS_RING_GFX:
183 p->ring = RADEON_RING_TYPE_GFX_INDEX;
185 case RADEON_CS_RING_COMPUTE:
186 if (p->rdev->family >= CHIP_TAHITI) {
188 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
190 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
192 p->ring = RADEON_RING_TYPE_GFX_INDEX;
194 case RADEON_CS_RING_DMA:
195 if (p->rdev->family >= CHIP_CAYMAN) {
197 p->ring = R600_RING_TYPE_DMA_INDEX;
199 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
200 } else if (p->rdev->family >= CHIP_RV770) {
201 p->ring = R600_RING_TYPE_DMA_INDEX;
206 case RADEON_CS_RING_UVD:
207 p->ring = R600_RING_TYPE_UVD_INDEX;
209 case RADEON_CS_RING_VCE:
210 /* TODO: only use the low priority ring for now */
211 p->ring = TN_RING_TYPE_VCE1_INDEX;
217 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
221 for (i = 0; i < p->nrelocs; i++) {
222 if (!p->relocs[i].robj)
225 radeon_semaphore_sync_to(p->ib.semaphore,
226 p->relocs[i].robj->tbo.sync_obj);
230 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
231 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
233 struct drm_radeon_cs *cs = data;
234 uint64_t *chunk_array_ptr;
236 u32 ring = RADEON_CS_RING_GFX;
239 if (!cs->num_chunks) {
243 INIT_LIST_HEAD(&p->validated);
246 p->ib.semaphore = NULL;
247 p->const_ib.sa_bo = NULL;
248 p->const_ib.semaphore = NULL;
249 p->chunk_ib_idx = -1;
250 p->chunk_relocs_idx = -1;
251 p->chunk_flags_idx = -1;
252 p->chunk_const_ib_idx = -1;
253 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
254 if (p->chunks_array == NULL) {
257 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
258 if (copy_from_user(p->chunks_array, chunk_array_ptr,
259 sizeof(uint64_t)*cs->num_chunks)) {
263 p->nchunks = cs->num_chunks;
264 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
265 if (p->chunks == NULL) {
268 for (i = 0; i < p->nchunks; i++) {
269 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
270 struct drm_radeon_cs_chunk user_chunk;
271 uint32_t __user *cdata;
273 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
274 if (copy_from_user(&user_chunk, chunk_ptr,
275 sizeof(struct drm_radeon_cs_chunk))) {
278 p->chunks[i].length_dw = user_chunk.length_dw;
279 p->chunks[i].chunk_id = user_chunk.chunk_id;
280 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
281 p->chunk_relocs_idx = i;
283 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
285 /* zero length IB isn't useful */
286 if (p->chunks[i].length_dw == 0)
289 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
290 p->chunk_const_ib_idx = i;
291 /* zero length CONST IB isn't useful */
292 if (p->chunks[i].length_dw == 0)
295 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
296 p->chunk_flags_idx = i;
297 /* zero length flags aren't useful */
298 if (p->chunks[i].length_dw == 0)
302 size = p->chunks[i].length_dw;
303 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
304 p->chunks[i].user_ptr = cdata;
305 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB)
308 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
309 if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
313 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
314 size *= sizeof(uint32_t);
315 if (p->chunks[i].kdata == NULL) {
318 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
321 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
322 p->cs_flags = p->chunks[i].kdata[0];
323 if (p->chunks[i].length_dw > 1)
324 ring = p->chunks[i].kdata[1];
325 if (p->chunks[i].length_dw > 2)
326 priority = (s32)p->chunks[i].kdata[2];
330 /* these are KMS only */
332 if ((p->cs_flags & RADEON_CS_USE_VM) &&
333 !p->rdev->vm_manager.enabled) {
334 DRM_ERROR("VM not active on asic!\n");
338 if (radeon_cs_get_ring(p, ring, priority))
341 /* we only support VM on some SI+ rings */
342 if ((p->rdev->asic->ring[p->ring]->cs_parse == NULL) &&
343 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
344 DRM_ERROR("Ring %d requires VM!\n", p->ring);
352 static int cmp_size_smaller_first(void *priv, struct list_head *a,
355 struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head);
356 struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head);
358 /* Sort A before B if A is smaller. */
359 return (int)la->bo->tbo.num_pages - (int)lb->bo->tbo.num_pages;
363 * cs_parser_fini() - clean parser states
364 * @parser: parser structure holding parsing context.
365 * @error: error number
367 * If error is set than unvalidate buffer, otherwise just free memory
368 * used by parsing context.
370 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
375 /* Sort the buffer list from the smallest to largest buffer,
376 * which affects the order of buffers in the LRU list.
377 * This assures that the smallest buffers are added first
378 * to the LRU list, so they are likely to be later evicted
379 * first, instead of large buffers whose eviction is more
382 * This slightly lowers the number of bytes moved by TTM
383 * per frame under memory pressure.
385 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
387 ttm_eu_fence_buffer_objects(&parser->ticket,
390 } else if (backoff) {
391 ttm_eu_backoff_reservation(&parser->ticket,
395 if (parser->relocs != NULL) {
396 for (i = 0; i < parser->nrelocs; i++) {
397 if (parser->relocs[i].gobj)
398 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
401 kfree(parser->track);
402 kfree(parser->relocs);
403 kfree(parser->relocs_ptr);
404 for (i = 0; i < parser->nchunks; i++)
405 drm_free_large(parser->chunks[i].kdata);
406 kfree(parser->chunks);
407 kfree(parser->chunks_array);
408 radeon_ib_free(parser->rdev, &parser->ib);
409 radeon_ib_free(parser->rdev, &parser->const_ib);
412 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
413 struct radeon_cs_parser *parser)
417 if (parser->chunk_ib_idx == -1)
420 if (parser->cs_flags & RADEON_CS_USE_VM)
423 r = radeon_cs_parse(rdev, parser->ring, parser);
424 if (r || parser->parser_error) {
425 DRM_ERROR("Invalid command stream !\n");
429 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
430 radeon_uvd_note_usage(rdev);
431 else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
432 (parser->ring == TN_RING_TYPE_VCE2_INDEX))
433 radeon_vce_note_usage(rdev);
435 radeon_cs_sync_rings(parser);
436 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
438 DRM_ERROR("Failed to schedule IB !\n");
443 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
444 struct radeon_vm *vm)
446 struct radeon_device *rdev = parser->rdev;
447 struct radeon_bo_list *lobj;
448 struct radeon_bo *bo;
451 r = radeon_vm_bo_update(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
455 list_for_each_entry(lobj, &parser->validated, tv.head) {
457 r = radeon_vm_bo_update(parser->rdev, vm, bo, &bo->tbo.mem);
465 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
466 struct radeon_cs_parser *parser)
468 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
469 struct radeon_vm *vm = &fpriv->vm;
472 if (parser->chunk_ib_idx == -1)
474 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
477 if (parser->const_ib.length_dw) {
478 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
484 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
489 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
490 radeon_uvd_note_usage(rdev);
492 mutex_lock(&rdev->vm_manager.lock);
493 mutex_lock(&vm->mutex);
494 r = radeon_vm_alloc_pt(rdev, vm);
498 r = radeon_bo_vm_update_pte(parser, vm);
502 radeon_cs_sync_rings(parser);
503 radeon_semaphore_sync_to(parser->ib.semaphore, vm->fence);
504 radeon_semaphore_sync_to(parser->ib.semaphore,
505 radeon_vm_grab_id(rdev, vm, parser->ring));
507 if ((rdev->family >= CHIP_TAHITI) &&
508 (parser->chunk_const_ib_idx != -1)) {
509 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
511 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
515 radeon_vm_add_to_lru(rdev, vm);
516 mutex_unlock(&vm->mutex);
517 mutex_unlock(&rdev->vm_manager.lock);
521 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
524 r = radeon_gpu_reset(rdev);
531 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
533 struct radeon_cs_chunk *ib_chunk;
534 struct radeon_vm *vm = NULL;
537 if (parser->chunk_ib_idx == -1)
540 if (parser->cs_flags & RADEON_CS_USE_VM) {
541 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
544 if ((rdev->family >= CHIP_TAHITI) &&
545 (parser->chunk_const_ib_idx != -1)) {
546 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
547 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
548 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
551 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
552 vm, ib_chunk->length_dw * 4);
554 DRM_ERROR("Failed to get const ib !\n");
557 parser->const_ib.is_const_ib = true;
558 parser->const_ib.length_dw = ib_chunk->length_dw;
559 if (copy_from_user(parser->const_ib.ptr,
561 ib_chunk->length_dw * 4))
565 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
566 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
567 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
571 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
573 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
574 vm, ib_chunk->length_dw * 4);
576 DRM_ERROR("Failed to get ib !\n");
579 parser->ib.length_dw = ib_chunk->length_dw;
581 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
582 else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
587 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
589 struct radeon_device *rdev = dev->dev_private;
590 struct radeon_cs_parser parser;
593 down_read(&rdev->exclusive_lock);
594 if (!rdev->accel_working) {
595 up_read(&rdev->exclusive_lock);
598 /* initialize parser */
599 memset(&parser, 0, sizeof(struct radeon_cs_parser));
602 parser.dev = rdev->dev;
603 parser.family = rdev->family;
604 r = radeon_cs_parser_init(&parser, data);
606 DRM_ERROR("Failed to initialize parser !\n");
607 radeon_cs_parser_fini(&parser, r, false);
608 up_read(&rdev->exclusive_lock);
609 r = radeon_cs_handle_lockup(rdev, r);
613 r = radeon_cs_ib_fill(rdev, &parser);
615 r = radeon_cs_parser_relocs(&parser);
616 if (r && r != -ERESTARTSYS)
617 DRM_ERROR("Failed to parse relocation %d!\n", r);
621 radeon_cs_parser_fini(&parser, r, false);
622 up_read(&rdev->exclusive_lock);
623 r = radeon_cs_handle_lockup(rdev, r);
627 trace_radeon_cs(&parser);
629 r = radeon_cs_ib_chunk(rdev, &parser);
633 r = radeon_cs_ib_vm_chunk(rdev, &parser);
638 radeon_cs_parser_fini(&parser, r, true);
639 up_read(&rdev->exclusive_lock);
640 r = radeon_cs_handle_lockup(rdev, r);
645 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
646 * @parser: parser structure holding parsing context.
647 * @pkt: where to store packet information
649 * Assume that chunk_ib_index is properly set. Will return -EINVAL
650 * if packet is bigger than remaining ib size. or if packets is unknown.
652 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
653 struct radeon_cs_packet *pkt,
656 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
657 struct radeon_device *rdev = p->rdev;
660 if (idx >= ib_chunk->length_dw) {
661 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
662 idx, ib_chunk->length_dw);
665 header = radeon_get_ib_value(p, idx);
667 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
668 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
671 case RADEON_PACKET_TYPE0:
672 if (rdev->family < CHIP_R600) {
673 pkt->reg = R100_CP_PACKET0_GET_REG(header);
675 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
677 pkt->reg = R600_CP_PACKET0_GET_REG(header);
679 case RADEON_PACKET_TYPE3:
680 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
682 case RADEON_PACKET_TYPE2:
686 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
689 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
690 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
691 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
698 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
699 * @p: structure holding the parser context.
701 * Check if the next packet is NOP relocation packet3.
703 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
705 struct radeon_cs_packet p3reloc;
708 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
711 if (p3reloc.type != RADEON_PACKET_TYPE3)
713 if (p3reloc.opcode != RADEON_PACKET3_NOP)
719 * radeon_cs_dump_packet() - dump raw packet context
720 * @p: structure holding the parser context.
721 * @pkt: structure holding the packet.
723 * Used mostly for debugging and error reporting.
725 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
726 struct radeon_cs_packet *pkt)
728 volatile uint32_t *ib;
734 for (i = 0; i <= (pkt->count + 1); i++, idx++)
735 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
739 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
740 * @parser: parser structure holding parsing context.
741 * @data: pointer to relocation data
742 * @offset_start: starting offset
743 * @offset_mask: offset mask (to align start offset on)
744 * @reloc: reloc informations
746 * Check if next packet is relocation packet3, do bo validation and compute
747 * GPU offset using the provided start.
749 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
750 struct radeon_cs_reloc **cs_reloc,
753 struct radeon_cs_chunk *relocs_chunk;
754 struct radeon_cs_packet p3reloc;
758 if (p->chunk_relocs_idx == -1) {
759 DRM_ERROR("No relocation chunk !\n");
763 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
764 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
767 p->idx += p3reloc.count + 2;
768 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
769 p3reloc.opcode != RADEON_PACKET3_NOP) {
770 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
772 radeon_cs_dump_packet(p, &p3reloc);
775 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
776 if (idx >= relocs_chunk->length_dw) {
777 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
778 idx, relocs_chunk->length_dw);
779 radeon_cs_dump_packet(p, &p3reloc);
782 /* FIXME: we assume reloc size is 4 dwords */
784 *cs_reloc = p->relocs;
785 (*cs_reloc)->lobj.gpu_offset =
786 (u64)relocs_chunk->kdata[idx + 3] << 32;
787 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
789 *cs_reloc = p->relocs_ptr[(idx / 4)];