2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 #include <linux/list_sort.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon_reg.h"
32 #include "radeon_trace.h"
34 #define RADEON_CS_MAX_PRIORITY 32u
35 #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1)
37 /* This is based on the bucket sort with O(n) time complexity.
38 * An item with priority "i" is added to bucket[i]. The lists are then
39 * concatenated in descending order.
41 struct radeon_cs_buckets {
42 struct list_head bucket[RADEON_CS_NUM_BUCKETS];
45 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
49 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
50 INIT_LIST_HEAD(&b->bucket[i]);
53 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
54 struct list_head *item, unsigned priority)
56 /* Since buffers which appear sooner in the relocation list are
57 * likely to be used more often than buffers which appear later
58 * in the list, the sort mustn't change the ordering of buffers
59 * with the same priority, i.e. it must be stable.
61 list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
64 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
65 struct list_head *out_list)
69 /* Connect the sorted buckets in the output list. */
70 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
71 list_splice(&b->bucket[i], out_list);
75 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
77 struct drm_device *ddev = p->rdev->ddev;
78 struct radeon_cs_chunk *chunk;
79 struct radeon_cs_buckets buckets;
83 if (p->chunk_relocs_idx == -1) {
86 chunk = &p->chunks[p->chunk_relocs_idx];
88 /* FIXME: we assume that each relocs use 4 dwords */
89 p->nrelocs = chunk->length_dw / 4;
90 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
91 if (p->relocs_ptr == NULL) {
94 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
95 if (p->relocs == NULL) {
99 radeon_cs_buckets_init(&buckets);
101 for (i = 0; i < p->nrelocs; i++) {
102 struct drm_radeon_cs_reloc *r;
106 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
107 for (j = 0; j < i; j++) {
108 if (r->handle == p->relocs[j].handle) {
109 p->relocs_ptr[i] = &p->relocs[j];
115 p->relocs[i].handle = 0;
119 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
121 if (p->relocs[i].gobj == NULL) {
122 DRM_ERROR("gem object lookup failed 0x%x\n",
126 p->relocs_ptr[i] = &p->relocs[i];
127 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
129 /* The userspace buffer priorities are from 0 to 15. A higher
130 * number means the buffer is more important.
131 * Also, the buffers used for write have a higher priority than
132 * the buffers used for read only, which doubles the range
133 * to 0 to 31. 32 is reserved for the kernel driver.
135 priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
138 /* the first reloc of an UVD job is the msg and that must be in
139 VRAM, also but everything into VRAM on AGP cards to avoid
141 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
142 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
143 /* TODO: is this still needed for NI+ ? */
144 p->relocs[i].prefered_domains =
145 RADEON_GEM_DOMAIN_VRAM;
147 p->relocs[i].allowed_domains =
148 RADEON_GEM_DOMAIN_VRAM;
150 /* prioritize this over any other relocation */
151 priority = RADEON_CS_MAX_PRIORITY;
153 uint32_t domain = r->write_domain ?
154 r->write_domain : r->read_domains;
156 if (domain & RADEON_GEM_DOMAIN_CPU) {
157 DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
158 "for command submission\n");
162 p->relocs[i].prefered_domains = domain;
163 if (domain == RADEON_GEM_DOMAIN_VRAM)
164 domain |= RADEON_GEM_DOMAIN_GTT;
165 p->relocs[i].allowed_domains = domain;
168 p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
169 p->relocs[i].handle = r->handle;
171 radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head,
175 radeon_cs_buckets_get_list(&buckets, &p->validated);
177 if (p->cs_flags & RADEON_CS_USE_VM)
178 p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
181 return radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);
184 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
186 p->priority = priority;
190 DRM_ERROR("unknown ring id: %d\n", ring);
192 case RADEON_CS_RING_GFX:
193 p->ring = RADEON_RING_TYPE_GFX_INDEX;
195 case RADEON_CS_RING_COMPUTE:
196 if (p->rdev->family >= CHIP_TAHITI) {
198 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
200 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
202 p->ring = RADEON_RING_TYPE_GFX_INDEX;
204 case RADEON_CS_RING_DMA:
205 if (p->rdev->family >= CHIP_CAYMAN) {
207 p->ring = R600_RING_TYPE_DMA_INDEX;
209 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
210 } else if (p->rdev->family >= CHIP_RV770) {
211 p->ring = R600_RING_TYPE_DMA_INDEX;
216 case RADEON_CS_RING_UVD:
217 p->ring = R600_RING_TYPE_UVD_INDEX;
219 case RADEON_CS_RING_VCE:
220 /* TODO: only use the low priority ring for now */
221 p->ring = TN_RING_TYPE_VCE1_INDEX;
227 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
231 for (i = 0; i < p->nrelocs; i++) {
232 if (!p->relocs[i].robj)
235 radeon_semaphore_sync_to(p->ib.semaphore,
236 p->relocs[i].robj->tbo.sync_obj);
240 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
241 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
243 struct drm_radeon_cs *cs = data;
244 uint64_t *chunk_array_ptr;
246 u32 ring = RADEON_CS_RING_GFX;
249 if (!cs->num_chunks) {
253 INIT_LIST_HEAD(&p->validated);
256 p->ib.semaphore = NULL;
257 p->const_ib.sa_bo = NULL;
258 p->const_ib.semaphore = NULL;
259 p->chunk_ib_idx = -1;
260 p->chunk_relocs_idx = -1;
261 p->chunk_flags_idx = -1;
262 p->chunk_const_ib_idx = -1;
263 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
264 if (p->chunks_array == NULL) {
267 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
268 if (copy_from_user(p->chunks_array, chunk_array_ptr,
269 sizeof(uint64_t)*cs->num_chunks)) {
273 p->nchunks = cs->num_chunks;
274 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
275 if (p->chunks == NULL) {
278 for (i = 0; i < p->nchunks; i++) {
279 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
280 struct drm_radeon_cs_chunk user_chunk;
281 uint32_t __user *cdata;
283 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
284 if (copy_from_user(&user_chunk, chunk_ptr,
285 sizeof(struct drm_radeon_cs_chunk))) {
288 p->chunks[i].length_dw = user_chunk.length_dw;
289 p->chunks[i].chunk_id = user_chunk.chunk_id;
290 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
291 p->chunk_relocs_idx = i;
293 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
295 /* zero length IB isn't useful */
296 if (p->chunks[i].length_dw == 0)
299 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
300 p->chunk_const_ib_idx = i;
301 /* zero length CONST IB isn't useful */
302 if (p->chunks[i].length_dw == 0)
305 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
306 p->chunk_flags_idx = i;
307 /* zero length flags aren't useful */
308 if (p->chunks[i].length_dw == 0)
312 size = p->chunks[i].length_dw;
313 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
314 p->chunks[i].user_ptr = cdata;
315 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB)
318 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
319 if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
323 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
324 size *= sizeof(uint32_t);
325 if (p->chunks[i].kdata == NULL) {
328 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
331 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
332 p->cs_flags = p->chunks[i].kdata[0];
333 if (p->chunks[i].length_dw > 1)
334 ring = p->chunks[i].kdata[1];
335 if (p->chunks[i].length_dw > 2)
336 priority = (s32)p->chunks[i].kdata[2];
340 /* these are KMS only */
342 if ((p->cs_flags & RADEON_CS_USE_VM) &&
343 !p->rdev->vm_manager.enabled) {
344 DRM_ERROR("VM not active on asic!\n");
348 if (radeon_cs_get_ring(p, ring, priority))
351 /* we only support VM on some SI+ rings */
352 if ((p->cs_flags & RADEON_CS_USE_VM) == 0) {
353 if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) {
354 DRM_ERROR("Ring %d requires VM!\n", p->ring);
358 if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) {
359 DRM_ERROR("VM not supported on ring %d!\n",
369 static int cmp_size_smaller_first(void *priv, struct list_head *a,
372 struct radeon_cs_reloc *la = list_entry(a, struct radeon_cs_reloc, tv.head);
373 struct radeon_cs_reloc *lb = list_entry(b, struct radeon_cs_reloc, tv.head);
375 /* Sort A before B if A is smaller. */
376 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
380 * cs_parser_fini() - clean parser states
381 * @parser: parser structure holding parsing context.
382 * @error: error number
384 * If error is set than unvalidate buffer, otherwise just free memory
385 * used by parsing context.
387 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
392 /* Sort the buffer list from the smallest to largest buffer,
393 * which affects the order of buffers in the LRU list.
394 * This assures that the smallest buffers are added first
395 * to the LRU list, so they are likely to be later evicted
396 * first, instead of large buffers whose eviction is more
399 * This slightly lowers the number of bytes moved by TTM
400 * per frame under memory pressure.
402 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
404 ttm_eu_fence_buffer_objects(&parser->ticket,
407 } else if (backoff) {
408 ttm_eu_backoff_reservation(&parser->ticket,
412 if (parser->relocs != NULL) {
413 for (i = 0; i < parser->nrelocs; i++) {
414 if (parser->relocs[i].gobj)
415 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
418 kfree(parser->track);
419 kfree(parser->relocs);
420 kfree(parser->relocs_ptr);
421 kfree(parser->vm_bos);
422 for (i = 0; i < parser->nchunks; i++)
423 drm_free_large(parser->chunks[i].kdata);
424 kfree(parser->chunks);
425 kfree(parser->chunks_array);
426 radeon_ib_free(parser->rdev, &parser->ib);
427 radeon_ib_free(parser->rdev, &parser->const_ib);
430 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
431 struct radeon_cs_parser *parser)
435 if (parser->chunk_ib_idx == -1)
438 if (parser->cs_flags & RADEON_CS_USE_VM)
441 r = radeon_cs_parse(rdev, parser->ring, parser);
442 if (r || parser->parser_error) {
443 DRM_ERROR("Invalid command stream !\n");
447 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
448 radeon_uvd_note_usage(rdev);
449 else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
450 (parser->ring == TN_RING_TYPE_VCE2_INDEX))
451 radeon_vce_note_usage(rdev);
453 radeon_cs_sync_rings(parser);
454 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
456 DRM_ERROR("Failed to schedule IB !\n");
461 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
462 struct radeon_vm *vm)
464 struct radeon_device *rdev = p->rdev;
465 struct radeon_bo_va *bo_va;
468 r = radeon_vm_update_page_directory(rdev, vm);
472 r = radeon_vm_clear_freed(rdev, vm);
476 if (vm->ib_bo_va == NULL) {
477 DRM_ERROR("Tmp BO not in VM!\n");
481 r = radeon_vm_bo_update(rdev, vm->ib_bo_va,
482 &rdev->ring_tmp_bo.bo->tbo.mem);
486 for (i = 0; i < p->nrelocs; i++) {
487 struct radeon_bo *bo;
489 /* ignore duplicates */
490 if (p->relocs_ptr[i] != &p->relocs[i])
493 bo = p->relocs[i].robj;
494 bo_va = radeon_vm_bo_find(vm, bo);
496 dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
500 r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem);
505 return radeon_vm_clear_invalids(rdev, vm);
508 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
509 struct radeon_cs_parser *parser)
511 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
512 struct radeon_vm *vm = &fpriv->vm;
515 if (parser->chunk_ib_idx == -1)
517 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
520 if (parser->const_ib.length_dw) {
521 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
527 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
532 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
533 radeon_uvd_note_usage(rdev);
535 mutex_lock(&vm->mutex);
536 r = radeon_bo_vm_update_pte(parser, vm);
540 radeon_cs_sync_rings(parser);
541 radeon_semaphore_sync_to(parser->ib.semaphore, vm->fence);
543 if ((rdev->family >= CHIP_TAHITI) &&
544 (parser->chunk_const_ib_idx != -1)) {
545 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
547 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
551 mutex_unlock(&vm->mutex);
555 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
558 r = radeon_gpu_reset(rdev);
565 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
567 struct radeon_cs_chunk *ib_chunk;
568 struct radeon_vm *vm = NULL;
571 if (parser->chunk_ib_idx == -1)
574 if (parser->cs_flags & RADEON_CS_USE_VM) {
575 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
578 if ((rdev->family >= CHIP_TAHITI) &&
579 (parser->chunk_const_ib_idx != -1)) {
580 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
581 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
582 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
585 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
586 vm, ib_chunk->length_dw * 4);
588 DRM_ERROR("Failed to get const ib !\n");
591 parser->const_ib.is_const_ib = true;
592 parser->const_ib.length_dw = ib_chunk->length_dw;
593 if (copy_from_user(parser->const_ib.ptr,
595 ib_chunk->length_dw * 4))
599 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
600 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
601 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
605 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
607 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
608 vm, ib_chunk->length_dw * 4);
610 DRM_ERROR("Failed to get ib !\n");
613 parser->ib.length_dw = ib_chunk->length_dw;
615 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
616 else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
621 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
623 struct radeon_device *rdev = dev->dev_private;
624 struct radeon_cs_parser parser;
627 down_read(&rdev->exclusive_lock);
628 if (!rdev->accel_working) {
629 up_read(&rdev->exclusive_lock);
632 /* initialize parser */
633 memset(&parser, 0, sizeof(struct radeon_cs_parser));
636 parser.dev = rdev->dev;
637 parser.family = rdev->family;
638 r = radeon_cs_parser_init(&parser, data);
640 DRM_ERROR("Failed to initialize parser !\n");
641 radeon_cs_parser_fini(&parser, r, false);
642 up_read(&rdev->exclusive_lock);
643 r = radeon_cs_handle_lockup(rdev, r);
647 r = radeon_cs_ib_fill(rdev, &parser);
649 r = radeon_cs_parser_relocs(&parser);
650 if (r && r != -ERESTARTSYS)
651 DRM_ERROR("Failed to parse relocation %d!\n", r);
655 radeon_cs_parser_fini(&parser, r, false);
656 up_read(&rdev->exclusive_lock);
657 r = radeon_cs_handle_lockup(rdev, r);
661 trace_radeon_cs(&parser);
663 r = radeon_cs_ib_chunk(rdev, &parser);
667 r = radeon_cs_ib_vm_chunk(rdev, &parser);
672 radeon_cs_parser_fini(&parser, r, true);
673 up_read(&rdev->exclusive_lock);
674 r = radeon_cs_handle_lockup(rdev, r);
679 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
680 * @parser: parser structure holding parsing context.
681 * @pkt: where to store packet information
683 * Assume that chunk_ib_index is properly set. Will return -EINVAL
684 * if packet is bigger than remaining ib size. or if packets is unknown.
686 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
687 struct radeon_cs_packet *pkt,
690 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
691 struct radeon_device *rdev = p->rdev;
694 if (idx >= ib_chunk->length_dw) {
695 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
696 idx, ib_chunk->length_dw);
699 header = radeon_get_ib_value(p, idx);
701 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
702 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
705 case RADEON_PACKET_TYPE0:
706 if (rdev->family < CHIP_R600) {
707 pkt->reg = R100_CP_PACKET0_GET_REG(header);
709 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
711 pkt->reg = R600_CP_PACKET0_GET_REG(header);
713 case RADEON_PACKET_TYPE3:
714 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
716 case RADEON_PACKET_TYPE2:
720 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
723 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
724 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
725 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
732 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
733 * @p: structure holding the parser context.
735 * Check if the next packet is NOP relocation packet3.
737 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
739 struct radeon_cs_packet p3reloc;
742 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
745 if (p3reloc.type != RADEON_PACKET_TYPE3)
747 if (p3reloc.opcode != RADEON_PACKET3_NOP)
753 * radeon_cs_dump_packet() - dump raw packet context
754 * @p: structure holding the parser context.
755 * @pkt: structure holding the packet.
757 * Used mostly for debugging and error reporting.
759 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
760 struct radeon_cs_packet *pkt)
762 volatile uint32_t *ib;
768 for (i = 0; i <= (pkt->count + 1); i++, idx++)
769 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
773 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
774 * @parser: parser structure holding parsing context.
775 * @data: pointer to relocation data
776 * @offset_start: starting offset
777 * @offset_mask: offset mask (to align start offset on)
778 * @reloc: reloc informations
780 * Check if next packet is relocation packet3, do bo validation and compute
781 * GPU offset using the provided start.
783 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
784 struct radeon_cs_reloc **cs_reloc,
787 struct radeon_cs_chunk *relocs_chunk;
788 struct radeon_cs_packet p3reloc;
792 if (p->chunk_relocs_idx == -1) {
793 DRM_ERROR("No relocation chunk !\n");
797 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
798 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
801 p->idx += p3reloc.count + 2;
802 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
803 p3reloc.opcode != RADEON_PACKET3_NOP) {
804 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
806 radeon_cs_dump_packet(p, &p3reloc);
809 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
810 if (idx >= relocs_chunk->length_dw) {
811 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
812 idx, relocs_chunk->length_dw);
813 radeon_cs_dump_packet(p, &p3reloc);
816 /* FIXME: we assume reloc size is 4 dwords */
818 *cs_reloc = p->relocs;
819 (*cs_reloc)->gpu_offset =
820 (u64)relocs_chunk->kdata[idx + 3] << 32;
821 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
823 *cs_reloc = p->relocs_ptr[(idx / 4)];