2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/radeon_drm.h>
30 static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
32 struct radeon_device *rdev = crtc->dev->dev_private;
33 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
36 if (ASIC_IS_DCE4(rdev)) {
37 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
39 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
41 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
42 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
43 } else if (ASIC_IS_AVIVO(rdev)) {
44 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
46 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
48 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
49 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
51 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
53 cur_lock |= RADEON_CUR_LOCK;
55 cur_lock &= ~RADEON_CUR_LOCK;
56 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
60 static void radeon_hide_cursor(struct drm_crtc *crtc)
62 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
63 struct radeon_device *rdev = crtc->dev->dev_private;
65 if (ASIC_IS_DCE4(rdev)) {
66 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
67 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
68 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
69 } else if (ASIC_IS_AVIVO(rdev)) {
70 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
71 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
74 switch (radeon_crtc->crtc_id) {
76 reg = RADEON_CRTC_GEN_CNTL;
79 reg = RADEON_CRTC2_GEN_CNTL;
84 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
88 static void radeon_show_cursor(struct drm_crtc *crtc)
90 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
91 struct radeon_device *rdev = crtc->dev->dev_private;
93 if (ASIC_IS_DCE4(rdev)) {
94 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
95 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
96 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
97 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
98 } else if (ASIC_IS_AVIVO(rdev)) {
99 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
100 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
101 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
103 switch (radeon_crtc->crtc_id) {
105 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
108 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
114 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
115 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
116 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
120 static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
122 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
123 struct radeon_device *rdev = crtc->dev->dev_private;
124 int xorigin = 0, yorigin = 0;
125 int w = radeon_crtc->cursor_width;
127 if (ASIC_IS_AVIVO(rdev)) {
128 /* avivo cursor are offset into the total surface */
132 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
135 xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
139 yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
143 /* fixed on DCE6 and newer */
144 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
146 struct drm_crtc *crtc_p;
149 * avivo cursor image can't end on 128 pixel boundary or
150 * go past the end of the frame if both crtcs are enabled
152 * NOTE: It is safe to access crtc->enabled of other crtcs
153 * without holding either the mode_config lock or the other
154 * crtc's lock as long as write access to this flag _always_
157 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
162 int cursor_end, frame_end;
164 cursor_end = x - xorigin + w;
165 frame_end = crtc->x + crtc->mode.crtc_hdisplay;
166 if (cursor_end >= frame_end) {
167 w = w - (cursor_end - frame_end);
168 if (!(frame_end & 0x7f))
171 if (!(cursor_end & 0x7f))
176 cursor_end = x - xorigin + w;
177 if (!(cursor_end & 0x7f)) {
185 if (ASIC_IS_DCE4(rdev)) {
186 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
187 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
188 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
189 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
190 } else if (ASIC_IS_AVIVO(rdev)) {
191 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
192 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
193 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
194 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
196 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
199 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
203 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
207 /* offset is from DISP(2)_BASE_ADDRESS */
208 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
212 radeon_crtc->cursor_x = x;
213 radeon_crtc->cursor_y = y;
218 int radeon_crtc_cursor_move(struct drm_crtc *crtc,
223 radeon_lock_cursor(crtc, true);
224 ret = radeon_cursor_move_locked(crtc, x, y);
225 radeon_lock_cursor(crtc, false);
230 static int radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj)
232 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
233 struct radeon_device *rdev = crtc->dev->dev_private;
234 struct radeon_bo *robj = gem_to_radeon_bo(obj);
238 ret = radeon_bo_reserve(robj, false);
239 if (unlikely(ret != 0))
241 /* Only 27 bit offset for legacy cursor */
242 ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
243 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
245 radeon_bo_unreserve(robj);
249 if (ASIC_IS_DCE4(rdev)) {
250 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
251 upper_32_bits(gpu_addr));
252 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
253 gpu_addr & 0xffffffff);
254 } else if (ASIC_IS_AVIVO(rdev)) {
255 if (rdev->family >= CHIP_RV770) {
256 if (radeon_crtc->crtc_id)
257 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
259 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
261 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
262 gpu_addr & 0xffffffff);
264 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
265 /* offset is from DISP(2)_BASE_ADDRESS */
266 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
272 drm_gem_object_unreference_unlocked(obj);
277 int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
278 struct drm_file *file_priv,
285 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
286 struct drm_gem_object *obj;
290 /* turn off cursor */
291 radeon_hide_cursor(crtc);
296 if ((width > radeon_crtc->max_cursor_width) ||
297 (height > radeon_crtc->max_cursor_height)) {
298 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
302 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
304 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
308 radeon_crtc->cursor_width = width;
309 radeon_crtc->cursor_height = height;
311 radeon_lock_cursor(crtc, true);
313 if (hot_x != radeon_crtc->cursor_hot_x ||
314 hot_y != radeon_crtc->cursor_hot_y) {
317 x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x;
318 y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y;
320 radeon_cursor_move_locked(crtc, x, y);
322 radeon_crtc->cursor_hot_x = hot_x;
323 radeon_crtc->cursor_hot_y = hot_y;
326 ret = radeon_set_cursor(crtc, obj);
329 DRM_ERROR("radeon_set_cursor returned %d, not changing cursor\n",
332 radeon_show_cursor(crtc);
334 radeon_lock_cursor(crtc, false);
337 if (radeon_crtc->cursor_bo) {
338 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
339 ret = radeon_bo_reserve(robj, false);
340 if (likely(ret == 0)) {
341 radeon_bo_unpin(robj);
342 radeon_bo_unreserve(robj);
344 if (radeon_crtc->cursor_bo != obj)
345 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
348 radeon_crtc->cursor_bo = obj;
353 * radeon_cursor_reset - Re-set the current cursor, if any.
357 * If the CRTC passed in currently has a cursor assigned, this function
358 * makes sure it's visible.
360 void radeon_cursor_reset(struct drm_crtc *crtc)
362 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
365 if (radeon_crtc->cursor_bo) {
366 radeon_lock_cursor(crtc, true);
368 radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x,
369 radeon_crtc->cursor_y);
371 ret = radeon_set_cursor(crtc, radeon_crtc->cursor_bo);
373 DRM_ERROR("radeon_set_cursor returned %d, not showing "
376 radeon_show_cursor(crtc);
378 radeon_lock_cursor(crtc, false);