2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name[][16] = {
106 bool radeon_is_px(struct drm_device *dev)
108 struct radeon_device *rdev = dev->dev_private;
110 if (rdev->flags & RADEON_IS_PX)
116 * radeon_program_register_sequence - program an array of registers.
118 * @rdev: radeon_device pointer
119 * @registers: pointer to the register array
120 * @array_size: size of the register array
122 * Programs an array or registers with and and or masks.
123 * This is a helper for setting golden registers.
125 void radeon_program_register_sequence(struct radeon_device *rdev,
126 const u32 *registers,
127 const u32 array_size)
129 u32 tmp, reg, and_mask, or_mask;
135 for (i = 0; i < array_size; i +=3) {
136 reg = registers[i + 0];
137 and_mask = registers[i + 1];
138 or_mask = registers[i + 2];
140 if (and_mask == 0xffffffff) {
151 void radeon_pci_config_reset(struct radeon_device *rdev)
153 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
157 * radeon_surface_init - Clear GPU surface registers.
159 * @rdev: radeon_device pointer
161 * Clear GPU surface registers (r1xx-r5xx).
163 void radeon_surface_init(struct radeon_device *rdev)
165 /* FIXME: check this out */
166 if (rdev->family < CHIP_R600) {
169 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
170 if (rdev->surface_regs[i].bo)
171 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
173 radeon_clear_surface_reg(rdev, i);
175 /* enable surfaces */
176 WREG32(RADEON_SURFACE_CNTL, 0);
181 * GPU scratch registers helpers function.
184 * radeon_scratch_init - Init scratch register driver information.
186 * @rdev: radeon_device pointer
188 * Init CP scratch register driver information (r1xx-r5xx)
190 void radeon_scratch_init(struct radeon_device *rdev)
194 /* FIXME: check this out */
195 if (rdev->family < CHIP_R300) {
196 rdev->scratch.num_reg = 5;
198 rdev->scratch.num_reg = 7;
200 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
201 for (i = 0; i < rdev->scratch.num_reg; i++) {
202 rdev->scratch.free[i] = true;
203 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
208 * radeon_scratch_get - Allocate a scratch register
210 * @rdev: radeon_device pointer
211 * @reg: scratch register mmio offset
213 * Allocate a CP scratch register for use by the driver (all asics).
214 * Returns 0 on success or -EINVAL on failure.
216 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
220 for (i = 0; i < rdev->scratch.num_reg; i++) {
221 if (rdev->scratch.free[i]) {
222 rdev->scratch.free[i] = false;
223 *reg = rdev->scratch.reg[i];
231 * radeon_scratch_free - Free a scratch register
233 * @rdev: radeon_device pointer
234 * @reg: scratch register mmio offset
236 * Free a CP scratch register allocated for use by the driver (all asics)
238 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
242 for (i = 0; i < rdev->scratch.num_reg; i++) {
243 if (rdev->scratch.reg[i] == reg) {
244 rdev->scratch.free[i] = true;
251 * GPU doorbell aperture helpers function.
254 * radeon_doorbell_init - Init doorbell driver information.
256 * @rdev: radeon_device pointer
258 * Init doorbell driver information (CIK)
259 * Returns 0 on success, error on failure.
261 static int radeon_doorbell_init(struct radeon_device *rdev)
263 /* doorbell bar mapping */
264 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
265 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
267 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
268 if (rdev->doorbell.num_doorbells == 0)
271 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
272 if (rdev->doorbell.ptr == NULL) {
275 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
276 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
278 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
284 * radeon_doorbell_fini - Tear down doorbell driver information.
286 * @rdev: radeon_device pointer
288 * Tear down doorbell driver information (CIK)
290 static void radeon_doorbell_fini(struct radeon_device *rdev)
292 iounmap(rdev->doorbell.ptr);
293 rdev->doorbell.ptr = NULL;
297 * radeon_doorbell_get - Allocate a doorbell entry
299 * @rdev: radeon_device pointer
300 * @doorbell: doorbell index
302 * Allocate a doorbell for use by the driver (all asics).
303 * Returns 0 on success or -EINVAL on failure.
305 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
307 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
308 if (offset < rdev->doorbell.num_doorbells) {
309 __set_bit(offset, rdev->doorbell.used);
318 * radeon_doorbell_free - Free a doorbell entry
320 * @rdev: radeon_device pointer
321 * @doorbell: doorbell index
323 * Free a doorbell allocated for use by the driver (all asics)
325 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
327 if (doorbell < rdev->doorbell.num_doorbells)
328 __clear_bit(doorbell, rdev->doorbell.used);
333 * Writeback is the the method by which the the GPU updates special pages
334 * in memory with the status of certain GPU events (fences, ring pointers,
339 * radeon_wb_disable - Disable Writeback
341 * @rdev: radeon_device pointer
343 * Disables Writeback (all asics). Used for suspend.
345 void radeon_wb_disable(struct radeon_device *rdev)
347 rdev->wb.enabled = false;
351 * radeon_wb_fini - Disable Writeback and free memory
353 * @rdev: radeon_device pointer
355 * Disables Writeback and frees the Writeback memory (all asics).
356 * Used at driver shutdown.
358 void radeon_wb_fini(struct radeon_device *rdev)
360 radeon_wb_disable(rdev);
361 if (rdev->wb.wb_obj) {
362 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
363 radeon_bo_kunmap(rdev->wb.wb_obj);
364 radeon_bo_unpin(rdev->wb.wb_obj);
365 radeon_bo_unreserve(rdev->wb.wb_obj);
367 radeon_bo_unref(&rdev->wb.wb_obj);
369 rdev->wb.wb_obj = NULL;
374 * radeon_wb_init- Init Writeback driver info and allocate memory
376 * @rdev: radeon_device pointer
378 * Disables Writeback and frees the Writeback memory (all asics).
379 * Used at driver startup.
380 * Returns 0 on success or an -error on failure.
382 int radeon_wb_init(struct radeon_device *rdev)
386 if (rdev->wb.wb_obj == NULL) {
387 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
388 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
390 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
393 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
394 if (unlikely(r != 0)) {
395 radeon_wb_fini(rdev);
398 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
401 radeon_bo_unreserve(rdev->wb.wb_obj);
402 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
403 radeon_wb_fini(rdev);
406 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
407 radeon_bo_unreserve(rdev->wb.wb_obj);
409 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
410 radeon_wb_fini(rdev);
415 /* clear wb memory */
416 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
417 /* disable event_write fences */
418 rdev->wb.use_event = false;
419 /* disabled via module param */
420 if (radeon_no_wb == 1) {
421 rdev->wb.enabled = false;
423 if (rdev->flags & RADEON_IS_AGP) {
424 /* often unreliable on AGP */
425 rdev->wb.enabled = false;
426 } else if (rdev->family < CHIP_R300) {
427 /* often unreliable on pre-r300 */
428 rdev->wb.enabled = false;
430 rdev->wb.enabled = true;
431 /* event_write fences are only available on r600+ */
432 if (rdev->family >= CHIP_R600) {
433 rdev->wb.use_event = true;
437 /* always use writeback/events on NI, APUs */
438 if (rdev->family >= CHIP_PALM) {
439 rdev->wb.enabled = true;
440 rdev->wb.use_event = true;
443 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
449 * radeon_vram_location - try to find VRAM location
450 * @rdev: radeon device structure holding all necessary informations
451 * @mc: memory controller structure holding memory informations
452 * @base: base address at which to put VRAM
454 * Function will place try to place VRAM at base address provided
455 * as parameter (which is so far either PCI aperture address or
456 * for IGP TOM base address).
458 * If there is not enough space to fit the unvisible VRAM in the 32bits
459 * address space then we limit the VRAM size to the aperture.
461 * If we are using AGP and if the AGP aperture doesn't allow us to have
462 * room for all the VRAM than we restrict the VRAM to the PCI aperture
463 * size and print a warning.
465 * This function will never fails, worst case are limiting VRAM.
467 * Note: GTT start, end, size should be initialized before calling this
468 * function on AGP platform.
470 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
471 * this shouldn't be a problem as we are using the PCI aperture as a reference.
472 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
475 * Note: we use mc_vram_size as on some board we need to program the mc to
476 * cover the whole aperture even if VRAM size is inferior to aperture size
477 * Novell bug 204882 + along with lots of ubuntu ones
479 * Note: when limiting vram it's safe to overwritte real_vram_size because
480 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
481 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
484 * Note: IGP TOM addr should be the same as the aperture addr, we don't
485 * explicitly check for that thought.
487 * FIXME: when reducing VRAM size align new size on power of 2.
489 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
491 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
493 mc->vram_start = base;
494 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
495 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
496 mc->real_vram_size = mc->aper_size;
497 mc->mc_vram_size = mc->aper_size;
499 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
500 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
501 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
502 mc->real_vram_size = mc->aper_size;
503 mc->mc_vram_size = mc->aper_size;
505 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
506 if (limit && limit < mc->real_vram_size)
507 mc->real_vram_size = limit;
508 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
509 mc->mc_vram_size >> 20, mc->vram_start,
510 mc->vram_end, mc->real_vram_size >> 20);
514 * radeon_gtt_location - try to find GTT location
515 * @rdev: radeon device structure holding all necessary informations
516 * @mc: memory controller structure holding memory informations
518 * Function will place try to place GTT before or after VRAM.
520 * If GTT size is bigger than space left then we ajust GTT size.
521 * Thus function will never fails.
523 * FIXME: when reducing GTT size align new size on power of 2.
525 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
527 u64 size_af, size_bf;
529 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
530 size_bf = mc->vram_start & ~mc->gtt_base_align;
531 if (size_bf > size_af) {
532 if (mc->gtt_size > size_bf) {
533 dev_warn(rdev->dev, "limiting GTT\n");
534 mc->gtt_size = size_bf;
536 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
538 if (mc->gtt_size > size_af) {
539 dev_warn(rdev->dev, "limiting GTT\n");
540 mc->gtt_size = size_af;
542 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
544 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
545 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
546 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
550 * GPU helpers function.
553 * radeon_card_posted - check if the hw has already been initialized
555 * @rdev: radeon_device pointer
557 * Check if the asic has been initialized (all asics).
558 * Used at driver startup.
559 * Returns true if initialized or false if not.
561 bool radeon_card_posted(struct radeon_device *rdev)
565 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
566 if (efi_enabled(EFI_BOOT) &&
567 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
568 (rdev->family < CHIP_R600))
571 if (ASIC_IS_NODCE(rdev))
574 /* first check CRTCs */
575 if (ASIC_IS_DCE4(rdev)) {
576 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
577 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
578 if (rdev->num_crtc >= 4) {
579 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
580 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
582 if (rdev->num_crtc >= 6) {
583 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
584 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
586 if (reg & EVERGREEN_CRTC_MASTER_EN)
588 } else if (ASIC_IS_AVIVO(rdev)) {
589 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
590 RREG32(AVIVO_D2CRTC_CONTROL);
591 if (reg & AVIVO_CRTC_EN) {
595 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
596 RREG32(RADEON_CRTC2_GEN_CNTL);
597 if (reg & RADEON_CRTC_EN) {
603 /* then check MEM_SIZE, in case the crtcs are off */
604 if (rdev->family >= CHIP_R600)
605 reg = RREG32(R600_CONFIG_MEMSIZE);
607 reg = RREG32(RADEON_CONFIG_MEMSIZE);
617 * radeon_update_bandwidth_info - update display bandwidth params
619 * @rdev: radeon_device pointer
621 * Used when sclk/mclk are switched or display modes are set.
622 * params are used to calculate display watermarks (all asics)
624 void radeon_update_bandwidth_info(struct radeon_device *rdev)
627 u32 sclk = rdev->pm.current_sclk;
628 u32 mclk = rdev->pm.current_mclk;
630 /* sclk/mclk in Mhz */
631 a.full = dfixed_const(100);
632 rdev->pm.sclk.full = dfixed_const(sclk);
633 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
634 rdev->pm.mclk.full = dfixed_const(mclk);
635 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
637 if (rdev->flags & RADEON_IS_IGP) {
638 a.full = dfixed_const(16);
639 /* core_bandwidth = sclk(Mhz) * 16 */
640 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
645 * radeon_boot_test_post_card - check and possibly initialize the hw
647 * @rdev: radeon_device pointer
649 * Check if the asic is initialized and if not, attempt to initialize
651 * Returns true if initialized or false if not.
653 bool radeon_boot_test_post_card(struct radeon_device *rdev)
655 if (radeon_card_posted(rdev))
659 DRM_INFO("GPU not posted. posting now...\n");
660 if (rdev->is_atom_bios)
661 atom_asic_init(rdev->mode_info.atom_context);
663 radeon_combios_asic_init(rdev->ddev);
666 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
672 * radeon_dummy_page_init - init dummy page used by the driver
674 * @rdev: radeon_device pointer
676 * Allocate the dummy page used by the driver (all asics).
677 * This dummy page is used by the driver as a filler for gart entries
678 * when pages are taken out of the GART
679 * Returns 0 on sucess, -ENOMEM on failure.
681 int radeon_dummy_page_init(struct radeon_device *rdev)
683 if (rdev->dummy_page.page)
685 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
686 if (rdev->dummy_page.page == NULL)
688 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
689 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
690 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
691 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
692 __free_page(rdev->dummy_page.page);
693 rdev->dummy_page.page = NULL;
700 * radeon_dummy_page_fini - free dummy page used by the driver
702 * @rdev: radeon_device pointer
704 * Frees the dummy page used by the driver (all asics).
706 void radeon_dummy_page_fini(struct radeon_device *rdev)
708 if (rdev->dummy_page.page == NULL)
710 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
711 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
712 __free_page(rdev->dummy_page.page);
713 rdev->dummy_page.page = NULL;
717 /* ATOM accessor methods */
719 * ATOM is an interpreted byte code stored in tables in the vbios. The
720 * driver registers callbacks to access registers and the interpreter
721 * in the driver parses the tables and executes then to program specific
722 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
723 * atombios.h, and atom.c
727 * cail_pll_read - read PLL register
729 * @info: atom card_info pointer
730 * @reg: PLL register offset
732 * Provides a PLL register accessor for the atom interpreter (r4xx+).
733 * Returns the value of the PLL register.
735 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
737 struct radeon_device *rdev = info->dev->dev_private;
740 r = rdev->pll_rreg(rdev, reg);
745 * cail_pll_write - write PLL register
747 * @info: atom card_info pointer
748 * @reg: PLL register offset
749 * @val: value to write to the pll register
751 * Provides a PLL register accessor for the atom interpreter (r4xx+).
753 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
755 struct radeon_device *rdev = info->dev->dev_private;
757 rdev->pll_wreg(rdev, reg, val);
761 * cail_mc_read - read MC (Memory Controller) register
763 * @info: atom card_info pointer
764 * @reg: MC register offset
766 * Provides an MC register accessor for the atom interpreter (r4xx+).
767 * Returns the value of the MC register.
769 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
771 struct radeon_device *rdev = info->dev->dev_private;
774 r = rdev->mc_rreg(rdev, reg);
779 * cail_mc_write - write MC (Memory Controller) register
781 * @info: atom card_info pointer
782 * @reg: MC register offset
783 * @val: value to write to the pll register
785 * Provides a MC register accessor for the atom interpreter (r4xx+).
787 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
789 struct radeon_device *rdev = info->dev->dev_private;
791 rdev->mc_wreg(rdev, reg, val);
795 * cail_reg_write - write MMIO register
797 * @info: atom card_info pointer
798 * @reg: MMIO register offset
799 * @val: value to write to the pll register
801 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
803 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
805 struct radeon_device *rdev = info->dev->dev_private;
811 * cail_reg_read - read MMIO register
813 * @info: atom card_info pointer
814 * @reg: MMIO register offset
816 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
817 * Returns the value of the MMIO register.
819 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
821 struct radeon_device *rdev = info->dev->dev_private;
829 * cail_ioreg_write - write IO register
831 * @info: atom card_info pointer
832 * @reg: IO register offset
833 * @val: value to write to the pll register
835 * Provides a IO register accessor for the atom interpreter (r4xx+).
837 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
839 struct radeon_device *rdev = info->dev->dev_private;
841 WREG32_IO(reg*4, val);
845 * cail_ioreg_read - read IO register
847 * @info: atom card_info pointer
848 * @reg: IO register offset
850 * Provides an IO register accessor for the atom interpreter (r4xx+).
851 * Returns the value of the IO register.
853 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
855 struct radeon_device *rdev = info->dev->dev_private;
858 r = RREG32_IO(reg*4);
863 * radeon_atombios_init - init the driver info and callbacks for atombios
865 * @rdev: radeon_device pointer
867 * Initializes the driver info and register access callbacks for the
868 * ATOM interpreter (r4xx+).
869 * Returns 0 on sucess, -ENOMEM on failure.
870 * Called at driver startup.
872 int radeon_atombios_init(struct radeon_device *rdev)
874 struct card_info *atom_card_info =
875 kzalloc(sizeof(struct card_info), GFP_KERNEL);
880 rdev->mode_info.atom_card_info = atom_card_info;
881 atom_card_info->dev = rdev->ddev;
882 atom_card_info->reg_read = cail_reg_read;
883 atom_card_info->reg_write = cail_reg_write;
884 /* needed for iio ops */
886 atom_card_info->ioreg_read = cail_ioreg_read;
887 atom_card_info->ioreg_write = cail_ioreg_write;
889 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
890 atom_card_info->ioreg_read = cail_reg_read;
891 atom_card_info->ioreg_write = cail_reg_write;
893 atom_card_info->mc_read = cail_mc_read;
894 atom_card_info->mc_write = cail_mc_write;
895 atom_card_info->pll_read = cail_pll_read;
896 atom_card_info->pll_write = cail_pll_write;
898 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
899 if (!rdev->mode_info.atom_context) {
900 radeon_atombios_fini(rdev);
904 mutex_init(&rdev->mode_info.atom_context->mutex);
905 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
906 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
911 * radeon_atombios_fini - free the driver info and callbacks for atombios
913 * @rdev: radeon_device pointer
915 * Frees the driver info and register access callbacks for the ATOM
916 * interpreter (r4xx+).
917 * Called at driver shutdown.
919 void radeon_atombios_fini(struct radeon_device *rdev)
921 if (rdev->mode_info.atom_context) {
922 kfree(rdev->mode_info.atom_context->scratch);
924 kfree(rdev->mode_info.atom_context);
925 rdev->mode_info.atom_context = NULL;
926 kfree(rdev->mode_info.atom_card_info);
927 rdev->mode_info.atom_card_info = NULL;
932 * COMBIOS is the bios format prior to ATOM. It provides
933 * command tables similar to ATOM, but doesn't have a unified
934 * parser. See radeon_combios.c
938 * radeon_combios_init - init the driver info for combios
940 * @rdev: radeon_device pointer
942 * Initializes the driver info for combios (r1xx-r3xx).
943 * Returns 0 on sucess.
944 * Called at driver startup.
946 int radeon_combios_init(struct radeon_device *rdev)
948 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
953 * radeon_combios_fini - free the driver info for combios
955 * @rdev: radeon_device pointer
957 * Frees the driver info for combios (r1xx-r3xx).
958 * Called at driver shutdown.
960 void radeon_combios_fini(struct radeon_device *rdev)
964 /* if we get transitioned to only one device, take VGA back */
966 * radeon_vga_set_decode - enable/disable vga decode
968 * @cookie: radeon_device pointer
969 * @state: enable/disable vga decode
971 * Enable/disable vga decode (all asics).
972 * Returns VGA resource flags.
974 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
976 struct radeon_device *rdev = cookie;
977 radeon_vga_set_state(rdev, state);
979 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
980 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
982 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
986 * radeon_check_pot_argument - check that argument is a power of two
988 * @arg: value to check
990 * Validates that a certain argument is a power of two (all asics).
991 * Returns true if argument is valid.
993 static bool radeon_check_pot_argument(int arg)
995 return (arg & (arg - 1)) == 0;
999 * radeon_check_arguments - validate module params
1001 * @rdev: radeon_device pointer
1003 * Validates certain module parameters and updates
1004 * the associated values used by the driver (all asics).
1006 static void radeon_check_arguments(struct radeon_device *rdev)
1008 /* vramlimit must be a power of two */
1009 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1010 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1012 radeon_vram_limit = 0;
1015 if (radeon_gart_size == -1) {
1016 /* default to a larger gart size on newer asics */
1017 if (rdev->family >= CHIP_RV770)
1018 radeon_gart_size = 1024;
1020 radeon_gart_size = 512;
1022 /* gtt size must be power of two and greater or equal to 32M */
1023 if (radeon_gart_size < 32) {
1024 dev_warn(rdev->dev, "gart size (%d) too small\n",
1026 if (rdev->family >= CHIP_RV770)
1027 radeon_gart_size = 1024;
1029 radeon_gart_size = 512;
1030 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1031 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1033 if (rdev->family >= CHIP_RV770)
1034 radeon_gart_size = 1024;
1036 radeon_gart_size = 512;
1038 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1040 /* AGP mode can only be -1, 1, 2, 4, 8 */
1041 switch (radeon_agpmode) {
1050 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1051 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1058 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
1059 * needed for waking up.
1061 * @pdev: pci dev pointer
1063 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
1066 /* 6600m in a macbook pro */
1067 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1068 pdev->subsystem_device == 0x00e2) {
1069 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
1077 * radeon_switcheroo_set_state - set switcheroo state
1079 * @pdev: pci dev pointer
1080 * @state: vga switcheroo state
1082 * Callback for the switcheroo driver. Suspends or resumes the
1083 * the asics before or after it is powered up using ACPI methods.
1085 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1087 struct drm_device *dev = pci_get_drvdata(pdev);
1089 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1092 if (state == VGA_SWITCHEROO_ON) {
1093 unsigned d3_delay = dev->pdev->d3_delay;
1095 printk(KERN_INFO "radeon: switched on\n");
1096 /* don't suspend or resume card normally */
1097 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1099 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
1100 dev->pdev->d3_delay = 20;
1102 radeon_resume_kms(dev, true, true);
1104 dev->pdev->d3_delay = d3_delay;
1106 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1107 drm_kms_helper_poll_enable(dev);
1109 printk(KERN_INFO "radeon: switched off\n");
1110 drm_kms_helper_poll_disable(dev);
1111 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1112 radeon_suspend_kms(dev, true, true);
1113 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1118 * radeon_switcheroo_can_switch - see if switcheroo state can change
1120 * @pdev: pci dev pointer
1122 * Callback for the switcheroo driver. Check of the switcheroo
1123 * state can be changed.
1124 * Returns true if the state can be changed, false if not.
1126 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1128 struct drm_device *dev = pci_get_drvdata(pdev);
1131 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1132 * locking inversion with the driver load path. And the access here is
1133 * completely racy anyway. So don't bother with locking for now.
1135 return dev->open_count == 0;
1138 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1139 .set_gpu_state = radeon_switcheroo_set_state,
1141 .can_switch = radeon_switcheroo_can_switch,
1145 * radeon_device_init - initialize the driver
1147 * @rdev: radeon_device pointer
1148 * @pdev: drm dev pointer
1149 * @pdev: pci dev pointer
1150 * @flags: driver flags
1152 * Initializes the driver info and hw (all asics).
1153 * Returns 0 for success or an error on failure.
1154 * Called at driver startup.
1156 int radeon_device_init(struct radeon_device *rdev,
1157 struct drm_device *ddev,
1158 struct pci_dev *pdev,
1163 bool runtime = false;
1165 rdev->shutdown = false;
1166 rdev->dev = &pdev->dev;
1169 rdev->flags = flags;
1170 rdev->family = flags & RADEON_FAMILY_MASK;
1171 rdev->is_atom_bios = false;
1172 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1173 rdev->mc.gtt_size = 512 * 1024 * 1024;
1174 rdev->accel_working = false;
1175 /* set up ring ids */
1176 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1177 rdev->ring[i].idx = i;
1180 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1181 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1182 pdev->subsystem_vendor, pdev->subsystem_device);
1184 /* mutex initialization are all done here so we
1185 * can recall function without having locking issues */
1186 mutex_init(&rdev->ring_lock);
1187 mutex_init(&rdev->dc_hw_i2c_mutex);
1188 atomic_set(&rdev->ih.lock, 0);
1189 mutex_init(&rdev->gem.mutex);
1190 mutex_init(&rdev->pm.mutex);
1191 mutex_init(&rdev->gpu_clock_mutex);
1192 mutex_init(&rdev->srbm_mutex);
1193 init_rwsem(&rdev->pm.mclk_lock);
1194 init_rwsem(&rdev->exclusive_lock);
1195 init_waitqueue_head(&rdev->irq.vblank_queue);
1196 r = radeon_gem_init(rdev);
1200 /* Adjust VM size here.
1201 * Currently set to 4GB ((1 << 20) 4k pages).
1202 * Max GPUVM size for cayman and SI is 40 bits.
1204 rdev->vm_manager.max_pfn = 1 << 20;
1206 /* Set asic functions */
1207 r = radeon_asic_init(rdev);
1210 radeon_check_arguments(rdev);
1212 /* all of the newer IGP chips have an internal gart
1213 * However some rs4xx report as AGP, so remove that here.
1215 if ((rdev->family >= CHIP_RS400) &&
1216 (rdev->flags & RADEON_IS_IGP)) {
1217 rdev->flags &= ~RADEON_IS_AGP;
1220 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1221 radeon_agp_disable(rdev);
1224 /* Set the internal MC address mask
1225 * This is the max address of the GPU's
1226 * internal address space.
1228 if (rdev->family >= CHIP_CAYMAN)
1229 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1230 else if (rdev->family >= CHIP_CEDAR)
1231 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1233 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1235 /* set DMA mask + need_dma32 flags.
1236 * PCIE - can handle 40-bits.
1237 * IGP - can handle 40-bits
1238 * AGP - generally dma32 is safest
1239 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1241 rdev->need_dma32 = false;
1242 if (rdev->flags & RADEON_IS_AGP)
1243 rdev->need_dma32 = true;
1244 if ((rdev->flags & RADEON_IS_PCI) &&
1245 (rdev->family <= CHIP_RS740))
1246 rdev->need_dma32 = true;
1248 dma_bits = rdev->need_dma32 ? 32 : 40;
1249 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1251 rdev->need_dma32 = true;
1253 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1255 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1257 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1258 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1261 /* Registers mapping */
1262 /* TODO: block userspace mapping of io register */
1263 spin_lock_init(&rdev->mmio_idx_lock);
1264 spin_lock_init(&rdev->smc_idx_lock);
1265 spin_lock_init(&rdev->pll_idx_lock);
1266 spin_lock_init(&rdev->mc_idx_lock);
1267 spin_lock_init(&rdev->pcie_idx_lock);
1268 spin_lock_init(&rdev->pciep_idx_lock);
1269 spin_lock_init(&rdev->pif_idx_lock);
1270 spin_lock_init(&rdev->cg_idx_lock);
1271 spin_lock_init(&rdev->uvd_idx_lock);
1272 spin_lock_init(&rdev->rcu_idx_lock);
1273 spin_lock_init(&rdev->didt_idx_lock);
1274 spin_lock_init(&rdev->end_idx_lock);
1275 if (rdev->family >= CHIP_BONAIRE) {
1276 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1277 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1279 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1280 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1282 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1283 if (rdev->rmmio == NULL) {
1286 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1287 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1289 /* doorbell bar mapping */
1290 if (rdev->family >= CHIP_BONAIRE)
1291 radeon_doorbell_init(rdev);
1293 /* io port mapping */
1294 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1295 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1296 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1297 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1301 if (rdev->rio_mem == NULL)
1302 DRM_ERROR("Unable to find PCI I/O BAR\n");
1304 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1305 /* this will fail for cards that aren't VGA class devices, just
1307 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1309 if (rdev->flags & RADEON_IS_PX)
1311 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1313 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1315 r = radeon_init(rdev);
1319 r = radeon_ib_ring_tests(rdev);
1321 DRM_ERROR("ib ring test failed (%d).\n", r);
1323 r = radeon_gem_debugfs_init(rdev);
1325 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1328 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1329 /* Acceleration not working on AGP card try again
1330 * with fallback to PCI or PCIE GART
1332 radeon_asic_reset(rdev);
1334 radeon_agp_disable(rdev);
1335 r = radeon_init(rdev);
1340 if ((radeon_testing & 1)) {
1341 if (rdev->accel_working)
1342 radeon_test_moves(rdev);
1344 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1346 if ((radeon_testing & 2)) {
1347 if (rdev->accel_working)
1348 radeon_test_syncing(rdev);
1350 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1352 if (radeon_benchmarking) {
1353 if (rdev->accel_working)
1354 radeon_benchmark(rdev, radeon_benchmarking);
1356 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1361 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1364 * radeon_device_fini - tear down the driver
1366 * @rdev: radeon_device pointer
1368 * Tear down the driver info (all asics).
1369 * Called at driver shutdown.
1371 void radeon_device_fini(struct radeon_device *rdev)
1373 DRM_INFO("radeon: finishing device.\n");
1374 rdev->shutdown = true;
1375 /* evict vram memory */
1376 radeon_bo_evict_vram(rdev);
1378 vga_switcheroo_unregister_client(rdev->pdev);
1379 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1381 pci_iounmap(rdev->pdev, rdev->rio_mem);
1382 rdev->rio_mem = NULL;
1383 iounmap(rdev->rmmio);
1385 if (rdev->family >= CHIP_BONAIRE)
1386 radeon_doorbell_fini(rdev);
1387 radeon_debugfs_remove_files(rdev);
1395 * radeon_suspend_kms - initiate device suspend
1397 * @pdev: drm dev pointer
1398 * @state: suspend state
1400 * Puts the hw in the suspend state (all asics).
1401 * Returns 0 for success or an error on failure.
1402 * Called at driver suspend.
1404 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1406 struct radeon_device *rdev;
1407 struct drm_crtc *crtc;
1408 struct drm_connector *connector;
1410 bool force_completion = false;
1412 if (dev == NULL || dev->dev_private == NULL) {
1416 rdev = dev->dev_private;
1418 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1421 drm_kms_helper_poll_disable(dev);
1423 /* turn off display hw */
1424 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1425 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1428 /* unpin the front buffers */
1429 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1430 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1431 struct radeon_bo *robj;
1433 if (rfb == NULL || rfb->obj == NULL) {
1436 robj = gem_to_radeon_bo(rfb->obj);
1437 /* don't unpin kernel fb objects */
1438 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1439 r = radeon_bo_reserve(robj, false);
1441 radeon_bo_unpin(robj);
1442 radeon_bo_unreserve(robj);
1446 /* evict vram memory */
1447 radeon_bo_evict_vram(rdev);
1449 /* wait for gpu to finish processing current batch */
1450 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1451 r = radeon_fence_wait_empty(rdev, i);
1453 /* delay GPU reset to resume */
1454 force_completion = true;
1457 if (force_completion) {
1458 radeon_fence_driver_force_completion(rdev);
1461 radeon_save_bios_scratch_regs(rdev);
1463 radeon_suspend(rdev);
1464 radeon_hpd_fini(rdev);
1465 /* evict remaining vram memory */
1466 radeon_bo_evict_vram(rdev);
1468 radeon_agp_suspend(rdev);
1470 pci_save_state(dev->pdev);
1472 /* Shut down the device */
1473 pci_disable_device(dev->pdev);
1474 pci_set_power_state(dev->pdev, PCI_D3hot);
1479 radeon_fbdev_set_suspend(rdev, 1);
1486 * radeon_resume_kms - initiate device resume
1488 * @pdev: drm dev pointer
1490 * Bring the hw back to operating state (all asics).
1491 * Returns 0 for success or an error on failure.
1492 * Called at driver resume.
1494 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1496 struct drm_connector *connector;
1497 struct radeon_device *rdev = dev->dev_private;
1500 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1507 pci_set_power_state(dev->pdev, PCI_D0);
1508 pci_restore_state(dev->pdev);
1509 if (pci_enable_device(dev->pdev)) {
1515 /* resume AGP if in use */
1516 radeon_agp_resume(rdev);
1517 radeon_resume(rdev);
1519 r = radeon_ib_ring_tests(rdev);
1521 DRM_ERROR("ib ring test failed (%d).\n", r);
1523 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1524 /* do dpm late init */
1525 r = radeon_pm_late_init(rdev);
1527 rdev->pm.dpm_enabled = false;
1528 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1531 /* resume old pm late */
1532 radeon_pm_resume(rdev);
1535 radeon_restore_bios_scratch_regs(rdev);
1537 /* init dig PHYs, disp eng pll */
1538 if (rdev->is_atom_bios) {
1539 radeon_atom_encoder_init(rdev);
1540 radeon_atom_disp_eng_pll_init(rdev);
1541 /* turn on the BL */
1542 if (rdev->mode_info.bl_encoder) {
1543 u8 bl_level = radeon_get_backlight_level(rdev,
1544 rdev->mode_info.bl_encoder);
1545 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1549 /* reset hpd state */
1550 radeon_hpd_init(rdev);
1551 /* blat the mode back in */
1553 drm_helper_resume_force_mode(dev);
1554 /* turn on display hw */
1555 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1556 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1560 drm_kms_helper_poll_enable(dev);
1562 /* set the power state here in case we are a PX system or headless */
1563 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1564 radeon_pm_compute_clocks(rdev);
1567 radeon_fbdev_set_suspend(rdev, 0);
1575 * radeon_gpu_reset - reset the asic
1577 * @rdev: radeon device pointer
1579 * Attempt the reset the GPU if it has hung (all asics).
1580 * Returns 0 for success or an error on failure.
1582 int radeon_gpu_reset(struct radeon_device *rdev)
1584 unsigned ring_sizes[RADEON_NUM_RINGS];
1585 uint32_t *ring_data[RADEON_NUM_RINGS];
1592 down_write(&rdev->exclusive_lock);
1594 if (!rdev->needs_reset) {
1595 up_write(&rdev->exclusive_lock);
1599 rdev->needs_reset = false;
1601 radeon_save_bios_scratch_regs(rdev);
1603 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1604 radeon_pm_suspend(rdev);
1605 radeon_suspend(rdev);
1607 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1608 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1610 if (ring_sizes[i]) {
1612 dev_info(rdev->dev, "Saved %d dwords of commands "
1613 "on ring %d.\n", ring_sizes[i], i);
1618 r = radeon_asic_reset(rdev);
1620 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1621 radeon_resume(rdev);
1624 radeon_restore_bios_scratch_regs(rdev);
1627 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1628 radeon_ring_restore(rdev, &rdev->ring[i],
1629 ring_sizes[i], ring_data[i]);
1631 ring_data[i] = NULL;
1634 r = radeon_ib_ring_tests(rdev);
1636 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1639 radeon_suspend(rdev);
1644 radeon_fence_driver_force_completion(rdev);
1645 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1646 kfree(ring_data[i]);
1650 radeon_pm_resume(rdev);
1651 drm_helper_resume_force_mode(rdev->ddev);
1653 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1655 /* bad news, how to tell it to userspace ? */
1656 dev_info(rdev->dev, "GPU reset failed\n");
1659 up_write(&rdev->exclusive_lock);
1667 int radeon_debugfs_add_files(struct radeon_device *rdev,
1668 struct drm_info_list *files,
1673 for (i = 0; i < rdev->debugfs_count; i++) {
1674 if (rdev->debugfs[i].files == files) {
1675 /* Already registered */
1680 i = rdev->debugfs_count + 1;
1681 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1682 DRM_ERROR("Reached maximum number of debugfs components.\n");
1683 DRM_ERROR("Report so we increase "
1684 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1687 rdev->debugfs[rdev->debugfs_count].files = files;
1688 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1689 rdev->debugfs_count = i;
1690 #if defined(CONFIG_DEBUG_FS)
1691 drm_debugfs_create_files(files, nfiles,
1692 rdev->ddev->control->debugfs_root,
1693 rdev->ddev->control);
1694 drm_debugfs_create_files(files, nfiles,
1695 rdev->ddev->primary->debugfs_root,
1696 rdev->ddev->primary);
1701 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1703 #if defined(CONFIG_DEBUG_FS)
1706 for (i = 0; i < rdev->debugfs_count; i++) {
1707 drm_debugfs_remove_files(rdev->debugfs[i].files,
1708 rdev->debugfs[i].num_files,
1709 rdev->ddev->control);
1710 drm_debugfs_remove_files(rdev->debugfs[i].files,
1711 rdev->debugfs[i].num_files,
1712 rdev->ddev->primary);
1717 #if defined(CONFIG_DEBUG_FS)
1718 int radeon_debugfs_init(struct drm_minor *minor)
1723 void radeon_debugfs_cleanup(struct drm_minor *minor)