2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/radeon_drm.h>
32 #include "radeon_reg.h"
34 #include "radeon_asic.h"
38 * Clear GPU surface registers.
40 static void radeon_surface_init(struct radeon_device *rdev)
42 /* FIXME: check this out */
43 if (rdev->family < CHIP_R600) {
46 for (i = 0; i < 8; i++) {
47 WREG32(RADEON_SURFACE0_INFO +
48 i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
55 * GPU scratch registers helpers function.
57 static void radeon_scratch_init(struct radeon_device *rdev)
61 /* FIXME: check this out */
62 if (rdev->family < CHIP_R300) {
63 rdev->scratch.num_reg = 5;
65 rdev->scratch.num_reg = 7;
67 for (i = 0; i < rdev->scratch.num_reg; i++) {
68 rdev->scratch.free[i] = true;
69 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
73 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
77 for (i = 0; i < rdev->scratch.num_reg; i++) {
78 if (rdev->scratch.free[i]) {
79 rdev->scratch.free[i] = false;
80 *reg = rdev->scratch.reg[i];
87 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
91 for (i = 0; i < rdev->scratch.num_reg; i++) {
92 if (rdev->scratch.reg[i] == reg) {
93 rdev->scratch.free[i] = true;
100 * MC common functions
102 int radeon_mc_setup(struct radeon_device *rdev)
106 /* Some chips have an "issue" with the memory controller, the
107 * location must be aligned to the size. We just align it down,
108 * too bad if we walk over the top of system memory, we don't
109 * use DMA without a remapped anyway.
110 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
112 /* FGLRX seems to setup like this, VRAM a 0, then GART.
115 * Note: from R6xx the address space is 40bits but here we only
116 * use 32bits (still have to see a card which would exhaust 4G
119 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
120 /* vram location was already setup try to put gtt after
122 tmp = rdev->mc.vram_location + rdev->mc.vram_size;
123 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
124 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
125 rdev->mc.gtt_location = tmp;
127 if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
128 printk(KERN_ERR "[drm] GTT too big to fit "
129 "before or after vram location.\n");
132 rdev->mc.gtt_location = 0;
134 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
135 /* gtt location was already setup try to put vram before
137 if (rdev->mc.vram_size < rdev->mc.gtt_location) {
138 rdev->mc.vram_location = 0;
140 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
141 tmp += (rdev->mc.vram_size - 1);
142 tmp &= ~(rdev->mc.vram_size - 1);
143 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
144 rdev->mc.vram_location = tmp;
146 printk(KERN_ERR "[drm] vram too big to fit "
147 "before or after GTT location.\n");
152 rdev->mc.vram_location = 0;
153 rdev->mc.gtt_location = rdev->mc.vram_size;
155 DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
156 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
157 rdev->mc.vram_location,
158 rdev->mc.vram_location + rdev->mc.vram_size - 1);
159 DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
160 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
161 rdev->mc.gtt_location,
162 rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
168 * GPU helpers function.
170 static bool radeon_card_posted(struct radeon_device *rdev)
174 /* first check CRTCs */
175 if (ASIC_IS_AVIVO(rdev)) {
176 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
177 RREG32(AVIVO_D2CRTC_CONTROL);
178 if (reg & AVIVO_CRTC_EN) {
182 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
183 RREG32(RADEON_CRTC2_GEN_CNTL);
184 if (reg & RADEON_CRTC_EN) {
189 /* then check MEM_SIZE, in case the crtcs are off */
190 if (rdev->family >= CHIP_R600)
191 reg = RREG32(R600_CONFIG_MEMSIZE);
193 reg = RREG32(RADEON_CONFIG_MEMSIZE);
204 * Registers accessors functions.
206 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
208 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
213 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
215 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
220 void radeon_register_accessor_init(struct radeon_device *rdev)
222 rdev->mm_rreg = &r100_mm_rreg;
223 rdev->mm_wreg = &r100_mm_wreg;
224 rdev->mc_rreg = &radeon_invalid_rreg;
225 rdev->mc_wreg = &radeon_invalid_wreg;
226 rdev->pll_rreg = &radeon_invalid_rreg;
227 rdev->pll_wreg = &radeon_invalid_wreg;
228 rdev->pcie_rreg = &radeon_invalid_rreg;
229 rdev->pcie_wreg = &radeon_invalid_wreg;
230 rdev->pciep_rreg = &radeon_invalid_rreg;
231 rdev->pciep_wreg = &radeon_invalid_wreg;
233 /* Don't change order as we are overridding accessor. */
234 if (rdev->family < CHIP_RV515) {
235 rdev->pcie_rreg = &rv370_pcie_rreg;
236 rdev->pcie_wreg = &rv370_pcie_wreg;
238 if (rdev->family >= CHIP_RV515) {
239 rdev->pcie_rreg = &rv515_pcie_rreg;
240 rdev->pcie_wreg = &rv515_pcie_wreg;
242 /* FIXME: not sure here */
243 if (rdev->family <= CHIP_R580) {
244 rdev->pll_rreg = &r100_pll_rreg;
245 rdev->pll_wreg = &r100_pll_wreg;
247 if (rdev->family >= CHIP_RV515) {
248 rdev->mc_rreg = &rv515_mc_rreg;
249 rdev->mc_wreg = &rv515_mc_wreg;
251 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
252 rdev->mc_rreg = &rs400_mc_rreg;
253 rdev->mc_wreg = &rs400_mc_wreg;
255 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
256 rdev->mc_rreg = &rs690_mc_rreg;
257 rdev->mc_wreg = &rs690_mc_wreg;
259 if (rdev->family == CHIP_RS600) {
260 rdev->mc_rreg = &rs600_mc_rreg;
261 rdev->mc_wreg = &rs600_mc_wreg;
263 if (rdev->family >= CHIP_R600) {
264 rdev->pciep_rreg = &r600_pciep_rreg;
265 rdev->pciep_wreg = &r600_pciep_wreg;
273 int radeon_asic_init(struct radeon_device *rdev)
275 radeon_register_accessor_init(rdev);
276 switch (rdev->family) {
286 rdev->asic = &r100_asic;
292 rdev->asic = &r300_asic;
297 rdev->asic = &r420_asic;
301 rdev->asic = &rs400_asic;
304 rdev->asic = &rs600_asic;
308 rdev->asic = &rs690_asic;
311 rdev->asic = &rv515_asic;
318 rdev->asic = &r520_asic;
331 /* FIXME: not supported yet */
339 * Wrapper around modesetting bits.
341 int radeon_clocks_init(struct radeon_device *rdev)
345 radeon_get_clock_info(rdev->ddev);
346 r = radeon_static_clocks_init(rdev->ddev);
350 DRM_INFO("Clocks initialized !\n");
354 void radeon_clocks_fini(struct radeon_device *rdev)
358 /* ATOM accessor methods */
359 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
361 struct radeon_device *rdev = info->dev->dev_private;
364 r = rdev->pll_rreg(rdev, reg);
368 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
370 struct radeon_device *rdev = info->dev->dev_private;
372 rdev->pll_wreg(rdev, reg, val);
375 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
377 struct radeon_device *rdev = info->dev->dev_private;
380 r = rdev->mc_rreg(rdev, reg);
384 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
386 struct radeon_device *rdev = info->dev->dev_private;
388 rdev->mc_wreg(rdev, reg, val);
391 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
393 struct radeon_device *rdev = info->dev->dev_private;
398 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
400 struct radeon_device *rdev = info->dev->dev_private;
407 static struct card_info atom_card_info = {
409 .reg_read = cail_reg_read,
410 .reg_write = cail_reg_write,
411 .mc_read = cail_mc_read,
412 .mc_write = cail_mc_write,
413 .pll_read = cail_pll_read,
414 .pll_write = cail_pll_write,
417 int radeon_atombios_init(struct radeon_device *rdev)
419 atom_card_info.dev = rdev->ddev;
420 rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
421 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
425 void radeon_atombios_fini(struct radeon_device *rdev)
427 kfree(rdev->mode_info.atom_context);
430 int radeon_combios_init(struct radeon_device *rdev)
432 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
436 void radeon_combios_fini(struct radeon_device *rdev)
440 int radeon_modeset_init(struct radeon_device *rdev);
441 void radeon_modeset_fini(struct radeon_device *rdev);
447 int radeon_device_init(struct radeon_device *rdev,
448 struct drm_device *ddev,
449 struct pci_dev *pdev,
455 DRM_INFO("radeon: Initializing kernel modesetting.\n");
456 rdev->shutdown = false;
460 rdev->family = flags & RADEON_FAMILY_MASK;
461 rdev->is_atom_bios = false;
462 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
463 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
464 rdev->gpu_lockup = false;
465 /* mutex initialization are all done here so we
466 * can recall function without having locking issues */
467 mutex_init(&rdev->cs_mutex);
468 mutex_init(&rdev->ib_pool.mutex);
469 mutex_init(&rdev->cp.mutex);
470 rwlock_init(&rdev->fence_drv.lock);
472 if (radeon_agpmode == -1) {
473 rdev->flags &= ~RADEON_IS_AGP;
474 if (rdev->family > CHIP_RV515 ||
475 rdev->family == CHIP_RV380 ||
476 rdev->family == CHIP_RV410 ||
477 rdev->family == CHIP_R423) {
478 DRM_INFO("Forcing AGP to PCIE mode\n");
479 rdev->flags |= RADEON_IS_PCIE;
481 DRM_INFO("Forcing AGP to PCI mode\n");
482 rdev->flags |= RADEON_IS_PCI;
486 /* Set asic functions */
487 r = radeon_asic_init(rdev);
491 r = radeon_init(rdev);
496 /* set DMA mask + need_dma32 flags.
497 * PCIE - can handle 40-bits.
498 * IGP - can handle 40-bits (in theory)
499 * AGP - generally dma32 is safest
502 rdev->need_dma32 = false;
503 if (rdev->flags & RADEON_IS_AGP)
504 rdev->need_dma32 = true;
505 if (rdev->flags & RADEON_IS_PCI)
506 rdev->need_dma32 = true;
508 dma_bits = rdev->need_dma32 ? 32 : 40;
509 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
511 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
514 /* Registers mapping */
515 /* TODO: block userspace mapping of io register */
516 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
517 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
518 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
519 if (rdev->rmmio == NULL) {
522 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
523 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
525 /* Setup errata flags */
527 /* Initialize scratch registers */
528 radeon_scratch_init(rdev);
529 /* Initialize surface registers */
530 radeon_surface_init(rdev);
532 /* TODO: disable VGA need to use VGA request */
534 if (!radeon_get_bios(rdev)) {
535 if (ASIC_IS_AVIVO(rdev))
538 if (rdev->is_atom_bios) {
539 r = radeon_atombios_init(rdev);
544 r = radeon_combios_init(rdev);
549 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
550 if (radeon_gpu_reset(rdev)) {
551 /* FIXME: what do we want to do here ? */
553 /* check if cards are posted or not */
554 if (!radeon_card_posted(rdev) && rdev->bios) {
555 DRM_INFO("GPU not posted. posting now...\n");
556 if (rdev->is_atom_bios) {
557 atom_asic_init(rdev->mode_info.atom_context);
559 radeon_combios_asic_init(rdev->ddev);
562 /* Get vram informations */
563 radeon_vram_info(rdev);
564 /* Device is severly broken if aper size > vram size.
565 * for RN50/M6/M7 - Novell bug 204882 ?
567 if (rdev->mc.vram_size < rdev->mc.aper_size) {
568 rdev->mc.vram_size = rdev->mc.aper_size;
570 /* Add an MTRR for the VRAM */
571 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
572 MTRR_TYPE_WRCOMB, 1);
573 DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
574 rdev->mc.vram_size >> 20,
575 (unsigned)rdev->mc.aper_size >> 20);
576 DRM_INFO("RAM width %dbits %cDR\n",
577 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
578 /* Initialize clocks */
579 r = radeon_clocks_init(rdev);
583 /* Initialize memory controller (also test AGP) */
584 r = radeon_mc_init(rdev);
589 r = radeon_fence_driver_init(rdev);
593 r = radeon_irq_kms_init(rdev);
598 r = radeon_object_init(rdev);
602 /* Initialize GART (initialize after TTM so we can allocate
603 * memory through TTM but finalize after TTM) */
604 r = radeon_gart_enable(rdev);
606 r = radeon_gem_init(rdev);
611 r = radeon_cp_init(rdev, 1024 * 1024);
614 r = radeon_wb_init(rdev);
616 DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
621 r = radeon_ib_pool_init(rdev);
623 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
628 r = radeon_ib_test(rdev);
630 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
635 r = radeon_modeset_init(rdev);
640 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
642 if (radeon_benchmarking) {
643 radeon_benchmark(rdev);
648 void radeon_device_fini(struct radeon_device *rdev)
650 if (rdev == NULL || rdev->rmmio == NULL) {
653 DRM_INFO("radeon: finishing device.\n");
654 rdev->shutdown = true;
655 /* Order matter so becarefull if you rearrange anythings */
656 radeon_modeset_fini(rdev);
657 radeon_ib_pool_fini(rdev);
658 radeon_cp_fini(rdev);
659 radeon_wb_fini(rdev);
660 radeon_gem_fini(rdev);
661 radeon_object_fini(rdev);
662 /* mc_fini must be after object_fini */
663 radeon_mc_fini(rdev);
665 radeon_agp_fini(rdev);
667 radeon_irq_kms_fini(rdev);
668 radeon_fence_driver_fini(rdev);
669 radeon_clocks_fini(rdev);
670 if (rdev->is_atom_bios) {
671 radeon_atombios_fini(rdev);
673 radeon_combios_fini(rdev);
677 iounmap(rdev->rmmio);
685 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
687 struct radeon_device *rdev = dev->dev_private;
688 struct drm_crtc *crtc;
690 if (dev == NULL || rdev == NULL) {
693 if (state.event == PM_EVENT_PRETHAW) {
696 /* unpin the front buffers */
697 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
698 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
699 struct radeon_object *robj;
701 if (rfb == NULL || rfb->obj == NULL) {
704 robj = rfb->obj->driver_private;
705 if (robj != rdev->fbdev_robj) {
706 radeon_object_unpin(robj);
709 /* evict vram memory */
710 radeon_object_evict_vram(rdev);
711 /* wait for gpu to finish processing current batch */
712 radeon_fence_wait_last(rdev);
714 radeon_cp_disable(rdev);
715 radeon_gart_disable(rdev);
717 /* evict remaining vram memory */
718 radeon_object_evict_vram(rdev);
720 rdev->irq.sw_int = false;
721 radeon_irq_set(rdev);
723 pci_save_state(dev->pdev);
724 if (state.event == PM_EVENT_SUSPEND) {
725 /* Shut down the device */
726 pci_disable_device(dev->pdev);
727 pci_set_power_state(dev->pdev, PCI_D3hot);
729 acquire_console_sem();
730 fb_set_suspend(rdev->fbdev_info, 1);
731 release_console_sem();
735 int radeon_resume_kms(struct drm_device *dev)
737 struct radeon_device *rdev = dev->dev_private;
740 acquire_console_sem();
741 pci_set_power_state(dev->pdev, PCI_D0);
742 pci_restore_state(dev->pdev);
743 if (pci_enable_device(dev->pdev)) {
744 release_console_sem();
747 pci_set_master(dev->pdev);
748 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
749 if (radeon_gpu_reset(rdev)) {
750 /* FIXME: what do we want to do here ? */
753 if (rdev->is_atom_bios) {
754 atom_asic_init(rdev->mode_info.atom_context);
756 radeon_combios_asic_init(rdev->ddev);
758 /* Initialize clocks */
759 r = radeon_clocks_init(rdev);
761 release_console_sem();
765 rdev->irq.sw_int = true;
766 radeon_irq_set(rdev);
767 /* Initialize GPU Memory Controller */
768 r = radeon_mc_init(rdev);
772 r = radeon_gart_enable(rdev);
776 r = radeon_cp_init(rdev, rdev->cp.ring_size);
781 fb_set_suspend(rdev->fbdev_info, 0);
782 release_console_sem();
784 /* blat the mode back in */
785 drm_helper_resume_force_mode(dev);
793 struct radeon_debugfs {
794 struct drm_info_list *files;
797 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
798 static unsigned _radeon_debugfs_count = 0;
800 int radeon_debugfs_add_files(struct radeon_device *rdev,
801 struct drm_info_list *files,
806 for (i = 0; i < _radeon_debugfs_count; i++) {
807 if (_radeon_debugfs[i].files == files) {
808 /* Already registered */
812 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
813 DRM_ERROR("Reached maximum number of debugfs files.\n");
814 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
817 _radeon_debugfs[_radeon_debugfs_count].files = files;
818 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
819 _radeon_debugfs_count++;
820 #if defined(CONFIG_DEBUG_FS)
821 drm_debugfs_create_files(files, nfiles,
822 rdev->ddev->control->debugfs_root,
823 rdev->ddev->control);
824 drm_debugfs_create_files(files, nfiles,
825 rdev->ddev->primary->debugfs_root,
826 rdev->ddev->primary);
831 #if defined(CONFIG_DEBUG_FS)
832 int radeon_debugfs_init(struct drm_minor *minor)
837 void radeon_debugfs_cleanup(struct drm_minor *minor)
841 for (i = 0; i < _radeon_debugfs_count; i++) {
842 drm_debugfs_remove_files(_radeon_debugfs[i].files,
843 _radeon_debugfs[i].num_files, minor);