drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_edid.h>
  36
  37 #include <linux/gcd.h>
  38
  39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  40 {
  41         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  42         struct drm_device *dev = crtc->dev;
  43         struct radeon_device *rdev = dev->dev_private;
  44         int i;
  45
  46         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  47         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  48
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  52
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  56
  57         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  58         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  59         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  60
  61         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  62         for (i = 0; i < 256; i++) {
  63                 WREG32(AVIVO_DC_LUT_30_COLOR,
  64                              (radeon_crtc->lut_r[i] << 20) |
  65                              (radeon_crtc->lut_g[i] << 10) |
  66                              (radeon_crtc->lut_b[i] << 0));
  67         }
  68
  69         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  70 }
  71
  72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  73 {
  74         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  75         struct drm_device *dev = crtc->dev;
  76         struct radeon_device *rdev = dev->dev_private;
  77         int i;
  78
  79         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  80         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  81
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  85
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  91         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  92
  93         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  94         for (i = 0; i < 256; i++) {
  95                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  96                        (radeon_crtc->lut_r[i] << 20) |
  97                        (radeon_crtc->lut_g[i] << 10) |
  98                        (radeon_crtc->lut_b[i] << 0));
  99         }
 100 }
 101
 102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 103 {
 104         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 105         struct drm_device *dev = crtc->dev;
 106         struct radeon_device *rdev = dev->dev_private;
 107         int i;
 108
 109         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 110
 111         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 112                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 113                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 114         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 115                NI_GRPH_PRESCALE_BYPASS);
 116         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 117                NI_OVL_PRESCALE_BYPASS);
 118         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 119                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 120                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 121
 122         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 123
 124         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 125         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 127
 128         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 129         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 133         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 134
 135         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 136         for (i = 0; i < 256; i++) {
 137                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 138                        (radeon_crtc->lut_r[i] << 20) |
 139                        (radeon_crtc->lut_g[i] << 10) |
 140                        (radeon_crtc->lut_b[i] << 0));
 141         }
 142
 143         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 144                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 145                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 146                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 148         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 150                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 151         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 153                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 154         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 155                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 156                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 157         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 158         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 159         if (ASIC_IS_DCE8(rdev)) {
 160                 /* XXX this only needs to be programmed once per crtc at startup,
 161                  * not sure where the best place for it is
 162                  */
 163                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 164                        CIK_CURSOR_ALPHA_BLND_ENA);
 165         }
 166 }
 167
 168 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 169 {
 170         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 171         struct drm_device *dev = crtc->dev;
 172         struct radeon_device *rdev = dev->dev_private;
 173         int i;
 174         uint32_t dac2_cntl;
 175
 176         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 177         if (radeon_crtc->crtc_id == 0)
 178                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 179         else
 180                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 181         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 182
 183         WREG8(RADEON_PALETTE_INDEX, 0);
 184         for (i = 0; i < 256; i++) {
 185                 WREG32(RADEON_PALETTE_30_DATA,
 186                              (radeon_crtc->lut_r[i] << 20) |
 187                              (radeon_crtc->lut_g[i] << 10) |
 188                              (radeon_crtc->lut_b[i] << 0));
 189         }
 190 }
 191
 192 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 193 {
 194         struct drm_device *dev = crtc->dev;
 195         struct radeon_device *rdev = dev->dev_private;
 196
 197         if (!crtc->enabled)
 198                 return;
 199
 200         if (ASIC_IS_DCE5(rdev))
 201                 dce5_crtc_load_lut(crtc);
 202         else if (ASIC_IS_DCE4(rdev))
 203                 dce4_crtc_load_lut(crtc);
 204         else if (ASIC_IS_AVIVO(rdev))
 205                 avivo_crtc_load_lut(crtc);
 206         else
 207                 legacy_crtc_load_lut(crtc);
 208 }
 209
 210 /** Sets the color ramps on behalf of fbcon */
 211 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 212                               u16 blue, int regno)
 213 {
 214         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 215
 216         radeon_crtc->lut_r[regno] = red >> 6;
 217         radeon_crtc->lut_g[regno] = green >> 6;
 218         radeon_crtc->lut_b[regno] = blue >> 6;
 219 }
 220
 221 /** Gets the color ramps on behalf of fbcon */
 222 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 223                               u16 *blue, int regno)
 224 {
 225         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 226
 227         *red = radeon_crtc->lut_r[regno] << 6;
 228         *green = radeon_crtc->lut_g[regno] << 6;
 229         *blue = radeon_crtc->lut_b[regno] << 6;
 230 }
 231
 232 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 233                                   u16 *blue, uint32_t start, uint32_t size)
 234 {
 235         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 236         int end = (start + size > 256) ? 256 : start + size, i;
 237
 238         /* userspace palettes are always correct as is */
 239         for (i = start; i < end; i++) {
 240                 radeon_crtc->lut_r[i] = red[i] >> 6;
 241                 radeon_crtc->lut_g[i] = green[i] >> 6;
 242                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 243         }
 244         radeon_crtc_load_lut(crtc);
 245 }
 246
 247 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 248 {
 249         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 250
 251         drm_crtc_cleanup(crtc);
 252         kfree(radeon_crtc);
 253 }
 254
 255 /*
 256  * Handle unpin events outside the interrupt handler proper.
 257  */
 258 static void radeon_unpin_work_func(struct work_struct *__work)
 259 {
 260         struct radeon_unpin_work *work =
 261                 container_of(__work, struct radeon_unpin_work, work);
 262         int r;
 263
 264         /* unpin of the old buffer */
 265         r = radeon_bo_reserve(work->old_rbo, false);
 266         if (likely(r == 0)) {
 267                 r = radeon_bo_unpin(work->old_rbo);
 268                 if (unlikely(r != 0)) {
 269                         DRM_ERROR("failed to unpin buffer after flip\n");
 270                 }
 271                 radeon_bo_unreserve(work->old_rbo);
 272         } else
 273                 DRM_ERROR("failed to reserve buffer after flip\n");
 274
 275         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 276         kfree(work);
 277 }
 278
 279 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 280 {
 281         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 282         struct radeon_unpin_work *work;
 283         unsigned long flags;
 284         u32 update_pending;
 285         int vpos, hpos;
 286
 287         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 288         work = radeon_crtc->unpin_work;
 289         if (work == NULL ||
 290             (work->fence && !radeon_fence_signaled(work->fence))) {
 291                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 292                 return;
 293         }
 294         /* New pageflip, or just completion of a previous one? */
 295         if (!radeon_crtc->deferred_flip_completion) {
 296                 /* do the flip (mmio) */
 297                 radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 298                 update_pending = radeon_page_flip_pending(rdev, crtc_id);
 299         } else {
 300                 /* This is just a completion of a flip queued in crtc
 301                  * at last invocation. Make sure we go directly to
 302                  * completion routine.
 303                  */
 304                 update_pending = 0;
 305                 radeon_crtc->deferred_flip_completion = 0;
 306         }
 307
 308         /* Has the pageflip already completed in crtc, or is it certain
 309          * to complete in this vblank?
 310          */
 311         if (update_pending &&
 312             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
 313                                                                &vpos, &hpos, NULL, NULL)) &&
 314             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 315              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 316                 /* crtc didn't flip in this target vblank interval,
 317                  * but flip is pending in crtc. Based on the current
 318                  * scanout position we know that the current frame is
 319                  * (nearly) complete and the flip will (likely)
 320                  * complete before the start of the next frame.
 321                  */
 322                 update_pending = 0;
 323         }
 324         if (update_pending) {
 325                 /* crtc didn't flip in this target vblank interval,
 326                  * but flip is pending in crtc. It will complete it
 327                  * in next vblank interval, so complete the flip at
 328                  * next vblank irq.
 329                  */
 330                 radeon_crtc->deferred_flip_completion = 1;
 331                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 332                 return;
 333         }
 334
 335         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 336         radeon_crtc->unpin_work = NULL;
 337
 338         /* wakeup userspace */
 339         if (work->event)
 340                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 341
 342         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 343
 344         radeon_fence_unref(&work->fence);
 345         radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id);
 346         schedule_work(&work->work);
 347 }
 348
 349 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 350                                  struct drm_framebuffer *fb,
 351                                  struct drm_pending_vblank_event *event,
 352                                  uint32_t page_flip_flags)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         struct radeon_device *rdev = dev->dev_private;
 356         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 357         struct radeon_framebuffer *old_radeon_fb;
 358         struct radeon_framebuffer *new_radeon_fb;
 359         struct drm_gem_object *obj;
 360         struct radeon_bo *rbo;
 361         struct radeon_unpin_work *work;
 362         unsigned long flags;
 363         u32 tiling_flags, pitch_pixels;
 364         u64 base;
 365         int r;
 366
 367         work = kzalloc(sizeof *work, GFP_KERNEL);
 368         if (work == NULL)
 369                 return -ENOMEM;
 370
 371         work->event = event;
 372         work->rdev = rdev;
 373         work->crtc_id = radeon_crtc->crtc_id;
 374         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 375         new_radeon_fb = to_radeon_framebuffer(fb);
 376         /* schedule unpin of the old buffer */
 377         obj = old_radeon_fb->obj;
 378         /* take a reference to the old object */
 379         drm_gem_object_reference(obj);
 380         rbo = gem_to_radeon_bo(obj);
 381         work->old_rbo = rbo;
 382         obj = new_radeon_fb->obj;
 383         rbo = gem_to_radeon_bo(obj);
 384
 385         spin_lock(&rbo->tbo.bdev->fence_lock);
 386         if (rbo->tbo.sync_obj)
 387                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 388         spin_unlock(&rbo->tbo.bdev->fence_lock);
 389
 390         INIT_WORK(&work->work, radeon_unpin_work_func);
 391
 392         /* We borrow the event spin lock for protecting unpin_work */
 393         spin_lock_irqsave(&dev->event_lock, flags);
 394         if (radeon_crtc->unpin_work) {
 395                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 396                 r = -EBUSY;
 397                 goto unlock_free;
 398         }
 399         radeon_crtc->unpin_work = work;
 400         radeon_crtc->deferred_flip_completion = 0;
 401         spin_unlock_irqrestore(&dev->event_lock, flags);
 402
 403         /* pin the new buffer */
 404         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 405                          work->old_rbo, rbo);
 406
 407         r = radeon_bo_reserve(rbo, false);
 408         if (unlikely(r != 0)) {
 409                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 410                 goto pflip_cleanup;
 411         }
 412         /* Only 27 bit offset for legacy CRTC */
 413         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 414                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 415         if (unlikely(r != 0)) {
 416                 radeon_bo_unreserve(rbo);
 417                 r = -EINVAL;
 418                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 419                 goto pflip_cleanup;
 420         }
 421         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 422         radeon_bo_unreserve(rbo);
 423
 424         if (!ASIC_IS_AVIVO(rdev)) {
 425                 /* crtc offset is from display base addr not FB location */
 426                 base -= radeon_crtc->legacy_display_base_addr;
 427                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 428
 429                 if (tiling_flags & RADEON_TILING_MACRO) {
 430                         if (ASIC_IS_R300(rdev)) {
 431                                 base &= ~0x7ff;
 432                         } else {
 433                                 int byteshift = fb->bits_per_pixel >> 4;
 434                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 435                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 436                         }
 437                 } else {
 438                         int offset = crtc->y * pitch_pixels + crtc->x;
 439                         switch (fb->bits_per_pixel) {
 440                         case 8:
 441                         default:
 442                                 offset *= 1;
 443                                 break;
 444                         case 15:
 445                         case 16:
 446                                 offset *= 2;
 447                                 break;
 448                         case 24:
 449                                 offset *= 3;
 450                                 break;
 451                         case 32:
 452                                 offset *= 4;
 453                                 break;
 454                         }
 455                         base += offset;
 456                 }
 457                 base &= ~7;
 458         }
 459
 460         spin_lock_irqsave(&dev->event_lock, flags);
 461         work->new_crtc_base = base;
 462         spin_unlock_irqrestore(&dev->event_lock, flags);
 463
 464         /* update crtc fb */
 465         crtc->primary->fb = fb;
 466
 467         /* set the proper interrupt */
 468         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 469
 470         return 0;
 471
 472 pflip_cleanup:
 473         spin_lock_irqsave(&dev->event_lock, flags);
 474         radeon_crtc->unpin_work = NULL;
 475 unlock_free:
 476         spin_unlock_irqrestore(&dev->event_lock, flags);
 477         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 478         radeon_fence_unref(&work->fence);
 479         kfree(work);
 480
 481         return r;
 482 }
 483
 484 static int
 485 radeon_crtc_set_config(struct drm_mode_set *set)
 486 {
 487         struct drm_device *dev;
 488         struct radeon_device *rdev;
 489         struct drm_crtc *crtc;
 490         bool active = false;
 491         int ret;
 492
 493         if (!set || !set->crtc)
 494                 return -EINVAL;
 495
 496         dev = set->crtc->dev;
 497
 498         ret = pm_runtime_get_sync(dev->dev);
 499         if (ret < 0)
 500                 return ret;
 501
 502         ret = drm_crtc_helper_set_config(set);
 503
 504         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 505                 if (crtc->enabled)
 506                         active = true;
 507
 508         pm_runtime_mark_last_busy(dev->dev);
 509
 510         rdev = dev->dev_private;
 511         /* if we have active crtcs and we don't have a power ref,
 512            take the current one */
 513         if (active && !rdev->have_disp_power_ref) {
 514                 rdev->have_disp_power_ref = true;
 515                 return ret;
 516         }
 517         /* if we have no active crtcs, then drop the power ref
 518            we got before */
 519         if (!active && rdev->have_disp_power_ref) {
 520                 pm_runtime_put_autosuspend(dev->dev);
 521                 rdev->have_disp_power_ref = false;
 522         }
 523
 524         /* drop the power reference we got coming in here */
 525         pm_runtime_put_autosuspend(dev->dev);
 526         return ret;
 527 }
 528 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 529         .cursor_set = radeon_crtc_cursor_set,
 530         .cursor_move = radeon_crtc_cursor_move,
 531         .gamma_set = radeon_crtc_gamma_set,
 532         .set_config = radeon_crtc_set_config,
 533         .destroy = radeon_crtc_destroy,
 534         .page_flip = radeon_crtc_page_flip,
 535 };
 536
 537 static void radeon_crtc_init(struct drm_device *dev, int index)
 538 {
 539         struct radeon_device *rdev = dev->dev_private;
 540         struct radeon_crtc *radeon_crtc;
 541         int i;
 542
 543         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 544         if (radeon_crtc == NULL)
 545                 return;
 546
 547         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 548
 549         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 550         radeon_crtc->crtc_id = index;
 551         rdev->mode_info.crtcs[index] = radeon_crtc;
 552
 553         if (rdev->family >= CHIP_BONAIRE) {
 554                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 555                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 556         } else {
 557                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 558                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 559         }
 560         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 561         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 562
 563 #if 0
 564         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 565         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 566         radeon_crtc->mode_set.num_connectors = 0;
 567 #endif
 568
 569         for (i = 0; i < 256; i++) {
 570                 radeon_crtc->lut_r[i] = i << 2;
 571                 radeon_crtc->lut_g[i] = i << 2;
 572                 radeon_crtc->lut_b[i] = i << 2;
 573         }
 574
 575         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 576                 radeon_atombios_init_crtc(dev, radeon_crtc);
 577         else
 578                 radeon_legacy_init_crtc(dev, radeon_crtc);
 579 }
 580
 581 static const char *encoder_names[38] = {
 582         "NONE",
 583         "INTERNAL_LVDS",
 584         "INTERNAL_TMDS1",
 585         "INTERNAL_TMDS2",
 586         "INTERNAL_DAC1",
 587         "INTERNAL_DAC2",
 588         "INTERNAL_SDVOA",
 589         "INTERNAL_SDVOB",
 590         "SI170B",
 591         "CH7303",
 592         "CH7301",
 593         "INTERNAL_DVO1",
 594         "EXTERNAL_SDVOA",
 595         "EXTERNAL_SDVOB",
 596         "TITFP513",
 597         "INTERNAL_LVTM1",
 598         "VT1623",
 599         "HDMI_SI1930",
 600         "HDMI_INTERNAL",
 601         "INTERNAL_KLDSCP_TMDS1",
 602         "INTERNAL_KLDSCP_DVO1",
 603         "INTERNAL_KLDSCP_DAC1",
 604         "INTERNAL_KLDSCP_DAC2",
 605         "SI178",
 606         "MVPU_FPGA",
 607         "INTERNAL_DDI",
 608         "VT1625",
 609         "HDMI_SI1932",
 610         "DP_AN9801",
 611         "DP_DP501",
 612         "INTERNAL_UNIPHY",
 613         "INTERNAL_KLDSCP_LVTMA",
 614         "INTERNAL_UNIPHY1",
 615         "INTERNAL_UNIPHY2",
 616         "NUTMEG",
 617         "TRAVIS",
 618         "INTERNAL_VCE",
 619         "INTERNAL_UNIPHY3",
 620 };
 621
 622 static const char *hpd_names[6] = {
 623         "HPD1",
 624         "HPD2",
 625         "HPD3",
 626         "HPD4",
 627         "HPD5",
 628         "HPD6",
 629 };
 630
 631 static void radeon_print_display_setup(struct drm_device *dev)
 632 {
 633         struct drm_connector *connector;
 634         struct radeon_connector *radeon_connector;
 635         struct drm_encoder *encoder;
 636         struct radeon_encoder *radeon_encoder;
 637         uint32_t devices;
 638         int i = 0;
 639
 640         DRM_INFO("Radeon Display Connectors\n");
 641         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 642                 radeon_connector = to_radeon_connector(connector);
 643                 DRM_INFO("Connector %d:\n", i);
 644                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 645                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 646                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 647                 if (radeon_connector->ddc_bus) {
 648                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 649                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 650                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 651                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 652                                  radeon_connector->ddc_bus->rec.a_data_reg,
 653                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 654                                  radeon_connector->ddc_bus->rec.en_data_reg,
 655                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 656                                  radeon_connector->ddc_bus->rec.y_data_reg);
 657                         if (radeon_connector->router.ddc_valid)
 658                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 659                                          radeon_connector->router.ddc_mux_control_pin,
 660                                          radeon_connector->router.ddc_mux_state);
 661                         if (radeon_connector->router.cd_valid)
 662                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 663                                          radeon_connector->router.cd_mux_control_pin,
 664                                          radeon_connector->router.cd_mux_state);
 665                 } else {
 666                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 667                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 668                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 669                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 670                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 671                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 672                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 673                 }
 674                 DRM_INFO("  Encoders:\n");
 675                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 676                         radeon_encoder = to_radeon_encoder(encoder);
 677                         devices = radeon_encoder->devices & radeon_connector->devices;
 678                         if (devices) {
 679                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 680                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 681                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 682                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 683                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 684                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 685                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 686                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 687                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 688                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 689                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 690                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 691                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 692                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 693                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 694                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 695                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 696                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 697                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 698                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 699                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 700                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 701                         }
 702                 }
 703                 i++;
 704         }
 705 }
 706
 707 static bool radeon_setup_enc_conn(struct drm_device *dev)
 708 {
 709         struct radeon_device *rdev = dev->dev_private;
 710         bool ret = false;
 711
 712         if (rdev->bios) {
 713                 if (rdev->is_atom_bios) {
 714                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 715                         if (ret == false)
 716                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 717                 } else {
 718                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 719                         if (ret == false)
 720                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 721                 }
 722         } else {
 723                 if (!ASIC_IS_AVIVO(rdev))
 724                         ret = radeon_get_legacy_connector_info_from_table(dev);
 725         }
 726         if (ret) {
 727                 radeon_setup_encoder_clones(dev);
 728                 radeon_print_display_setup(dev);
 729         }
 730
 731         return ret;
 732 }
 733
 734 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 735 {
 736         struct drm_device *dev = radeon_connector->base.dev;
 737         struct radeon_device *rdev = dev->dev_private;
 738         int ret = 0;
 739
 740         /* on hw with routers, select right port */
 741         if (radeon_connector->router.ddc_valid)
 742                 radeon_router_select_ddc_port(radeon_connector);
 743
 744         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 745             ENCODER_OBJECT_ID_NONE) {
 746                 if (radeon_connector->ddc_bus->has_aux)
 747                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 748                                                               &radeon_connector->ddc_bus->aux.ddc);
 749         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 750                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 751                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 752
 753                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 754                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 755                     radeon_connector->ddc_bus->has_aux)
 756                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 757                                                               &radeon_connector->ddc_bus->aux.ddc);
 758                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 759                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 760                                                               &radeon_connector->ddc_bus->adapter);
 761         } else {
 762                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 763                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 764                                                               &radeon_connector->ddc_bus->adapter);
 765         }
 766
 767         if (!radeon_connector->edid) {
 768                 if (rdev->is_atom_bios) {
 769                         /* some laptops provide a hardcoded edid in rom for LCDs */
 770                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 771                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 772                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 773                 } else
 774                         /* some servers provide a hardcoded edid in rom for KVMs */
 775                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 776         }
 777         if (radeon_connector->edid) {
 778                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 779                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 780                 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
 781                 return ret;
 782         }
 783         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 784         return 0;
 785 }
 786
 787 /* avivo */
 788
 789 /**
 790  * avivo_reduce_ratio - fractional number reduction
 791  *
 792  * @nom: nominator
 793  * @den: denominator
 794  * @nom_min: minimum value for nominator
 795  * @den_min: minimum value for denominator
 796  *
 797  * Find the greatest common divisor and apply it on both nominator and
 798  * denominator, but make nominator and denominator are at least as large
 799  * as their minimum values.
 800  */
 801 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 802                                unsigned nom_min, unsigned den_min)
 803 {
 804         unsigned tmp;
 805
 806         /* reduce the numbers to a simpler ratio */
 807         tmp = gcd(*nom, *den);
 808         *nom /= tmp;
 809         *den /= tmp;
 810
 811         /* make sure nominator is large enough */
 812         if (*nom < nom_min) {
 813                 tmp = (nom_min + *nom - 1) / *nom;
 814                 *nom *= tmp;
 815                 *den *= tmp;
 816         }
 817
 818         /* make sure the denominator is large enough */
 819         if (*den < den_min) {
 820                 tmp = (den_min + *den - 1) / *den;
 821                 *nom *= tmp;
 822                 *den *= tmp;
 823         }
 824 }
 825
 826 /**
 827  * avivo_get_fb_ref_div - feedback and ref divider calculation
 828  *
 829  * @nom: nominator
 830  * @den: denominator
 831  * @post_div: post divider
 832  * @fb_div_max: feedback divider maximum
 833  * @ref_div_max: reference divider maximum
 834  * @fb_div: resulting feedback divider
 835  * @ref_div: resulting reference divider
 836  *
 837  * Calculate feedback and reference divider for a given post divider. Makes
 838  * sure we stay within the limits.
 839  */
 840 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 841                                  unsigned fb_div_max, unsigned ref_div_max,
 842                                  unsigned *fb_div, unsigned *ref_div)
 843 {
 844         /* limit reference * post divider to a maximum */
 845         ref_div_max = min(210 / post_div, ref_div_max);
 846
 847         /* get matching reference and feedback divider */
 848         *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
 849         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 850
 851         /* limit fb divider to its maximum */
 852         if (*fb_div > fb_div_max) {
 853                 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
 854                 *fb_div = fb_div_max;
 855         }
 856 }
 857
 858 /**
 859  * radeon_compute_pll_avivo - compute PLL paramaters
 860  *
 861  * @pll: information about the PLL
 862  * @dot_clock_p: resulting pixel clock
 863  * fb_div_p: resulting feedback divider
 864  * frac_fb_div_p: fractional part of the feedback divider
 865  * ref_div_p: resulting reference divider
 866  * post_div_p: resulting reference divider
 867  *
 868  * Try to calculate the PLL parameters to generate the given frequency:
 869  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 870  */
 871 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 872                               u32 freq,
 873                               u32 *dot_clock_p,
 874                               u32 *fb_div_p,
 875                               u32 *frac_fb_div_p,
 876                               u32 *ref_div_p,
 877                               u32 *post_div_p)
 878 {
 879         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 880                 freq : freq / 10;
 881
 882         unsigned fb_div_min, fb_div_max, fb_div;
 883         unsigned post_div_min, post_div_max, post_div;
 884         unsigned ref_div_min, ref_div_max, ref_div;
 885         unsigned post_div_best, diff_best;
 886         unsigned nom, den;
 887
 888         /* determine allowed feedback divider range */
 889         fb_div_min = pll->min_feedback_div;
 890         fb_div_max = pll->max_feedback_div;
 891
 892         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 893                 fb_div_min *= 10;
 894                 fb_div_max *= 10;
 895         }
 896
 897         /* determine allowed ref divider range */
 898         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 899                 ref_div_min = pll->reference_div;
 900         else
 901                 ref_div_min = pll->min_ref_div;
 902
 903         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 904             pll->flags & RADEON_PLL_USE_REF_DIV)
 905                 ref_div_max = pll->reference_div;
 906         else
 907                 ref_div_max = pll->max_ref_div;
 908
 909         /* determine allowed post divider range */
 910         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 911                 post_div_min = pll->post_div;
 912                 post_div_max = pll->post_div;
 913         } else {
 914                 unsigned vco_min, vco_max;
 915
 916                 if (pll->flags & RADEON_PLL_IS_LCD) {
 917                         vco_min = pll->lcd_pll_out_min;
 918                         vco_max = pll->lcd_pll_out_max;
 919                 } else {
 920                         vco_min = pll->pll_out_min;
 921                         vco_max = pll->pll_out_max;
 922                 }
 923
 924                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 925                         vco_min *= 10;
 926                         vco_max *= 10;
 927                 }
 928
 929                 post_div_min = vco_min / target_clock;
 930                 if ((target_clock * post_div_min) < vco_min)
 931                         ++post_div_min;
 932                 if (post_div_min < pll->min_post_div)
 933                         post_div_min = pll->min_post_div;
 934
 935                 post_div_max = vco_max / target_clock;
 936                 if ((target_clock * post_div_max) > vco_max)
 937                         --post_div_max;
 938                 if (post_div_max > pll->max_post_div)
 939                         post_div_max = pll->max_post_div;
 940         }
 941
 942         /* represent the searched ratio as fractional number */
 943         nom = target_clock;
 944         den = pll->reference_freq;
 945
 946         /* reduce the numbers to a simpler ratio */
 947         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
 948
 949         /* now search for a post divider */
 950         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 951                 post_div_best = post_div_min;
 952         else
 953                 post_div_best = post_div_max;
 954         diff_best = ~0;
 955
 956         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
 957                 unsigned diff;
 958                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
 959                                      ref_div_max, &fb_div, &ref_div);
 960                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
 961                         (ref_div * post_div));
 962
 963                 if (diff < diff_best || (diff == diff_best &&
 964                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
 965
 966                         post_div_best = post_div;
 967                         diff_best = diff;
 968                 }
 969         }
 970         post_div = post_div_best;
 971
 972         /* get the feedback and reference divider for the optimal value */
 973         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
 974                              &fb_div, &ref_div);
 975
 976         /* reduce the numbers to a simpler ratio once more */
 977         /* this also makes sure that the reference divider is large enough */
 978         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
 979
 980         /* and finally save the result */
 981         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 982                 *fb_div_p = fb_div / 10;
 983                 *frac_fb_div_p = fb_div % 10;
 984         } else {
 985                 *fb_div_p = fb_div;
 986                 *frac_fb_div_p = 0;
 987         }
 988
 989         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
 990                         (pll->reference_freq * *frac_fb_div_p)) /
 991                        (ref_div * post_div * 10);
 992         *ref_div_p = ref_div;
 993         *post_div_p = post_div;
 994
 995         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 996                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
 997                       ref_div, post_div);
 998 }
 999
1000 /* pre-avivo */
1001 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1002 {
1003         uint64_t mod;
1004
1005         n += d / 2;
1006
1007         mod = do_div(n, d);
1008         return n;
1009 }
1010
1011 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1012                                uint64_t freq,
1013                                uint32_t *dot_clock_p,
1014                                uint32_t *fb_div_p,
1015                                uint32_t *frac_fb_div_p,
1016                                uint32_t *ref_div_p,
1017                                uint32_t *post_div_p)
1018 {
1019         uint32_t min_ref_div = pll->min_ref_div;
1020         uint32_t max_ref_div = pll->max_ref_div;
1021         uint32_t min_post_div = pll->min_post_div;
1022         uint32_t max_post_div = pll->max_post_div;
1023         uint32_t min_fractional_feed_div = 0;
1024         uint32_t max_fractional_feed_div = 0;
1025         uint32_t best_vco = pll->best_vco;
1026         uint32_t best_post_div = 1;
1027         uint32_t best_ref_div = 1;
1028         uint32_t best_feedback_div = 1;
1029         uint32_t best_frac_feedback_div = 0;
1030         uint32_t best_freq = -1;
1031         uint32_t best_error = 0xffffffff;
1032         uint32_t best_vco_diff = 1;
1033         uint32_t post_div;
1034         u32 pll_out_min, pll_out_max;
1035
1036         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1037         freq = freq * 1000;
1038
1039         if (pll->flags & RADEON_PLL_IS_LCD) {
1040                 pll_out_min = pll->lcd_pll_out_min;
1041                 pll_out_max = pll->lcd_pll_out_max;
1042         } else {
1043                 pll_out_min = pll->pll_out_min;
1044                 pll_out_max = pll->pll_out_max;
1045         }
1046
1047         if (pll_out_min > 64800)
1048                 pll_out_min = 64800;
1049
1050         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1051                 min_ref_div = max_ref_div = pll->reference_div;
1052         else {
1053                 while (min_ref_div < max_ref_div-1) {
1054                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1055                         uint32_t pll_in = pll->reference_freq / mid;
1056                         if (pll_in < pll->pll_in_min)
1057                                 max_ref_div = mid;
1058                         else if (pll_in > pll->pll_in_max)
1059                                 min_ref_div = mid;
1060                         else
1061                                 break;
1062                 }
1063         }
1064
1065         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1066                 min_post_div = max_post_div = pll->post_div;
1067
1068         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1069                 min_fractional_feed_div = pll->min_frac_feedback_div;
1070                 max_fractional_feed_div = pll->max_frac_feedback_div;
1071         }
1072
1073         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1074                 uint32_t ref_div;
1075
1076                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1077                         continue;
1078
1079                 /* legacy radeons only have a few post_divs */
1080                 if (pll->flags & RADEON_PLL_LEGACY) {
1081                         if ((post_div == 5) ||
1082                             (post_div == 7) ||
1083                             (post_div == 9) ||
1084                             (post_div == 10) ||
1085                             (post_div == 11) ||
1086                             (post_div == 13) ||
1087                             (post_div == 14) ||
1088                             (post_div == 15))
1089                                 continue;
1090                 }
1091
1092                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1093                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1094                         uint32_t pll_in = pll->reference_freq / ref_div;
1095                         uint32_t min_feed_div = pll->min_feedback_div;
1096                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1097
1098                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1099                                 continue;
1100
1101                         while (min_feed_div < max_feed_div) {
1102                                 uint32_t vco;
1103                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1104                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1105                                 uint32_t frac_feedback_div;
1106                                 uint64_t tmp;
1107
1108                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1109
1110                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1111                                 vco = radeon_div(tmp, ref_div);
1112
1113                                 if (vco < pll_out_min) {
1114                                         min_feed_div = feedback_div + 1;
1115                                         continue;
1116                                 } else if (vco > pll_out_max) {
1117                                         max_feed_div = feedback_div;
1118                                         continue;
1119                                 }
1120
1121                                 while (min_frac_feed_div < max_frac_feed_div) {
1122                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1123                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1124                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1125                                         current_freq = radeon_div(tmp, ref_div * post_div);
1126
1127                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1128                                                 if (freq < current_freq)
1129                                                         error = 0xffffffff;
1130                                                 else
1131                                                         error = freq - current_freq;
1132                                         } else
1133                                                 error = abs(current_freq - freq);
1134                                         vco_diff = abs(vco - best_vco);
1135
1136                                         if ((best_vco == 0 && error < best_error) ||
1137                                             (best_vco != 0 &&
1138                                              ((best_error > 100 && error < best_error - 100) ||
1139                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1140                                                 best_post_div = post_div;
1141                                                 best_ref_div = ref_div;
1142                                                 best_feedback_div = feedback_div;
1143                                                 best_frac_feedback_div = frac_feedback_div;
1144                                                 best_freq = current_freq;
1145                                                 best_error = error;
1146                                                 best_vco_diff = vco_diff;
1147                                         } else if (current_freq == freq) {
1148                                                 if (best_freq == -1) {
1149                                                         best_post_div = post_div;
1150                                                         best_ref_div = ref_div;
1151                                                         best_feedback_div = feedback_div;
1152                                                         best_frac_feedback_div = frac_feedback_div;
1153                                                         best_freq = current_freq;
1154                                                         best_error = error;
1155                                                         best_vco_diff = vco_diff;
1156                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1157                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1158                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1159                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1160                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1161                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1162                                                         best_post_div = post_div;
1163                                                         best_ref_div = ref_div;
1164                                                         best_feedback_div = feedback_div;
1165                                                         best_frac_feedback_div = frac_feedback_div;
1166                                                         best_freq = current_freq;
1167                                                         best_error = error;
1168                                                         best_vco_diff = vco_diff;
1169                                                 }
1170                                         }
1171                                         if (current_freq < freq)
1172                                                 min_frac_feed_div = frac_feedback_div + 1;
1173                                         else
1174                                                 max_frac_feed_div = frac_feedback_div;
1175                                 }
1176                                 if (current_freq < freq)
1177                                         min_feed_div = feedback_div + 1;
1178                                 else
1179                                         max_feed_div = feedback_div;
1180                         }
1181                 }
1182         }
1183
1184         *dot_clock_p = best_freq / 10000;
1185         *fb_div_p = best_feedback_div;
1186         *frac_fb_div_p = best_frac_feedback_div;
1187         *ref_div_p = best_ref_div;
1188         *post_div_p = best_post_div;
1189         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1190                       (long long)freq,
1191                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1192                       best_ref_div, best_post_div);
1193
1194 }
1195
1196 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1197 {
1198         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1199
1200         if (radeon_fb->obj) {
1201                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1202         }
1203         drm_framebuffer_cleanup(fb);
1204         kfree(radeon_fb);
1205 }
1206
1207 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1208                                                   struct drm_file *file_priv,
1209                                                   unsigned int *handle)
1210 {
1211         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1212
1213         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1214 }
1215
1216 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1217         .destroy = radeon_user_framebuffer_destroy,
1218         .create_handle = radeon_user_framebuffer_create_handle,
1219 };
1220
1221 int
1222 radeon_framebuffer_init(struct drm_device *dev,
1223                         struct radeon_framebuffer *rfb,
1224                         struct drm_mode_fb_cmd2 *mode_cmd,
1225                         struct drm_gem_object *obj)
1226 {
1227         int ret;
1228         rfb->obj = obj;
1229         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1230         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1231         if (ret) {
1232                 rfb->obj = NULL;
1233                 return ret;
1234         }
1235         return 0;
1236 }
1237
1238 static struct drm_framebuffer *
1239 radeon_user_framebuffer_create(struct drm_device *dev,
1240                                struct drm_file *file_priv,
1241                                struct drm_mode_fb_cmd2 *mode_cmd)
1242 {
1243         struct drm_gem_object *obj;
1244         struct radeon_framebuffer *radeon_fb;
1245         int ret;
1246
1247         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1248         if (obj ==  NULL) {
1249                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1250                         "can't create framebuffer\n", mode_cmd->handles[0]);
1251                 return ERR_PTR(-ENOENT);
1252         }
1253
1254         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1255         if (radeon_fb == NULL) {
1256                 drm_gem_object_unreference_unlocked(obj);
1257                 return ERR_PTR(-ENOMEM);
1258         }
1259
1260         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1261         if (ret) {
1262                 kfree(radeon_fb);
1263                 drm_gem_object_unreference_unlocked(obj);
1264                 return ERR_PTR(ret);
1265         }
1266
1267         return &radeon_fb->base;
1268 }
1269
1270 static void radeon_output_poll_changed(struct drm_device *dev)
1271 {
1272         struct radeon_device *rdev = dev->dev_private;
1273         radeon_fb_output_poll_changed(rdev);
1274 }
1275
1276 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1277         .fb_create = radeon_user_framebuffer_create,
1278         .output_poll_changed = radeon_output_poll_changed
1279 };
1280
1281 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1282 {       { 0, "driver" },
1283         { 1, "bios" },
1284 };
1285
1286 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1287 {       { TV_STD_NTSC, "ntsc" },
1288         { TV_STD_PAL, "pal" },
1289         { TV_STD_PAL_M, "pal-m" },
1290         { TV_STD_PAL_60, "pal-60" },
1291         { TV_STD_NTSC_J, "ntsc-j" },
1292         { TV_STD_SCART_PAL, "scart-pal" },
1293         { TV_STD_PAL_CN, "pal-cn" },
1294         { TV_STD_SECAM, "secam" },
1295 };
1296
1297 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1298 {       { UNDERSCAN_OFF, "off" },
1299         { UNDERSCAN_ON, "on" },
1300         { UNDERSCAN_AUTO, "auto" },
1301 };
1302
1303 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1304 {       { RADEON_AUDIO_DISABLE, "off" },
1305         { RADEON_AUDIO_ENABLE, "on" },
1306         { RADEON_AUDIO_AUTO, "auto" },
1307 };
1308
1309 /* XXX support different dither options? spatial, temporal, both, etc. */
1310 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1311 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1312         { RADEON_FMT_DITHER_ENABLE, "on" },
1313 };
1314
1315 static int radeon_modeset_create_props(struct radeon_device *rdev)
1316 {
1317         int sz;
1318
1319         if (rdev->is_atom_bios) {
1320                 rdev->mode_info.coherent_mode_property =
1321                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1322                 if (!rdev->mode_info.coherent_mode_property)
1323                         return -ENOMEM;
1324         }
1325
1326         if (!ASIC_IS_AVIVO(rdev)) {
1327                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1328                 rdev->mode_info.tmds_pll_property =
1329                         drm_property_create_enum(rdev->ddev, 0,
1330                                             "tmds_pll",
1331                                             radeon_tmds_pll_enum_list, sz);
1332         }
1333
1334         rdev->mode_info.load_detect_property =
1335                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1336         if (!rdev->mode_info.load_detect_property)
1337                 return -ENOMEM;
1338
1339         drm_mode_create_scaling_mode_property(rdev->ddev);
1340
1341         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1342         rdev->mode_info.tv_std_property =
1343                 drm_property_create_enum(rdev->ddev, 0,
1344                                     "tv standard",
1345                                     radeon_tv_std_enum_list, sz);
1346
1347         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1348         rdev->mode_info.underscan_property =
1349                 drm_property_create_enum(rdev->ddev, 0,
1350                                     "underscan",
1351                                     radeon_underscan_enum_list, sz);
1352
1353         rdev->mode_info.underscan_hborder_property =
1354                 drm_property_create_range(rdev->ddev, 0,
1355                                         "underscan hborder", 0, 128);
1356         if (!rdev->mode_info.underscan_hborder_property)
1357                 return -ENOMEM;
1358
1359         rdev->mode_info.underscan_vborder_property =
1360                 drm_property_create_range(rdev->ddev, 0,
1361                                         "underscan vborder", 0, 128);
1362         if (!rdev->mode_info.underscan_vborder_property)
1363                 return -ENOMEM;
1364
1365         sz = ARRAY_SIZE(radeon_audio_enum_list);
1366         rdev->mode_info.audio_property =
1367                 drm_property_create_enum(rdev->ddev, 0,
1368                                          "audio",
1369                                          radeon_audio_enum_list, sz);
1370
1371         sz = ARRAY_SIZE(radeon_dither_enum_list);
1372         rdev->mode_info.dither_property =
1373                 drm_property_create_enum(rdev->ddev, 0,
1374                                          "dither",
1375                                          radeon_dither_enum_list, sz);
1376
1377         return 0;
1378 }
1379
1380 void radeon_update_display_priority(struct radeon_device *rdev)
1381 {
1382         /* adjustment options for the display watermarks */
1383         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1384                 /* set display priority to high for r3xx, rv515 chips
1385                  * this avoids flickering due to underflow to the
1386                  * display controllers during heavy acceleration.
1387                  * Don't force high on rs4xx igp chips as it seems to
1388                  * affect the sound card.  See kernel bug 15982.
1389                  */
1390                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1391                     !(rdev->flags & RADEON_IS_IGP))
1392                         rdev->disp_priority = 2;
1393                 else
1394                         rdev->disp_priority = 0;
1395         } else
1396                 rdev->disp_priority = radeon_disp_priority;
1397
1398 }
1399
1400 /*
1401  * Allocate hdmi structs and determine register offsets
1402  */
1403 static void radeon_afmt_init(struct radeon_device *rdev)
1404 {
1405         int i;
1406
1407         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1408                 rdev->mode_info.afmt[i] = NULL;
1409
1410         if (ASIC_IS_NODCE(rdev)) {
1411                 /* nothing to do */
1412         } else if (ASIC_IS_DCE4(rdev)) {
1413                 static uint32_t eg_offsets[] = {
1414                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1415                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1416                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1417                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1418                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1419                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1420                         0x13830 - 0x7030,
1421                 };
1422                 int num_afmt;
1423
1424                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1425                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1426                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1427                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1428                 if (ASIC_IS_DCE8(rdev))
1429                         num_afmt = 7;
1430                 else if (ASIC_IS_DCE6(rdev))
1431                         num_afmt = 6;
1432                 else if (ASIC_IS_DCE5(rdev))
1433                         num_afmt = 6;
1434                 else if (ASIC_IS_DCE41(rdev))
1435                         num_afmt = 2;
1436                 else /* DCE4 */
1437                         num_afmt = 6;
1438
1439                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1440                 for (i = 0; i < num_afmt; i++) {
1441                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1442                         if (rdev->mode_info.afmt[i]) {
1443                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1444                                 rdev->mode_info.afmt[i]->id = i;
1445                         }
1446                 }
1447         } else if (ASIC_IS_DCE3(rdev)) {
1448                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1449                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1450                 if (rdev->mode_info.afmt[0]) {
1451                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1452                         rdev->mode_info.afmt[0]->id = 0;
1453                 }
1454                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1455                 if (rdev->mode_info.afmt[1]) {
1456                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1457                         rdev->mode_info.afmt[1]->id = 1;
1458                 }
1459         } else if (ASIC_IS_DCE2(rdev)) {
1460                 /* DCE2 has at least 1 routable audio block */
1461                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1462                 if (rdev->mode_info.afmt[0]) {
1463                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1464                         rdev->mode_info.afmt[0]->id = 0;
1465                 }
1466                 /* r6xx has 2 routable audio blocks */
1467                 if (rdev->family >= CHIP_R600) {
1468                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1469                         if (rdev->mode_info.afmt[1]) {
1470                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1471                                 rdev->mode_info.afmt[1]->id = 1;
1472                         }
1473                 }
1474         }
1475 }
1476
1477 static void radeon_afmt_fini(struct radeon_device *rdev)
1478 {
1479         int i;
1480
1481         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1482                 kfree(rdev->mode_info.afmt[i]);
1483                 rdev->mode_info.afmt[i] = NULL;
1484         }
1485 }
1486
1487 int radeon_modeset_init(struct radeon_device *rdev)
1488 {
1489         int i;
1490         int ret;
1491
1492         drm_mode_config_init(rdev->ddev);
1493         rdev->mode_info.mode_config_initialized = true;
1494
1495         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1496
1497         if (ASIC_IS_DCE5(rdev)) {
1498                 rdev->ddev->mode_config.max_width = 16384;
1499                 rdev->ddev->mode_config.max_height = 16384;
1500         } else if (ASIC_IS_AVIVO(rdev)) {
1501                 rdev->ddev->mode_config.max_width = 8192;
1502                 rdev->ddev->mode_config.max_height = 8192;
1503         } else {
1504                 rdev->ddev->mode_config.max_width = 4096;
1505                 rdev->ddev->mode_config.max_height = 4096;
1506         }
1507
1508         rdev->ddev->mode_config.preferred_depth = 24;
1509         rdev->ddev->mode_config.prefer_shadow = 1;
1510
1511         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1512
1513         ret = radeon_modeset_create_props(rdev);
1514         if (ret) {
1515                 return ret;
1516         }
1517
1518         /* init i2c buses */
1519         radeon_i2c_init(rdev);
1520
1521         /* check combios for a valid hardcoded EDID - Sun servers */
1522         if (!rdev->is_atom_bios) {
1523                 /* check for hardcoded EDID in BIOS */
1524                 radeon_combios_check_hardcoded_edid(rdev);
1525         }
1526
1527         /* allocate crtcs */
1528         for (i = 0; i < rdev->num_crtc; i++) {
1529                 radeon_crtc_init(rdev->ddev, i);
1530         }
1531
1532         /* okay we should have all the bios connectors */
1533         ret = radeon_setup_enc_conn(rdev->ddev);
1534         if (!ret) {
1535                 return ret;
1536         }
1537
1538         /* init dig PHYs, disp eng pll */
1539         if (rdev->is_atom_bios) {
1540                 radeon_atom_encoder_init(rdev);
1541                 radeon_atom_disp_eng_pll_init(rdev);
1542         }
1543
1544         /* initialize hpd */
1545         radeon_hpd_init(rdev);
1546
1547         /* setup afmt */
1548         radeon_afmt_init(rdev);
1549
1550         radeon_fbdev_init(rdev);
1551         drm_kms_helper_poll_init(rdev->ddev);
1552
1553         if (rdev->pm.dpm_enabled) {
1554                 /* do dpm late init */
1555                 ret = radeon_pm_late_init(rdev);
1556                 if (ret) {
1557                         rdev->pm.dpm_enabled = false;
1558                         DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1559                 }
1560                 /* set the dpm state for PX since there won't be
1561                  * a modeset to call this.
1562                  */
1563                 radeon_pm_compute_clocks(rdev);
1564         }
1565
1566         return 0;
1567 }
1568
1569 void radeon_modeset_fini(struct radeon_device *rdev)
1570 {
1571         radeon_fbdev_fini(rdev);
1572         kfree(rdev->mode_info.bios_hardcoded_edid);
1573
1574         if (rdev->mode_info.mode_config_initialized) {
1575                 radeon_afmt_fini(rdev);
1576                 drm_kms_helper_poll_fini(rdev->ddev);
1577                 radeon_hpd_fini(rdev);
1578                 drm_mode_config_cleanup(rdev->ddev);
1579                 rdev->mode_info.mode_config_initialized = false;
1580         }
1581         /* free i2c buses */
1582         radeon_i2c_fini(rdev);
1583 }
1584
1585 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1586 {
1587         /* try and guess if this is a tv or a monitor */
1588         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1589             (mode->vdisplay == 576) || /* 576p */
1590             (mode->vdisplay == 720) || /* 720p */
1591             (mode->vdisplay == 1080)) /* 1080p */
1592                 return true;
1593         else
1594                 return false;
1595 }
1596
1597 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1598                                 const struct drm_display_mode *mode,
1599                                 struct drm_display_mode *adjusted_mode)
1600 {
1601         struct drm_device *dev = crtc->dev;
1602         struct radeon_device *rdev = dev->dev_private;
1603         struct drm_encoder *encoder;
1604         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1605         struct radeon_encoder *radeon_encoder;
1606         struct drm_connector *connector;
1607         struct radeon_connector *radeon_connector;
1608         bool first = true;
1609         u32 src_v = 1, dst_v = 1;
1610         u32 src_h = 1, dst_h = 1;
1611
1612         radeon_crtc->h_border = 0;
1613         radeon_crtc->v_border = 0;
1614
1615         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1616                 if (encoder->crtc != crtc)
1617                         continue;
1618                 radeon_encoder = to_radeon_encoder(encoder);
1619                 connector = radeon_get_connector_for_encoder(encoder);
1620                 radeon_connector = to_radeon_connector(connector);
1621
1622                 if (first) {
1623                         /* set scaling */
1624                         if (radeon_encoder->rmx_type == RMX_OFF)
1625                                 radeon_crtc->rmx_type = RMX_OFF;
1626                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1627                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1628                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1629                         else
1630                                 radeon_crtc->rmx_type = RMX_OFF;
1631                         /* copy native mode */
1632                         memcpy(&radeon_crtc->native_mode,
1633                                &radeon_encoder->native_mode,
1634                                 sizeof(struct drm_display_mode));
1635                         src_v = crtc->mode.vdisplay;
1636                         dst_v = radeon_crtc->native_mode.vdisplay;
1637                         src_h = crtc->mode.hdisplay;
1638                         dst_h = radeon_crtc->native_mode.hdisplay;
1639
1640                         /* fix up for overscan on hdmi */
1641                         if (ASIC_IS_AVIVO(rdev) &&
1642                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1643                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1644                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1645                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1646                               is_hdtv_mode(mode)))) {
1647                                 if (radeon_encoder->underscan_hborder != 0)
1648                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1649                                 else
1650                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1651                                 if (radeon_encoder->underscan_vborder != 0)
1652                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1653                                 else
1654                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1655                                 radeon_crtc->rmx_type = RMX_FULL;
1656                                 src_v = crtc->mode.vdisplay;
1657                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1658                                 src_h = crtc->mode.hdisplay;
1659                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1660                         }
1661                         first = false;
1662                 } else {
1663                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1664                                 /* WARNING: Right now this can't happen but
1665                                  * in the future we need to check that scaling
1666                                  * are consistent across different encoder
1667                                  * (ie all encoder can work with the same
1668                                  *  scaling).
1669                                  */
1670                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1671                                 return false;
1672                         }
1673                 }
1674         }
1675         if (radeon_crtc->rmx_type != RMX_OFF) {
1676                 fixed20_12 a, b;
1677                 a.full = dfixed_const(src_v);
1678                 b.full = dfixed_const(dst_v);
1679                 radeon_crtc->vsc.full = dfixed_div(a, b);
1680                 a.full = dfixed_const(src_h);
1681                 b.full = dfixed_const(dst_h);
1682                 radeon_crtc->hsc.full = dfixed_div(a, b);
1683         } else {
1684                 radeon_crtc->vsc.full = dfixed_const(1);
1685                 radeon_crtc->hsc.full = dfixed_const(1);
1686         }
1687         return true;
1688 }
1689
1690 /*
1691  * Retrieve current video scanout position of crtc on a given gpu, and
1692  * an optional accurate timestamp of when query happened.
1693  *
1694  * \param dev Device to query.
1695  * \param crtc Crtc to query.
1696  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1697  * \param *vpos Location where vertical scanout position should be stored.
1698  * \param *hpos Location where horizontal scanout position should go.
1699  * \param *stime Target location for timestamp taken immediately before
1700  *               scanout position query. Can be NULL to skip timestamp.
1701  * \param *etime Target location for timestamp taken immediately after
1702  *               scanout position query. Can be NULL to skip timestamp.
1703  *
1704  * Returns vpos as a positive number while in active scanout area.
1705  * Returns vpos as a negative number inside vblank, counting the number
1706  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1707  * until start of active scanout / end of vblank."
1708  *
1709  * \return Flags, or'ed together as follows:
1710  *
1711  * DRM_SCANOUTPOS_VALID = Query successful.
1712  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1713  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1714  * this flag means that returned position may be offset by a constant but
1715  * unknown small number of scanlines wrt. real scanout position.
1716  *
1717  */
1718 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1719                                int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1720 {
1721         u32 stat_crtc = 0, vbl = 0, position = 0;
1722         int vbl_start, vbl_end, vtotal, ret = 0;
1723         bool in_vbl = true;
1724
1725         struct radeon_device *rdev = dev->dev_private;
1726
1727         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1728
1729         /* Get optional system timestamp before query. */
1730         if (stime)
1731                 *stime = ktime_get();
1732
1733         if (ASIC_IS_DCE4(rdev)) {
1734                 if (crtc == 0) {
1735                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1736                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1737                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1738                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1739                         ret |= DRM_SCANOUTPOS_VALID;
1740                 }
1741                 if (crtc == 1) {
1742                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1743                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1744                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1745                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1746                         ret |= DRM_SCANOUTPOS_VALID;
1747                 }
1748                 if (crtc == 2) {
1749                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1750                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1751                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1752                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1753                         ret |= DRM_SCANOUTPOS_VALID;
1754                 }
1755                 if (crtc == 3) {
1756                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1757                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1758                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1759                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1760                         ret |= DRM_SCANOUTPOS_VALID;
1761                 }
1762                 if (crtc == 4) {
1763                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1764                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1765                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1766                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1767                         ret |= DRM_SCANOUTPOS_VALID;
1768                 }
1769                 if (crtc == 5) {
1770                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1771                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1772                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1773                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1774                         ret |= DRM_SCANOUTPOS_VALID;
1775                 }
1776         } else if (ASIC_IS_AVIVO(rdev)) {
1777                 if (crtc == 0) {
1778                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1779                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1780                         ret |= DRM_SCANOUTPOS_VALID;
1781                 }
1782                 if (crtc == 1) {
1783                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1784                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1785                         ret |= DRM_SCANOUTPOS_VALID;
1786                 }
1787         } else {
1788                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1789                 if (crtc == 0) {
1790                         /* Assume vbl_end == 0, get vbl_start from
1791                          * upper 16 bits.
1792                          */
1793                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1794                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1795                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1796                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1797                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1798                         if (!(stat_crtc & 1))
1799                                 in_vbl = false;
1800
1801                         ret |= DRM_SCANOUTPOS_VALID;
1802                 }
1803                 if (crtc == 1) {
1804                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1805                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1806                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1807                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1808                         if (!(stat_crtc & 1))
1809                                 in_vbl = false;
1810
1811                         ret |= DRM_SCANOUTPOS_VALID;
1812                 }
1813         }
1814
1815         /* Get optional system timestamp after query. */
1816         if (etime)
1817                 *etime = ktime_get();
1818
1819         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1820
1821         /* Decode into vertical and horizontal scanout position. */
1822         *vpos = position & 0x1fff;
1823         *hpos = (position >> 16) & 0x1fff;
1824
1825         /* Valid vblank area boundaries from gpu retrieved? */
1826         if (vbl > 0) {
1827                 /* Yes: Decode. */
1828                 ret |= DRM_SCANOUTPOS_ACCURATE;
1829                 vbl_start = vbl & 0x1fff;
1830                 vbl_end = (vbl >> 16) & 0x1fff;
1831         }
1832         else {
1833                 /* No: Fake something reasonable which gives at least ok results. */
1834                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1835                 vbl_end = 0;
1836         }
1837
1838         /* Test scanout position against vblank region. */
1839         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1840                 in_vbl = false;
1841
1842         /* Check if inside vblank area and apply corrective offsets:
1843          * vpos will then be >=0 in video scanout area, but negative
1844          * within vblank area, counting down the number of lines until
1845          * start of scanout.
1846          */
1847
1848         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1849         if (in_vbl && (*vpos >= vbl_start)) {
1850                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1851                 *vpos = *vpos - vtotal;
1852         }
1853
1854         /* Correct for shifted end of vbl at vbl_end. */
1855         *vpos = *vpos - vbl_end;
1856
1857         /* In vblank? */
1858         if (in_vbl)
1859                 ret |= DRM_SCANOUTPOS_INVBL;
1860
1861         /* Is vpos outside nominal vblank area, but less than
1862          * 1/100 of a frame height away from start of vblank?
1863          * If so, assume this isn't a massively delayed vblank
1864          * interrupt, but a vblank interrupt that fired a few
1865          * microseconds before true start of vblank. Compensate
1866          * by adding a full frame duration to the final timestamp.
1867          * Happens, e.g., on ATI R500, R600.
1868          *
1869          * We only do this if DRM_CALLED_FROM_VBLIRQ.
1870          */
1871         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1872                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1873                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1874
1875                 if (vbl_start - *vpos < vtotal / 100) {
1876                         *vpos -= vtotal;
1877
1878                         /* Signal this correction as "applied". */
1879                         ret |= 0x8;
1880                 }
1881         }
1882
1883         return ret;
1884 }