drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
 103                         else
 104                                 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 112                                   else*/
 113                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
 119                         else
 120                                 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
 127                 else
 128                         ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
 137                 else
 138                         ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
 148                 else
 149                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179
 180 void
 181 radeon_link_encoder_connector(struct drm_device *dev)
 182 {
 183         struct drm_connector *connector;
 184         struct radeon_connector *radeon_connector;
 185         struct drm_encoder *encoder;
 186         struct radeon_encoder *radeon_encoder;
 187
 188         /* walk the list and link encoders to connectors */
 189         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 190                 radeon_connector = to_radeon_connector(connector);
 191                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 192                         radeon_encoder = to_radeon_encoder(encoder);
 193                         if (radeon_encoder->devices & radeon_connector->devices)
 194                                 drm_mode_connector_attach_encoder(connector, encoder);
 195                 }
 196         }
 197 }
 198
 199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 200 {
 201         struct drm_device *dev = encoder->dev;
 202         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 203         struct drm_connector *connector;
 204
 205         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 206                 if (connector->encoder == encoder) {
 207                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 208                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 209                         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 210                                   radeon_encoder->active_device, radeon_encoder->devices,
 211                                   radeon_connector->devices, encoder->encoder_type);
 212                 }
 213         }
 214 }
 215
 216 struct drm_connector *
 217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 218 {
 219         struct drm_device *dev = encoder->dev;
 220         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 221         struct drm_connector *connector;
 222         struct radeon_connector *radeon_connector;
 223
 224         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 225                 radeon_connector = to_radeon_connector(connector);
 226                 if (radeon_encoder->active_device & radeon_connector->devices)
 227                         return connector;
 228         }
 229         return NULL;
 230 }
 231
 232 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
 233                              struct drm_display_mode *adjusted_mode)
 234 {
 235         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 236         struct drm_device *dev = encoder->dev;
 237         struct radeon_device *rdev = dev->dev_private;
 238         struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 239         unsigned hblank = native_mode->htotal - native_mode->hdisplay;
 240         unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
 241         unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
 242         unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
 243         unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
 244         unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
 245
 246         adjusted_mode->clock = native_mode->clock;
 247         adjusted_mode->flags = native_mode->flags;
 248
 249         if (ASIC_IS_AVIVO(rdev)) {
 250                 adjusted_mode->hdisplay = native_mode->hdisplay;
 251                 adjusted_mode->vdisplay = native_mode->vdisplay;
 252         }
 253
 254         adjusted_mode->htotal = native_mode->hdisplay + hblank;
 255         adjusted_mode->hsync_start = native_mode->hdisplay + hover;
 256         adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
 257
 258         adjusted_mode->vtotal = native_mode->vdisplay + vblank;
 259         adjusted_mode->vsync_start = native_mode->vdisplay + vover;
 260         adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
 261
 262         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
 263
 264         if (ASIC_IS_AVIVO(rdev)) {
 265                 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
 266                 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
 267         }
 268
 269         adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
 270         adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
 271         adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
 272
 273         adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
 274         adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
 275         adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
 276
 277 }
 278
 279 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 280                                    struct drm_display_mode *mode,
 281                                    struct drm_display_mode *adjusted_mode)
 282 {
 283         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 284         struct drm_device *dev = encoder->dev;
 285         struct radeon_device *rdev = dev->dev_private;
 286
 287         /* set the active encoder to connector routing */
 288         radeon_encoder_set_active_device(encoder);
 289         drm_mode_set_crtcinfo(adjusted_mode, 0);
 290
 291         /* hw bug */
 292         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 293             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 294                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 295
 296         /* get the native mode for LVDS */
 297         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 298                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 299
 300         /* get the native mode for TV */
 301         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 302                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 303                 if (tv_dac) {
 304                         if (tv_dac->tv_std == TV_STD_NTSC ||
 305                             tv_dac->tv_std == TV_STD_NTSC_J ||
 306                             tv_dac->tv_std == TV_STD_PAL_M)
 307                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 308                         else
 309                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 310                 }
 311         }
 312
 313         if (ASIC_IS_DCE3(rdev) &&
 314             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
 315                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 316                 radeon_dp_set_link_config(connector, mode);
 317         }
 318
 319         return true;
 320 }
 321
 322 static void
 323 atombios_dac_setup(struct drm_encoder *encoder, int action)
 324 {
 325         struct drm_device *dev = encoder->dev;
 326         struct radeon_device *rdev = dev->dev_private;
 327         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 328         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 329         int index = 0;
 330         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 331
 332         memset(&args, 0, sizeof(args));
 333
 334         switch (radeon_encoder->encoder_id) {
 335         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 336         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 337                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 338                 break;
 339         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 340         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 341                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 342                 break;
 343         }
 344
 345         args.ucAction = action;
 346
 347         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 348                 args.ucDacStandard = ATOM_DAC1_PS2;
 349         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 350                 args.ucDacStandard = ATOM_DAC1_CV;
 351         else {
 352                 switch (dac_info->tv_std) {
 353                 case TV_STD_PAL:
 354                 case TV_STD_PAL_M:
 355                 case TV_STD_SCART_PAL:
 356                 case TV_STD_SECAM:
 357                 case TV_STD_PAL_CN:
 358                         args.ucDacStandard = ATOM_DAC1_PAL;
 359                         break;
 360                 case TV_STD_NTSC:
 361                 case TV_STD_NTSC_J:
 362                 case TV_STD_PAL_60:
 363                 default:
 364                         args.ucDacStandard = ATOM_DAC1_NTSC;
 365                         break;
 366                 }
 367         }
 368         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 369
 370         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 371
 372 }
 373
 374 static void
 375 atombios_tv_setup(struct drm_encoder *encoder, int action)
 376 {
 377         struct drm_device *dev = encoder->dev;
 378         struct radeon_device *rdev = dev->dev_private;
 379         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 380         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 381         int index = 0;
 382         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 383
 384         memset(&args, 0, sizeof(args));
 385
 386         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 387
 388         args.sTVEncoder.ucAction = action;
 389
 390         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 391                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 392         else {
 393                 switch (dac_info->tv_std) {
 394                 case TV_STD_NTSC:
 395                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 396                         break;
 397                 case TV_STD_PAL:
 398                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 399                         break;
 400                 case TV_STD_PAL_M:
 401                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 402                         break;
 403                 case TV_STD_PAL_60:
 404                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 405                         break;
 406                 case TV_STD_NTSC_J:
 407                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 408                         break;
 409                 case TV_STD_SCART_PAL:
 410                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 411                         break;
 412                 case TV_STD_SECAM:
 413                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 414                         break;
 415                 case TV_STD_PAL_CN:
 416                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 417                         break;
 418                 default:
 419                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 420                         break;
 421                 }
 422         }
 423
 424         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 425
 426         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 427
 428 }
 429
 430 union dvo_encoder_control {
 431         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 432         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 433         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 434 };
 435
 436 void
 437 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 438 {
 439         struct drm_device *dev = encoder->dev;
 440         struct radeon_device *rdev = dev->dev_private;
 441         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 442         union dvo_encoder_control args;
 443         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 444
 445         memset(&args, 0, sizeof(args));
 446
 447         if (ASIC_IS_DCE3(rdev)) {
 448                 /* DCE3+ */
 449                 args.dvo_v3.ucAction = action;
 450                 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 451                 args.dvo_v3.ucDVOConfig = 0; /* XXX */
 452         } else if (ASIC_IS_DCE2(rdev)) {
 453                 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
 454                 args.dvo.sDVOEncoder.ucAction = action;
 455                 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 456                 /* DFP1, CRT1, TV1 depending on the type of port */
 457                 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 458
 459                 if (radeon_encoder->pixel_clock > 165000)
 460                         args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 461         } else {
 462                 /* R4xx, R5xx */
 463                 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 464
 465                 if (radeon_encoder->pixel_clock > 165000)
 466                         args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 467
 468                 /*if (pScrn->rgbBits == 8)*/
 469                 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 470         }
 471
 472         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 473 }
 474
 475 union lvds_encoder_control {
 476         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 477         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 478 };
 479
 480 void
 481 atombios_digital_setup(struct drm_encoder *encoder, int action)
 482 {
 483         struct drm_device *dev = encoder->dev;
 484         struct radeon_device *rdev = dev->dev_private;
 485         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 486         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 487         union lvds_encoder_control args;
 488         int index = 0;
 489         int hdmi_detected = 0;
 490         uint8_t frev, crev;
 491
 492         if (!dig)
 493                 return;
 494
 495         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 496                 hdmi_detected = 1;
 497
 498         memset(&args, 0, sizeof(args));
 499
 500         switch (radeon_encoder->encoder_id) {
 501         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 502                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 503                 break;
 504         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 505         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 506                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 507                 break;
 508         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 509                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 510                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 511                 else
 512                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 513                 break;
 514         }
 515
 516         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 517                 return;
 518
 519         switch (frev) {
 520         case 1:
 521         case 2:
 522                 switch (crev) {
 523                 case 1:
 524                         args.v1.ucMisc = 0;
 525                         args.v1.ucAction = action;
 526                         if (hdmi_detected)
 527                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 528                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 529                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 530                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 531                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 532                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 533                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 534                         } else {
 535                                 if (dig->linkb)
 536                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 537                                 if (radeon_encoder->pixel_clock > 165000)
 538                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 539                                 /*if (pScrn->rgbBits == 8) */
 540                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 541                         }
 542                         break;
 543                 case 2:
 544                 case 3:
 545                         args.v2.ucMisc = 0;
 546                         args.v2.ucAction = action;
 547                         if (crev == 3) {
 548                                 if (dig->coherent_mode)
 549                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 550                         }
 551                         if (hdmi_detected)
 552                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 553                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 554                         args.v2.ucTruncate = 0;
 555                         args.v2.ucSpatial = 0;
 556                         args.v2.ucTemporal = 0;
 557                         args.v2.ucFRC = 0;
 558                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 559                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 560                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 561                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 562                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 563                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 564                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 565                                 }
 566                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 567                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 568                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 569                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 570                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 571                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 572                                 }
 573                         } else {
 574                                 if (dig->linkb)
 575                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 576                                 if (radeon_encoder->pixel_clock > 165000)
 577                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 578                         }
 579                         break;
 580                 default:
 581                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 582                         break;
 583                 }
 584                 break;
 585         default:
 586                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 587                 break;
 588         }
 589
 590         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 591 }
 592
 593 int
 594 atombios_get_encoder_mode(struct drm_encoder *encoder)
 595 {
 596         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 597         struct drm_device *dev = encoder->dev;
 598         struct radeon_device *rdev = dev->dev_private;
 599         struct drm_connector *connector;
 600         struct radeon_connector *radeon_connector;
 601         struct radeon_connector_atom_dig *dig_connector;
 602
 603         connector = radeon_get_connector_for_encoder(encoder);
 604         if (!connector) {
 605                 switch (radeon_encoder->encoder_id) {
 606                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 607                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 608                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 609                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 610                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 611                         return ATOM_ENCODER_MODE_DVI;
 612                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 613                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 614                 default:
 615                         return ATOM_ENCODER_MODE_CRT;
 616                 }
 617         }
 618         radeon_connector = to_radeon_connector(connector);
 619
 620         switch (connector->connector_type) {
 621         case DRM_MODE_CONNECTOR_DVII:
 622         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 623                 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
 624                         /* fix me */
 625                         if (ASIC_IS_DCE4(rdev))
 626                                 return ATOM_ENCODER_MODE_DVI;
 627                         else
 628                                 return ATOM_ENCODER_MODE_HDMI;
 629                 } else if (radeon_connector->use_digital)
 630                         return ATOM_ENCODER_MODE_DVI;
 631                 else
 632                         return ATOM_ENCODER_MODE_CRT;
 633                 break;
 634         case DRM_MODE_CONNECTOR_DVID:
 635         case DRM_MODE_CONNECTOR_HDMIA:
 636         default:
 637                 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
 638                         /* fix me */
 639                         if (ASIC_IS_DCE4(rdev))
 640                                 return ATOM_ENCODER_MODE_DVI;
 641                         else
 642                                 return ATOM_ENCODER_MODE_HDMI;
 643                 } else
 644                         return ATOM_ENCODER_MODE_DVI;
 645                 break;
 646         case DRM_MODE_CONNECTOR_LVDS:
 647                 return ATOM_ENCODER_MODE_LVDS;
 648                 break;
 649         case DRM_MODE_CONNECTOR_DisplayPort:
 650         case DRM_MODE_CONNECTOR_eDP:
 651                 dig_connector = radeon_connector->con_priv;
 652                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 653                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 654                         return ATOM_ENCODER_MODE_DP;
 655                 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
 656                         /* fix me */
 657                         if (ASIC_IS_DCE4(rdev))
 658                                 return ATOM_ENCODER_MODE_DVI;
 659                         else
 660                                 return ATOM_ENCODER_MODE_HDMI;
 661                 } else
 662                         return ATOM_ENCODER_MODE_DVI;
 663                 break;
 664         case DRM_MODE_CONNECTOR_DVIA:
 665         case DRM_MODE_CONNECTOR_VGA:
 666                 return ATOM_ENCODER_MODE_CRT;
 667                 break;
 668         case DRM_MODE_CONNECTOR_Composite:
 669         case DRM_MODE_CONNECTOR_SVIDEO:
 670         case DRM_MODE_CONNECTOR_9PinDIN:
 671                 /* fix me */
 672                 return ATOM_ENCODER_MODE_TV;
 673                 /*return ATOM_ENCODER_MODE_CV;*/
 674                 break;
 675         }
 676 }
 677
 678 /*
 679  * DIG Encoder/Transmitter Setup
 680  *
 681  * DCE 3.0/3.1
 682  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 683  * Supports up to 3 digital outputs
 684  * - 2 DIG encoder blocks.
 685  * DIG1 can drive UNIPHY link A or link B
 686  * DIG2 can drive UNIPHY link B or LVTMA
 687  *
 688  * DCE 3.2
 689  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 690  * Supports up to 5 digital outputs
 691  * - 2 DIG encoder blocks.
 692  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 693  *
 694  * DCE 4.0
 695  * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
 696  * Supports up to 6 digital outputs
 697  * - 6 DIG encoder blocks.
 698  * - DIG to PHY mapping is hardcoded
 699  * DIG1 drives UNIPHY0 link A, A+B
 700  * DIG2 drives UNIPHY0 link B
 701  * DIG3 drives UNIPHY1 link A, A+B
 702  * DIG4 drives UNIPHY1 link B
 703  * DIG5 drives UNIPHY2 link A, A+B
 704  * DIG6 drives UNIPHY2 link B
 705  *
 706  * Routing
 707  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 708  * Examples:
 709  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 710  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 711  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 712  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 713  */
 714
 715 union dig_encoder_control {
 716         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 717         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 718         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 719 };
 720
 721 void
 722 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 723 {
 724         struct drm_device *dev = encoder->dev;
 725         struct radeon_device *rdev = dev->dev_private;
 726         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 727         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 728         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 729         union dig_encoder_control args;
 730         int index = 0;
 731         uint8_t frev, crev;
 732         int dp_clock = 0;
 733         int dp_lane_count = 0;
 734
 735         if (connector) {
 736                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 737                 struct radeon_connector_atom_dig *dig_connector =
 738                         radeon_connector->con_priv;
 739
 740                 dp_clock = dig_connector->dp_clock;
 741                 dp_lane_count = dig_connector->dp_lane_count;
 742         }
 743
 744         /* no dig encoder assigned */
 745         if (dig->dig_encoder == -1)
 746                 return;
 747
 748         memset(&args, 0, sizeof(args));
 749
 750         if (ASIC_IS_DCE4(rdev))
 751                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 752         else {
 753                 if (dig->dig_encoder)
 754                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 755                 else
 756                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 757         }
 758
 759         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 760                 return;
 761
 762         args.v1.ucAction = action;
 763         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 764         args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 765
 766         if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 767                 if (dp_clock == 270000)
 768                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 769                 args.v1.ucLaneNum = dp_lane_count;
 770         } else if (radeon_encoder->pixel_clock > 165000)
 771                 args.v1.ucLaneNum = 8;
 772         else
 773                 args.v1.ucLaneNum = 4;
 774
 775         if (ASIC_IS_DCE4(rdev)) {
 776                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 777                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 778         } else {
 779                 switch (radeon_encoder->encoder_id) {
 780                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 781                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 782                         break;
 783                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 784                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 785                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 786                         break;
 787                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 788                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 789                         break;
 790                 }
 791                 if (dig->linkb)
 792                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 793                 else
 794                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 795         }
 796
 797         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 798
 799 }
 800
 801 union dig_transmitter_control {
 802         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 803         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 804         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 805 };
 806
 807 void
 808 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 809 {
 810         struct drm_device *dev = encoder->dev;
 811         struct radeon_device *rdev = dev->dev_private;
 812         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 813         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 814         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 815         union dig_transmitter_control args;
 816         int index = 0;
 817         uint8_t frev, crev;
 818         bool is_dp = false;
 819         int pll_id = 0;
 820         int dp_clock = 0;
 821         int dp_lane_count = 0;
 822         int connector_object_id = 0;
 823         int igp_lane_info = 0;
 824
 825         if (connector) {
 826                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 827                 struct radeon_connector_atom_dig *dig_connector =
 828                         radeon_connector->con_priv;
 829
 830                 dp_clock = dig_connector->dp_clock;
 831                 dp_lane_count = dig_connector->dp_lane_count;
 832                 connector_object_id =
 833                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 834                 igp_lane_info = dig_connector->igp_lane_info;
 835         }
 836
 837         /* no dig encoder assigned */
 838         if (dig->dig_encoder == -1)
 839                 return;
 840
 841         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 842                 is_dp = true;
 843
 844         memset(&args, 0, sizeof(args));
 845
 846         switch (radeon_encoder->encoder_id) {
 847         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 848                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 849                 break;
 850         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 851         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 852         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 853                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 854                 break;
 855         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 856                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
 857                 break;
 858         }
 859
 860         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 861                 return;
 862
 863         args.v1.ucAction = action;
 864         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 865                 args.v1.usInitInfo = connector_object_id;
 866         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 867                 args.v1.asMode.ucLaneSel = lane_num;
 868                 args.v1.asMode.ucLaneSet = lane_set;
 869         } else {
 870                 if (is_dp)
 871                         args.v1.usPixelClock =
 872                                 cpu_to_le16(dp_clock / 10);
 873                 else if (radeon_encoder->pixel_clock > 165000)
 874                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 875                 else
 876                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 877         }
 878         if (ASIC_IS_DCE4(rdev)) {
 879                 if (is_dp)
 880                         args.v3.ucLaneNum = dp_lane_count;
 881                 else if (radeon_encoder->pixel_clock > 165000)
 882                         args.v3.ucLaneNum = 8;
 883                 else
 884                         args.v3.ucLaneNum = 4;
 885
 886                 if (dig->linkb) {
 887                         args.v3.acConfig.ucLinkSel = 1;
 888                         args.v3.acConfig.ucEncoderSel = 1;
 889                 }
 890
 891                 /* Select the PLL for the PHY
 892                  * DP PHY should be clocked from external src if there is
 893                  * one.
 894                  */
 895                 if (encoder->crtc) {
 896                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 897                         pll_id = radeon_crtc->pll_id;
 898                 }
 899                 if (is_dp && rdev->clock.dp_extclk)
 900                         args.v3.acConfig.ucRefClkSource = 2; /* external src */
 901                 else
 902                         args.v3.acConfig.ucRefClkSource = pll_id;
 903
 904                 switch (radeon_encoder->encoder_id) {
 905                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 906                         args.v3.acConfig.ucTransmitterSel = 0;
 907                         break;
 908                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 909                         args.v3.acConfig.ucTransmitterSel = 1;
 910                         break;
 911                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 912                         args.v3.acConfig.ucTransmitterSel = 2;
 913                         break;
 914                 }
 915
 916                 if (is_dp)
 917                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 918                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 919                         if (dig->coherent_mode)
 920                                 args.v3.acConfig.fCoherentMode = 1;
 921                         if (radeon_encoder->pixel_clock > 165000)
 922                                 args.v3.acConfig.fDualLinkConnector = 1;
 923                 }
 924         } else if (ASIC_IS_DCE32(rdev)) {
 925                 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
 926                 if (dig->linkb)
 927                         args.v2.acConfig.ucLinkSel = 1;
 928
 929                 switch (radeon_encoder->encoder_id) {
 930                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 931                         args.v2.acConfig.ucTransmitterSel = 0;
 932                         break;
 933                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 934                         args.v2.acConfig.ucTransmitterSel = 1;
 935                         break;
 936                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 937                         args.v2.acConfig.ucTransmitterSel = 2;
 938                         break;
 939                 }
 940
 941                 if (is_dp)
 942                         args.v2.acConfig.fCoherentMode = 1;
 943                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 944                         if (dig->coherent_mode)
 945                                 args.v2.acConfig.fCoherentMode = 1;
 946                         if (radeon_encoder->pixel_clock > 165000)
 947                                 args.v2.acConfig.fDualLinkConnector = 1;
 948                 }
 949         } else {
 950                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 951
 952                 if (dig->dig_encoder)
 953                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 954                 else
 955                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 956
 957                 if ((rdev->flags & RADEON_IS_IGP) &&
 958                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 959                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
 960                                 if (igp_lane_info & 0x1)
 961                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 962                                 else if (igp_lane_info & 0x2)
 963                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 964                                 else if (igp_lane_info & 0x4)
 965                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 966                                 else if (igp_lane_info & 0x8)
 967                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 968                         } else {
 969                                 if (igp_lane_info & 0x3)
 970                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 971                                 else if (igp_lane_info & 0xc)
 972                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 973                         }
 974                 }
 975
 976                 if (dig->linkb)
 977                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 978                 else
 979                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 980
 981                 if (is_dp)
 982                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 983                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 984                         if (dig->coherent_mode)
 985                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 986                         if (radeon_encoder->pixel_clock > 165000)
 987                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 988                 }
 989         }
 990
 991         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 992 }
 993
 994 void
 995 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
 996 {
 997         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 998         struct drm_device *dev = radeon_connector->base.dev;
 999         struct radeon_device *rdev = dev->dev_private;
1000         union dig_transmitter_control args;
1001         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1002         uint8_t frev, crev;
1003
1004         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1005                 return;
1006
1007         if (!ASIC_IS_DCE4(rdev))
1008                 return;
1009
1010         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) ||
1011             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1012                 return;
1013
1014         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1015                 return;
1016
1017         memset(&args, 0, sizeof(args));
1018
1019         args.v1.ucAction = action;
1020
1021         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1022 }
1023
1024 static void
1025 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1026 {
1027         struct drm_device *dev = encoder->dev;
1028         struct radeon_device *rdev = dev->dev_private;
1029         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1030         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1031         ENABLE_YUV_PS_ALLOCATION args;
1032         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1033         uint32_t temp, reg;
1034
1035         memset(&args, 0, sizeof(args));
1036
1037         if (rdev->family >= CHIP_R600)
1038                 reg = R600_BIOS_3_SCRATCH;
1039         else
1040                 reg = RADEON_BIOS_3_SCRATCH;
1041
1042         /* XXX: fix up scratch reg handling */
1043         temp = RREG32(reg);
1044         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1045                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1046                              (radeon_crtc->crtc_id << 18)));
1047         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1048                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1049         else
1050                 WREG32(reg, 0);
1051
1052         if (enable)
1053                 args.ucEnable = ATOM_ENABLE;
1054         args.ucCRTC = radeon_crtc->crtc_id;
1055
1056         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1057
1058         WREG32(reg, temp);
1059 }
1060
1061 static void
1062 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1063 {
1064         struct drm_device *dev = encoder->dev;
1065         struct radeon_device *rdev = dev->dev_private;
1066         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1067         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1068         int index = 0;
1069         bool is_dig = false;
1070
1071         memset(&args, 0, sizeof(args));
1072
1073         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1074                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1075                   radeon_encoder->active_device);
1076         switch (radeon_encoder->encoder_id) {
1077         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1078         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1079                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1080                 break;
1081         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1082         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1083         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1084         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1085                 is_dig = true;
1086                 break;
1087         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1088         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1089                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1090                 break;
1091         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1092                 if (ASIC_IS_DCE3(rdev))
1093                         is_dig = true;
1094                 else
1095                         index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1096                 break;
1097         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1098                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1099                 break;
1100         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1101                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1102                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1103                 else
1104                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1105                 break;
1106         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1107         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1108                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1109                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1110                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1111                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1112                 else
1113                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1114                 break;
1115         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1116         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1117                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1118                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1119                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1120                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1121                 else
1122                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1123                 break;
1124         }
1125
1126         if (is_dig) {
1127                 switch (mode) {
1128                 case DRM_MODE_DPMS_ON:
1129                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1130                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1131                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1132
1133                                 if (connector &&
1134                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1135                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1136                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1137                                                 radeon_connector->con_priv;
1138                                         atombios_set_edp_panel_power(connector,
1139                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1140                                         radeon_dig_connector->edp_on = true;
1141                                 }
1142                                 dp_link_train(encoder, connector);
1143                                 if (ASIC_IS_DCE4(rdev))
1144                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1145                         }
1146                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1147                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1148                         break;
1149                 case DRM_MODE_DPMS_STANDBY:
1150                 case DRM_MODE_DPMS_SUSPEND:
1151                 case DRM_MODE_DPMS_OFF:
1152                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1153                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1154                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1155
1156                                 if (ASIC_IS_DCE4(rdev))
1157                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1158                                 if (connector &&
1159                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1160                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1161                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1162                                                 radeon_connector->con_priv;
1163                                         atombios_set_edp_panel_power(connector,
1164                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1165                                         radeon_dig_connector->edp_on = false;
1166                                 }
1167                         }
1168                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1169                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1170                         break;
1171                 }
1172         } else {
1173                 switch (mode) {
1174                 case DRM_MODE_DPMS_ON:
1175                         args.ucAction = ATOM_ENABLE;
1176                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1177                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1178                                 args.ucAction = ATOM_LCD_BLON;
1179                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1180                         }
1181                         break;
1182                 case DRM_MODE_DPMS_STANDBY:
1183                 case DRM_MODE_DPMS_SUSPEND:
1184                 case DRM_MODE_DPMS_OFF:
1185                         args.ucAction = ATOM_DISABLE;
1186                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1187                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1188                                 args.ucAction = ATOM_LCD_BLOFF;
1189                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1190                         }
1191                         break;
1192                 }
1193         }
1194         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1195
1196 }
1197
1198 union crtc_source_param {
1199         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1200         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1201 };
1202
1203 static void
1204 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1205 {
1206         struct drm_device *dev = encoder->dev;
1207         struct radeon_device *rdev = dev->dev_private;
1208         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1209         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1210         union crtc_source_param args;
1211         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1212         uint8_t frev, crev;
1213         struct radeon_encoder_atom_dig *dig;
1214
1215         memset(&args, 0, sizeof(args));
1216
1217         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1218                 return;
1219
1220         switch (frev) {
1221         case 1:
1222                 switch (crev) {
1223                 case 1:
1224                 default:
1225                         if (ASIC_IS_AVIVO(rdev))
1226                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1227                         else {
1228                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1229                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1230                                 } else {
1231                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1232                                 }
1233                         }
1234                         switch (radeon_encoder->encoder_id) {
1235                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1236                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1237                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1238                                 break;
1239                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1240                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1241                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1242                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1243                                 else
1244                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1245                                 break;
1246                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1247                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1248                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1249                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1250                                 break;
1251                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1252                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1253                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1254                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1255                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1256                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1257                                 else
1258                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1259                                 break;
1260                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1261                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1262                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1263                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1264                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1265                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1266                                 else
1267                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1268                                 break;
1269                         }
1270                         break;
1271                 case 2:
1272                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1273                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1274                         switch (radeon_encoder->encoder_id) {
1275                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1276                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1277                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1278                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1279                                 dig = radeon_encoder->enc_priv;
1280                                 switch (dig->dig_encoder) {
1281                                 case 0:
1282                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1283                                         break;
1284                                 case 1:
1285                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1286                                         break;
1287                                 case 2:
1288                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1289                                         break;
1290                                 case 3:
1291                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1292                                         break;
1293                                 case 4:
1294                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1295                                         break;
1296                                 case 5:
1297                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1298                                         break;
1299                                 }
1300                                 break;
1301                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1302                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1303                                 break;
1304                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1305                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1306                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1307                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1308                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1309                                 else
1310                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1311                                 break;
1312                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1313                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1314                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1315                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1316                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1317                                 else
1318                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1319                                 break;
1320                         }
1321                         break;
1322                 }
1323                 break;
1324         default:
1325                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1326                 return;
1327         }
1328
1329         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1330
1331         /* update scratch regs with new routing */
1332         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1333 }
1334
1335 static void
1336 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1337                               struct drm_display_mode *mode)
1338 {
1339         struct drm_device *dev = encoder->dev;
1340         struct radeon_device *rdev = dev->dev_private;
1341         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1342         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1343
1344         /* Funky macbooks */
1345         if ((dev->pdev->device == 0x71C5) &&
1346             (dev->pdev->subsystem_vendor == 0x106b) &&
1347             (dev->pdev->subsystem_device == 0x0080)) {
1348                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1349                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1350
1351                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1352                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1353
1354                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1355                 }
1356         }
1357
1358         /* set scaler clears this on some chips */
1359         /* XXX check DCE4 */
1360         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1361                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1362                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1363                                AVIVO_D1MODE_INTERLEAVE_EN);
1364         }
1365 }
1366
1367 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1368 {
1369         struct drm_device *dev = encoder->dev;
1370         struct radeon_device *rdev = dev->dev_private;
1371         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1372         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1373         struct drm_encoder *test_encoder;
1374         struct radeon_encoder_atom_dig *dig;
1375         uint32_t dig_enc_in_use = 0;
1376
1377         if (ASIC_IS_DCE4(rdev)) {
1378                 dig = radeon_encoder->enc_priv;
1379                 switch (radeon_encoder->encoder_id) {
1380                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1381                         if (dig->linkb)
1382                                 return 1;
1383                         else
1384                                 return 0;
1385                         break;
1386                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1387                         if (dig->linkb)
1388                                 return 3;
1389                         else
1390                                 return 2;
1391                         break;
1392                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1393                         if (dig->linkb)
1394                                 return 5;
1395                         else
1396                                 return 4;
1397                         break;
1398                 }
1399         }
1400
1401         /* on DCE32 and encoder can driver any block so just crtc id */
1402         if (ASIC_IS_DCE32(rdev)) {
1403                 return radeon_crtc->crtc_id;
1404         }
1405
1406         /* on DCE3 - LVTMA can only be driven by DIGB */
1407         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1408                 struct radeon_encoder *radeon_test_encoder;
1409
1410                 if (encoder == test_encoder)
1411                         continue;
1412
1413                 if (!radeon_encoder_is_digital(test_encoder))
1414                         continue;
1415
1416                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1417                 dig = radeon_test_encoder->enc_priv;
1418
1419                 if (dig->dig_encoder >= 0)
1420                         dig_enc_in_use |= (1 << dig->dig_encoder);
1421         }
1422
1423         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1424                 if (dig_enc_in_use & 0x2)
1425                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1426                 return 1;
1427         }
1428         if (!(dig_enc_in_use & 1))
1429                 return 0;
1430         return 1;
1431 }
1432
1433 static void
1434 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1435                              struct drm_display_mode *mode,
1436                              struct drm_display_mode *adjusted_mode)
1437 {
1438         struct drm_device *dev = encoder->dev;
1439         struct radeon_device *rdev = dev->dev_private;
1440         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1441
1442         radeon_encoder->pixel_clock = adjusted_mode->clock;
1443
1444         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1445                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1446                         atombios_yuv_setup(encoder, true);
1447                 else
1448                         atombios_yuv_setup(encoder, false);
1449         }
1450
1451         switch (radeon_encoder->encoder_id) {
1452         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1453         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1454         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1455         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1456                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1457                 break;
1458         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1459         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1460         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1461         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1462                 if (ASIC_IS_DCE4(rdev)) {
1463                         /* disable the transmitter */
1464                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1465                         /* setup and enable the encoder */
1466                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1467
1468                         /* init and enable the transmitter */
1469                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1470                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1471                 } else {
1472                         /* disable the encoder and transmitter */
1473                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1474                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1475
1476                         /* setup and enable the encoder and transmitter */
1477                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1478                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1479                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1480                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1481                 }
1482                 break;
1483         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1484         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1485         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1486                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1487                 break;
1488         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1489         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1490         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1491         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1492                 atombios_dac_setup(encoder, ATOM_ENABLE);
1493                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1494                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1495                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1496                         else
1497                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1498                 }
1499                 break;
1500         }
1501         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1502
1503         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1504                 r600_hdmi_enable(encoder);
1505                 r600_hdmi_setmode(encoder, adjusted_mode);
1506         }
1507 }
1508
1509 static bool
1510 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1511 {
1512         struct drm_device *dev = encoder->dev;
1513         struct radeon_device *rdev = dev->dev_private;
1514         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1515         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1516
1517         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1518                                        ATOM_DEVICE_CV_SUPPORT |
1519                                        ATOM_DEVICE_CRT_SUPPORT)) {
1520                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1521                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1522                 uint8_t frev, crev;
1523
1524                 memset(&args, 0, sizeof(args));
1525
1526                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1527                         return false;
1528
1529                 args.sDacload.ucMisc = 0;
1530
1531                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1532                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1533                         args.sDacload.ucDacType = ATOM_DAC_A;
1534                 else
1535                         args.sDacload.ucDacType = ATOM_DAC_B;
1536
1537                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1538                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1539                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1540                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1541                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1542                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1543                         if (crev >= 3)
1544                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1545                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1546                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1547                         if (crev >= 3)
1548                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1549                 }
1550
1551                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1552
1553                 return true;
1554         } else
1555                 return false;
1556 }
1557
1558 static enum drm_connector_status
1559 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1560 {
1561         struct drm_device *dev = encoder->dev;
1562         struct radeon_device *rdev = dev->dev_private;
1563         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1564         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1565         uint32_t bios_0_scratch;
1566
1567         if (!atombios_dac_load_detect(encoder, connector)) {
1568                 DRM_DEBUG_KMS("detect returned false \n");
1569                 return connector_status_unknown;
1570         }
1571
1572         if (rdev->family >= CHIP_R600)
1573                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1574         else
1575                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1576
1577         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1578         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1579                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1580                         return connector_status_connected;
1581         }
1582         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1583                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1584                         return connector_status_connected;
1585         }
1586         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1587                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1588                         return connector_status_connected;
1589         }
1590         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1591                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1592                         return connector_status_connected; /* CTV */
1593                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1594                         return connector_status_connected; /* STV */
1595         }
1596         return connector_status_disconnected;
1597 }
1598
1599 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1600 {
1601         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1602         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1603
1604         if (radeon_encoder->active_device &
1605             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1606                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1607                 if (dig)
1608                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1609         }
1610
1611         radeon_atom_output_lock(encoder, true);
1612         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1613
1614         /* select the clock/data port if it uses a router */
1615         if (connector) {
1616                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1617                 if (radeon_connector->router.cd_valid)
1618                         radeon_router_select_cd_port(radeon_connector);
1619         }
1620
1621         /* this is needed for the pll/ss setup to work correctly in some cases */
1622         atombios_set_encoder_crtc_source(encoder);
1623 }
1624
1625 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1626 {
1627         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1628         radeon_atom_output_lock(encoder, false);
1629 }
1630
1631 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1632 {
1633         struct drm_device *dev = encoder->dev;
1634         struct radeon_device *rdev = dev->dev_private;
1635         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1636         struct radeon_encoder_atom_dig *dig;
1637
1638         /* check for pre-DCE3 cards with shared encoders;
1639          * can't really use the links individually, so don't disable
1640          * the encoder if it's in use by another connector
1641          */
1642         if (!ASIC_IS_DCE3(rdev)) {
1643                 struct drm_encoder *other_encoder;
1644                 struct radeon_encoder *other_radeon_encoder;
1645
1646                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1647                         other_radeon_encoder = to_radeon_encoder(other_encoder);
1648                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1649                             drm_helper_encoder_in_use(other_encoder))
1650                                 goto disable_done;
1651                 }
1652         }
1653
1654         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1655
1656         switch (radeon_encoder->encoder_id) {
1657         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1658         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1659         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1660         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1661                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1662                 break;
1663         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1664         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1665         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1666         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1667                 if (ASIC_IS_DCE4(rdev))
1668                         /* disable the transmitter */
1669                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1670                 else {
1671                         /* disable the encoder and transmitter */
1672                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1673                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1674                 }
1675                 break;
1676         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1677         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1678         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1679                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1680                 break;
1681         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1682         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1683         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1684         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1685                 atombios_dac_setup(encoder, ATOM_DISABLE);
1686                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1687                         atombios_tv_setup(encoder, ATOM_DISABLE);
1688                 break;
1689         }
1690
1691 disable_done:
1692         if (radeon_encoder_is_digital(encoder)) {
1693                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1694                         r600_hdmi_disable(encoder);
1695                 dig = radeon_encoder->enc_priv;
1696                 dig->dig_encoder = -1;
1697         }
1698         radeon_encoder->active_device = 0;
1699 }
1700
1701 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1702         .dpms = radeon_atom_encoder_dpms,
1703         .mode_fixup = radeon_atom_mode_fixup,
1704         .prepare = radeon_atom_encoder_prepare,
1705         .mode_set = radeon_atom_encoder_mode_set,
1706         .commit = radeon_atom_encoder_commit,
1707         .disable = radeon_atom_encoder_disable,
1708         /* no detect for TMDS/LVDS yet */
1709 };
1710
1711 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1712         .dpms = radeon_atom_encoder_dpms,
1713         .mode_fixup = radeon_atom_mode_fixup,
1714         .prepare = radeon_atom_encoder_prepare,
1715         .mode_set = radeon_atom_encoder_mode_set,
1716         .commit = radeon_atom_encoder_commit,
1717         .detect = radeon_atom_dac_detect,
1718 };
1719
1720 void radeon_enc_destroy(struct drm_encoder *encoder)
1721 {
1722         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1723         kfree(radeon_encoder->enc_priv);
1724         drm_encoder_cleanup(encoder);
1725         kfree(radeon_encoder);
1726 }
1727
1728 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1729         .destroy = radeon_enc_destroy,
1730 };
1731
1732 struct radeon_encoder_atom_dac *
1733 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1734 {
1735         struct drm_device *dev = radeon_encoder->base.dev;
1736         struct radeon_device *rdev = dev->dev_private;
1737         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1738
1739         if (!dac)
1740                 return NULL;
1741
1742         dac->tv_std = radeon_atombios_get_tv_info(rdev);
1743         return dac;
1744 }
1745
1746 struct radeon_encoder_atom_dig *
1747 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1748 {
1749         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1750         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1751
1752         if (!dig)
1753                 return NULL;
1754
1755         /* coherent mode by default */
1756         dig->coherent_mode = true;
1757         dig->dig_encoder = -1;
1758
1759         if (encoder_enum == 2)
1760                 dig->linkb = true;
1761         else
1762                 dig->linkb = false;
1763
1764         return dig;
1765 }
1766
1767 void
1768 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1769 {
1770         struct radeon_device *rdev = dev->dev_private;
1771         struct drm_encoder *encoder;
1772         struct radeon_encoder *radeon_encoder;
1773
1774         /* see if we already added it */
1775         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1776                 radeon_encoder = to_radeon_encoder(encoder);
1777                 if (radeon_encoder->encoder_enum == encoder_enum) {
1778                         radeon_encoder->devices |= supported_device;
1779                         return;
1780                 }
1781
1782         }
1783
1784         /* add a new one */
1785         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1786         if (!radeon_encoder)
1787                 return;
1788
1789         encoder = &radeon_encoder->base;
1790         switch (rdev->num_crtc) {
1791         case 1:
1792                 encoder->possible_crtcs = 0x1;
1793                 break;
1794         case 2:
1795         default:
1796                 encoder->possible_crtcs = 0x3;
1797                 break;
1798         case 6:
1799                 encoder->possible_crtcs = 0x3f;
1800                 break;
1801         }
1802
1803         radeon_encoder->enc_priv = NULL;
1804
1805         radeon_encoder->encoder_enum = encoder_enum;
1806         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1807         radeon_encoder->devices = supported_device;
1808         radeon_encoder->rmx_type = RMX_OFF;
1809         radeon_encoder->underscan_type = UNDERSCAN_OFF;
1810
1811         switch (radeon_encoder->encoder_id) {
1812         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1813         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1814         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1815         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1816                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1817                         radeon_encoder->rmx_type = RMX_FULL;
1818                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1819                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1820                 } else {
1821                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1822                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1823                         if (ASIC_IS_AVIVO(rdev))
1824                                 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1825                 }
1826                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1827                 break;
1828         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1829                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1830                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1831                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1832                 break;
1833         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1834         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1835         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1836                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1837                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1838                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1839                 break;
1840         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1841         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1842         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1843         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1844         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1845         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1846         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1847                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1848                         radeon_encoder->rmx_type = RMX_FULL;
1849                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1850                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1851                 } else {
1852                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1853                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1854                         if (ASIC_IS_AVIVO(rdev))
1855                                 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1856                 }
1857                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1858                 break;
1859         }
1860 }