2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 #include <linux/export.h>
29 #include <drm/drm_edid.h>
30 #include <drm/radeon_drm.h>
34 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
35 struct i2c_msg *msgs, int num);
36 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);
42 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
47 struct i2c_msg msgs[] = {
62 /* on hw with routers, select right port */
63 if (radeon_connector->router.ddc_valid)
64 radeon_router_select_ddc_port(radeon_connector);
67 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
68 ret = i2c_transfer(&dig->dp_i2c_bus->adapter, msgs, 2);
70 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
74 /* Couldn't find an accessible DDC on this connector */
76 /* Probe also for valid EDID header
77 * EDID header starts with:
78 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
79 * Only the first 6 bytes must be valid as
80 * drm_edid_block_valid() can fix the last 2 bytes */
81 if (drm_edid_header_is_valid(buf) < 6) {
82 /* Couldn't find an accessible EDID on this
91 static int pre_xfer(struct i2c_adapter *i2c_adap)
93 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
94 struct radeon_device *rdev = i2c->dev->dev_private;
95 struct radeon_i2c_bus_rec *rec = &i2c->rec;
98 /* RV410 appears to have a bug where the hw i2c in reset
99 * holds the i2c port in a bad state - switch hw i2c away before
100 * doing DDC - do this for all r200s/r300s/r400s for safety sake
102 if (rec->hw_capable) {
103 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
106 if (rdev->family >= CHIP_RV350)
107 reg = RADEON_GPIO_MONID;
108 else if ((rdev->family == CHIP_R300) ||
109 (rdev->family == CHIP_R350))
110 reg = RADEON_GPIO_DVI_DDC;
112 reg = RADEON_GPIO_CRT2_DDC;
114 mutex_lock(&rdev->dc_hw_i2c_mutex);
115 if (rec->a_clk_reg == reg) {
116 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
117 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
119 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
120 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
122 mutex_unlock(&rdev->dc_hw_i2c_mutex);
126 /* switch the pads to ddc mode */
127 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
128 temp = RREG32(rec->mask_clk_reg);
130 WREG32(rec->mask_clk_reg, temp);
133 /* clear the output pin values */
134 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
135 WREG32(rec->a_clk_reg, temp);
137 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
138 WREG32(rec->a_data_reg, temp);
140 /* set the pins to input */
141 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
142 WREG32(rec->en_clk_reg, temp);
144 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
145 WREG32(rec->en_data_reg, temp);
147 /* mask the gpio pins for software use */
148 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
149 WREG32(rec->mask_clk_reg, temp);
150 temp = RREG32(rec->mask_clk_reg);
152 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
153 WREG32(rec->mask_data_reg, temp);
154 temp = RREG32(rec->mask_data_reg);
159 static void post_xfer(struct i2c_adapter *i2c_adap)
161 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
162 struct radeon_device *rdev = i2c->dev->dev_private;
163 struct radeon_i2c_bus_rec *rec = &i2c->rec;
166 /* unmask the gpio pins for software use */
167 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
168 WREG32(rec->mask_clk_reg, temp);
169 temp = RREG32(rec->mask_clk_reg);
171 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
172 WREG32(rec->mask_data_reg, temp);
173 temp = RREG32(rec->mask_data_reg);
176 static int get_clock(void *i2c_priv)
178 struct radeon_i2c_chan *i2c = i2c_priv;
179 struct radeon_device *rdev = i2c->dev->dev_private;
180 struct radeon_i2c_bus_rec *rec = &i2c->rec;
183 /* read the value off the pin */
184 val = RREG32(rec->y_clk_reg);
185 val &= rec->y_clk_mask;
191 static int get_data(void *i2c_priv)
193 struct radeon_i2c_chan *i2c = i2c_priv;
194 struct radeon_device *rdev = i2c->dev->dev_private;
195 struct radeon_i2c_bus_rec *rec = &i2c->rec;
198 /* read the value off the pin */
199 val = RREG32(rec->y_data_reg);
200 val &= rec->y_data_mask;
205 static void set_clock(void *i2c_priv, int clock)
207 struct radeon_i2c_chan *i2c = i2c_priv;
208 struct radeon_device *rdev = i2c->dev->dev_private;
209 struct radeon_i2c_bus_rec *rec = &i2c->rec;
212 /* set pin direction */
213 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
214 val |= clock ? 0 : rec->en_clk_mask;
215 WREG32(rec->en_clk_reg, val);
218 static void set_data(void *i2c_priv, int data)
220 struct radeon_i2c_chan *i2c = i2c_priv;
221 struct radeon_device *rdev = i2c->dev->dev_private;
222 struct radeon_i2c_bus_rec *rec = &i2c->rec;
225 /* set pin direction */
226 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
227 val |= data ? 0 : rec->en_data_mask;
228 WREG32(rec->en_data_reg, val);
233 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
235 u32 sclk = rdev->pm.current_sclk;
241 switch (rdev->family) {
255 nm = (sclk * 10) / (i2c_clock * 4);
256 for (loop = 1; loop < 255; loop++) {
257 if ((nm / loop) < loop)
262 prescale = m | (n << 8);
270 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
284 if (rdev->family == CHIP_R520)
285 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
287 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
313 DRM_ERROR("i2c: unhandled radeon chip\n");
320 /* hw i2c engine for r1xx-4xx hardware
321 * hw can buffer up to 15 bytes
323 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
324 struct i2c_msg *msgs, int num)
326 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
327 struct radeon_device *rdev = i2c->dev->dev_private;
328 struct radeon_i2c_bus_rec *rec = &i2c->rec;
330 int i, j, k, ret = num;
332 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
335 mutex_lock(&rdev->dc_hw_i2c_mutex);
336 /* take the pm lock since we need a constant sclk */
337 mutex_lock(&rdev->pm.mutex);
339 prescale = radeon_get_i2c_prescale(rdev);
341 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
342 RADEON_I2C_DRIVE_EN |
347 if (rdev->is_atom_bios) {
348 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
349 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
353 i2c_cntl_0 = RADEON_I2C_CNTL_0;
354 i2c_cntl_1 = RADEON_I2C_CNTL_1;
355 i2c_data = RADEON_I2C_DATA;
357 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
358 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
359 i2c_data = RADEON_DVI_I2C_DATA;
361 switch (rdev->family) {
368 switch (rec->mask_clk_reg) {
369 case RADEON_GPIO_DVI_DDC:
370 /* no gpio select bit */
373 DRM_ERROR("gpio not supported with hw i2c\n");
379 /* only bit 4 on r200 */
380 switch (rec->mask_clk_reg) {
381 case RADEON_GPIO_DVI_DDC:
382 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
384 case RADEON_GPIO_MONID:
385 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
388 DRM_ERROR("gpio not supported with hw i2c\n");
396 switch (rec->mask_clk_reg) {
397 case RADEON_GPIO_DVI_DDC:
398 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
400 case RADEON_GPIO_VGA_DDC:
401 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
403 case RADEON_GPIO_CRT2_DDC:
404 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
407 DRM_ERROR("gpio not supported with hw i2c\n");
414 /* only bit 4 on r300/r350 */
415 switch (rec->mask_clk_reg) {
416 case RADEON_GPIO_VGA_DDC:
417 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
419 case RADEON_GPIO_DVI_DDC:
420 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
423 DRM_ERROR("gpio not supported with hw i2c\n");
436 switch (rec->mask_clk_reg) {
437 case RADEON_GPIO_VGA_DDC:
438 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
440 case RADEON_GPIO_DVI_DDC:
441 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
443 case RADEON_GPIO_MONID:
444 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
447 DRM_ERROR("gpio not supported with hw i2c\n");
453 DRM_ERROR("unsupported asic\n");
460 /* check for bus probe */
462 if ((num == 1) && (p->len == 0)) {
463 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
466 RADEON_I2C_SOFT_RST));
467 WREG32(i2c_data, (p->addr << 1) & 0xff);
469 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
470 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
472 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
473 WREG32(i2c_cntl_0, reg);
474 for (k = 0; k < 32; k++) {
476 tmp = RREG32(i2c_cntl_0);
477 if (tmp & RADEON_I2C_GO)
479 tmp = RREG32(i2c_cntl_0);
480 if (tmp & RADEON_I2C_DONE)
483 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
484 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
492 for (i = 0; i < num; i++) {
494 for (j = 0; j < p->len; j++) {
495 if (p->flags & I2C_M_RD) {
496 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
499 RADEON_I2C_SOFT_RST));
500 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
501 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
502 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
504 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
505 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
506 for (k = 0; k < 32; k++) {
508 tmp = RREG32(i2c_cntl_0);
509 if (tmp & RADEON_I2C_GO)
511 tmp = RREG32(i2c_cntl_0);
512 if (tmp & RADEON_I2C_DONE)
515 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
516 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
521 p->buf[j] = RREG32(i2c_data) & 0xff;
523 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
526 RADEON_I2C_SOFT_RST));
527 WREG32(i2c_data, (p->addr << 1) & 0xff);
528 WREG32(i2c_data, p->buf[j]);
529 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
530 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
532 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
533 WREG32(i2c_cntl_0, reg);
534 for (k = 0; k < 32; k++) {
536 tmp = RREG32(i2c_cntl_0);
537 if (tmp & RADEON_I2C_GO)
539 tmp = RREG32(i2c_cntl_0);
540 if (tmp & RADEON_I2C_DONE)
543 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
544 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
554 WREG32(i2c_cntl_0, 0);
555 WREG32(i2c_cntl_1, 0);
556 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
559 RADEON_I2C_SOFT_RST));
561 if (rdev->is_atom_bios) {
562 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
563 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
564 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
567 mutex_unlock(&rdev->pm.mutex);
568 mutex_unlock(&rdev->dc_hw_i2c_mutex);
573 /* hw i2c engine for r5xx hardware
574 * hw can buffer up to 15 bytes
576 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
577 struct i2c_msg *msgs, int num)
579 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
580 struct radeon_device *rdev = i2c->dev->dev_private;
581 struct radeon_i2c_bus_rec *rec = &i2c->rec;
583 int i, j, remaining, current_count, buffer_offset, ret = num;
588 mutex_lock(&rdev->dc_hw_i2c_mutex);
589 /* take the pm lock since we need a constant sclk */
590 mutex_lock(&rdev->pm.mutex);
592 prescale = radeon_get_i2c_prescale(rdev);
594 /* clear gpio mask bits */
595 tmp = RREG32(rec->mask_clk_reg);
596 tmp &= ~rec->mask_clk_mask;
597 WREG32(rec->mask_clk_reg, tmp);
598 tmp = RREG32(rec->mask_clk_reg);
600 tmp = RREG32(rec->mask_data_reg);
601 tmp &= ~rec->mask_data_mask;
602 WREG32(rec->mask_data_reg, tmp);
603 tmp = RREG32(rec->mask_data_reg);
605 /* clear pin values */
606 tmp = RREG32(rec->a_clk_reg);
607 tmp &= ~rec->a_clk_mask;
608 WREG32(rec->a_clk_reg, tmp);
609 tmp = RREG32(rec->a_clk_reg);
611 tmp = RREG32(rec->a_data_reg);
612 tmp &= ~rec->a_data_mask;
613 WREG32(rec->a_data_reg, tmp);
614 tmp = RREG32(rec->a_data_reg);
616 /* set the pins to input */
617 tmp = RREG32(rec->en_clk_reg);
618 tmp &= ~rec->en_clk_mask;
619 WREG32(rec->en_clk_reg, tmp);
620 tmp = RREG32(rec->en_clk_reg);
622 tmp = RREG32(rec->en_data_reg);
623 tmp &= ~rec->en_data_mask;
624 WREG32(rec->en_data_reg, tmp);
625 tmp = RREG32(rec->en_data_reg);
628 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
629 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
630 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
631 saved2 = RREG32(0x494);
632 WREG32(0x494, saved2 | 0x1);
634 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
635 for (i = 0; i < 50; i++) {
637 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
641 DRM_ERROR("failed to get i2c bus\n");
646 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
647 switch (rec->mask_clk_reg) {
648 case AVIVO_DC_GPIO_DDC1_MASK:
649 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
651 case AVIVO_DC_GPIO_DDC2_MASK:
652 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
654 case AVIVO_DC_GPIO_DDC3_MASK:
655 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
658 DRM_ERROR("gpio not supported with hw i2c\n");
663 /* check for bus probe */
665 if ((num == 1) && (p->len == 0)) {
666 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
669 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
671 WREG32(AVIVO_DC_I2C_RESET, 0);
673 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
674 WREG32(AVIVO_DC_I2C_DATA, 0);
676 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
677 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
678 AVIVO_DC_I2C_DATA_COUNT(1) |
680 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
681 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
682 for (j = 0; j < 200; j++) {
684 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
685 if (tmp & AVIVO_DC_I2C_GO)
687 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
688 if (tmp & AVIVO_DC_I2C_DONE)
691 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
692 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
700 for (i = 0; i < num; i++) {
704 if (p->flags & I2C_M_RD) {
709 current_count = remaining;
710 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
713 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
715 WREG32(AVIVO_DC_I2C_RESET, 0);
717 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
718 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
719 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
720 AVIVO_DC_I2C_DATA_COUNT(current_count) |
722 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
723 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
724 for (j = 0; j < 200; j++) {
726 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
727 if (tmp & AVIVO_DC_I2C_GO)
729 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
730 if (tmp & AVIVO_DC_I2C_DONE)
733 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
734 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
739 for (j = 0; j < current_count; j++)
740 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
741 remaining -= current_count;
742 buffer_offset += current_count;
749 current_count = remaining;
750 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
753 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
755 WREG32(AVIVO_DC_I2C_RESET, 0);
757 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
758 for (j = 0; j < current_count; j++)
759 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
761 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
762 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
763 AVIVO_DC_I2C_DATA_COUNT(current_count) |
765 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
766 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
767 for (j = 0; j < 200; j++) {
769 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
770 if (tmp & AVIVO_DC_I2C_GO)
772 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
773 if (tmp & AVIVO_DC_I2C_DONE)
776 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
777 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
782 remaining -= current_count;
783 buffer_offset += current_count;
789 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
792 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
794 WREG32(AVIVO_DC_I2C_RESET, 0);
796 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
797 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
798 WREG32(0x494, saved2);
799 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
800 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
801 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
803 mutex_unlock(&rdev->pm.mutex);
804 mutex_unlock(&rdev->dc_hw_i2c_mutex);
809 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
810 struct i2c_msg *msgs, int num)
812 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
813 struct radeon_device *rdev = i2c->dev->dev_private;
814 struct radeon_i2c_bus_rec *rec = &i2c->rec;
817 switch (rdev->family) {
836 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
841 /* XXX fill in hw i2c implementation */
850 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
852 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
858 /* XXX fill in hw i2c implementation */
868 /* XXX fill in hw i2c implementation */
875 /* XXX fill in hw i2c implementation */
878 DRM_ERROR("i2c: unhandled radeon chip\n");
886 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
888 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
891 static const struct i2c_algorithm radeon_i2c_algo = {
892 .master_xfer = radeon_hw_i2c_xfer,
893 .functionality = radeon_hw_i2c_func,
896 static const struct i2c_algorithm radeon_atom_i2c_algo = {
897 .master_xfer = radeon_atom_hw_i2c_xfer,
898 .functionality = radeon_atom_hw_i2c_func,
901 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
902 struct radeon_i2c_bus_rec *rec,
905 struct radeon_device *rdev = dev->dev_private;
906 struct radeon_i2c_chan *i2c;
909 /* don't add the mm_i2c bus unless hw_i2c is enabled */
910 if (rec->mm_i2c && (radeon_hw_i2c == 0))
913 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
918 i2c->adapter.owner = THIS_MODULE;
919 i2c->adapter.class = I2C_CLASS_DDC;
920 i2c->adapter.dev.parent = &dev->pdev->dev;
922 i2c_set_adapdata(&i2c->adapter, i2c);
926 ((rdev->family <= CHIP_RS480) ||
927 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
928 /* set the radeon hw i2c adapter */
929 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
930 "Radeon i2c hw bus %s", name);
931 i2c->adapter.algo = &radeon_i2c_algo;
932 ret = i2c_add_adapter(&i2c->adapter);
934 DRM_ERROR("Failed to register hw i2c %s\n", name);
937 } else if (rec->hw_capable &&
939 ASIC_IS_DCE3(rdev)) {
940 /* hw i2c using atom */
941 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
942 "Radeon i2c hw bus %s", name);
943 i2c->adapter.algo = &radeon_atom_i2c_algo;
944 ret = i2c_add_adapter(&i2c->adapter);
946 DRM_ERROR("Failed to register hw i2c %s\n", name);
950 /* set the radeon bit adapter */
951 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
952 "Radeon i2c bit bus %s", name);
953 i2c->adapter.algo_data = &i2c->algo.bit;
954 i2c->algo.bit.pre_xfer = pre_xfer;
955 i2c->algo.bit.post_xfer = post_xfer;
956 i2c->algo.bit.setsda = set_data;
957 i2c->algo.bit.setscl = set_clock;
958 i2c->algo.bit.getsda = get_data;
959 i2c->algo.bit.getscl = get_clock;
960 i2c->algo.bit.udelay = 10;
961 i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */
962 i2c->algo.bit.data = i2c;
963 ret = i2c_bit_add_bus(&i2c->adapter);
965 DRM_ERROR("Failed to register bit i2c %s\n", name);
977 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
978 struct radeon_i2c_bus_rec *rec,
981 struct radeon_i2c_chan *i2c;
984 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
989 i2c->adapter.owner = THIS_MODULE;
990 i2c->adapter.class = I2C_CLASS_DDC;
991 i2c->adapter.dev.parent = &dev->pdev->dev;
993 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
994 "Radeon aux bus %s", name);
995 i2c_set_adapdata(&i2c->adapter, i2c);
996 i2c->adapter.algo_data = &i2c->algo.dp;
997 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
998 i2c->algo.dp.address = 0;
999 ret = i2c_dp_aux_add_bus(&i2c->adapter);
1001 DRM_INFO("Failed to register i2c %s\n", name);
1012 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
1016 i2c_del_adapter(&i2c->adapter);
1020 /* Add the default buses */
1021 void radeon_i2c_init(struct radeon_device *rdev)
1024 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
1026 if (rdev->is_atom_bios)
1027 radeon_atombios_i2c_init(rdev);
1029 radeon_combios_i2c_init(rdev);
1032 /* remove all the buses */
1033 void radeon_i2c_fini(struct radeon_device *rdev)
1037 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1038 if (rdev->i2c_bus[i]) {
1039 radeon_i2c_destroy(rdev->i2c_bus[i]);
1040 rdev->i2c_bus[i] = NULL;
1045 /* Add additional buses */
1046 void radeon_i2c_add(struct radeon_device *rdev,
1047 struct radeon_i2c_bus_rec *rec,
1050 struct drm_device *dev = rdev->ddev;
1053 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1054 if (!rdev->i2c_bus[i]) {
1055 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1061 /* looks up bus based on id */
1062 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1063 struct radeon_i2c_bus_rec *i2c_bus)
1067 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1068 if (rdev->i2c_bus[i] &&
1069 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1070 return rdev->i2c_bus[i];
1076 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1081 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1088 struct i2c_msg msgs[] = {
1106 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1108 DRM_DEBUG("val = 0x%02x\n", *val);
1110 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1115 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1121 struct i2c_msg msg = {
1131 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1132 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1136 /* ddc router switching */
1137 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1141 if (!radeon_connector->router.ddc_valid)
1144 if (!radeon_connector->router_bus)
1147 radeon_i2c_get_byte(radeon_connector->router_bus,
1148 radeon_connector->router.i2c_addr,
1150 val &= ~radeon_connector->router.ddc_mux_control_pin;
1151 radeon_i2c_put_byte(radeon_connector->router_bus,
1152 radeon_connector->router.i2c_addr,
1154 radeon_i2c_get_byte(radeon_connector->router_bus,
1155 radeon_connector->router.i2c_addr,
1157 val &= ~radeon_connector->router.ddc_mux_control_pin;
1158 val |= radeon_connector->router.ddc_mux_state;
1159 radeon_i2c_put_byte(radeon_connector->router_bus,
1160 radeon_connector->router.i2c_addr,
1164 /* clock/data router switching */
1165 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1169 if (!radeon_connector->router.cd_valid)
1172 if (!radeon_connector->router_bus)
1175 radeon_i2c_get_byte(radeon_connector->router_bus,
1176 radeon_connector->router.i2c_addr,
1178 val &= ~radeon_connector->router.cd_mux_control_pin;
1179 radeon_i2c_put_byte(radeon_connector->router_bus,
1180 radeon_connector->router.i2c_addr,
1182 radeon_i2c_get_byte(radeon_connector->router_bus,
1183 radeon_connector->router.i2c_addr,
1185 val &= ~radeon_connector->router.cd_mux_control_pin;
1186 val |= radeon_connector->router.cd_mux_state;
1187 radeon_i2c_put_byte(radeon_connector->router_bus,
1188 radeon_connector->router.i2c_addr,