2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
35 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
37 u8 out_buf[] = { 0x0, 0x0};
40 struct i2c_msg msgs[] = {
55 /* on hw with routers, select right port */
56 if (radeon_connector->router.ddc_valid)
57 radeon_router_select_ddc_port(radeon_connector);
59 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
68 static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
70 struct radeon_device *rdev = i2c->dev->dev_private;
71 struct radeon_i2c_bus_rec *rec = &i2c->rec;
74 /* RV410 appears to have a bug where the hw i2c in reset
75 * holds the i2c port in a bad state - switch hw i2c away before
76 * doing DDC - do this for all r200s/r300s/r400s for safety sake
78 if (rec->hw_capable) {
79 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
82 if (rdev->family >= CHIP_RV350)
83 reg = RADEON_GPIO_MONID;
84 else if ((rdev->family == CHIP_R300) ||
85 (rdev->family == CHIP_R350))
86 reg = RADEON_GPIO_DVI_DDC;
88 reg = RADEON_GPIO_CRT2_DDC;
90 mutex_lock(&rdev->dc_hw_i2c_mutex);
91 if (rec->a_clk_reg == reg) {
92 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
93 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
95 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
96 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
98 mutex_unlock(&rdev->dc_hw_i2c_mutex);
102 /* switch the pads to ddc mode */
103 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
104 temp = RREG32(rec->mask_clk_reg);
106 WREG32(rec->mask_clk_reg, temp);
109 /* clear the output pin values */
110 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
111 WREG32(rec->a_clk_reg, temp);
113 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
114 WREG32(rec->a_data_reg, temp);
116 /* set the pins to input */
117 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
118 WREG32(rec->en_clk_reg, temp);
120 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
121 WREG32(rec->en_data_reg, temp);
123 /* mask the gpio pins for software use */
124 temp = RREG32(rec->mask_clk_reg);
126 temp |= rec->mask_clk_mask;
128 temp &= ~rec->mask_clk_mask;
129 WREG32(rec->mask_clk_reg, temp);
130 temp = RREG32(rec->mask_clk_reg);
132 temp = RREG32(rec->mask_data_reg);
134 temp |= rec->mask_data_mask;
136 temp &= ~rec->mask_data_mask;
137 WREG32(rec->mask_data_reg, temp);
138 temp = RREG32(rec->mask_data_reg);
141 static int get_clock(void *i2c_priv)
143 struct radeon_i2c_chan *i2c = i2c_priv;
144 struct radeon_device *rdev = i2c->dev->dev_private;
145 struct radeon_i2c_bus_rec *rec = &i2c->rec;
148 /* read the value off the pin */
149 val = RREG32(rec->y_clk_reg);
150 val &= rec->y_clk_mask;
156 static int get_data(void *i2c_priv)
158 struct radeon_i2c_chan *i2c = i2c_priv;
159 struct radeon_device *rdev = i2c->dev->dev_private;
160 struct radeon_i2c_bus_rec *rec = &i2c->rec;
163 /* read the value off the pin */
164 val = RREG32(rec->y_data_reg);
165 val &= rec->y_data_mask;
170 static void set_clock(void *i2c_priv, int clock)
172 struct radeon_i2c_chan *i2c = i2c_priv;
173 struct radeon_device *rdev = i2c->dev->dev_private;
174 struct radeon_i2c_bus_rec *rec = &i2c->rec;
177 /* set pin direction */
178 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
179 val |= clock ? 0 : rec->en_clk_mask;
180 WREG32(rec->en_clk_reg, val);
183 static void set_data(void *i2c_priv, int data)
185 struct radeon_i2c_chan *i2c = i2c_priv;
186 struct radeon_device *rdev = i2c->dev->dev_private;
187 struct radeon_i2c_bus_rec *rec = &i2c->rec;
190 /* set pin direction */
191 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
192 val |= data ? 0 : rec->en_data_mask;
193 WREG32(rec->en_data_reg, val);
196 static int pre_xfer(struct i2c_adapter *i2c_adap)
198 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
200 radeon_i2c_do_lock(i2c, 1);
205 static void post_xfer(struct i2c_adapter *i2c_adap)
207 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
209 radeon_i2c_do_lock(i2c, 0);
214 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
216 u32 sclk = rdev->pm.current_sclk;
222 switch (rdev->family) {
236 nm = (sclk * 10) / (i2c_clock * 4);
237 for (loop = 1; loop < 255; loop++) {
238 if ((nm / loop) < loop)
243 prescale = m | (n << 8);
251 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
265 if (rdev->family == CHIP_R520)
266 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
268 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
294 DRM_ERROR("i2c: unhandled radeon chip\n");
301 /* hw i2c engine for r1xx-4xx hardware
302 * hw can buffer up to 15 bytes
304 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
305 struct i2c_msg *msgs, int num)
307 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
308 struct radeon_device *rdev = i2c->dev->dev_private;
309 struct radeon_i2c_bus_rec *rec = &i2c->rec;
311 int i, j, k, ret = num;
313 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
316 mutex_lock(&rdev->dc_hw_i2c_mutex);
317 /* take the pm lock since we need a constant sclk */
318 mutex_lock(&rdev->pm.mutex);
320 prescale = radeon_get_i2c_prescale(rdev);
322 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
323 RADEON_I2C_DRIVE_EN |
328 if (rdev->is_atom_bios) {
329 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
330 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
334 i2c_cntl_0 = RADEON_I2C_CNTL_0;
335 i2c_cntl_1 = RADEON_I2C_CNTL_1;
336 i2c_data = RADEON_I2C_DATA;
338 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
339 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
340 i2c_data = RADEON_DVI_I2C_DATA;
342 switch (rdev->family) {
349 switch (rec->mask_clk_reg) {
350 case RADEON_GPIO_DVI_DDC:
351 /* no gpio select bit */
354 DRM_ERROR("gpio not supported with hw i2c\n");
360 /* only bit 4 on r200 */
361 switch (rec->mask_clk_reg) {
362 case RADEON_GPIO_DVI_DDC:
363 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
365 case RADEON_GPIO_MONID:
366 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
369 DRM_ERROR("gpio not supported with hw i2c\n");
377 switch (rec->mask_clk_reg) {
378 case RADEON_GPIO_DVI_DDC:
379 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
381 case RADEON_GPIO_VGA_DDC:
382 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
384 case RADEON_GPIO_CRT2_DDC:
385 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
388 DRM_ERROR("gpio not supported with hw i2c\n");
395 /* only bit 4 on r300/r350 */
396 switch (rec->mask_clk_reg) {
397 case RADEON_GPIO_VGA_DDC:
398 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
400 case RADEON_GPIO_DVI_DDC:
401 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
404 DRM_ERROR("gpio not supported with hw i2c\n");
417 switch (rec->mask_clk_reg) {
418 case RADEON_GPIO_VGA_DDC:
419 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
421 case RADEON_GPIO_DVI_DDC:
422 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
424 case RADEON_GPIO_MONID:
425 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
428 DRM_ERROR("gpio not supported with hw i2c\n");
434 DRM_ERROR("unsupported asic\n");
441 /* check for bus probe */
443 if ((num == 1) && (p->len == 0)) {
444 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
447 RADEON_I2C_SOFT_RST));
448 WREG32(i2c_data, (p->addr << 1) & 0xff);
450 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
451 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
453 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
454 WREG32(i2c_cntl_0, reg);
455 for (k = 0; k < 32; k++) {
457 tmp = RREG32(i2c_cntl_0);
458 if (tmp & RADEON_I2C_GO)
460 tmp = RREG32(i2c_cntl_0);
461 if (tmp & RADEON_I2C_DONE)
464 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
465 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
473 for (i = 0; i < num; i++) {
475 for (j = 0; j < p->len; j++) {
476 if (p->flags & I2C_M_RD) {
477 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
480 RADEON_I2C_SOFT_RST));
481 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
482 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
483 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
485 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
486 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
487 for (k = 0; k < 32; k++) {
489 tmp = RREG32(i2c_cntl_0);
490 if (tmp & RADEON_I2C_GO)
492 tmp = RREG32(i2c_cntl_0);
493 if (tmp & RADEON_I2C_DONE)
496 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
497 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
502 p->buf[j] = RREG32(i2c_data) & 0xff;
504 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
507 RADEON_I2C_SOFT_RST));
508 WREG32(i2c_data, (p->addr << 1) & 0xff);
509 WREG32(i2c_data, p->buf[j]);
510 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
511 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
513 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
514 WREG32(i2c_cntl_0, reg);
515 for (k = 0; k < 32; k++) {
517 tmp = RREG32(i2c_cntl_0);
518 if (tmp & RADEON_I2C_GO)
520 tmp = RREG32(i2c_cntl_0);
521 if (tmp & RADEON_I2C_DONE)
524 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
525 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
535 WREG32(i2c_cntl_0, 0);
536 WREG32(i2c_cntl_1, 0);
537 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
540 RADEON_I2C_SOFT_RST));
542 if (rdev->is_atom_bios) {
543 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
544 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
545 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
548 mutex_unlock(&rdev->pm.mutex);
549 mutex_unlock(&rdev->dc_hw_i2c_mutex);
554 /* hw i2c engine for r5xx hardware
555 * hw can buffer up to 15 bytes
557 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
558 struct i2c_msg *msgs, int num)
560 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
561 struct radeon_device *rdev = i2c->dev->dev_private;
562 struct radeon_i2c_bus_rec *rec = &i2c->rec;
564 int i, j, remaining, current_count, buffer_offset, ret = num;
569 mutex_lock(&rdev->dc_hw_i2c_mutex);
570 /* take the pm lock since we need a constant sclk */
571 mutex_lock(&rdev->pm.mutex);
573 prescale = radeon_get_i2c_prescale(rdev);
575 /* clear gpio mask bits */
576 tmp = RREG32(rec->mask_clk_reg);
577 tmp &= ~rec->mask_clk_mask;
578 WREG32(rec->mask_clk_reg, tmp);
579 tmp = RREG32(rec->mask_clk_reg);
581 tmp = RREG32(rec->mask_data_reg);
582 tmp &= ~rec->mask_data_mask;
583 WREG32(rec->mask_data_reg, tmp);
584 tmp = RREG32(rec->mask_data_reg);
586 /* clear pin values */
587 tmp = RREG32(rec->a_clk_reg);
588 tmp &= ~rec->a_clk_mask;
589 WREG32(rec->a_clk_reg, tmp);
590 tmp = RREG32(rec->a_clk_reg);
592 tmp = RREG32(rec->a_data_reg);
593 tmp &= ~rec->a_data_mask;
594 WREG32(rec->a_data_reg, tmp);
595 tmp = RREG32(rec->a_data_reg);
597 /* set the pins to input */
598 tmp = RREG32(rec->en_clk_reg);
599 tmp &= ~rec->en_clk_mask;
600 WREG32(rec->en_clk_reg, tmp);
601 tmp = RREG32(rec->en_clk_reg);
603 tmp = RREG32(rec->en_data_reg);
604 tmp &= ~rec->en_data_mask;
605 WREG32(rec->en_data_reg, tmp);
606 tmp = RREG32(rec->en_data_reg);
609 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
610 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
611 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
612 saved2 = RREG32(0x494);
613 WREG32(0x494, saved2 | 0x1);
615 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
616 for (i = 0; i < 50; i++) {
618 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
622 DRM_ERROR("failed to get i2c bus\n");
627 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
628 switch (rec->mask_clk_reg) {
629 case AVIVO_DC_GPIO_DDC1_MASK:
630 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
632 case AVIVO_DC_GPIO_DDC2_MASK:
633 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
635 case AVIVO_DC_GPIO_DDC3_MASK:
636 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
639 DRM_ERROR("gpio not supported with hw i2c\n");
644 /* check for bus probe */
646 if ((num == 1) && (p->len == 0)) {
647 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
650 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
652 WREG32(AVIVO_DC_I2C_RESET, 0);
654 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
655 WREG32(AVIVO_DC_I2C_DATA, 0);
657 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
658 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
659 AVIVO_DC_I2C_DATA_COUNT(1) |
661 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
662 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
663 for (j = 0; j < 200; j++) {
665 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
666 if (tmp & AVIVO_DC_I2C_GO)
668 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
669 if (tmp & AVIVO_DC_I2C_DONE)
672 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
673 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
681 for (i = 0; i < num; i++) {
685 if (p->flags & I2C_M_RD) {
690 current_count = remaining;
691 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
694 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
696 WREG32(AVIVO_DC_I2C_RESET, 0);
698 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
699 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
700 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
701 AVIVO_DC_I2C_DATA_COUNT(current_count) |
703 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
704 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
705 for (j = 0; j < 200; j++) {
707 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
708 if (tmp & AVIVO_DC_I2C_GO)
710 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
711 if (tmp & AVIVO_DC_I2C_DONE)
714 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
715 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
720 for (j = 0; j < current_count; j++)
721 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
722 remaining -= current_count;
723 buffer_offset += current_count;
730 current_count = remaining;
731 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
734 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
736 WREG32(AVIVO_DC_I2C_RESET, 0);
738 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
739 for (j = 0; j < current_count; j++)
740 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
742 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
743 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
744 AVIVO_DC_I2C_DATA_COUNT(current_count) |
746 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
747 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
748 for (j = 0; j < 200; j++) {
750 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
751 if (tmp & AVIVO_DC_I2C_GO)
753 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
754 if (tmp & AVIVO_DC_I2C_DONE)
757 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
758 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
763 remaining -= current_count;
764 buffer_offset += current_count;
770 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
773 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
775 WREG32(AVIVO_DC_I2C_RESET, 0);
777 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
778 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
779 WREG32(0x494, saved2);
780 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
781 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
782 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
784 mutex_unlock(&rdev->pm.mutex);
785 mutex_unlock(&rdev->dc_hw_i2c_mutex);
790 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
791 struct i2c_msg *msgs, int num)
793 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
794 struct radeon_device *rdev = i2c->dev->dev_private;
795 struct radeon_i2c_bus_rec *rec = &i2c->rec;
798 switch (rdev->family) {
817 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
822 /* XXX fill in hw i2c implementation */
831 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
833 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
839 /* XXX fill in hw i2c implementation */
849 /* XXX fill in hw i2c implementation */
856 /* XXX fill in hw i2c implementation */
859 DRM_ERROR("i2c: unhandled radeon chip\n");
867 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
869 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
872 static const struct i2c_algorithm radeon_i2c_algo = {
873 .master_xfer = radeon_hw_i2c_xfer,
874 .functionality = radeon_hw_i2c_func,
877 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
878 struct radeon_i2c_bus_rec *rec,
881 struct radeon_device *rdev = dev->dev_private;
882 struct radeon_i2c_chan *i2c;
885 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
890 i2c->adapter.owner = THIS_MODULE;
892 i2c_set_adapdata(&i2c->adapter, i2c);
896 ((rdev->family <= CHIP_RS480) ||
897 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
898 /* set the radeon hw i2c adapter */
899 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
900 "Radeon i2c hw bus %s", name);
901 i2c->adapter.algo = &radeon_i2c_algo;
902 ret = i2c_add_adapter(&i2c->adapter);
904 DRM_ERROR("Failed to register hw i2c %s\n", name);
908 /* set the radeon bit adapter */
909 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
910 "Radeon i2c bit bus %s", name);
911 i2c->adapter.algo_data = &i2c->algo.bit;
912 i2c->algo.bit.pre_xfer = pre_xfer;
913 i2c->algo.bit.post_xfer = post_xfer;
914 i2c->algo.bit.setsda = set_data;
915 i2c->algo.bit.setscl = set_clock;
916 i2c->algo.bit.getsda = get_data;
917 i2c->algo.bit.getscl = get_clock;
918 i2c->algo.bit.udelay = 20;
919 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
920 * make this, 2 jiffies is a lot more reliable */
921 i2c->algo.bit.timeout = 2;
922 i2c->algo.bit.data = i2c;
923 ret = i2c_bit_add_bus(&i2c->adapter);
925 DRM_ERROR("Failed to register bit i2c %s\n", name);
937 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
938 struct radeon_i2c_bus_rec *rec,
941 struct radeon_i2c_chan *i2c;
944 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
949 i2c->adapter.owner = THIS_MODULE;
951 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
952 "Radeon aux bus %s", name);
953 i2c_set_adapdata(&i2c->adapter, i2c);
954 i2c->adapter.algo_data = &i2c->algo.dp;
955 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
956 i2c->algo.dp.address = 0;
957 ret = i2c_dp_aux_add_bus(&i2c->adapter);
959 DRM_INFO("Failed to register i2c %s\n", name);
970 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
974 i2c_del_adapter(&i2c->adapter);
978 /* Add the default buses */
979 void radeon_i2c_init(struct radeon_device *rdev)
981 if (rdev->is_atom_bios)
982 radeon_atombios_i2c_init(rdev);
984 radeon_combios_i2c_init(rdev);
987 /* remove all the buses */
988 void radeon_i2c_fini(struct radeon_device *rdev)
992 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
993 if (rdev->i2c_bus[i]) {
994 radeon_i2c_destroy(rdev->i2c_bus[i]);
995 rdev->i2c_bus[i] = NULL;
1000 /* Add additional buses */
1001 void radeon_i2c_add(struct radeon_device *rdev,
1002 struct radeon_i2c_bus_rec *rec,
1005 struct drm_device *dev = rdev->ddev;
1008 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1009 if (!rdev->i2c_bus[i]) {
1010 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1016 /* looks up bus based on id */
1017 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1018 struct radeon_i2c_bus_rec *i2c_bus)
1022 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1023 if (rdev->i2c_bus[i] &&
1024 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1025 return rdev->i2c_bus[i];
1031 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1036 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1043 struct i2c_msg msgs[] = {
1061 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1063 DRM_DEBUG("val = 0x%02x\n", *val);
1065 DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
1070 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1076 struct i2c_msg msg = {
1086 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1087 DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",
1091 /* ddc router switching */
1092 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1096 if (!radeon_connector->router.ddc_valid)
1099 radeon_i2c_get_byte(radeon_connector->router_bus,
1100 radeon_connector->router.i2c_addr,
1102 val &= ~radeon_connector->router.ddc_mux_control_pin;
1103 radeon_i2c_put_byte(radeon_connector->router_bus,
1104 radeon_connector->router.i2c_addr,
1106 radeon_i2c_get_byte(radeon_connector->router_bus,
1107 radeon_connector->router.i2c_addr,
1109 val &= ~radeon_connector->router.ddc_mux_control_pin;
1110 val |= radeon_connector->router.ddc_mux_state;
1111 radeon_i2c_put_byte(radeon_connector->router_bus,
1112 radeon_connector->router.i2c_addr,
1116 /* clock/data router switching */
1117 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1121 if (!radeon_connector->router.cd_valid)
1124 radeon_i2c_get_byte(radeon_connector->router_bus,
1125 radeon_connector->router.i2c_addr,
1127 val &= ~radeon_connector->router.cd_mux_control_pin;
1128 radeon_i2c_put_byte(radeon_connector->router_bus,
1129 radeon_connector->router.i2c_addr,
1131 radeon_i2c_get_byte(radeon_connector->router_bus,
1132 radeon_connector->router.i2c_addr,
1134 val &= ~radeon_connector->router.cd_mux_control_pin;
1135 val |= radeon_connector->router.cd_mux_state;
1136 radeon_i2c_put_byte(radeon_connector->router_bus,
1137 radeon_connector->router.i2c_addr,