2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
34 * IBs (Indirect Buffers) and areas of GPU accessible memory where
35 * commands are stored. You can put a pointer to the IB in the
36 * command ring and the hw will fetch the commands from the IB
37 * and execute them. Generally userspace acceleration drivers
38 * produce command buffers which are send to the kernel and
39 * put in IBs for execution by the requested ring.
41 static int radeon_debugfs_sa_init(struct radeon_device *rdev);
44 * radeon_ib_get - request an IB (Indirect Buffer)
46 * @rdev: radeon_device pointer
47 * @ring: ring index the IB is associated with
48 * @ib: IB object returned
49 * @size: requested IB size
51 * Request an IB (all asics). IBs are allocated using the
53 * Returns 0 on success, error on failure.
55 int radeon_ib_get(struct radeon_device *rdev, int ring,
56 struct radeon_ib *ib, struct radeon_vm *vm,
61 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
63 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
67 r = radeon_semaphore_create(rdev, &ib->semaphore);
74 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
77 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
78 * space and soffset is the offset inside the pool bo
80 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
82 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
84 ib->is_const_ib = false;
90 * radeon_ib_free - free an IB (Indirect Buffer)
92 * @rdev: radeon_device pointer
93 * @ib: IB object to free
95 * Free an IB (all asics).
97 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
99 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
100 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
101 radeon_fence_unref(&ib->fence);
105 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
107 * @rdev: radeon_device pointer
108 * @ib: IB object to schedule
109 * @const_ib: Const IB to schedule (SI only)
110 * @hdp_flush: Whether or not to perform an HDP cache flush
112 * Schedule an IB on the associated ring (all asics).
113 * Returns 0 on success, error on failure.
115 * On SI, there are two parallel engines fed from the primary ring,
116 * the CE (Constant Engine) and the DE (Drawing Engine). Since
117 * resource descriptors have moved to memory, the CE allows you to
118 * prime the caches while the DE is updating register state so that
119 * the resource descriptors will be already in cache when the draw is
120 * processed. To accomplish this, the userspace driver submits two
121 * IBs, one for the CE and one for the DE. If there is a CE IB (called
122 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
123 * to SI there was just a DE IB.
125 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
126 struct radeon_ib *const_ib, bool hdp_flush)
128 struct radeon_ring *ring = &rdev->ring[ib->ring];
131 if (!ib->length_dw || !ring->ready) {
132 /* TODO: Nothings in the ib we should report. */
133 dev_err(rdev->dev, "couldn't schedule ib\n");
137 /* 64 dwords should be enough for fence too */
138 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
140 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
144 /* grab a vm id if necessary */
146 struct radeon_fence *vm_id_fence;
147 vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
148 radeon_semaphore_sync_fence(ib->semaphore, vm_id_fence);
151 /* sync with other rings */
152 r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring);
154 dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
155 radeon_ring_unlock_undo(rdev, ring);
160 radeon_vm_flush(rdev, ib->vm, ib->ring);
163 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
164 radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
166 radeon_ring_ib_execute(rdev, ib->ring, ib);
167 r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
169 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
170 radeon_ring_unlock_undo(rdev, ring);
174 const_ib->fence = radeon_fence_ref(ib->fence);
178 radeon_vm_fence(rdev, ib->vm, ib->fence);
180 radeon_ring_unlock_commit(rdev, ring, hdp_flush);
185 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
187 * @rdev: radeon_device pointer
189 * Initialize the suballocator to manage a pool of memory
190 * for use as IBs (all asics).
191 * Returns 0 on success, error on failure.
193 int radeon_ib_pool_init(struct radeon_device *rdev)
197 if (rdev->ib_pool_ready) {
201 if (rdev->family >= CHIP_BONAIRE) {
202 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
203 RADEON_IB_POOL_SIZE*64*1024,
204 RADEON_GPU_PAGE_SIZE,
205 RADEON_GEM_DOMAIN_GTT,
208 /* Before CIK, it's better to stick to cacheable GTT due
209 * to the command stream checking
211 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
212 RADEON_IB_POOL_SIZE*64*1024,
213 RADEON_GPU_PAGE_SIZE,
214 RADEON_GEM_DOMAIN_GTT, 0);
220 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
225 rdev->ib_pool_ready = true;
226 if (radeon_debugfs_sa_init(rdev)) {
227 dev_err(rdev->dev, "failed to register debugfs file for SA\n");
233 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
235 * @rdev: radeon_device pointer
237 * Tear down the suballocator managing the pool of memory
238 * for use as IBs (all asics).
240 void radeon_ib_pool_fini(struct radeon_device *rdev)
242 if (rdev->ib_pool_ready) {
243 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
244 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
245 rdev->ib_pool_ready = false;
250 * radeon_ib_ring_tests - test IBs on the rings
252 * @rdev: radeon_device pointer
254 * Test an IB (Indirect Buffer) on each ring.
255 * If the test fails, disable the ring.
256 * Returns 0 on success, error if the primary GFX ring
259 int radeon_ib_ring_tests(struct radeon_device *rdev)
264 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
265 struct radeon_ring *ring = &rdev->ring[i];
270 r = radeon_ib_test(rdev, i, ring);
272 radeon_fence_driver_force_completion(rdev, i);
274 rdev->needs_reset = false;
276 if (i == RADEON_RING_TYPE_GFX_INDEX) {
277 /* oh, oh, that's really bad */
278 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
279 rdev->accel_working = false;
283 /* still not good, but we can live with it */
284 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
294 #if defined(CONFIG_DEBUG_FS)
296 static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
298 struct drm_info_node *node = (struct drm_info_node *) m->private;
299 struct drm_device *dev = node->minor->dev;
300 struct radeon_device *rdev = dev->dev_private;
302 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
308 static struct drm_info_list radeon_debugfs_sa_list[] = {
309 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
314 static int radeon_debugfs_sa_init(struct radeon_device *rdev)
316 #if defined(CONFIG_DEBUG_FS)
317 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);