2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
27 * Kernel port Author: Dave Airlie
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_dp_helper.h>
36 #include <drm/drm_fixed.h>
37 #include <drm/drm_crtc_helper.h>
38 #include <linux/i2c.h>
39 #include <linux/i2c-algo-bit.h>
44 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49 enum radeon_rmx_type {
68 enum radeon_underscan_type {
81 RADEON_HPD_NONE = 0xff,
84 #define RADEON_MAX_I2C_BUS 16
86 /* radeon gpio-based i2c
87 * 1. "mask" reg and bits
88 * grabs the gpio pins for software use
93 * 3. "en" reg and bits
94 * sets the pin direction
100 struct radeon_i2c_bus_rec {
102 /* id used by atom */
104 /* id used by atom */
105 enum radeon_hpd_id hpd;
106 /* can be used with hw i2c engine */
108 /* uses multi-media i2c engine */
111 uint32_t mask_clk_reg;
112 uint32_t mask_data_reg;
116 uint32_t en_data_reg;
119 uint32_t mask_clk_mask;
120 uint32_t mask_data_mask;
122 uint32_t a_data_mask;
123 uint32_t en_clk_mask;
124 uint32_t en_data_mask;
126 uint32_t y_data_mask;
129 struct radeon_tmds_pll {
134 #define RADEON_MAX_BIOS_CONNECTOR 16
137 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
138 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
139 #define RADEON_PLL_USE_REF_DIV (1 << 2)
140 #define RADEON_PLL_LEGACY (1 << 3)
141 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
142 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
143 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
144 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
145 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
146 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
147 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
148 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
149 #define RADEON_PLL_USE_POST_DIV (1 << 12)
150 #define RADEON_PLL_IS_LCD (1 << 13)
151 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
154 /* reference frequency */
155 uint32_t reference_freq;
158 uint32_t reference_div;
161 /* pll in/out limits */
164 uint32_t pll_out_min;
165 uint32_t pll_out_max;
166 uint32_t lcd_pll_out_min;
167 uint32_t lcd_pll_out_max;
171 uint32_t min_ref_div;
172 uint32_t max_ref_div;
173 uint32_t min_post_div;
174 uint32_t max_post_div;
175 uint32_t min_feedback_div;
176 uint32_t max_feedback_div;
177 uint32_t min_frac_feedback_div;
178 uint32_t max_frac_feedback_div;
180 /* flags for the current clock */
187 struct radeon_i2c_chan {
188 struct i2c_adapter adapter;
189 struct drm_device *dev;
191 struct i2c_algo_bit_data bit;
192 struct i2c_algo_dp_aux_data dp;
194 struct radeon_i2c_bus_rec rec;
197 /* mostly for macs, but really any system without connector tables */
198 enum radeon_connector_table {
202 CT_POWERBOOK_EXTERNAL,
203 CT_POWERBOOK_INTERNAL,
216 enum radeon_dvo_chip {
226 bool last_buffer_filled_status;
228 struct r600_audio_pin *pin;
231 struct radeon_mode_info {
232 struct atom_context *atom_context;
233 struct card_info *atom_card_info;
234 enum radeon_connector_table connector_table;
235 bool mode_config_initialized;
236 struct radeon_crtc *crtcs[6];
237 struct radeon_afmt *afmt[7];
238 /* DVI-I properties */
239 struct drm_property *coherent_mode_property;
240 /* DAC enable load detect */
241 struct drm_property *load_detect_property;
243 struct drm_property *tv_std_property;
244 /* legacy TMDS PLL detect */
245 struct drm_property *tmds_pll_property;
247 struct drm_property *underscan_property;
248 struct drm_property *underscan_hborder_property;
249 struct drm_property *underscan_vborder_property;
250 /* hardcoded DFP edid from BIOS */
251 struct edid *bios_hardcoded_edid;
252 int bios_hardcoded_edid_size;
254 /* pointer to fbdev info structure */
255 struct radeon_fbdev *rfbdev;
258 /* pointer to backlight encoder */
259 struct radeon_encoder *bl_encoder;
262 #define RADEON_MAX_BL_LEVEL 0xFF
264 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
266 struct radeon_backlight_privdata {
267 struct radeon_encoder *encoder;
273 #define MAX_H_CODE_TIMING_LEN 32
274 #define MAX_V_CODE_TIMING_LEN 32
276 /* need to store these as reading
277 back code tables is excessive */
278 struct radeon_tv_regs {
280 uint32_t timing_cntl;
284 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
285 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
288 struct radeon_atom_ss {
301 struct drm_crtc base;
303 u16 lut_r[256], lut_g[256], lut_b[256];
306 uint32_t crtc_offset;
307 struct drm_gem_object *cursor_bo;
308 uint64_t cursor_addr;
311 int max_cursor_width;
312 int max_cursor_height;
313 uint32_t legacy_display_base_addr;
314 uint32_t legacy_cursor_offset;
315 enum radeon_rmx_type rmx_type;
320 struct drm_display_mode native_mode;
323 struct radeon_unpin_work *unpin_work;
324 int deferred_flip_completion;
326 struct radeon_atom_ss ss;
330 u32 pll_reference_div;
333 struct drm_encoder *encoder;
334 struct drm_connector *connector;
339 struct drm_display_mode hw_mode;
342 struct radeon_encoder_primary_dac {
343 /* legacy primary dac */
344 uint32_t ps2_pdac_adj;
347 struct radeon_encoder_lvds {
349 uint16_t panel_vcc_delay;
350 uint8_t panel_pwr_delay;
351 uint8_t panel_digon_delay;
352 uint8_t panel_blon_delay;
353 uint16_t panel_ref_divider;
354 uint8_t panel_post_divider;
355 uint16_t panel_fb_divider;
356 bool use_bios_dividers;
357 uint32_t lvds_gen_cntl;
359 struct drm_display_mode native_mode;
360 struct backlight_device *bl_dev;
362 uint8_t backlight_level;
365 struct radeon_encoder_tv_dac {
367 uint32_t ps2_tvdac_adj;
368 uint32_t ntsc_tvdac_adj;
369 uint32_t pal_tvdac_adj;
374 int supported_tv_stds;
376 enum radeon_tv_std tv_std;
377 struct radeon_tv_regs tv;
380 struct radeon_encoder_int_tmds {
381 /* legacy int tmds */
382 struct radeon_tmds_pll tmds_pll[4];
385 struct radeon_encoder_ext_tmds {
387 struct radeon_i2c_chan *i2c_bus;
389 enum radeon_dvo_chip dvo_chip;
392 /* spread spectrum */
393 struct radeon_encoder_atom_dig {
397 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
400 uint16_t panel_pwr_delay;
403 struct drm_display_mode native_mode;
404 struct backlight_device *bl_dev;
406 uint8_t backlight_level;
408 struct radeon_afmt *afmt;
411 struct radeon_encoder_atom_dac {
412 enum radeon_tv_std tv_std;
415 struct radeon_encoder {
416 struct drm_encoder base;
417 uint32_t encoder_enum;
420 uint32_t active_device;
422 uint32_t pixel_clock;
423 enum radeon_rmx_type rmx_type;
424 enum radeon_underscan_type underscan_type;
425 uint32_t underscan_hborder;
426 uint32_t underscan_vborder;
427 struct drm_display_mode native_mode;
429 int audio_polling_active;
434 struct radeon_connector_atom_dig {
435 uint32_t igp_lane_info;
437 struct radeon_i2c_chan *dp_i2c_bus;
438 u8 dpcd[DP_RECEIVER_CAP_SIZE];
445 struct radeon_gpio_rec {
453 enum radeon_hpd_id hpd;
455 struct radeon_gpio_rec gpio;
458 struct radeon_router {
460 struct radeon_i2c_bus_rec i2c_info;
465 u8 ddc_mux_control_pin;
470 u8 cd_mux_control_pin;
474 struct radeon_connector {
475 struct drm_connector base;
476 uint32_t connector_id;
478 struct radeon_i2c_chan *ddc_bus;
479 /* some systems have an hdmi and vga port with a shared ddc line */
482 /* we need to mind the EDID between detect
483 and get modes due to analog/digital/tvencoder */
486 bool dac_load_detect;
487 bool detected_by_load; /* if the connection status was determined by load */
488 uint16_t connector_object_id;
489 struct radeon_hpd hpd;
490 struct radeon_router router;
491 struct radeon_i2c_chan *router_bus;
494 struct radeon_framebuffer {
495 struct drm_framebuffer base;
496 struct drm_gem_object *obj;
499 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
500 ((em) == ATOM_ENCODER_MODE_DP_MST))
502 struct atom_clock_dividers {
508 u32 whole_fb_div : 12;
509 u32 frac_fb_div : 14;
511 u32 frac_fb_div : 14;
512 u32 whole_fb_div : 12;
519 bool enable_post_div;
528 struct atom_mpll_param {
552 #define MEM_TYPE_GDDR5 0x50
553 #define MEM_TYPE_GDDR4 0x40
554 #define MEM_TYPE_GDDR3 0x30
555 #define MEM_TYPE_DDR2 0x20
556 #define MEM_TYPE_GDDR1 0x10
557 #define MEM_TYPE_DDR3 0xb0
558 #define MEM_TYPE_MASK 0xf0
560 struct atom_memory_info {
565 #define MAX_AC_TIMING_ENTRIES 16
567 struct atom_memory_clock_range_table
571 u32 mclk[MAX_AC_TIMING_ENTRIES];
574 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
575 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
577 struct atom_mc_reg_entry {
579 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
582 struct atom_mc_register_address {
587 struct atom_mc_reg_table {
590 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
591 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
594 #define MAX_VOLTAGE_ENTRIES 32
596 struct atom_voltage_table_entry
602 struct atom_voltage_table
607 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
610 extern enum radeon_tv_std
611 radeon_combios_get_tv_info(struct radeon_device *rdev);
612 extern enum radeon_tv_std
613 radeon_atombios_get_tv_info(struct radeon_device *rdev);
614 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
615 u16 *vddc, u16 *vddci, u16 *mvdd);
617 extern struct drm_connector *
618 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
619 extern struct drm_connector *
620 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
621 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
624 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
625 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
626 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
627 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
628 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
630 extern void radeon_connector_hotplug(struct drm_connector *connector);
631 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
632 struct drm_display_mode *mode);
633 extern void radeon_dp_set_link_config(struct drm_connector *connector,
634 const struct drm_display_mode *mode);
635 extern void radeon_dp_link_train(struct drm_encoder *encoder,
636 struct drm_connector *connector);
637 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
638 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
639 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
640 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
641 struct drm_connector *connector);
642 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
643 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
644 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
645 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
646 int action, uint8_t lane_num,
648 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
649 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
650 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
651 u8 write_byte, u8 *read_byte);
653 extern void radeon_i2c_init(struct radeon_device *rdev);
654 extern void radeon_i2c_fini(struct radeon_device *rdev);
655 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
656 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
657 extern void radeon_i2c_add(struct radeon_device *rdev,
658 struct radeon_i2c_bus_rec *rec,
660 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
661 struct radeon_i2c_bus_rec *i2c_bus);
662 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
663 struct radeon_i2c_bus_rec *rec,
665 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
666 struct radeon_i2c_bus_rec *rec,
668 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
669 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
673 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
677 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
678 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
679 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
680 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
682 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
684 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
685 struct radeon_atom_ss *ss,
687 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
688 struct radeon_atom_ss *ss,
691 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
693 uint32_t *dot_clock_p,
695 uint32_t *frac_fb_div_p,
697 uint32_t *post_div_p);
699 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
707 extern void radeon_setup_encoder_clones(struct drm_device *dev);
709 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
710 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
711 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
712 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
713 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
714 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
715 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
716 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
717 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
718 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
720 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
721 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
722 struct drm_framebuffer *old_fb);
723 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
724 struct drm_framebuffer *fb,
726 enum mode_set_atomic state);
727 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
728 struct drm_display_mode *mode,
729 struct drm_display_mode *adjusted_mode,
731 struct drm_framebuffer *old_fb);
732 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
734 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
735 struct drm_framebuffer *old_fb);
736 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
737 struct drm_framebuffer *fb,
739 enum mode_set_atomic state);
740 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
741 struct drm_framebuffer *fb,
742 int x, int y, int atomic);
743 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
744 struct drm_file *file_priv,
748 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
751 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
752 int *vpos, int *hpos);
754 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
756 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
757 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
758 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
759 extern struct radeon_encoder_atom_dig *
760 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
761 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
762 struct radeon_encoder_int_tmds *tmds);
763 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
764 struct radeon_encoder_int_tmds *tmds);
765 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
766 struct radeon_encoder_int_tmds *tmds);
767 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
768 struct radeon_encoder_ext_tmds *tmds);
769 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
770 struct radeon_encoder_ext_tmds *tmds);
771 extern struct radeon_encoder_primary_dac *
772 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
773 extern struct radeon_encoder_tv_dac *
774 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
775 extern struct radeon_encoder_lvds *
776 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
777 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
778 extern struct radeon_encoder_tv_dac *
779 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
780 extern struct radeon_encoder_primary_dac *
781 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
782 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
783 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
784 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
785 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
786 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
787 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
788 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
789 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
791 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
793 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
795 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
797 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
798 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
799 u16 blue, int regno);
800 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
801 u16 *blue, int regno);
802 int radeon_framebuffer_init(struct drm_device *dev,
803 struct radeon_framebuffer *rfb,
804 struct drm_mode_fb_cmd2 *mode_cmd,
805 struct drm_gem_object *obj);
807 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
808 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
809 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
810 void radeon_atombios_init_crtc(struct drm_device *dev,
811 struct radeon_crtc *radeon_crtc);
812 void radeon_legacy_init_crtc(struct drm_device *dev,
813 struct radeon_crtc *radeon_crtc);
815 void radeon_get_clock_info(struct drm_device *dev);
817 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
818 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
820 void radeon_enc_destroy(struct drm_encoder *encoder);
821 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
822 void radeon_combios_asic_init(struct drm_device *dev);
823 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
824 const struct drm_display_mode *mode,
825 struct drm_display_mode *adjusted_mode);
826 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
827 struct drm_display_mode *adjusted_mode);
828 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
831 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
832 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
833 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
834 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
835 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
836 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
837 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
838 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
839 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
840 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
841 struct drm_display_mode *mode,
842 struct drm_display_mode *adjusted_mode);
845 int radeon_fbdev_init(struct radeon_device *rdev);
846 void radeon_fbdev_fini(struct radeon_device *rdev);
847 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
848 int radeon_fbdev_total_size(struct radeon_device *rdev);
849 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
851 void radeon_fb_output_poll_changed(struct radeon_device *rdev);
853 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
855 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);