2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
27 * Kernel port Author: Dave Airlie
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_dp_helper.h>
36 #include <drm/drm_fixed.h>
37 #include <drm/drm_crtc_helper.h>
38 #include <linux/i2c.h>
39 #include <linux/i2c-algo-bit.h>
44 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49 enum radeon_rmx_type {
68 enum radeon_underscan_type {
81 RADEON_HPD_NONE = 0xff,
84 #define RADEON_MAX_I2C_BUS 16
86 /* radeon gpio-based i2c
87 * 1. "mask" reg and bits
88 * grabs the gpio pins for software use
93 * 3. "en" reg and bits
94 * sets the pin direction
100 struct radeon_i2c_bus_rec {
102 /* id used by atom */
104 /* id used by atom */
105 enum radeon_hpd_id hpd;
106 /* can be used with hw i2c engine */
108 /* uses multi-media i2c engine */
111 uint32_t mask_clk_reg;
112 uint32_t mask_data_reg;
116 uint32_t en_data_reg;
119 uint32_t mask_clk_mask;
120 uint32_t mask_data_mask;
122 uint32_t a_data_mask;
123 uint32_t en_clk_mask;
124 uint32_t en_data_mask;
126 uint32_t y_data_mask;
129 struct radeon_tmds_pll {
134 #define RADEON_MAX_BIOS_CONNECTOR 16
137 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
138 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
139 #define RADEON_PLL_USE_REF_DIV (1 << 2)
140 #define RADEON_PLL_LEGACY (1 << 3)
141 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
142 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
143 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
144 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
145 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
146 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
147 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
148 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
149 #define RADEON_PLL_USE_POST_DIV (1 << 12)
150 #define RADEON_PLL_IS_LCD (1 << 13)
151 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
154 /* reference frequency */
155 uint32_t reference_freq;
158 uint32_t reference_div;
161 /* pll in/out limits */
164 uint32_t pll_out_min;
165 uint32_t pll_out_max;
166 uint32_t lcd_pll_out_min;
167 uint32_t lcd_pll_out_max;
171 uint32_t min_ref_div;
172 uint32_t max_ref_div;
173 uint32_t min_post_div;
174 uint32_t max_post_div;
175 uint32_t min_feedback_div;
176 uint32_t max_feedback_div;
177 uint32_t min_frac_feedback_div;
178 uint32_t max_frac_feedback_div;
180 /* flags for the current clock */
187 struct radeon_i2c_chan {
188 struct i2c_adapter adapter;
189 struct drm_device *dev;
191 struct i2c_algo_bit_data bit;
192 struct i2c_algo_dp_aux_data dp;
194 struct radeon_i2c_bus_rec rec;
195 struct drm_dp_aux aux;
198 /* mostly for macs, but really any system without connector tables */
199 enum radeon_connector_table {
203 CT_POWERBOOK_EXTERNAL,
204 CT_POWERBOOK_INTERNAL,
217 enum radeon_dvo_chip {
227 bool last_buffer_filled_status;
229 struct r600_audio_pin *pin;
232 struct radeon_mode_info {
233 struct atom_context *atom_context;
234 struct card_info *atom_card_info;
235 enum radeon_connector_table connector_table;
236 bool mode_config_initialized;
237 struct radeon_crtc *crtcs[6];
238 struct radeon_afmt *afmt[7];
239 /* DVI-I properties */
240 struct drm_property *coherent_mode_property;
241 /* DAC enable load detect */
242 struct drm_property *load_detect_property;
244 struct drm_property *tv_std_property;
245 /* legacy TMDS PLL detect */
246 struct drm_property *tmds_pll_property;
248 struct drm_property *underscan_property;
249 struct drm_property *underscan_hborder_property;
250 struct drm_property *underscan_vborder_property;
252 struct drm_property *audio_property;
254 struct drm_property *dither_property;
255 /* hardcoded DFP edid from BIOS */
256 struct edid *bios_hardcoded_edid;
257 int bios_hardcoded_edid_size;
259 /* pointer to fbdev info structure */
260 struct radeon_fbdev *rfbdev;
263 /* pointer to backlight encoder */
264 struct radeon_encoder *bl_encoder;
267 #define RADEON_MAX_BL_LEVEL 0xFF
269 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
271 struct radeon_backlight_privdata {
272 struct radeon_encoder *encoder;
278 #define MAX_H_CODE_TIMING_LEN 32
279 #define MAX_V_CODE_TIMING_LEN 32
281 /* need to store these as reading
282 back code tables is excessive */
283 struct radeon_tv_regs {
285 uint32_t timing_cntl;
289 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
290 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
293 struct radeon_atom_ss {
295 uint16_t percentage_divider;
307 struct drm_crtc base;
309 u16 lut_r[256], lut_g[256], lut_b[256];
312 uint32_t crtc_offset;
313 struct drm_gem_object *cursor_bo;
314 uint64_t cursor_addr;
317 int max_cursor_width;
318 int max_cursor_height;
319 uint32_t legacy_display_base_addr;
320 uint32_t legacy_cursor_offset;
321 enum radeon_rmx_type rmx_type;
326 struct drm_display_mode native_mode;
329 struct radeon_unpin_work *unpin_work;
330 int deferred_flip_completion;
332 struct radeon_atom_ss ss;
336 u32 pll_reference_div;
339 struct drm_encoder *encoder;
340 struct drm_connector *connector;
345 struct drm_display_mode hw_mode;
348 struct radeon_encoder_primary_dac {
349 /* legacy primary dac */
350 uint32_t ps2_pdac_adj;
353 struct radeon_encoder_lvds {
355 uint16_t panel_vcc_delay;
356 uint8_t panel_pwr_delay;
357 uint8_t panel_digon_delay;
358 uint8_t panel_blon_delay;
359 uint16_t panel_ref_divider;
360 uint8_t panel_post_divider;
361 uint16_t panel_fb_divider;
362 bool use_bios_dividers;
363 uint32_t lvds_gen_cntl;
365 struct drm_display_mode native_mode;
366 struct backlight_device *bl_dev;
368 uint8_t backlight_level;
371 struct radeon_encoder_tv_dac {
373 uint32_t ps2_tvdac_adj;
374 uint32_t ntsc_tvdac_adj;
375 uint32_t pal_tvdac_adj;
380 int supported_tv_stds;
382 enum radeon_tv_std tv_std;
383 struct radeon_tv_regs tv;
386 struct radeon_encoder_int_tmds {
387 /* legacy int tmds */
388 struct radeon_tmds_pll tmds_pll[4];
391 struct radeon_encoder_ext_tmds {
393 struct radeon_i2c_chan *i2c_bus;
395 enum radeon_dvo_chip dvo_chip;
398 /* spread spectrum */
399 struct radeon_encoder_atom_dig {
403 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
406 uint16_t panel_pwr_delay;
409 struct drm_display_mode native_mode;
410 struct backlight_device *bl_dev;
412 uint8_t backlight_level;
414 struct radeon_afmt *afmt;
417 struct radeon_encoder_atom_dac {
418 enum radeon_tv_std tv_std;
421 struct radeon_encoder {
422 struct drm_encoder base;
423 uint32_t encoder_enum;
426 uint32_t active_device;
428 uint32_t pixel_clock;
429 enum radeon_rmx_type rmx_type;
430 enum radeon_underscan_type underscan_type;
431 uint32_t underscan_hborder;
432 uint32_t underscan_vborder;
433 struct drm_display_mode native_mode;
435 int audio_polling_active;
440 struct radeon_connector_atom_dig {
441 uint32_t igp_lane_info;
443 struct radeon_i2c_chan *dp_i2c_bus;
444 u8 dpcd[DP_RECEIVER_CAP_SIZE];
451 struct radeon_gpio_rec {
459 enum radeon_hpd_id hpd;
461 struct radeon_gpio_rec gpio;
464 struct radeon_router {
466 struct radeon_i2c_bus_rec i2c_info;
471 u8 ddc_mux_control_pin;
476 u8 cd_mux_control_pin;
480 enum radeon_connector_audio {
481 RADEON_AUDIO_DISABLE = 0,
482 RADEON_AUDIO_ENABLE = 1,
483 RADEON_AUDIO_AUTO = 2
486 enum radeon_connector_dither {
487 RADEON_FMT_DITHER_DISABLE = 0,
488 RADEON_FMT_DITHER_ENABLE = 1,
491 struct radeon_connector {
492 struct drm_connector base;
493 uint32_t connector_id;
495 struct radeon_i2c_chan *ddc_bus;
496 /* some systems have an hdmi and vga port with a shared ddc line */
499 /* we need to mind the EDID between detect
500 and get modes due to analog/digital/tvencoder */
503 bool dac_load_detect;
504 bool detected_by_load; /* if the connection status was determined by load */
505 uint16_t connector_object_id;
506 struct radeon_hpd hpd;
507 struct radeon_router router;
508 struct radeon_i2c_chan *router_bus;
509 enum radeon_connector_audio audio;
510 enum radeon_connector_dither dither;
513 struct radeon_framebuffer {
514 struct drm_framebuffer base;
515 struct drm_gem_object *obj;
518 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
519 ((em) == ATOM_ENCODER_MODE_DP_MST))
521 struct atom_clock_dividers {
527 u32 whole_fb_div : 12;
528 u32 frac_fb_div : 14;
530 u32 frac_fb_div : 14;
531 u32 whole_fb_div : 12;
538 bool enable_post_div;
547 struct atom_mpll_param {
571 #define MEM_TYPE_GDDR5 0x50
572 #define MEM_TYPE_GDDR4 0x40
573 #define MEM_TYPE_GDDR3 0x30
574 #define MEM_TYPE_DDR2 0x20
575 #define MEM_TYPE_GDDR1 0x10
576 #define MEM_TYPE_DDR3 0xb0
577 #define MEM_TYPE_MASK 0xf0
579 struct atom_memory_info {
584 #define MAX_AC_TIMING_ENTRIES 16
586 struct atom_memory_clock_range_table
590 u32 mclk[MAX_AC_TIMING_ENTRIES];
593 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
594 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
596 struct atom_mc_reg_entry {
598 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
601 struct atom_mc_register_address {
606 struct atom_mc_reg_table {
609 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
610 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
613 #define MAX_VOLTAGE_ENTRIES 32
615 struct atom_voltage_table_entry
621 struct atom_voltage_table
626 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
631 radeon_add_atom_connector(struct drm_device *dev,
632 uint32_t connector_id,
633 uint32_t supported_device,
635 struct radeon_i2c_bus_rec *i2c_bus,
636 uint32_t igp_lane_info,
637 uint16_t connector_object_id,
638 struct radeon_hpd *hpd,
639 struct radeon_router *router);
641 radeon_add_legacy_connector(struct drm_device *dev,
642 uint32_t connector_id,
643 uint32_t supported_device,
645 struct radeon_i2c_bus_rec *i2c_bus,
646 uint16_t connector_object_id,
647 struct radeon_hpd *hpd);
649 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
651 extern void radeon_link_encoder_connector(struct drm_device *dev);
653 extern enum radeon_tv_std
654 radeon_combios_get_tv_info(struct radeon_device *rdev);
655 extern enum radeon_tv_std
656 radeon_atombios_get_tv_info(struct radeon_device *rdev);
657 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
658 u16 *vddc, u16 *vddci, u16 *mvdd);
661 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
662 struct drm_encoder *encoder,
665 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
666 struct drm_encoder *encoder,
669 extern struct drm_connector *
670 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
671 extern struct drm_connector *
672 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
673 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
676 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
677 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
678 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
679 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
680 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
682 extern void radeon_connector_hotplug(struct drm_connector *connector);
683 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
684 struct drm_display_mode *mode);
685 extern void radeon_dp_set_link_config(struct drm_connector *connector,
686 const struct drm_display_mode *mode);
687 extern void radeon_dp_link_train(struct drm_encoder *encoder,
688 struct drm_connector *connector);
689 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
690 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
691 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
692 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
693 struct drm_connector *connector);
694 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
696 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
697 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
698 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
699 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
700 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
701 int action, uint8_t lane_num,
703 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
704 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
705 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
706 u8 write_byte, u8 *read_byte);
707 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
709 extern void radeon_i2c_init(struct radeon_device *rdev);
710 extern void radeon_i2c_fini(struct radeon_device *rdev);
711 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
712 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
713 extern void radeon_i2c_add(struct radeon_device *rdev,
714 struct radeon_i2c_bus_rec *rec,
716 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
717 struct radeon_i2c_bus_rec *i2c_bus);
718 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
719 struct radeon_i2c_bus_rec *rec,
721 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
722 struct radeon_i2c_bus_rec *rec,
724 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
725 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
729 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
733 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
734 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
735 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
736 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
738 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
740 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
741 struct radeon_atom_ss *ss,
743 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
744 struct radeon_atom_ss *ss,
747 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
749 uint32_t *dot_clock_p,
751 uint32_t *frac_fb_div_p,
753 uint32_t *post_div_p);
755 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
763 extern void radeon_setup_encoder_clones(struct drm_device *dev);
765 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
766 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
767 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
768 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
769 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
770 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
771 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
772 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
773 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
774 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
776 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
777 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
778 struct drm_framebuffer *old_fb);
779 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
780 struct drm_framebuffer *fb,
782 enum mode_set_atomic state);
783 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
784 struct drm_display_mode *mode,
785 struct drm_display_mode *adjusted_mode,
787 struct drm_framebuffer *old_fb);
788 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
790 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
791 struct drm_framebuffer *old_fb);
792 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
793 struct drm_framebuffer *fb,
795 enum mode_set_atomic state);
796 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
797 struct drm_framebuffer *fb,
798 int x, int y, int atomic);
799 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
800 struct drm_file *file_priv,
804 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
807 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
809 int *vpos, int *hpos, ktime_t *stime,
812 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
814 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
815 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
816 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
817 extern struct radeon_encoder_atom_dig *
818 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
819 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
820 struct radeon_encoder_int_tmds *tmds);
821 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
822 struct radeon_encoder_int_tmds *tmds);
823 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
824 struct radeon_encoder_int_tmds *tmds);
825 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
826 struct radeon_encoder_ext_tmds *tmds);
827 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
828 struct radeon_encoder_ext_tmds *tmds);
829 extern struct radeon_encoder_primary_dac *
830 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
831 extern struct radeon_encoder_tv_dac *
832 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
833 extern struct radeon_encoder_lvds *
834 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
835 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
836 extern struct radeon_encoder_tv_dac *
837 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
838 extern struct radeon_encoder_primary_dac *
839 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
840 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
841 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
842 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
843 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
844 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
845 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
846 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
847 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
849 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
851 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
853 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
855 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
856 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
857 u16 blue, int regno);
858 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
859 u16 *blue, int regno);
860 int radeon_framebuffer_init(struct drm_device *dev,
861 struct radeon_framebuffer *rfb,
862 struct drm_mode_fb_cmd2 *mode_cmd,
863 struct drm_gem_object *obj);
865 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
866 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
867 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
868 void radeon_atombios_init_crtc(struct drm_device *dev,
869 struct radeon_crtc *radeon_crtc);
870 void radeon_legacy_init_crtc(struct drm_device *dev,
871 struct radeon_crtc *radeon_crtc);
873 void radeon_get_clock_info(struct drm_device *dev);
875 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
876 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
878 void radeon_enc_destroy(struct drm_encoder *encoder);
879 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
880 void radeon_combios_asic_init(struct drm_device *dev);
881 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
882 const struct drm_display_mode *mode,
883 struct drm_display_mode *adjusted_mode);
884 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
885 struct drm_display_mode *adjusted_mode);
886 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
889 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
890 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
891 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
892 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
893 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
894 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
895 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
896 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
897 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
898 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
899 struct drm_display_mode *mode,
900 struct drm_display_mode *adjusted_mode);
903 void avivo_program_fmt(struct drm_encoder *encoder);
904 void dce3_program_fmt(struct drm_encoder *encoder);
905 void dce4_program_fmt(struct drm_encoder *encoder);
906 void dce8_program_fmt(struct drm_encoder *encoder);
909 int radeon_fbdev_init(struct radeon_device *rdev);
910 void radeon_fbdev_fini(struct radeon_device *rdev);
911 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
912 int radeon_fbdev_total_size(struct radeon_device *rdev);
913 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
915 void radeon_fb_output_poll_changed(struct radeon_device *rdev);
917 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
919 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);