2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/radeon_drm.h>
37 #include "radeon_trace.h"
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
49 static void radeon_update_memory_usage(struct radeon_bo *bo,
50 unsigned mem_type, int sign)
52 struct radeon_device *rdev = bo->rdev;
53 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
58 atomic64_add(size, &rdev->gtt_usage);
60 atomic64_sub(size, &rdev->gtt_usage);
64 atomic64_add(size, &rdev->vram_usage);
66 atomic64_sub(size, &rdev->vram_usage);
71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
75 bo = container_of(tbo, struct radeon_bo, tbo);
77 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
79 mutex_lock(&bo->rdev->gem.mutex);
80 list_del_init(&bo->list);
81 mutex_unlock(&bo->rdev->gem.mutex);
82 radeon_bo_clear_surface_reg(bo);
83 WARN_ON(!list_empty(&bo->va));
84 drm_gem_object_release(&bo->gem_base);
88 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
90 if (bo->destroy == &radeon_ttm_bo_destroy)
95 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
99 rbo->placement.placement = rbo->placements;
100 rbo->placement.busy_placement = rbo->placements;
101 if (domain & RADEON_GEM_DOMAIN_VRAM) {
102 /* Try placing BOs which don't need CPU access outside of the
103 * CPU accessible part of VRAM
105 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
106 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
107 rbo->placements[c].fpfn =
108 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
109 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
110 TTM_PL_FLAG_UNCACHED |
114 rbo->placements[c].fpfn = 0;
115 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
116 TTM_PL_FLAG_UNCACHED |
120 if (domain & RADEON_GEM_DOMAIN_GTT) {
121 if (rbo->flags & RADEON_GEM_GTT_UC) {
122 rbo->placements[c].fpfn = 0;
123 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
126 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
127 (rbo->rdev->flags & RADEON_IS_AGP)) {
128 rbo->placements[c].fpfn = 0;
129 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
130 TTM_PL_FLAG_UNCACHED |
133 rbo->placements[c].fpfn = 0;
134 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
139 if (domain & RADEON_GEM_DOMAIN_CPU) {
140 if (rbo->flags & RADEON_GEM_GTT_UC) {
141 rbo->placements[c].fpfn = 0;
142 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
145 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
146 rbo->rdev->flags & RADEON_IS_AGP) {
147 rbo->placements[c].fpfn = 0;
148 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
149 TTM_PL_FLAG_UNCACHED |
152 rbo->placements[c].fpfn = 0;
153 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
158 rbo->placements[c].fpfn = 0;
159 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
163 rbo->placement.num_placement = c;
164 rbo->placement.num_busy_placement = c;
166 for (i = 0; i < c; ++i) {
167 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
168 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
169 !rbo->placements[i].fpfn)
170 rbo->placements[i].lpfn =
171 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
173 rbo->placements[i].lpfn = 0;
177 int radeon_bo_create(struct radeon_device *rdev,
178 unsigned long size, int byte_align, bool kernel,
179 u32 domain, u32 flags, struct sg_table *sg,
180 struct reservation_object *resv,
181 struct radeon_bo **bo_ptr)
183 struct radeon_bo *bo;
184 enum ttm_bo_type type;
185 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
189 size = ALIGN(size, PAGE_SIZE);
192 type = ttm_bo_type_kernel;
194 type = ttm_bo_type_sg;
196 type = ttm_bo_type_device;
200 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
201 sizeof(struct radeon_bo));
203 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
206 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
212 bo->surface_reg = -1;
213 INIT_LIST_HEAD(&bo->list);
214 INIT_LIST_HEAD(&bo->va);
215 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
216 RADEON_GEM_DOMAIN_GTT |
217 RADEON_GEM_DOMAIN_CPU);
220 /* PCI GART is always snooped */
221 if (!(rdev->flags & RADEON_IS_PCIE))
222 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
224 /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
225 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
227 if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
228 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
231 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
232 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
234 bo->flags &= ~RADEON_GEM_GTT_WC;
235 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
236 /* Don't try to enable write-combining when it can't work, or things
238 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
241 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
242 thanks to write-combining
244 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
245 "better performance thanks to write-combining\n");
246 bo->flags &= ~RADEON_GEM_GTT_WC;
249 radeon_ttm_placement_from_domain(bo, domain);
250 /* Kernel allocation are uninterruptible */
251 down_read(&rdev->pm.mclk_lock);
252 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
253 &bo->placement, page_align, !kernel, NULL,
254 acc_size, sg, resv, &radeon_ttm_bo_destroy);
255 up_read(&rdev->pm.mclk_lock);
256 if (unlikely(r != 0)) {
261 trace_radeon_bo_create(bo);
266 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
277 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
281 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
285 radeon_bo_check_tiling(bo, 0, 0);
289 void radeon_bo_kunmap(struct radeon_bo *bo)
291 if (bo->kptr == NULL)
294 radeon_bo_check_tiling(bo, 0, 0);
295 ttm_bo_kunmap(&bo->kmap);
298 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
303 ttm_bo_reference(&bo->tbo);
307 void radeon_bo_unref(struct radeon_bo **bo)
309 struct ttm_buffer_object *tbo;
310 struct radeon_device *rdev;
321 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
326 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
332 *gpu_addr = radeon_bo_gpu_offset(bo);
334 if (max_offset != 0) {
337 if (domain == RADEON_GEM_DOMAIN_VRAM)
338 domain_start = bo->rdev->mc.vram_start;
340 domain_start = bo->rdev->mc.gtt_start;
341 WARN_ON_ONCE(max_offset <
342 (radeon_bo_gpu_offset(bo) - domain_start));
347 radeon_ttm_placement_from_domain(bo, domain);
348 for (i = 0; i < bo->placement.num_placement; i++) {
349 /* force to pin into visible video ram */
350 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
351 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
352 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
353 bo->placements[i].lpfn =
354 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
356 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
358 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
361 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
362 if (likely(r == 0)) {
364 if (gpu_addr != NULL)
365 *gpu_addr = radeon_bo_gpu_offset(bo);
366 if (domain == RADEON_GEM_DOMAIN_VRAM)
367 bo->rdev->vram_pin_size += radeon_bo_size(bo);
369 bo->rdev->gart_pin_size += radeon_bo_size(bo);
371 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
376 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
378 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
381 int radeon_bo_unpin(struct radeon_bo *bo)
385 if (!bo->pin_count) {
386 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
392 for (i = 0; i < bo->placement.num_placement; i++) {
393 bo->placements[i].lpfn = 0;
394 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
396 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
397 if (likely(r == 0)) {
398 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
399 bo->rdev->vram_pin_size -= radeon_bo_size(bo);
401 bo->rdev->gart_pin_size -= radeon_bo_size(bo);
403 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
408 int radeon_bo_evict_vram(struct radeon_device *rdev)
410 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
411 if (0 && (rdev->flags & RADEON_IS_IGP)) {
412 if (rdev->mc.igp_sideport_enabled == false)
413 /* Useless to evict on IGP chips */
416 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
419 void radeon_bo_force_delete(struct radeon_device *rdev)
421 struct radeon_bo *bo, *n;
423 if (list_empty(&rdev->gem.objects)) {
426 dev_err(rdev->dev, "Userspace still has active objects !\n");
427 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
428 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
429 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
430 *((unsigned long *)&bo->gem_base.refcount));
431 mutex_lock(&bo->rdev->gem.mutex);
432 list_del_init(&bo->list);
433 mutex_unlock(&bo->rdev->gem.mutex);
434 /* this should unref the ttm bo */
435 drm_gem_object_unreference_unlocked(&bo->gem_base);
439 int radeon_bo_init(struct radeon_device *rdev)
441 /* Add an MTRR for the VRAM */
442 if (!rdev->fastfb_working) {
443 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
446 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
447 rdev->mc.mc_vram_size >> 20,
448 (unsigned long long)rdev->mc.aper_size >> 20);
449 DRM_INFO("RAM width %dbits %cDR\n",
450 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
451 return radeon_ttm_init(rdev);
454 void radeon_bo_fini(struct radeon_device *rdev)
456 radeon_ttm_fini(rdev);
457 arch_phys_wc_del(rdev->mc.vram_mtrr);
460 /* Returns how many bytes TTM can move per IB.
462 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
464 u64 real_vram_size = rdev->mc.real_vram_size;
465 u64 vram_usage = atomic64_read(&rdev->vram_usage);
467 /* This function is based on the current VRAM usage.
469 * - If all of VRAM is free, allow relocating the number of bytes that
470 * is equal to 1/4 of the size of VRAM for this IB.
472 * - If more than one half of VRAM is occupied, only allow relocating
473 * 1 MB of data for this IB.
475 * - From 0 to one half of used VRAM, the threshold decreases
490 * Note: It's a threshold, not a limit. The threshold must be crossed
491 * for buffer relocations to stop, so any buffer of an arbitrary size
492 * can be moved as long as the threshold isn't crossed before
493 * the relocation takes place. We don't want to disable buffer
494 * relocations completely.
496 * The idea is that buffers should be placed in VRAM at creation time
497 * and TTM should only do a minimum number of relocations during
498 * command submission. In practice, you need to submit at least
499 * a dozen IBs to move all buffers to VRAM if they are in GTT.
501 * Also, things can get pretty crazy under memory pressure and actual
502 * VRAM usage can change a lot, so playing safe even at 50% does
503 * consistently increase performance.
506 u64 half_vram = real_vram_size >> 1;
507 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
508 u64 bytes_moved_threshold = half_free_vram >> 1;
509 return max(bytes_moved_threshold, 1024*1024ull);
512 int radeon_bo_list_validate(struct radeon_device *rdev,
513 struct ww_acquire_ctx *ticket,
514 struct list_head *head, int ring)
516 struct radeon_bo_list *lobj;
517 struct list_head duplicates;
519 u64 bytes_moved = 0, initial_bytes_moved;
520 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
522 INIT_LIST_HEAD(&duplicates);
523 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
524 if (unlikely(r != 0)) {
528 list_for_each_entry(lobj, head, tv.head) {
529 struct radeon_bo *bo = lobj->robj;
530 if (!bo->pin_count) {
531 u32 domain = lobj->prefered_domains;
532 u32 allowed = lobj->allowed_domains;
534 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
536 /* Check if this buffer will be moved and don't move it
537 * if we have moved too many buffers for this IB already.
539 * Note that this allows moving at least one buffer of
540 * any size, because it doesn't take the current "bo"
541 * into account. We don't want to disallow buffer moves
544 if ((allowed & current_domain) != 0 &&
545 (domain & current_domain) == 0 && /* will be moved */
546 bytes_moved > bytes_moved_threshold) {
548 domain = current_domain;
552 radeon_ttm_placement_from_domain(bo, domain);
553 if (ring == R600_RING_TYPE_UVD_INDEX)
554 radeon_uvd_force_into_uvd_segment(bo, allowed);
556 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
557 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
558 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
562 if (r != -ERESTARTSYS &&
563 domain != lobj->allowed_domains) {
564 domain = lobj->allowed_domains;
567 ttm_eu_backoff_reservation(ticket, head);
571 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
572 lobj->tiling_flags = bo->tiling_flags;
575 list_for_each_entry(lobj, &duplicates, tv.head) {
576 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
577 lobj->tiling_flags = lobj->robj->tiling_flags;
583 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
585 struct radeon_device *rdev = bo->rdev;
586 struct radeon_surface_reg *reg;
587 struct radeon_bo *old_object;
591 lockdep_assert_held(&bo->tbo.resv->lock.base);
593 if (!bo->tiling_flags)
596 if (bo->surface_reg >= 0) {
597 reg = &rdev->surface_regs[bo->surface_reg];
603 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
605 reg = &rdev->surface_regs[i];
609 old_object = reg->bo;
610 if (old_object->pin_count == 0)
614 /* if we are all out */
615 if (i == RADEON_GEM_MAX_SURFACES) {
618 /* find someone with a surface reg and nuke their BO */
619 reg = &rdev->surface_regs[steal];
620 old_object = reg->bo;
621 /* blow away the mapping */
622 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
623 ttm_bo_unmap_virtual(&old_object->tbo);
624 old_object->surface_reg = -1;
632 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
633 bo->tbo.mem.start << PAGE_SHIFT,
634 bo->tbo.num_pages << PAGE_SHIFT);
638 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
640 struct radeon_device *rdev = bo->rdev;
641 struct radeon_surface_reg *reg;
643 if (bo->surface_reg == -1)
646 reg = &rdev->surface_regs[bo->surface_reg];
647 radeon_clear_surface_reg(rdev, bo->surface_reg);
650 bo->surface_reg = -1;
653 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
654 uint32_t tiling_flags, uint32_t pitch)
656 struct radeon_device *rdev = bo->rdev;
659 if (rdev->family >= CHIP_CEDAR) {
660 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
662 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
663 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
664 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
665 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
666 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
700 if (stilesplit > 6) {
704 r = radeon_bo_reserve(bo, false);
705 if (unlikely(r != 0))
707 bo->tiling_flags = tiling_flags;
709 radeon_bo_unreserve(bo);
713 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
714 uint32_t *tiling_flags,
717 lockdep_assert_held(&bo->tbo.resv->lock.base);
720 *tiling_flags = bo->tiling_flags;
725 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
729 lockdep_assert_held(&bo->tbo.resv->lock.base);
731 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
735 radeon_bo_clear_surface_reg(bo);
739 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
743 if (bo->surface_reg >= 0)
744 radeon_bo_clear_surface_reg(bo);
748 if ((bo->surface_reg >= 0) && !has_moved)
751 return radeon_bo_get_surface_reg(bo);
754 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
755 struct ttm_mem_reg *new_mem)
757 struct radeon_bo *rbo;
759 if (!radeon_ttm_bo_is_radeon_bo(bo))
762 rbo = container_of(bo, struct radeon_bo, tbo);
763 radeon_bo_check_tiling(rbo, 0, 1);
764 radeon_vm_bo_invalidate(rbo->rdev, rbo);
766 /* update statistics */
770 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
771 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
774 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
776 struct radeon_device *rdev;
777 struct radeon_bo *rbo;
778 unsigned long offset, size, lpfn;
781 if (!radeon_ttm_bo_is_radeon_bo(bo))
783 rbo = container_of(bo, struct radeon_bo, tbo);
784 radeon_bo_check_tiling(rbo, 0, 0);
786 if (bo->mem.mem_type != TTM_PL_VRAM)
789 size = bo->mem.num_pages << PAGE_SHIFT;
790 offset = bo->mem.start << PAGE_SHIFT;
791 if ((offset + size) <= rdev->mc.visible_vram_size)
794 /* hurrah the memory is not visible ! */
795 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
796 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
797 for (i = 0; i < rbo->placement.num_placement; i++) {
798 /* Force into visible VRAM */
799 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
800 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
801 rbo->placements[i].lpfn = lpfn;
803 r = ttm_bo_validate(bo, &rbo->placement, false, false);
804 if (unlikely(r == -ENOMEM)) {
805 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
806 return ttm_bo_validate(bo, &rbo->placement, false, false);
807 } else if (unlikely(r != 0)) {
811 offset = bo->mem.start << PAGE_SHIFT;
812 /* this should never happen */
813 if ((offset + size) > rdev->mc.visible_vram_size)
819 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
823 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
824 if (unlikely(r != 0))
827 *mem_type = bo->tbo.mem.mem_type;
829 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
830 ttm_bo_unreserve(&bo->tbo);
835 * radeon_bo_fence - add fence to buffer object
837 * @bo: buffer object in question
838 * @fence: fence to add
839 * @shared: true if fence should be added shared
842 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
845 struct reservation_object *resv = bo->tbo.resv;
848 reservation_object_add_shared_fence(resv, &fence->base);
850 reservation_object_add_excl_fence(resv, &fence->base);