2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/radeon_drm.h>
37 #include "radeon_trace.h"
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
49 void radeon_bo_clear_va(struct radeon_bo *bo)
51 struct radeon_bo_va *bo_va, *tmp;
53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54 /* remove from all vm address space */
55 radeon_vm_bo_rmv(bo->rdev, bo_va);
59 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
63 bo = container_of(tbo, struct radeon_bo, tbo);
64 mutex_lock(&bo->rdev->gem.mutex);
65 list_del_init(&bo->list);
66 mutex_unlock(&bo->rdev->gem.mutex);
67 radeon_bo_clear_surface_reg(bo);
68 radeon_bo_clear_va(bo);
69 drm_gem_object_release(&bo->gem_base);
73 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
75 if (bo->destroy == &radeon_ttm_bo_destroy)
80 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
84 rbo->placement.fpfn = 0;
85 rbo->placement.lpfn = 0;
86 rbo->placement.placement = rbo->placements;
87 rbo->placement.busy_placement = rbo->placements;
88 if (domain & RADEON_GEM_DOMAIN_VRAM)
89 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
91 if (domain & RADEON_GEM_DOMAIN_GTT) {
92 if (rbo->rdev->flags & RADEON_IS_AGP) {
93 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
95 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
98 if (domain & RADEON_GEM_DOMAIN_CPU) {
99 if (rbo->rdev->flags & RADEON_IS_AGP) {
100 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
102 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
106 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
107 rbo->placement.num_placement = c;
108 rbo->placement.num_busy_placement = c;
111 int radeon_bo_create(struct radeon_device *rdev,
112 unsigned long size, int byte_align, bool kernel, u32 domain,
113 struct sg_table *sg, struct radeon_bo **bo_ptr)
115 struct radeon_bo *bo;
116 enum ttm_bo_type type;
117 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
121 size = ALIGN(size, PAGE_SIZE);
123 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
125 type = ttm_bo_type_kernel;
127 type = ttm_bo_type_sg;
129 type = ttm_bo_type_device;
133 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
134 sizeof(struct radeon_bo));
136 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
139 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
145 bo->gem_base.driver_private = NULL;
146 bo->surface_reg = -1;
147 INIT_LIST_HEAD(&bo->list);
148 INIT_LIST_HEAD(&bo->va);
149 radeon_ttm_placement_from_domain(bo, domain);
150 /* Kernel allocation are uninterruptible */
151 down_read(&rdev->pm.mclk_lock);
152 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
153 &bo->placement, page_align, !kernel, NULL,
154 acc_size, sg, &radeon_ttm_bo_destroy);
155 up_read(&rdev->pm.mclk_lock);
156 if (unlikely(r != 0)) {
161 trace_radeon_bo_create(bo);
166 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
177 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
181 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
185 radeon_bo_check_tiling(bo, 0, 0);
189 void radeon_bo_kunmap(struct radeon_bo *bo)
191 if (bo->kptr == NULL)
194 radeon_bo_check_tiling(bo, 0, 0);
195 ttm_bo_kunmap(&bo->kmap);
198 void radeon_bo_unref(struct radeon_bo **bo)
200 struct ttm_buffer_object *tbo;
201 struct radeon_device *rdev;
207 down_read(&rdev->pm.mclk_lock);
209 up_read(&rdev->pm.mclk_lock);
214 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
222 *gpu_addr = radeon_bo_gpu_offset(bo);
224 if (max_offset != 0) {
227 if (domain == RADEON_GEM_DOMAIN_VRAM)
228 domain_start = bo->rdev->mc.vram_start;
230 domain_start = bo->rdev->mc.gtt_start;
231 WARN_ON_ONCE(max_offset <
232 (radeon_bo_gpu_offset(bo) - domain_start));
237 radeon_ttm_placement_from_domain(bo, domain);
238 if (domain == RADEON_GEM_DOMAIN_VRAM) {
239 /* force to pin into visible video ram */
240 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
243 u64 lpfn = max_offset >> PAGE_SHIFT;
245 if (!bo->placement.lpfn)
246 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
248 if (lpfn < bo->placement.lpfn)
249 bo->placement.lpfn = lpfn;
251 for (i = 0; i < bo->placement.num_placement; i++)
252 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
253 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
254 if (likely(r == 0)) {
256 if (gpu_addr != NULL)
257 *gpu_addr = radeon_bo_gpu_offset(bo);
259 if (unlikely(r != 0))
260 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
264 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
266 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
269 int radeon_bo_unpin(struct radeon_bo *bo)
273 if (!bo->pin_count) {
274 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
280 for (i = 0; i < bo->placement.num_placement; i++)
281 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
282 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
283 if (unlikely(r != 0))
284 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
288 int radeon_bo_evict_vram(struct radeon_device *rdev)
290 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
291 if (0 && (rdev->flags & RADEON_IS_IGP)) {
292 if (rdev->mc.igp_sideport_enabled == false)
293 /* Useless to evict on IGP chips */
296 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
299 void radeon_bo_force_delete(struct radeon_device *rdev)
301 struct radeon_bo *bo, *n;
303 if (list_empty(&rdev->gem.objects)) {
306 dev_err(rdev->dev, "Userspace still has active objects !\n");
307 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
308 mutex_lock(&rdev->ddev->struct_mutex);
309 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
310 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
311 *((unsigned long *)&bo->gem_base.refcount));
312 mutex_lock(&bo->rdev->gem.mutex);
313 list_del_init(&bo->list);
314 mutex_unlock(&bo->rdev->gem.mutex);
315 /* this should unref the ttm bo */
316 drm_gem_object_unreference(&bo->gem_base);
317 mutex_unlock(&rdev->ddev->struct_mutex);
321 int radeon_bo_init(struct radeon_device *rdev)
323 /* Add an MTRR for the VRAM */
324 if (!rdev->fastfb_working) {
325 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
326 MTRR_TYPE_WRCOMB, 1);
328 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
329 rdev->mc.mc_vram_size >> 20,
330 (unsigned long long)rdev->mc.aper_size >> 20);
331 DRM_INFO("RAM width %dbits %cDR\n",
332 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
333 return radeon_ttm_init(rdev);
336 void radeon_bo_fini(struct radeon_device *rdev)
338 radeon_ttm_fini(rdev);
341 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
342 struct list_head *head)
345 list_add(&lobj->tv.head, head);
347 list_add_tail(&lobj->tv.head, head);
351 int radeon_bo_list_validate(struct list_head *head, int ring)
353 struct radeon_bo_list *lobj;
354 struct radeon_bo *bo;
358 r = ttm_eu_reserve_buffers(head);
359 if (unlikely(r != 0)) {
362 list_for_each_entry(lobj, head, tv.head) {
364 if (!bo->pin_count) {
365 domain = lobj->domain;
368 radeon_ttm_placement_from_domain(bo, domain);
369 if (ring == R600_RING_TYPE_UVD_INDEX)
370 radeon_uvd_force_into_uvd_segment(bo);
371 r = ttm_bo_validate(&bo->tbo, &bo->placement,
374 if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
375 domain = lobj->alt_domain;
381 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
382 lobj->tiling_flags = bo->tiling_flags;
387 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
388 struct vm_area_struct *vma)
390 return ttm_fbdev_mmap(vma, &bo->tbo);
393 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
395 struct radeon_device *rdev = bo->rdev;
396 struct radeon_surface_reg *reg;
397 struct radeon_bo *old_object;
401 BUG_ON(!radeon_bo_is_reserved(bo));
403 if (!bo->tiling_flags)
406 if (bo->surface_reg >= 0) {
407 reg = &rdev->surface_regs[bo->surface_reg];
413 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
415 reg = &rdev->surface_regs[i];
419 old_object = reg->bo;
420 if (old_object->pin_count == 0)
424 /* if we are all out */
425 if (i == RADEON_GEM_MAX_SURFACES) {
428 /* find someone with a surface reg and nuke their BO */
429 reg = &rdev->surface_regs[steal];
430 old_object = reg->bo;
431 /* blow away the mapping */
432 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
433 ttm_bo_unmap_virtual(&old_object->tbo);
434 old_object->surface_reg = -1;
442 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
443 bo->tbo.mem.start << PAGE_SHIFT,
444 bo->tbo.num_pages << PAGE_SHIFT);
448 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
450 struct radeon_device *rdev = bo->rdev;
451 struct radeon_surface_reg *reg;
453 if (bo->surface_reg == -1)
456 reg = &rdev->surface_regs[bo->surface_reg];
457 radeon_clear_surface_reg(rdev, bo->surface_reg);
460 bo->surface_reg = -1;
463 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
464 uint32_t tiling_flags, uint32_t pitch)
466 struct radeon_device *rdev = bo->rdev;
469 if (rdev->family >= CHIP_CEDAR) {
470 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
472 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
473 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
474 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
475 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
476 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
510 if (stilesplit > 6) {
514 r = radeon_bo_reserve(bo, false);
515 if (unlikely(r != 0))
517 bo->tiling_flags = tiling_flags;
519 radeon_bo_unreserve(bo);
523 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
524 uint32_t *tiling_flags,
527 BUG_ON(!radeon_bo_is_reserved(bo));
529 *tiling_flags = bo->tiling_flags;
534 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
537 BUG_ON(!radeon_bo_is_reserved(bo) && !force_drop);
539 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
543 radeon_bo_clear_surface_reg(bo);
547 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
551 if (bo->surface_reg >= 0)
552 radeon_bo_clear_surface_reg(bo);
556 if ((bo->surface_reg >= 0) && !has_moved)
559 return radeon_bo_get_surface_reg(bo);
562 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
563 struct ttm_mem_reg *mem)
565 struct radeon_bo *rbo;
566 if (!radeon_ttm_bo_is_radeon_bo(bo))
568 rbo = container_of(bo, struct radeon_bo, tbo);
569 radeon_bo_check_tiling(rbo, 0, 1);
570 radeon_vm_bo_invalidate(rbo->rdev, rbo);
573 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
575 struct radeon_device *rdev;
576 struct radeon_bo *rbo;
577 unsigned long offset, size;
580 if (!radeon_ttm_bo_is_radeon_bo(bo))
582 rbo = container_of(bo, struct radeon_bo, tbo);
583 radeon_bo_check_tiling(rbo, 0, 0);
585 if (bo->mem.mem_type == TTM_PL_VRAM) {
586 size = bo->mem.num_pages << PAGE_SHIFT;
587 offset = bo->mem.start << PAGE_SHIFT;
588 if ((offset + size) > rdev->mc.visible_vram_size) {
589 /* hurrah the memory is not visible ! */
590 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
591 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
592 r = ttm_bo_validate(bo, &rbo->placement, false, false);
593 if (unlikely(r != 0))
595 offset = bo->mem.start << PAGE_SHIFT;
596 /* this should not happen */
597 if ((offset + size) > rdev->mc.visible_vram_size)
604 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
608 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
609 if (unlikely(r != 0))
611 spin_lock(&bo->tbo.bdev->fence_lock);
613 *mem_type = bo->tbo.mem.mem_type;
614 if (bo->tbo.sync_obj)
615 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
616 spin_unlock(&bo->tbo.bdev->fence_lock);
617 ttm_bo_unreserve(&bo->tbo);
623 * radeon_bo_reserve - reserve bo
625 * @no_intr: don't return -ERESTARTSYS on pending signal
628 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
629 * a signal. Release all buffer reservations and return to user-space.
631 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
635 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
636 if (unlikely(r != 0)) {
637 if (r != -ERESTARTSYS)
638 dev_err(bo->rdev->dev, "%p reserve failed\n", bo);