2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/radeon_drm.h>
37 #include "radeon_trace.h"
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
49 static void radeon_update_memory_usage(struct radeon_bo *bo,
50 unsigned mem_type, int sign)
52 struct radeon_device *rdev = bo->rdev;
53 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
58 atomic64_add(size, &rdev->gtt_usage);
60 atomic64_sub(size, &rdev->gtt_usage);
64 atomic64_add(size, &rdev->vram_usage);
66 atomic64_sub(size, &rdev->vram_usage);
71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
75 bo = container_of(tbo, struct radeon_bo, tbo);
77 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
78 radeon_mn_unregister(bo);
80 mutex_lock(&bo->rdev->gem.mutex);
81 list_del_init(&bo->list);
82 mutex_unlock(&bo->rdev->gem.mutex);
83 radeon_bo_clear_surface_reg(bo);
84 WARN_ON(!list_empty(&bo->va));
85 drm_gem_object_release(&bo->gem_base);
89 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
91 if (bo->destroy == &radeon_ttm_bo_destroy)
96 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
100 rbo->placement.placement = rbo->placements;
101 rbo->placement.busy_placement = rbo->placements;
102 if (domain & RADEON_GEM_DOMAIN_VRAM)
103 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
104 TTM_PL_FLAG_UNCACHED |
107 if (domain & RADEON_GEM_DOMAIN_GTT) {
108 if (rbo->flags & RADEON_GEM_GTT_UC) {
109 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
112 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
113 (rbo->rdev->flags & RADEON_IS_AGP)) {
114 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
115 TTM_PL_FLAG_UNCACHED |
118 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
123 if (domain & RADEON_GEM_DOMAIN_CPU) {
124 if (rbo->flags & RADEON_GEM_GTT_UC) {
125 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
128 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
129 rbo->rdev->flags & RADEON_IS_AGP) {
130 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
131 TTM_PL_FLAG_UNCACHED |
134 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
139 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
142 rbo->placement.num_placement = c;
143 rbo->placement.num_busy_placement = c;
145 for (i = 0; i < c; ++i) {
146 rbo->placements[i].fpfn = 0;
147 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
148 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM))
149 rbo->placements[i].lpfn =
150 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
152 rbo->placements[i].lpfn = 0;
156 * Use two-ended allocation depending on the buffer size to
157 * improve fragmentation quality.
158 * 512kb was measured as the most optimal number.
160 if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
161 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) &&
162 rbo->tbo.mem.size > 512 * 1024) {
163 for (i = 0; i < c; i++) {
164 rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
169 int radeon_bo_create(struct radeon_device *rdev,
170 unsigned long size, int byte_align, bool kernel,
171 u32 domain, u32 flags, struct sg_table *sg,
172 struct reservation_object *resv,
173 struct radeon_bo **bo_ptr)
175 struct radeon_bo *bo;
176 enum ttm_bo_type type;
177 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
181 size = ALIGN(size, PAGE_SIZE);
184 type = ttm_bo_type_kernel;
186 type = ttm_bo_type_sg;
188 type = ttm_bo_type_device;
192 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
193 sizeof(struct radeon_bo));
195 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
198 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
204 bo->surface_reg = -1;
205 INIT_LIST_HEAD(&bo->list);
206 INIT_LIST_HEAD(&bo->va);
207 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
208 RADEON_GEM_DOMAIN_GTT |
209 RADEON_GEM_DOMAIN_CPU);
212 /* PCI GART is always snooped */
213 if (!(rdev->flags & RADEON_IS_PCIE))
214 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
216 radeon_ttm_placement_from_domain(bo, domain);
217 /* Kernel allocation are uninterruptible */
218 down_read(&rdev->pm.mclk_lock);
219 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
220 &bo->placement, page_align, !kernel, NULL,
221 acc_size, sg, resv, &radeon_ttm_bo_destroy);
222 up_read(&rdev->pm.mclk_lock);
223 if (unlikely(r != 0)) {
228 trace_radeon_bo_create(bo);
233 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
244 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
248 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
252 radeon_bo_check_tiling(bo, 0, 0);
256 void radeon_bo_kunmap(struct radeon_bo *bo)
258 if (bo->kptr == NULL)
261 radeon_bo_check_tiling(bo, 0, 0);
262 ttm_bo_kunmap(&bo->kmap);
265 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
270 ttm_bo_reference(&bo->tbo);
274 void radeon_bo_unref(struct radeon_bo **bo)
276 struct ttm_buffer_object *tbo;
277 struct radeon_device *rdev;
288 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
293 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
299 *gpu_addr = radeon_bo_gpu_offset(bo);
301 if (max_offset != 0) {
304 if (domain == RADEON_GEM_DOMAIN_VRAM)
305 domain_start = bo->rdev->mc.vram_start;
307 domain_start = bo->rdev->mc.gtt_start;
308 WARN_ON_ONCE(max_offset <
309 (radeon_bo_gpu_offset(bo) - domain_start));
314 radeon_ttm_placement_from_domain(bo, domain);
315 for (i = 0; i < bo->placement.num_placement; i++) {
316 /* force to pin into visible video ram */
317 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
318 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
319 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
320 bo->placements[i].lpfn =
321 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
323 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
325 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
328 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
329 if (likely(r == 0)) {
331 if (gpu_addr != NULL)
332 *gpu_addr = radeon_bo_gpu_offset(bo);
333 if (domain == RADEON_GEM_DOMAIN_VRAM)
334 bo->rdev->vram_pin_size += radeon_bo_size(bo);
336 bo->rdev->gart_pin_size += radeon_bo_size(bo);
338 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
343 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
345 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
348 int radeon_bo_unpin(struct radeon_bo *bo)
352 if (!bo->pin_count) {
353 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
359 for (i = 0; i < bo->placement.num_placement; i++) {
360 bo->placements[i].lpfn = 0;
361 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
363 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
364 if (likely(r == 0)) {
365 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
366 bo->rdev->vram_pin_size -= radeon_bo_size(bo);
368 bo->rdev->gart_pin_size -= radeon_bo_size(bo);
370 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
375 int radeon_bo_evict_vram(struct radeon_device *rdev)
377 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
378 if (0 && (rdev->flags & RADEON_IS_IGP)) {
379 if (rdev->mc.igp_sideport_enabled == false)
380 /* Useless to evict on IGP chips */
383 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
386 void radeon_bo_force_delete(struct radeon_device *rdev)
388 struct radeon_bo *bo, *n;
390 if (list_empty(&rdev->gem.objects)) {
393 dev_err(rdev->dev, "Userspace still has active objects !\n");
394 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
395 mutex_lock(&rdev->ddev->struct_mutex);
396 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
397 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
398 *((unsigned long *)&bo->gem_base.refcount));
399 mutex_lock(&bo->rdev->gem.mutex);
400 list_del_init(&bo->list);
401 mutex_unlock(&bo->rdev->gem.mutex);
402 /* this should unref the ttm bo */
403 drm_gem_object_unreference(&bo->gem_base);
404 mutex_unlock(&rdev->ddev->struct_mutex);
408 int radeon_bo_init(struct radeon_device *rdev)
410 /* Add an MTRR for the VRAM */
411 if (!rdev->fastfb_working) {
412 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
415 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
416 rdev->mc.mc_vram_size >> 20,
417 (unsigned long long)rdev->mc.aper_size >> 20);
418 DRM_INFO("RAM width %dbits %cDR\n",
419 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
420 return radeon_ttm_init(rdev);
423 void radeon_bo_fini(struct radeon_device *rdev)
425 radeon_ttm_fini(rdev);
426 arch_phys_wc_del(rdev->mc.vram_mtrr);
429 /* Returns how many bytes TTM can move per IB.
431 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
433 u64 real_vram_size = rdev->mc.real_vram_size;
434 u64 vram_usage = atomic64_read(&rdev->vram_usage);
436 /* This function is based on the current VRAM usage.
438 * - If all of VRAM is free, allow relocating the number of bytes that
439 * is equal to 1/4 of the size of VRAM for this IB.
441 * - If more than one half of VRAM is occupied, only allow relocating
442 * 1 MB of data for this IB.
444 * - From 0 to one half of used VRAM, the threshold decreases
459 * Note: It's a threshold, not a limit. The threshold must be crossed
460 * for buffer relocations to stop, so any buffer of an arbitrary size
461 * can be moved as long as the threshold isn't crossed before
462 * the relocation takes place. We don't want to disable buffer
463 * relocations completely.
465 * The idea is that buffers should be placed in VRAM at creation time
466 * and TTM should only do a minimum number of relocations during
467 * command submission. In practice, you need to submit at least
468 * a dozen IBs to move all buffers to VRAM if they are in GTT.
470 * Also, things can get pretty crazy under memory pressure and actual
471 * VRAM usage can change a lot, so playing safe even at 50% does
472 * consistently increase performance.
475 u64 half_vram = real_vram_size >> 1;
476 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
477 u64 bytes_moved_threshold = half_free_vram >> 1;
478 return max(bytes_moved_threshold, 1024*1024ull);
481 int radeon_bo_list_validate(struct radeon_device *rdev,
482 struct ww_acquire_ctx *ticket,
483 struct list_head *head, int ring)
485 struct radeon_cs_reloc *lobj;
486 struct radeon_bo *bo;
488 u64 bytes_moved = 0, initial_bytes_moved;
489 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
491 r = ttm_eu_reserve_buffers(ticket, head, true);
492 if (unlikely(r != 0)) {
496 list_for_each_entry(lobj, head, tv.head) {
498 if (!bo->pin_count) {
499 u32 domain = lobj->prefered_domains;
500 u32 allowed = lobj->allowed_domains;
502 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
504 /* Check if this buffer will be moved and don't move it
505 * if we have moved too many buffers for this IB already.
507 * Note that this allows moving at least one buffer of
508 * any size, because it doesn't take the current "bo"
509 * into account. We don't want to disallow buffer moves
512 if ((allowed & current_domain) != 0 &&
513 (domain & current_domain) == 0 && /* will be moved */
514 bytes_moved > bytes_moved_threshold) {
516 domain = current_domain;
520 radeon_ttm_placement_from_domain(bo, domain);
521 if (ring == R600_RING_TYPE_UVD_INDEX)
522 radeon_uvd_force_into_uvd_segment(bo, allowed);
524 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
525 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
526 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
530 if (r != -ERESTARTSYS &&
531 domain != lobj->allowed_domains) {
532 domain = lobj->allowed_domains;
535 ttm_eu_backoff_reservation(ticket, head);
539 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
540 lobj->tiling_flags = bo->tiling_flags;
545 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
546 struct vm_area_struct *vma)
548 return ttm_fbdev_mmap(vma, &bo->tbo);
551 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
553 struct radeon_device *rdev = bo->rdev;
554 struct radeon_surface_reg *reg;
555 struct radeon_bo *old_object;
559 lockdep_assert_held(&bo->tbo.resv->lock.base);
561 if (!bo->tiling_flags)
564 if (bo->surface_reg >= 0) {
565 reg = &rdev->surface_regs[bo->surface_reg];
571 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
573 reg = &rdev->surface_regs[i];
577 old_object = reg->bo;
578 if (old_object->pin_count == 0)
582 /* if we are all out */
583 if (i == RADEON_GEM_MAX_SURFACES) {
586 /* find someone with a surface reg and nuke their BO */
587 reg = &rdev->surface_regs[steal];
588 old_object = reg->bo;
589 /* blow away the mapping */
590 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
591 ttm_bo_unmap_virtual(&old_object->tbo);
592 old_object->surface_reg = -1;
600 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
601 bo->tbo.mem.start << PAGE_SHIFT,
602 bo->tbo.num_pages << PAGE_SHIFT);
606 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
608 struct radeon_device *rdev = bo->rdev;
609 struct radeon_surface_reg *reg;
611 if (bo->surface_reg == -1)
614 reg = &rdev->surface_regs[bo->surface_reg];
615 radeon_clear_surface_reg(rdev, bo->surface_reg);
618 bo->surface_reg = -1;
621 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
622 uint32_t tiling_flags, uint32_t pitch)
624 struct radeon_device *rdev = bo->rdev;
627 if (rdev->family >= CHIP_CEDAR) {
628 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
630 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
631 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
632 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
633 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
634 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
668 if (stilesplit > 6) {
672 r = radeon_bo_reserve(bo, false);
673 if (unlikely(r != 0))
675 bo->tiling_flags = tiling_flags;
677 radeon_bo_unreserve(bo);
681 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
682 uint32_t *tiling_flags,
685 lockdep_assert_held(&bo->tbo.resv->lock.base);
688 *tiling_flags = bo->tiling_flags;
693 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
697 lockdep_assert_held(&bo->tbo.resv->lock.base);
699 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
703 radeon_bo_clear_surface_reg(bo);
707 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
711 if (bo->surface_reg >= 0)
712 radeon_bo_clear_surface_reg(bo);
716 if ((bo->surface_reg >= 0) && !has_moved)
719 return radeon_bo_get_surface_reg(bo);
722 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
723 struct ttm_mem_reg *new_mem)
725 struct radeon_bo *rbo;
727 if (!radeon_ttm_bo_is_radeon_bo(bo))
730 rbo = container_of(bo, struct radeon_bo, tbo);
731 radeon_bo_check_tiling(rbo, 0, 1);
732 radeon_vm_bo_invalidate(rbo->rdev, rbo);
734 /* update statistics */
738 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
739 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
742 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
744 struct radeon_device *rdev;
745 struct radeon_bo *rbo;
746 unsigned long offset, size;
749 if (!radeon_ttm_bo_is_radeon_bo(bo))
751 rbo = container_of(bo, struct radeon_bo, tbo);
752 radeon_bo_check_tiling(rbo, 0, 0);
754 if (bo->mem.mem_type != TTM_PL_VRAM)
757 size = bo->mem.num_pages << PAGE_SHIFT;
758 offset = bo->mem.start << PAGE_SHIFT;
759 if ((offset + size) <= rdev->mc.visible_vram_size)
762 /* hurrah the memory is not visible ! */
763 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
764 rbo->placements[0].lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
765 r = ttm_bo_validate(bo, &rbo->placement, false, false);
766 if (unlikely(r == -ENOMEM)) {
767 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
768 return ttm_bo_validate(bo, &rbo->placement, false, false);
769 } else if (unlikely(r != 0)) {
773 offset = bo->mem.start << PAGE_SHIFT;
774 /* this should never happen */
775 if ((offset + size) > rdev->mc.visible_vram_size)
781 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
785 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
786 if (unlikely(r != 0))
789 *mem_type = bo->tbo.mem.mem_type;
791 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
792 ttm_bo_unreserve(&bo->tbo);