drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/radeon_drm.h>
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 static void radeon_update_memory_usage(struct radeon_bo *bo,
  50                                        unsigned mem_type, int sign)
  51 {
  52         struct radeon_device *rdev = bo->rdev;
  53         u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
  54
  55         switch (mem_type) {
  56         case TTM_PL_TT:
  57                 if (sign > 0)
  58                         atomic64_add(size, &rdev->gtt_usage);
  59                 else
  60                         atomic64_sub(size, &rdev->gtt_usage);
  61                 break;
  62         case TTM_PL_VRAM:
  63                 if (sign > 0)
  64                         atomic64_add(size, &rdev->vram_usage);
  65                 else
  66                         atomic64_sub(size, &rdev->vram_usage);
  67                 break;
  68         }
  69 }
  70
  71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  72 {
  73         struct radeon_bo *bo;
  74
  75         bo = container_of(tbo, struct radeon_bo, tbo);
  76
  77         radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
  78         radeon_mn_unregister(bo);
  79
  80         mutex_lock(&bo->rdev->gem.mutex);
  81         list_del_init(&bo->list);
  82         mutex_unlock(&bo->rdev->gem.mutex);
  83         radeon_bo_clear_surface_reg(bo);
  84         WARN_ON(!list_empty(&bo->va));
  85         drm_gem_object_release(&bo->gem_base);
  86         kfree(bo);
  87 }
  88
  89 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  90 {
  91         if (bo->destroy == &radeon_ttm_bo_destroy)
  92                 return true;
  93         return false;
  94 }
  95
  96 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  97 {
  98         u32 c = 0, i;
  99
 100         rbo->placement.placement = rbo->placements;
 101         rbo->placement.busy_placement = rbo->placements;
 102         if (domain & RADEON_GEM_DOMAIN_VRAM) {
 103                 /* Try placing BOs which don't need CPU access outside of the
 104                  * CPU accessible part of VRAM
 105                  */
 106                 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 107                     rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
 108                         rbo->placements[c].fpfn =
 109                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 110                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 111                                                      TTM_PL_FLAG_UNCACHED |
 112                                                      TTM_PL_FLAG_VRAM;
 113                 }
 114
 115                 rbo->placements[c].fpfn = 0;
 116                 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 117                                              TTM_PL_FLAG_UNCACHED |
 118                                              TTM_PL_FLAG_VRAM;
 119         }
 120
 121         if (domain & RADEON_GEM_DOMAIN_GTT) {
 122                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 123                         rbo->placements[c].fpfn = 0;
 124                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 125                                 TTM_PL_FLAG_TT;
 126
 127                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 128                            (rbo->rdev->flags & RADEON_IS_AGP)) {
 129                         rbo->placements[c].fpfn = 0;
 130                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 131                                 TTM_PL_FLAG_UNCACHED |
 132                                 TTM_PL_FLAG_TT;
 133                 } else {
 134                         rbo->placements[c].fpfn = 0;
 135                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 136                                                      TTM_PL_FLAG_TT;
 137                 }
 138         }
 139
 140         if (domain & RADEON_GEM_DOMAIN_CPU) {
 141                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 142                         rbo->placements[c].fpfn = 0;
 143                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 144                                 TTM_PL_FLAG_SYSTEM;
 145
 146                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 147                     rbo->rdev->flags & RADEON_IS_AGP) {
 148                         rbo->placements[c].fpfn = 0;
 149                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 150                                 TTM_PL_FLAG_UNCACHED |
 151                                 TTM_PL_FLAG_SYSTEM;
 152                 } else {
 153                         rbo->placements[c].fpfn = 0;
 154                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 155                                                      TTM_PL_FLAG_SYSTEM;
 156                 }
 157         }
 158         if (!c) {
 159                 rbo->placements[c].fpfn = 0;
 160                 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
 161                                              TTM_PL_FLAG_SYSTEM;
 162         }
 163
 164         rbo->placement.num_placement = c;
 165         rbo->placement.num_busy_placement = c;
 166
 167         for (i = 0; i < c; ++i) {
 168                 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 169                     (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 170                     !rbo->placements[i].fpfn)
 171                         rbo->placements[i].lpfn =
 172                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 173                 else
 174                         rbo->placements[i].lpfn = 0;
 175         }
 176
 177         /*
 178          * Use two-ended allocation depending on the buffer size to
 179          * improve fragmentation quality.
 180          * 512kb was measured as the most optimal number.
 181          */
 182         if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 183               (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) &&
 184             rbo->tbo.mem.size > 512 * 1024) {
 185                 for (i = 0; i < c; i++) {
 186                         rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
 187                 }
 188         }
 189 }
 190
 191 int radeon_bo_create(struct radeon_device *rdev,
 192                      unsigned long size, int byte_align, bool kernel,
 193                      u32 domain, u32 flags, struct sg_table *sg,
 194                      struct reservation_object *resv,
 195                      struct radeon_bo **bo_ptr)
 196 {
 197         struct radeon_bo *bo;
 198         enum ttm_bo_type type;
 199         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 200         size_t acc_size;
 201         int r;
 202
 203         size = ALIGN(size, PAGE_SIZE);
 204
 205         if (kernel) {
 206                 type = ttm_bo_type_kernel;
 207         } else if (sg) {
 208                 type = ttm_bo_type_sg;
 209         } else {
 210                 type = ttm_bo_type_device;
 211         }
 212         *bo_ptr = NULL;
 213
 214         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 215                                        sizeof(struct radeon_bo));
 216
 217         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 218         if (bo == NULL)
 219                 return -ENOMEM;
 220         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 221         if (unlikely(r)) {
 222                 kfree(bo);
 223                 return r;
 224         }
 225         bo->rdev = rdev;
 226         bo->surface_reg = -1;
 227         INIT_LIST_HEAD(&bo->list);
 228         INIT_LIST_HEAD(&bo->va);
 229         bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
 230                                        RADEON_GEM_DOMAIN_GTT |
 231                                        RADEON_GEM_DOMAIN_CPU);
 232
 233         bo->flags = flags;
 234         /* PCI GART is always snooped */
 235         if (!(rdev->flags & RADEON_IS_PCIE))
 236                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 237
 238         radeon_ttm_placement_from_domain(bo, domain);
 239         /* Kernel allocation are uninterruptible */
 240         down_read(&rdev->pm.mclk_lock);
 241         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 242                         &bo->placement, page_align, !kernel, NULL,
 243                         acc_size, sg, resv, &radeon_ttm_bo_destroy);
 244         up_read(&rdev->pm.mclk_lock);
 245         if (unlikely(r != 0)) {
 246                 return r;
 247         }
 248         *bo_ptr = bo;
 249
 250         trace_radeon_bo_create(bo);
 251
 252         return 0;
 253 }
 254
 255 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 256 {
 257         bool is_iomem;
 258         int r;
 259
 260         if (bo->kptr) {
 261                 if (ptr) {
 262                         *ptr = bo->kptr;
 263                 }
 264                 return 0;
 265         }
 266         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 267         if (r) {
 268                 return r;
 269         }
 270         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 271         if (ptr) {
 272                 *ptr = bo->kptr;
 273         }
 274         radeon_bo_check_tiling(bo, 0, 0);
 275         return 0;
 276 }
 277
 278 void radeon_bo_kunmap(struct radeon_bo *bo)
 279 {
 280         if (bo->kptr == NULL)
 281                 return;
 282         bo->kptr = NULL;
 283         radeon_bo_check_tiling(bo, 0, 0);
 284         ttm_bo_kunmap(&bo->kmap);
 285 }
 286
 287 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
 288 {
 289         if (bo == NULL)
 290                 return NULL;
 291
 292         ttm_bo_reference(&bo->tbo);
 293         return bo;
 294 }
 295
 296 void radeon_bo_unref(struct radeon_bo **bo)
 297 {
 298         struct ttm_buffer_object *tbo;
 299         struct radeon_device *rdev;
 300
 301         if ((*bo) == NULL)
 302                 return;
 303         rdev = (*bo)->rdev;
 304         tbo = &((*bo)->tbo);
 305         ttm_bo_unref(&tbo);
 306         if (tbo == NULL)
 307                 *bo = NULL;
 308 }
 309
 310 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 311                              u64 *gpu_addr)
 312 {
 313         int r, i;
 314
 315         if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
 316                 return -EPERM;
 317
 318         if (bo->pin_count) {
 319                 bo->pin_count++;
 320                 if (gpu_addr)
 321                         *gpu_addr = radeon_bo_gpu_offset(bo);
 322
 323                 if (max_offset != 0) {
 324                         u64 domain_start;
 325
 326                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 327                                 domain_start = bo->rdev->mc.vram_start;
 328                         else
 329                                 domain_start = bo->rdev->mc.gtt_start;
 330                         WARN_ON_ONCE(max_offset <
 331                                      (radeon_bo_gpu_offset(bo) - domain_start));
 332                 }
 333
 334                 return 0;
 335         }
 336         radeon_ttm_placement_from_domain(bo, domain);
 337         for (i = 0; i < bo->placement.num_placement; i++) {
 338                 /* force to pin into visible video ram */
 339                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 340                     !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 341                     (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
 342                         bo->placements[i].lpfn =
 343                                 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 344                 else
 345                         bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 346
 347                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 348         }
 349
 350         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 351         if (likely(r == 0)) {
 352                 bo->pin_count = 1;
 353                 if (gpu_addr != NULL)
 354                         *gpu_addr = radeon_bo_gpu_offset(bo);
 355                 if (domain == RADEON_GEM_DOMAIN_VRAM)
 356                         bo->rdev->vram_pin_size += radeon_bo_size(bo);
 357                 else
 358                         bo->rdev->gart_pin_size += radeon_bo_size(bo);
 359         } else {
 360                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 361         }
 362         return r;
 363 }
 364
 365 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 366 {
 367         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 368 }
 369
 370 int radeon_bo_unpin(struct radeon_bo *bo)
 371 {
 372         int r, i;
 373
 374         if (!bo->pin_count) {
 375                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 376                 return 0;
 377         }
 378         bo->pin_count--;
 379         if (bo->pin_count)
 380                 return 0;
 381         for (i = 0; i < bo->placement.num_placement; i++) {
 382                 bo->placements[i].lpfn = 0;
 383                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 384         }
 385         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 386         if (likely(r == 0)) {
 387                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 388                         bo->rdev->vram_pin_size -= radeon_bo_size(bo);
 389                 else
 390                         bo->rdev->gart_pin_size -= radeon_bo_size(bo);
 391         } else {
 392                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 393         }
 394         return r;
 395 }
 396
 397 int radeon_bo_evict_vram(struct radeon_device *rdev)
 398 {
 399         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 400         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 401                 if (rdev->mc.igp_sideport_enabled == false)
 402                         /* Useless to evict on IGP chips */
 403                         return 0;
 404         }
 405         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 406 }
 407
 408 void radeon_bo_force_delete(struct radeon_device *rdev)
 409 {
 410         struct radeon_bo *bo, *n;
 411
 412         if (list_empty(&rdev->gem.objects)) {
 413                 return;
 414         }
 415         dev_err(rdev->dev, "Userspace still has active objects !\n");
 416         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 417                 mutex_lock(&rdev->ddev->struct_mutex);
 418                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 419                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 420                         *((unsigned long *)&bo->gem_base.refcount));
 421                 mutex_lock(&bo->rdev->gem.mutex);
 422                 list_del_init(&bo->list);
 423                 mutex_unlock(&bo->rdev->gem.mutex);
 424                 /* this should unref the ttm bo */
 425                 drm_gem_object_unreference(&bo->gem_base);
 426                 mutex_unlock(&rdev->ddev->struct_mutex);
 427         }
 428 }
 429
 430 int radeon_bo_init(struct radeon_device *rdev)
 431 {
 432         /* Add an MTRR for the VRAM */
 433         if (!rdev->fastfb_working) {
 434                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
 435                                                       rdev->mc.aper_size);
 436         }
 437         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 438                 rdev->mc.mc_vram_size >> 20,
 439                 (unsigned long long)rdev->mc.aper_size >> 20);
 440         DRM_INFO("RAM width %dbits %cDR\n",
 441                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 442         return radeon_ttm_init(rdev);
 443 }
 444
 445 void radeon_bo_fini(struct radeon_device *rdev)
 446 {
 447         radeon_ttm_fini(rdev);
 448         arch_phys_wc_del(rdev->mc.vram_mtrr);
 449 }
 450
 451 /* Returns how many bytes TTM can move per IB.
 452  */
 453 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
 454 {
 455         u64 real_vram_size = rdev->mc.real_vram_size;
 456         u64 vram_usage = atomic64_read(&rdev->vram_usage);
 457
 458         /* This function is based on the current VRAM usage.
 459          *
 460          * - If all of VRAM is free, allow relocating the number of bytes that
 461          *   is equal to 1/4 of the size of VRAM for this IB.
 462
 463          * - If more than one half of VRAM is occupied, only allow relocating
 464          *   1 MB of data for this IB.
 465          *
 466          * - From 0 to one half of used VRAM, the threshold decreases
 467          *   linearly.
 468          *         __________________
 469          * 1/4 of -|\               |
 470          * VRAM    | \              |
 471          *         |  \             |
 472          *         |   \            |
 473          *         |    \           |
 474          *         |     \          |
 475          *         |      \         |
 476          *         |       \________|1 MB
 477          *         |----------------|
 478          *    VRAM 0 %             100 %
 479          *         used            used
 480          *
 481          * Note: It's a threshold, not a limit. The threshold must be crossed
 482          * for buffer relocations to stop, so any buffer of an arbitrary size
 483          * can be moved as long as the threshold isn't crossed before
 484          * the relocation takes place. We don't want to disable buffer
 485          * relocations completely.
 486          *
 487          * The idea is that buffers should be placed in VRAM at creation time
 488          * and TTM should only do a minimum number of relocations during
 489          * command submission. In practice, you need to submit at least
 490          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 491          *
 492          * Also, things can get pretty crazy under memory pressure and actual
 493          * VRAM usage can change a lot, so playing safe even at 50% does
 494          * consistently increase performance.
 495          */
 496
 497         u64 half_vram = real_vram_size >> 1;
 498         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 499         u64 bytes_moved_threshold = half_free_vram >> 1;
 500         return max(bytes_moved_threshold, 1024*1024ull);
 501 }
 502
 503 int radeon_bo_list_validate(struct radeon_device *rdev,
 504                             struct ww_acquire_ctx *ticket,
 505                             struct list_head *head, int ring)
 506 {
 507         struct radeon_cs_reloc *lobj;
 508         struct radeon_bo *bo;
 509         int r;
 510         u64 bytes_moved = 0, initial_bytes_moved;
 511         u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
 512
 513         r = ttm_eu_reserve_buffers(ticket, head, true);
 514         if (unlikely(r != 0)) {
 515                 return r;
 516         }
 517
 518         list_for_each_entry(lobj, head, tv.head) {
 519                 bo = lobj->robj;
 520                 if (!bo->pin_count) {
 521                         u32 domain = lobj->prefered_domains;
 522                         u32 allowed = lobj->allowed_domains;
 523                         u32 current_domain =
 524                                 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 525
 526                         /* Check if this buffer will be moved and don't move it
 527                          * if we have moved too many buffers for this IB already.
 528                          *
 529                          * Note that this allows moving at least one buffer of
 530                          * any size, because it doesn't take the current "bo"
 531                          * into account. We don't want to disallow buffer moves
 532                          * completely.
 533                          */
 534                         if ((allowed & current_domain) != 0 &&
 535                             (domain & current_domain) == 0 && /* will be moved */
 536                             bytes_moved > bytes_moved_threshold) {
 537                                 /* don't move it */
 538                                 domain = current_domain;
 539                         }
 540
 541                 retry:
 542                         radeon_ttm_placement_from_domain(bo, domain);
 543                         if (ring == R600_RING_TYPE_UVD_INDEX)
 544                                 radeon_uvd_force_into_uvd_segment(bo, allowed);
 545
 546                         initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
 547                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 548                         bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
 549                                        initial_bytes_moved;
 550
 551                         if (unlikely(r)) {
 552                                 if (r != -ERESTARTSYS &&
 553                                     domain != lobj->allowed_domains) {
 554                                         domain = lobj->allowed_domains;
 555                                         goto retry;
 556                                 }
 557                                 ttm_eu_backoff_reservation(ticket, head);
 558                                 return r;
 559                         }
 560                 }
 561                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 562                 lobj->tiling_flags = bo->tiling_flags;
 563         }
 564         return 0;
 565 }
 566
 567 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 568                              struct vm_area_struct *vma)
 569 {
 570         return ttm_fbdev_mmap(vma, &bo->tbo);
 571 }
 572
 573 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 574 {
 575         struct radeon_device *rdev = bo->rdev;
 576         struct radeon_surface_reg *reg;
 577         struct radeon_bo *old_object;
 578         int steal;
 579         int i;
 580
 581         lockdep_assert_held(&bo->tbo.resv->lock.base);
 582
 583         if (!bo->tiling_flags)
 584                 return 0;
 585
 586         if (bo->surface_reg >= 0) {
 587                 reg = &rdev->surface_regs[bo->surface_reg];
 588                 i = bo->surface_reg;
 589                 goto out;
 590         }
 591
 592         steal = -1;
 593         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 594
 595                 reg = &rdev->surface_regs[i];
 596                 if (!reg->bo)
 597                         break;
 598
 599                 old_object = reg->bo;
 600                 if (old_object->pin_count == 0)
 601                         steal = i;
 602         }
 603
 604         /* if we are all out */
 605         if (i == RADEON_GEM_MAX_SURFACES) {
 606                 if (steal == -1)
 607                         return -ENOMEM;
 608                 /* find someone with a surface reg and nuke their BO */
 609                 reg = &rdev->surface_regs[steal];
 610                 old_object = reg->bo;
 611                 /* blow away the mapping */
 612                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 613                 ttm_bo_unmap_virtual(&old_object->tbo);
 614                 old_object->surface_reg = -1;
 615                 i = steal;
 616         }
 617
 618         bo->surface_reg = i;
 619         reg->bo = bo;
 620
 621 out:
 622         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 623                                bo->tbo.mem.start << PAGE_SHIFT,
 624                                bo->tbo.num_pages << PAGE_SHIFT);
 625         return 0;
 626 }
 627
 628 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 629 {
 630         struct radeon_device *rdev = bo->rdev;
 631         struct radeon_surface_reg *reg;
 632
 633         if (bo->surface_reg == -1)
 634                 return;
 635
 636         reg = &rdev->surface_regs[bo->surface_reg];
 637         radeon_clear_surface_reg(rdev, bo->surface_reg);
 638
 639         reg->bo = NULL;
 640         bo->surface_reg = -1;
 641 }
 642
 643 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 644                                 uint32_t tiling_flags, uint32_t pitch)
 645 {
 646         struct radeon_device *rdev = bo->rdev;
 647         int r;
 648
 649         if (rdev->family >= CHIP_CEDAR) {
 650                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 651
 652                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 653                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 654                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 655                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 656                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 657                 switch (bankw) {
 658                 case 0:
 659                 case 1:
 660                 case 2:
 661                 case 4:
 662                 case 8:
 663                         break;
 664                 default:
 665                         return -EINVAL;
 666                 }
 667                 switch (bankh) {
 668                 case 0:
 669                 case 1:
 670                 case 2:
 671                 case 4:
 672                 case 8:
 673                         break;
 674                 default:
 675                         return -EINVAL;
 676                 }
 677                 switch (mtaspect) {
 678                 case 0:
 679                 case 1:
 680                 case 2:
 681                 case 4:
 682                 case 8:
 683                         break;
 684                 default:
 685                         return -EINVAL;
 686                 }
 687                 if (tilesplit > 6) {
 688                         return -EINVAL;
 689                 }
 690                 if (stilesplit > 6) {
 691                         return -EINVAL;
 692                 }
 693         }
 694         r = radeon_bo_reserve(bo, false);
 695         if (unlikely(r != 0))
 696                 return r;
 697         bo->tiling_flags = tiling_flags;
 698         bo->pitch = pitch;
 699         radeon_bo_unreserve(bo);
 700         return 0;
 701 }
 702
 703 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 704                                 uint32_t *tiling_flags,
 705                                 uint32_t *pitch)
 706 {
 707         lockdep_assert_held(&bo->tbo.resv->lock.base);
 708
 709         if (tiling_flags)
 710                 *tiling_flags = bo->tiling_flags;
 711         if (pitch)
 712                 *pitch = bo->pitch;
 713 }
 714
 715 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 716                                 bool force_drop)
 717 {
 718         if (!force_drop)
 719                 lockdep_assert_held(&bo->tbo.resv->lock.base);
 720
 721         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 722                 return 0;
 723
 724         if (force_drop) {
 725                 radeon_bo_clear_surface_reg(bo);
 726                 return 0;
 727         }
 728
 729         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 730                 if (!has_moved)
 731                         return 0;
 732
 733                 if (bo->surface_reg >= 0)
 734                         radeon_bo_clear_surface_reg(bo);
 735                 return 0;
 736         }
 737
 738         if ((bo->surface_reg >= 0) && !has_moved)
 739                 return 0;
 740
 741         return radeon_bo_get_surface_reg(bo);
 742 }
 743
 744 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 745                            struct ttm_mem_reg *new_mem)
 746 {
 747         struct radeon_bo *rbo;
 748
 749         if (!radeon_ttm_bo_is_radeon_bo(bo))
 750                 return;
 751
 752         rbo = container_of(bo, struct radeon_bo, tbo);
 753         radeon_bo_check_tiling(rbo, 0, 1);
 754         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 755
 756         /* update statistics */
 757         if (!new_mem)
 758                 return;
 759
 760         radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
 761         radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
 762 }
 763
 764 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 765 {
 766         struct radeon_device *rdev;
 767         struct radeon_bo *rbo;
 768         unsigned long offset, size, lpfn;
 769         int i, r;
 770
 771         if (!radeon_ttm_bo_is_radeon_bo(bo))
 772                 return 0;
 773         rbo = container_of(bo, struct radeon_bo, tbo);
 774         radeon_bo_check_tiling(rbo, 0, 0);
 775         rdev = rbo->rdev;
 776         if (bo->mem.mem_type != TTM_PL_VRAM)
 777                 return 0;
 778
 779         size = bo->mem.num_pages << PAGE_SHIFT;
 780         offset = bo->mem.start << PAGE_SHIFT;
 781         if ((offset + size) <= rdev->mc.visible_vram_size)
 782                 return 0;
 783
 784         /* hurrah the memory is not visible ! */
 785         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 786         lpfn =  rdev->mc.visible_vram_size >> PAGE_SHIFT;
 787         for (i = 0; i < rbo->placement.num_placement; i++) {
 788                 /* Force into visible VRAM */
 789                 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 790                     (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
 791                         rbo->placements[i].lpfn = lpfn;
 792         }
 793         r = ttm_bo_validate(bo, &rbo->placement, false, false);
 794         if (unlikely(r == -ENOMEM)) {
 795                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 796                 return ttm_bo_validate(bo, &rbo->placement, false, false);
 797         } else if (unlikely(r != 0)) {
 798                 return r;
 799         }
 800
 801         offset = bo->mem.start << PAGE_SHIFT;
 802         /* this should never happen */
 803         if ((offset + size) > rdev->mc.visible_vram_size)
 804                 return -EINVAL;
 805
 806         return 0;
 807 }
 808
 809 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 810 {
 811         int r;
 812
 813         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
 814         if (unlikely(r != 0))
 815                 return r;
 816         if (mem_type)
 817                 *mem_type = bo->tbo.mem.mem_type;
 818
 819         r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 820         ttm_bo_unreserve(&bo->tbo);
 821         return r;
 822 }