2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/radeon_drm.h>
31 #include "radeon_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * radeon_vm_num_pde - return the number of page directory entries
56 * @rdev: radeon_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size;
66 * radeon_vm_directory_size - returns the size of the page directory in bytes
68 * @rdev: radeon_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned radeon_vm_directory_size(struct radeon_device *rdev)
74 return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8);
78 * radeon_vm_manager_init - init the vm manager
80 * @rdev: radeon_device pointer
82 * Init the vm manager (cayman+).
83 * Returns 0 for success, error for failure.
85 int radeon_vm_manager_init(struct radeon_device *rdev)
89 if (!rdev->vm_manager.enabled) {
90 r = radeon_asic_vm_init(rdev);
94 rdev->vm_manager.enabled = true;
100 * radeon_vm_manager_fini - tear down the vm manager
102 * @rdev: radeon_device pointer
104 * Tear down the VM manager (cayman+).
106 void radeon_vm_manager_fini(struct radeon_device *rdev)
110 if (!rdev->vm_manager.enabled)
113 for (i = 0; i < RADEON_NUM_VM; ++i)
114 radeon_fence_unref(&rdev->vm_manager.active[i]);
115 radeon_asic_vm_fini(rdev);
116 rdev->vm_manager.enabled = false;
120 * radeon_vm_get_bos - add the vm BOs to a validation list
122 * @vm: vm providing the BOs
123 * @head: head of validation list
125 * Add the page directory to the list of BOs to
126 * validate for command submission (cayman+).
128 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
129 struct radeon_vm *vm,
130 struct list_head *head)
132 struct radeon_cs_reloc *list;
135 list = drm_malloc_ab(vm->max_pde_used + 2,
136 sizeof(struct radeon_cs_reloc));
140 /* add the vm page table to the list */
142 list[0].robj = vm->page_directory;
143 list[0].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
144 list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
145 list[0].tv.bo = &vm->page_directory->tbo;
146 list[0].tv.shared = true;
147 list[0].tiling_flags = 0;
149 list_add(&list[0].tv.head, head);
151 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
152 if (!vm->page_tables[i].bo)
155 list[idx].gobj = NULL;
156 list[idx].robj = vm->page_tables[i].bo;
157 list[idx].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
158 list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
159 list[idx].tv.bo = &list[idx].robj->tbo;
160 list[idx].tv.shared = true;
161 list[idx].tiling_flags = 0;
162 list[idx].handle = 0;
163 list_add(&list[idx++].tv.head, head);
170 * radeon_vm_grab_id - allocate the next free VMID
172 * @rdev: radeon_device pointer
173 * @vm: vm to allocate id for
174 * @ring: ring we want to submit job to
176 * Allocate an id for the vm (cayman+).
177 * Returns the fence we need to sync to (if any).
179 * Global and local mutex must be locked!
181 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
182 struct radeon_vm *vm, int ring)
184 struct radeon_fence *best[RADEON_NUM_RINGS] = {};
185 struct radeon_vm_id *vm_id = &vm->ids[ring];
187 unsigned choices[2] = {};
190 /* check if the id is still valid */
191 if (vm_id->id && vm_id->last_id_use &&
192 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id])
195 /* we definately need to flush */
196 vm_id->pd_gpu_addr = ~0ll;
198 /* skip over VMID 0, since it is the system VM */
199 for (i = 1; i < rdev->vm_manager.nvm; ++i) {
200 struct radeon_fence *fence = rdev->vm_manager.active[i];
203 /* found a free one */
205 trace_radeon_vm_grab_id(i, ring);
209 if (radeon_fence_is_earlier(fence, best[fence->ring])) {
210 best[fence->ring] = fence;
211 choices[fence->ring == ring ? 0 : 1] = i;
215 for (i = 0; i < 2; ++i) {
217 vm_id->id = choices[i];
218 trace_radeon_vm_grab_id(choices[i], ring);
219 return rdev->vm_manager.active[choices[i]];
223 /* should never happen */
229 * radeon_vm_flush - hardware flush the vm
231 * @rdev: radeon_device pointer
232 * @vm: vm we want to flush
233 * @ring: ring to use for flush
234 * @updates: last vm update that is waited for
236 * Flush the vm (cayman+).
238 * Global and local mutex must be locked!
240 void radeon_vm_flush(struct radeon_device *rdev,
241 struct radeon_vm *vm,
242 int ring, struct radeon_fence *updates)
244 uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
245 struct radeon_vm_id *vm_id = &vm->ids[ring];
247 if (pd_addr != vm_id->pd_gpu_addr || !vm_id->flushed_updates ||
248 radeon_fence_is_earlier(vm_id->flushed_updates, updates)) {
250 trace_radeon_vm_flush(pd_addr, ring, vm->ids[ring].id);
251 radeon_fence_unref(&vm_id->flushed_updates);
252 vm_id->flushed_updates = radeon_fence_ref(updates);
253 vm_id->pd_gpu_addr = pd_addr;
254 radeon_ring_vm_flush(rdev, &rdev->ring[ring],
255 vm_id->id, vm_id->pd_gpu_addr);
261 * radeon_vm_fence - remember fence for vm
263 * @rdev: radeon_device pointer
264 * @vm: vm we want to fence
265 * @fence: fence to remember
267 * Fence the vm (cayman+).
268 * Set the fence used to protect page table and id.
270 * Global and local mutex must be locked!
272 void radeon_vm_fence(struct radeon_device *rdev,
273 struct radeon_vm *vm,
274 struct radeon_fence *fence)
276 unsigned vm_id = vm->ids[fence->ring].id;
278 radeon_fence_unref(&rdev->vm_manager.active[vm_id]);
279 rdev->vm_manager.active[vm_id] = radeon_fence_ref(fence);
281 radeon_fence_unref(&vm->ids[fence->ring].last_id_use);
282 vm->ids[fence->ring].last_id_use = radeon_fence_ref(fence);
286 * radeon_vm_bo_find - find the bo_va for a specific vm & bo
289 * @bo: requested buffer object
291 * Find @bo inside the requested vm (cayman+).
292 * Search inside the @bos vm list for the requested vm
293 * Returns the found bo_va or NULL if none is found
295 * Object has to be reserved!
297 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
298 struct radeon_bo *bo)
300 struct radeon_bo_va *bo_va;
302 list_for_each_entry(bo_va, &bo->va, bo_list) {
303 if (bo_va->vm == vm) {
311 * radeon_vm_bo_add - add a bo to a specific vm
313 * @rdev: radeon_device pointer
315 * @bo: radeon buffer object
317 * Add @bo into the requested vm (cayman+).
318 * Add @bo to the list of bos associated with the vm
319 * Returns newly added bo_va or NULL for failure
321 * Object has to be reserved!
323 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
324 struct radeon_vm *vm,
325 struct radeon_bo *bo)
327 struct radeon_bo_va *bo_va;
329 bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
339 bo_va->ref_count = 1;
340 INIT_LIST_HEAD(&bo_va->bo_list);
341 INIT_LIST_HEAD(&bo_va->vm_status);
343 mutex_lock(&vm->mutex);
344 list_add_tail(&bo_va->bo_list, &bo->va);
345 mutex_unlock(&vm->mutex);
351 * radeon_vm_set_pages - helper to call the right asic function
353 * @rdev: radeon_device pointer
354 * @ib: indirect buffer to fill with commands
355 * @pe: addr of the page entry
356 * @addr: dst addr to write into pe
357 * @count: number of page entries to update
358 * @incr: increase next addr by incr bytes
359 * @flags: hw access flags
361 * Traces the parameters and calls the right asic functions
362 * to setup the page table using the DMA.
364 static void radeon_vm_set_pages(struct radeon_device *rdev,
365 struct radeon_ib *ib,
367 uint64_t addr, unsigned count,
368 uint32_t incr, uint32_t flags)
370 trace_radeon_vm_set_page(pe, addr, count, incr, flags);
372 if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
373 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
374 radeon_asic_vm_copy_pages(rdev, ib, pe, src, count);
376 } else if ((flags & R600_PTE_SYSTEM) || (count < 3)) {
377 radeon_asic_vm_write_pages(rdev, ib, pe, addr,
381 radeon_asic_vm_set_pages(rdev, ib, pe, addr,
387 * radeon_vm_clear_bo - initially clear the page dir/table
389 * @rdev: radeon_device pointer
392 static int radeon_vm_clear_bo(struct radeon_device *rdev,
393 struct radeon_bo *bo)
400 r = radeon_bo_reserve(bo, false);
404 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
406 goto error_unreserve;
408 addr = radeon_bo_gpu_offset(bo);
409 entries = radeon_bo_size(bo) / 8;
411 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, 256);
413 goto error_unreserve;
417 radeon_vm_set_pages(rdev, &ib, addr, 0, entries, 0, 0);
418 radeon_asic_vm_pad_ib(rdev, &ib);
419 WARN_ON(ib.length_dw > 64);
421 r = radeon_ib_schedule(rdev, &ib, NULL, false);
425 ib.fence->is_vm_update = true;
426 radeon_bo_fence(bo, ib.fence, false);
429 radeon_ib_free(rdev, &ib);
432 radeon_bo_unreserve(bo);
437 * radeon_vm_bo_set_addr - set bos virtual address inside a vm
439 * @rdev: radeon_device pointer
440 * @bo_va: bo_va to store the address
441 * @soffset: requested offset of the buffer in the VM address space
442 * @flags: attributes of pages (read/write/valid/etc.)
444 * Set offset of @bo_va (cayman+).
445 * Validate and set the offset requested within the vm address space.
446 * Returns 0 for success, error for failure.
448 * Object has to be reserved and gets unreserved by this function!
450 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
451 struct radeon_bo_va *bo_va,
455 uint64_t size = radeon_bo_size(bo_va->bo);
456 struct radeon_vm *vm = bo_va->vm;
457 unsigned last_pfn, pt_idx;
462 /* make sure object fit at this offset */
463 eoffset = soffset + size;
464 if (soffset >= eoffset) {
468 last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
469 if (last_pfn > rdev->vm_manager.max_pfn) {
470 dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n",
471 last_pfn, rdev->vm_manager.max_pfn);
476 eoffset = last_pfn = 0;
479 mutex_lock(&vm->mutex);
480 if (bo_va->it.start || bo_va->it.last) {
482 /* add a clone of the bo_va to clear the old address */
483 struct radeon_bo_va *tmp;
484 tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
486 mutex_unlock(&vm->mutex);
489 tmp->it.start = bo_va->it.start;
490 tmp->it.last = bo_va->it.last;
492 tmp->addr = bo_va->addr;
493 tmp->bo = radeon_bo_ref(bo_va->bo);
494 list_add(&tmp->vm_status, &vm->freed);
497 interval_tree_remove(&bo_va->it, &vm->va);
502 soffset /= RADEON_GPU_PAGE_SIZE;
503 eoffset /= RADEON_GPU_PAGE_SIZE;
504 if (soffset || eoffset) {
505 struct interval_tree_node *it;
506 it = interval_tree_iter_first(&vm->va, soffset, eoffset - 1);
508 struct radeon_bo_va *tmp;
509 tmp = container_of(it, struct radeon_bo_va, it);
510 /* bo and tmp overlap, invalid offset */
511 dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with "
512 "(bo %p 0x%010lx 0x%010lx)\n", bo_va->bo,
513 soffset, tmp->bo, tmp->it.start, tmp->it.last);
514 mutex_unlock(&vm->mutex);
517 bo_va->it.start = soffset;
518 bo_va->it.last = eoffset - 1;
519 interval_tree_insert(&bo_va->it, &vm->va);
522 bo_va->flags = flags;
525 soffset >>= radeon_vm_block_size;
526 eoffset >>= radeon_vm_block_size;
528 BUG_ON(eoffset >= radeon_vm_num_pdes(rdev));
530 if (eoffset > vm->max_pde_used)
531 vm->max_pde_used = eoffset;
533 radeon_bo_unreserve(bo_va->bo);
535 /* walk over the address space and allocate the page tables */
536 for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) {
537 struct radeon_bo *pt;
539 if (vm->page_tables[pt_idx].bo)
542 /* drop mutex to allocate and clear page table */
543 mutex_unlock(&vm->mutex);
545 r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
546 RADEON_GPU_PAGE_SIZE, true,
547 RADEON_GEM_DOMAIN_VRAM, 0,
552 r = radeon_vm_clear_bo(rdev, pt);
554 radeon_bo_unref(&pt);
555 radeon_bo_reserve(bo_va->bo, false);
559 /* aquire mutex again */
560 mutex_lock(&vm->mutex);
561 if (vm->page_tables[pt_idx].bo) {
562 /* someone else allocated the pt in the meantime */
563 mutex_unlock(&vm->mutex);
564 radeon_bo_unref(&pt);
565 mutex_lock(&vm->mutex);
569 vm->page_tables[pt_idx].addr = 0;
570 vm->page_tables[pt_idx].bo = pt;
573 mutex_unlock(&vm->mutex);
578 * radeon_vm_map_gart - get the physical address of a gart page
580 * @rdev: radeon_device pointer
581 * @addr: the unmapped addr
583 * Look up the physical address of the page that the pte resolves
585 * Returns the physical address of the page.
587 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
591 /* page table offset */
592 result = rdev->gart.pages_addr[addr >> PAGE_SHIFT];
594 /* in case cpu page size != gpu page size*/
595 result |= addr & (~PAGE_MASK);
601 * radeon_vm_page_flags - translate page flags to what the hw uses
603 * @flags: flags comming from userspace
605 * Translate the flags the userspace ABI uses to hw flags.
607 static uint32_t radeon_vm_page_flags(uint32_t flags)
609 uint32_t hw_flags = 0;
610 hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
611 hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
612 hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
613 if (flags & RADEON_VM_PAGE_SYSTEM) {
614 hw_flags |= R600_PTE_SYSTEM;
615 hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
621 * radeon_vm_update_pdes - make sure that page directory is valid
623 * @rdev: radeon_device pointer
625 * @start: start of GPU address range
626 * @end: end of GPU address range
628 * Allocates new page tables if necessary
629 * and updates the page directory (cayman+).
630 * Returns 0 for success, error for failure.
632 * Global and local mutex must be locked!
634 int radeon_vm_update_page_directory(struct radeon_device *rdev,
635 struct radeon_vm *vm)
637 struct radeon_bo *pd = vm->page_directory;
638 uint64_t pd_addr = radeon_bo_gpu_offset(pd);
639 uint32_t incr = RADEON_VM_PTE_COUNT * 8;
640 uint64_t last_pde = ~0, last_pt = ~0;
641 unsigned count = 0, pt_idx, ndw;
648 /* assume the worst case */
649 ndw += vm->max_pde_used * 6;
651 /* update too big for an IB */
655 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
660 /* walk over the address space and update the page directory */
661 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
662 struct radeon_bo *bo = vm->page_tables[pt_idx].bo;
668 pt = radeon_bo_gpu_offset(bo);
669 if (vm->page_tables[pt_idx].addr == pt)
671 vm->page_tables[pt_idx].addr = pt;
673 pde = pd_addr + pt_idx * 8;
674 if (((last_pde + 8 * count) != pde) ||
675 ((last_pt + incr * count) != pt)) {
678 radeon_vm_set_pages(rdev, &ib, last_pde,
679 last_pt, count, incr,
692 radeon_vm_set_pages(rdev, &ib, last_pde, last_pt, count,
693 incr, R600_PTE_VALID);
695 if (ib.length_dw != 0) {
696 radeon_asic_vm_pad_ib(rdev, &ib);
698 radeon_sync_resv(rdev, &ib.sync, pd->tbo.resv, true);
699 WARN_ON(ib.length_dw > ndw);
700 r = radeon_ib_schedule(rdev, &ib, NULL, false);
702 radeon_ib_free(rdev, &ib);
705 ib.fence->is_vm_update = true;
706 radeon_bo_fence(pd, ib.fence, false);
708 radeon_ib_free(rdev, &ib);
714 * radeon_vm_frag_ptes - add fragment information to PTEs
716 * @rdev: radeon_device pointer
717 * @ib: IB for the update
718 * @pe_start: first PTE to handle
719 * @pe_end: last PTE to handle
720 * @addr: addr those PTEs should point to
721 * @flags: hw mapping flags
723 * Global and local mutex must be locked!
725 static void radeon_vm_frag_ptes(struct radeon_device *rdev,
726 struct radeon_ib *ib,
727 uint64_t pe_start, uint64_t pe_end,
728 uint64_t addr, uint32_t flags)
731 * The MC L1 TLB supports variable sized pages, based on a fragment
732 * field in the PTE. When this field is set to a non-zero value, page
733 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
734 * flags are considered valid for all PTEs within the fragment range
735 * and corresponding mappings are assumed to be physically contiguous.
737 * The L1 TLB can store a single PTE for the whole fragment,
738 * significantly increasing the space available for translation
739 * caching. This leads to large improvements in throughput when the
740 * TLB is under pressure.
742 * The L2 TLB distributes small and large fragments into two
743 * asymmetric partitions. The large fragment cache is significantly
744 * larger. Thus, we try to use large fragments wherever possible.
745 * Userspace can support this by aligning virtual base address and
746 * allocation size to the fragment size.
749 /* NI is optimized for 256KB fragments, SI and newer for 64KB */
750 uint64_t frag_flags = rdev->family == CHIP_CAYMAN ?
751 R600_PTE_FRAG_256KB : R600_PTE_FRAG_64KB;
752 uint64_t frag_align = rdev->family == CHIP_CAYMAN ? 0x200 : 0x80;
754 uint64_t frag_start = ALIGN(pe_start, frag_align);
755 uint64_t frag_end = pe_end & ~(frag_align - 1);
759 /* system pages are non continuously */
760 if ((flags & R600_PTE_SYSTEM) || !(flags & R600_PTE_VALID) ||
761 (frag_start >= frag_end)) {
763 count = (pe_end - pe_start) / 8;
764 radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
765 RADEON_GPU_PAGE_SIZE, flags);
769 /* handle the 4K area at the beginning */
770 if (pe_start != frag_start) {
771 count = (frag_start - pe_start) / 8;
772 radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
773 RADEON_GPU_PAGE_SIZE, flags);
774 addr += RADEON_GPU_PAGE_SIZE * count;
777 /* handle the area in the middle */
778 count = (frag_end - frag_start) / 8;
779 radeon_vm_set_pages(rdev, ib, frag_start, addr, count,
780 RADEON_GPU_PAGE_SIZE, flags | frag_flags);
782 /* handle the 4K area at the end */
783 if (frag_end != pe_end) {
784 addr += RADEON_GPU_PAGE_SIZE * count;
785 count = (pe_end - frag_end) / 8;
786 radeon_vm_set_pages(rdev, ib, frag_end, addr, count,
787 RADEON_GPU_PAGE_SIZE, flags);
792 * radeon_vm_update_ptes - make sure that page tables are valid
794 * @rdev: radeon_device pointer
796 * @start: start of GPU address range
797 * @end: end of GPU address range
798 * @dst: destination address to map to
799 * @flags: mapping flags
801 * Update the page tables in the range @start - @end (cayman+).
803 * Global and local mutex must be locked!
805 static void radeon_vm_update_ptes(struct radeon_device *rdev,
806 struct radeon_vm *vm,
807 struct radeon_ib *ib,
808 uint64_t start, uint64_t end,
809 uint64_t dst, uint32_t flags)
811 uint64_t mask = RADEON_VM_PTE_COUNT - 1;
812 uint64_t last_pte = ~0, last_dst = ~0;
816 /* walk over the address space and update the page tables */
817 for (addr = start; addr < end; ) {
818 uint64_t pt_idx = addr >> radeon_vm_block_size;
819 struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
823 radeon_sync_resv(rdev, &ib->sync, pt->tbo.resv, true);
825 if ((addr & ~mask) == (end & ~mask))
828 nptes = RADEON_VM_PTE_COUNT - (addr & mask);
830 pte = radeon_bo_gpu_offset(pt);
831 pte += (addr & mask) * 8;
833 if ((last_pte + 8 * count) != pte) {
836 radeon_vm_frag_ptes(rdev, ib, last_pte,
837 last_pte + 8 * count,
849 dst += nptes * RADEON_GPU_PAGE_SIZE;
853 radeon_vm_frag_ptes(rdev, ib, last_pte,
854 last_pte + 8 * count,
860 * radeon_vm_fence_pts - fence page tables after an update
863 * @start: start of GPU address range
864 * @end: end of GPU address range
865 * @fence: fence to use
867 * Fence the page tables in the range @start - @end (cayman+).
869 * Global and local mutex must be locked!
871 static void radeon_vm_fence_pts(struct radeon_vm *vm,
872 uint64_t start, uint64_t end,
873 struct radeon_fence *fence)
877 start >>= radeon_vm_block_size;
878 end >>= radeon_vm_block_size;
880 for (i = start; i <= end; ++i)
881 radeon_bo_fence(vm->page_tables[i].bo, fence, false);
885 * radeon_vm_bo_update - map a bo into the vm page table
887 * @rdev: radeon_device pointer
889 * @bo: radeon buffer object
892 * Fill in the page table entries for @bo (cayman+).
893 * Returns 0 for success, -EINVAL for failure.
895 * Object have to be reserved and mutex must be locked!
897 int radeon_vm_bo_update(struct radeon_device *rdev,
898 struct radeon_bo_va *bo_va,
899 struct ttm_mem_reg *mem)
901 struct radeon_vm *vm = bo_va->vm;
903 unsigned nptes, ncmds, ndw;
908 if (!bo_va->it.start) {
909 dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
914 list_del_init(&bo_va->vm_status);
916 bo_va->flags &= ~RADEON_VM_PAGE_VALID;
917 bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
918 bo_va->flags &= ~RADEON_VM_PAGE_SNOOPED;
919 if (bo_va->bo && radeon_ttm_tt_is_readonly(bo_va->bo->tbo.ttm))
920 bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE;
923 addr = mem->start << PAGE_SHIFT;
924 if (mem->mem_type != TTM_PL_SYSTEM) {
925 bo_va->flags |= RADEON_VM_PAGE_VALID;
927 if (mem->mem_type == TTM_PL_TT) {
928 bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
929 if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC)))
930 bo_va->flags |= RADEON_VM_PAGE_SNOOPED;
933 addr += rdev->vm_manager.vram_base_offset;
939 if (addr == bo_va->addr)
943 trace_radeon_vm_bo_update(bo_va);
945 nptes = bo_va->it.last - bo_va->it.start + 1;
947 /* reserve space for one command every (1 << BLOCK_SIZE) entries
948 or 2k dwords (whatever is smaller) */
949 ncmds = (nptes >> min(radeon_vm_block_size, 11)) + 1;
954 flags = radeon_vm_page_flags(bo_va->flags);
955 if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
956 /* only copy commands needed */
959 } else if (flags & R600_PTE_SYSTEM) {
960 /* header for write data commands */
963 /* body of write data command */
967 /* set page commands needed */
970 /* two extra commands for begin/end of fragment */
974 /* update too big for an IB */
978 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
983 if (!(bo_va->flags & RADEON_VM_PAGE_VALID)) {
986 for (i = 0; i < RADEON_NUM_RINGS; ++i)
987 radeon_sync_fence(&ib.sync, vm->ids[i].last_id_use);
990 radeon_vm_update_ptes(rdev, vm, &ib, bo_va->it.start,
991 bo_va->it.last + 1, addr,
992 radeon_vm_page_flags(bo_va->flags));
994 radeon_asic_vm_pad_ib(rdev, &ib);
995 WARN_ON(ib.length_dw > ndw);
997 r = radeon_ib_schedule(rdev, &ib, NULL, false);
999 radeon_ib_free(rdev, &ib);
1002 ib.fence->is_vm_update = true;
1003 radeon_vm_fence_pts(vm, bo_va->it.start, bo_va->it.last + 1, ib.fence);
1004 radeon_fence_unref(&bo_va->last_pt_update);
1005 bo_va->last_pt_update = radeon_fence_ref(ib.fence);
1006 radeon_ib_free(rdev, &ib);
1012 * radeon_vm_clear_freed - clear freed BOs in the PT
1014 * @rdev: radeon_device pointer
1017 * Make sure all freed BOs are cleared in the PT.
1018 * Returns 0 for success.
1020 * PTs have to be reserved and mutex must be locked!
1022 int radeon_vm_clear_freed(struct radeon_device *rdev,
1023 struct radeon_vm *vm)
1025 struct radeon_bo_va *bo_va, *tmp;
1028 list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
1029 r = radeon_vm_bo_update(rdev, bo_va, NULL);
1030 radeon_bo_unref(&bo_va->bo);
1031 radeon_fence_unref(&bo_va->last_pt_update);
1041 * radeon_vm_clear_invalids - clear invalidated BOs in the PT
1043 * @rdev: radeon_device pointer
1046 * Make sure all invalidated BOs are cleared in the PT.
1047 * Returns 0 for success.
1049 * PTs have to be reserved and mutex must be locked!
1051 int radeon_vm_clear_invalids(struct radeon_device *rdev,
1052 struct radeon_vm *vm)
1054 struct radeon_bo_va *bo_va, *tmp;
1057 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, vm_status) {
1058 r = radeon_vm_bo_update(rdev, bo_va, NULL);
1066 * radeon_vm_bo_rmv - remove a bo to a specific vm
1068 * @rdev: radeon_device pointer
1069 * @bo_va: requested bo_va
1071 * Remove @bo_va->bo from the requested vm (cayman+).
1073 * Object have to be reserved!
1075 void radeon_vm_bo_rmv(struct radeon_device *rdev,
1076 struct radeon_bo_va *bo_va)
1078 struct radeon_vm *vm = bo_va->vm;
1080 list_del(&bo_va->bo_list);
1082 mutex_lock(&vm->mutex);
1083 interval_tree_remove(&bo_va->it, &vm->va);
1084 list_del(&bo_va->vm_status);
1087 bo_va->bo = radeon_bo_ref(bo_va->bo);
1088 list_add(&bo_va->vm_status, &vm->freed);
1090 radeon_fence_unref(&bo_va->last_pt_update);
1094 mutex_unlock(&vm->mutex);
1098 * radeon_vm_bo_invalidate - mark the bo as invalid
1100 * @rdev: radeon_device pointer
1102 * @bo: radeon buffer object
1104 * Mark @bo as invalid (cayman+).
1106 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1107 struct radeon_bo *bo)
1109 struct radeon_bo_va *bo_va;
1111 list_for_each_entry(bo_va, &bo->va, bo_list) {
1113 mutex_lock(&bo_va->vm->mutex);
1114 list_del(&bo_va->vm_status);
1115 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1116 mutex_unlock(&bo_va->vm->mutex);
1122 * radeon_vm_init - initialize a vm instance
1124 * @rdev: radeon_device pointer
1127 * Init @vm fields (cayman+).
1129 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
1131 const unsigned align = min(RADEON_VM_PTB_ALIGN_SIZE,
1132 RADEON_VM_PTE_COUNT * 8);
1133 unsigned pd_size, pd_entries, pts_size;
1136 vm->ib_bo_va = NULL;
1137 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1139 vm->ids[i].flushed_updates = NULL;
1140 vm->ids[i].last_id_use = NULL;
1142 mutex_init(&vm->mutex);
1144 INIT_LIST_HEAD(&vm->invalidated);
1145 INIT_LIST_HEAD(&vm->freed);
1147 pd_size = radeon_vm_directory_size(rdev);
1148 pd_entries = radeon_vm_num_pdes(rdev);
1150 /* allocate page table array */
1151 pts_size = pd_entries * sizeof(struct radeon_vm_pt);
1152 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
1153 if (vm->page_tables == NULL) {
1154 DRM_ERROR("Cannot allocate memory for page table array\n");
1158 r = radeon_bo_create(rdev, pd_size, align, true,
1159 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
1160 NULL, &vm->page_directory);
1164 r = radeon_vm_clear_bo(rdev, vm->page_directory);
1166 radeon_bo_unref(&vm->page_directory);
1167 vm->page_directory = NULL;
1175 * radeon_vm_fini - tear down a vm instance
1177 * @rdev: radeon_device pointer
1180 * Tear down @vm (cayman+).
1181 * Unbind the VM and remove all bos from the vm bo list
1183 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
1185 struct radeon_bo_va *bo_va, *tmp;
1188 if (!RB_EMPTY_ROOT(&vm->va)) {
1189 dev_err(rdev->dev, "still active bo inside vm\n");
1191 rbtree_postorder_for_each_entry_safe(bo_va, tmp, &vm->va, it.rb) {
1192 interval_tree_remove(&bo_va->it, &vm->va);
1193 r = radeon_bo_reserve(bo_va->bo, false);
1195 list_del_init(&bo_va->bo_list);
1196 radeon_bo_unreserve(bo_va->bo);
1197 radeon_fence_unref(&bo_va->last_pt_update);
1201 list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
1202 radeon_bo_unref(&bo_va->bo);
1203 radeon_fence_unref(&bo_va->last_pt_update);
1207 for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
1208 radeon_bo_unref(&vm->page_tables[i].bo);
1209 kfree(vm->page_tables);
1211 radeon_bo_unref(&vm->page_directory);
1213 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1214 radeon_fence_unref(&vm->ids[i].flushed_updates);
1215 radeon_fence_unref(&vm->ids[i].last_id_use);
1218 mutex_destroy(&vm->mutex);