2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/radeon_drm.h>
31 #include "radeon_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * radeon_vm_num_pde - return the number of page directory entries
56 * @rdev: radeon_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size;
66 * radeon_vm_directory_size - returns the size of the page directory in bytes
68 * @rdev: radeon_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned radeon_vm_directory_size(struct radeon_device *rdev)
74 return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8);
78 * radeon_vm_manager_init - init the vm manager
80 * @rdev: radeon_device pointer
82 * Init the vm manager (cayman+).
83 * Returns 0 for success, error for failure.
85 int radeon_vm_manager_init(struct radeon_device *rdev)
89 if (!rdev->vm_manager.enabled) {
90 r = radeon_asic_vm_init(rdev);
94 rdev->vm_manager.enabled = true;
100 * radeon_vm_manager_fini - tear down the vm manager
102 * @rdev: radeon_device pointer
104 * Tear down the VM manager (cayman+).
106 void radeon_vm_manager_fini(struct radeon_device *rdev)
110 if (!rdev->vm_manager.enabled)
113 for (i = 0; i < RADEON_NUM_VM; ++i)
114 radeon_fence_unref(&rdev->vm_manager.active[i]);
115 radeon_asic_vm_fini(rdev);
116 rdev->vm_manager.enabled = false;
120 * radeon_vm_get_bos - add the vm BOs to a validation list
122 * @vm: vm providing the BOs
123 * @head: head of validation list
125 * Add the page directory to the list of BOs to
126 * validate for command submission (cayman+).
128 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
129 struct radeon_vm *vm,
130 struct list_head *head)
132 struct radeon_cs_reloc *list;
135 list = drm_malloc_ab(vm->max_pde_used + 2,
136 sizeof(struct radeon_cs_reloc));
140 /* add the vm page table to the list */
142 list[0].robj = vm->page_directory;
143 list[0].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
144 list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
145 list[0].tv.bo = &vm->page_directory->tbo;
146 list[0].tv.shared = true;
147 list[0].tiling_flags = 0;
149 list_add(&list[0].tv.head, head);
151 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
152 if (!vm->page_tables[i].bo)
155 list[idx].gobj = NULL;
156 list[idx].robj = vm->page_tables[i].bo;
157 list[idx].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
158 list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
159 list[idx].tv.bo = &list[idx].robj->tbo;
160 list[idx].tv.shared = true;
161 list[idx].tiling_flags = 0;
162 list[idx].handle = 0;
163 list_add(&list[idx++].tv.head, head);
170 * radeon_vm_grab_id - allocate the next free VMID
172 * @rdev: radeon_device pointer
173 * @vm: vm to allocate id for
174 * @ring: ring we want to submit job to
176 * Allocate an id for the vm (cayman+).
177 * Returns the fence we need to sync to (if any).
179 * Global and local mutex must be locked!
181 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
182 struct radeon_vm *vm, int ring)
184 struct radeon_fence *best[RADEON_NUM_RINGS] = {};
185 unsigned choices[2] = {};
188 /* check if the id is still valid */
189 if (vm->last_id_use && vm->last_id_use == rdev->vm_manager.active[vm->id])
192 /* we definately need to flush */
193 radeon_fence_unref(&vm->last_flush);
195 /* skip over VMID 0, since it is the system VM */
196 for (i = 1; i < rdev->vm_manager.nvm; ++i) {
197 struct radeon_fence *fence = rdev->vm_manager.active[i];
200 /* found a free one */
202 trace_radeon_vm_grab_id(vm->id, ring);
206 if (radeon_fence_is_earlier(fence, best[fence->ring])) {
207 best[fence->ring] = fence;
208 choices[fence->ring == ring ? 0 : 1] = i;
212 for (i = 0; i < 2; ++i) {
215 trace_radeon_vm_grab_id(vm->id, ring);
216 return rdev->vm_manager.active[choices[i]];
220 /* should never happen */
226 * radeon_vm_flush - hardware flush the vm
228 * @rdev: radeon_device pointer
229 * @vm: vm we want to flush
230 * @ring: ring to use for flush
232 * Flush the vm (cayman+).
234 * Global and local mutex must be locked!
236 void radeon_vm_flush(struct radeon_device *rdev,
237 struct radeon_vm *vm,
240 uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
242 /* if we can't remember our last VM flush then flush now! */
243 if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
244 trace_radeon_vm_flush(pd_addr, ring, vm->id);
245 vm->pd_gpu_addr = pd_addr;
246 radeon_ring_vm_flush(rdev, &rdev->ring[ring],
247 vm->id, vm->pd_gpu_addr);
252 * radeon_vm_fence - remember fence for vm
254 * @rdev: radeon_device pointer
255 * @vm: vm we want to fence
256 * @fence: fence to remember
258 * Fence the vm (cayman+).
259 * Set the fence used to protect page table and id.
261 * Global and local mutex must be locked!
263 void radeon_vm_fence(struct radeon_device *rdev,
264 struct radeon_vm *vm,
265 struct radeon_fence *fence)
267 radeon_fence_unref(&vm->fence);
268 vm->fence = radeon_fence_ref(fence);
270 radeon_fence_unref(&rdev->vm_manager.active[vm->id]);
271 rdev->vm_manager.active[vm->id] = radeon_fence_ref(fence);
273 radeon_fence_unref(&vm->last_id_use);
274 vm->last_id_use = radeon_fence_ref(fence);
276 /* we just flushed the VM, remember that */
278 vm->last_flush = radeon_fence_ref(fence);
282 * radeon_vm_bo_find - find the bo_va for a specific vm & bo
285 * @bo: requested buffer object
287 * Find @bo inside the requested vm (cayman+).
288 * Search inside the @bos vm list for the requested vm
289 * Returns the found bo_va or NULL if none is found
291 * Object has to be reserved!
293 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
294 struct radeon_bo *bo)
296 struct radeon_bo_va *bo_va;
298 list_for_each_entry(bo_va, &bo->va, bo_list) {
299 if (bo_va->vm == vm) {
307 * radeon_vm_bo_add - add a bo to a specific vm
309 * @rdev: radeon_device pointer
311 * @bo: radeon buffer object
313 * Add @bo into the requested vm (cayman+).
314 * Add @bo to the list of bos associated with the vm
315 * Returns newly added bo_va or NULL for failure
317 * Object has to be reserved!
319 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
320 struct radeon_vm *vm,
321 struct radeon_bo *bo)
323 struct radeon_bo_va *bo_va;
325 bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
335 bo_va->ref_count = 1;
336 INIT_LIST_HEAD(&bo_va->bo_list);
337 INIT_LIST_HEAD(&bo_va->vm_status);
339 mutex_lock(&vm->mutex);
340 list_add_tail(&bo_va->bo_list, &bo->va);
341 mutex_unlock(&vm->mutex);
347 * radeon_vm_set_pages - helper to call the right asic function
349 * @rdev: radeon_device pointer
350 * @ib: indirect buffer to fill with commands
351 * @pe: addr of the page entry
352 * @addr: dst addr to write into pe
353 * @count: number of page entries to update
354 * @incr: increase next addr by incr bytes
355 * @flags: hw access flags
357 * Traces the parameters and calls the right asic functions
358 * to setup the page table using the DMA.
360 static void radeon_vm_set_pages(struct radeon_device *rdev,
361 struct radeon_ib *ib,
363 uint64_t addr, unsigned count,
364 uint32_t incr, uint32_t flags)
366 trace_radeon_vm_set_page(pe, addr, count, incr, flags);
368 if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
369 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
370 radeon_asic_vm_copy_pages(rdev, ib, pe, src, count);
372 } else if ((flags & R600_PTE_SYSTEM) || (count < 3)) {
373 radeon_asic_vm_write_pages(rdev, ib, pe, addr,
377 radeon_asic_vm_set_pages(rdev, ib, pe, addr,
383 * radeon_vm_clear_bo - initially clear the page dir/table
385 * @rdev: radeon_device pointer
388 static int radeon_vm_clear_bo(struct radeon_device *rdev,
389 struct radeon_bo *bo)
396 r = radeon_bo_reserve(bo, false);
400 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
402 goto error_unreserve;
404 addr = radeon_bo_gpu_offset(bo);
405 entries = radeon_bo_size(bo) / 8;
407 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, 256);
409 goto error_unreserve;
413 radeon_vm_set_pages(rdev, &ib, addr, 0, entries, 0, 0);
414 radeon_asic_vm_pad_ib(rdev, &ib);
415 WARN_ON(ib.length_dw > 64);
417 r = radeon_ib_schedule(rdev, &ib, NULL, false);
421 radeon_bo_fence(bo, ib.fence, false);
424 radeon_ib_free(rdev, &ib);
427 radeon_bo_unreserve(bo);
432 * radeon_vm_bo_set_addr - set bos virtual address inside a vm
434 * @rdev: radeon_device pointer
435 * @bo_va: bo_va to store the address
436 * @soffset: requested offset of the buffer in the VM address space
437 * @flags: attributes of pages (read/write/valid/etc.)
439 * Set offset of @bo_va (cayman+).
440 * Validate and set the offset requested within the vm address space.
441 * Returns 0 for success, error for failure.
443 * Object has to be reserved and gets unreserved by this function!
445 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
446 struct radeon_bo_va *bo_va,
450 uint64_t size = radeon_bo_size(bo_va->bo);
451 struct radeon_vm *vm = bo_va->vm;
452 unsigned last_pfn, pt_idx;
457 /* make sure object fit at this offset */
458 eoffset = soffset + size;
459 if (soffset >= eoffset) {
463 last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
464 if (last_pfn > rdev->vm_manager.max_pfn) {
465 dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n",
466 last_pfn, rdev->vm_manager.max_pfn);
471 eoffset = last_pfn = 0;
474 mutex_lock(&vm->mutex);
475 if (bo_va->it.start || bo_va->it.last) {
477 /* add a clone of the bo_va to clear the old address */
478 struct radeon_bo_va *tmp;
479 tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
481 mutex_unlock(&vm->mutex);
484 tmp->it.start = bo_va->it.start;
485 tmp->it.last = bo_va->it.last;
487 tmp->addr = bo_va->addr;
488 tmp->bo = radeon_bo_ref(bo_va->bo);
489 list_add(&tmp->vm_status, &vm->freed);
492 interval_tree_remove(&bo_va->it, &vm->va);
497 soffset /= RADEON_GPU_PAGE_SIZE;
498 eoffset /= RADEON_GPU_PAGE_SIZE;
499 if (soffset || eoffset) {
500 struct interval_tree_node *it;
501 it = interval_tree_iter_first(&vm->va, soffset, eoffset - 1);
503 struct radeon_bo_va *tmp;
504 tmp = container_of(it, struct radeon_bo_va, it);
505 /* bo and tmp overlap, invalid offset */
506 dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with "
507 "(bo %p 0x%010lx 0x%010lx)\n", bo_va->bo,
508 soffset, tmp->bo, tmp->it.start, tmp->it.last);
509 mutex_unlock(&vm->mutex);
512 bo_va->it.start = soffset;
513 bo_va->it.last = eoffset - 1;
514 interval_tree_insert(&bo_va->it, &vm->va);
517 bo_va->flags = flags;
520 soffset >>= radeon_vm_block_size;
521 eoffset >>= radeon_vm_block_size;
523 BUG_ON(eoffset >= radeon_vm_num_pdes(rdev));
525 if (eoffset > vm->max_pde_used)
526 vm->max_pde_used = eoffset;
528 radeon_bo_unreserve(bo_va->bo);
530 /* walk over the address space and allocate the page tables */
531 for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) {
532 struct radeon_bo *pt;
534 if (vm->page_tables[pt_idx].bo)
537 /* drop mutex to allocate and clear page table */
538 mutex_unlock(&vm->mutex);
540 r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
541 RADEON_GPU_PAGE_SIZE, true,
542 RADEON_GEM_DOMAIN_VRAM, 0,
547 r = radeon_vm_clear_bo(rdev, pt);
549 radeon_bo_unref(&pt);
550 radeon_bo_reserve(bo_va->bo, false);
554 /* aquire mutex again */
555 mutex_lock(&vm->mutex);
556 if (vm->page_tables[pt_idx].bo) {
557 /* someone else allocated the pt in the meantime */
558 mutex_unlock(&vm->mutex);
559 radeon_bo_unref(&pt);
560 mutex_lock(&vm->mutex);
564 vm->page_tables[pt_idx].addr = 0;
565 vm->page_tables[pt_idx].bo = pt;
568 mutex_unlock(&vm->mutex);
573 * radeon_vm_map_gart - get the physical address of a gart page
575 * @rdev: radeon_device pointer
576 * @addr: the unmapped addr
578 * Look up the physical address of the page that the pte resolves
580 * Returns the physical address of the page.
582 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
586 /* page table offset */
587 result = rdev->gart.pages_addr[addr >> PAGE_SHIFT];
589 /* in case cpu page size != gpu page size*/
590 result |= addr & (~PAGE_MASK);
596 * radeon_vm_page_flags - translate page flags to what the hw uses
598 * @flags: flags comming from userspace
600 * Translate the flags the userspace ABI uses to hw flags.
602 static uint32_t radeon_vm_page_flags(uint32_t flags)
604 uint32_t hw_flags = 0;
605 hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
606 hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
607 hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
608 if (flags & RADEON_VM_PAGE_SYSTEM) {
609 hw_flags |= R600_PTE_SYSTEM;
610 hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
616 * radeon_vm_update_pdes - make sure that page directory is valid
618 * @rdev: radeon_device pointer
620 * @start: start of GPU address range
621 * @end: end of GPU address range
623 * Allocates new page tables if necessary
624 * and updates the page directory (cayman+).
625 * Returns 0 for success, error for failure.
627 * Global and local mutex must be locked!
629 int radeon_vm_update_page_directory(struct radeon_device *rdev,
630 struct radeon_vm *vm)
632 struct radeon_bo *pd = vm->page_directory;
633 uint64_t pd_addr = radeon_bo_gpu_offset(pd);
634 uint32_t incr = RADEON_VM_PTE_COUNT * 8;
635 uint64_t last_pde = ~0, last_pt = ~0;
636 unsigned count = 0, pt_idx, ndw;
643 /* assume the worst case */
644 ndw += vm->max_pde_used * 6;
646 /* update too big for an IB */
650 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
655 /* walk over the address space and update the page directory */
656 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
657 struct radeon_bo *bo = vm->page_tables[pt_idx].bo;
663 pt = radeon_bo_gpu_offset(bo);
664 if (vm->page_tables[pt_idx].addr == pt)
666 vm->page_tables[pt_idx].addr = pt;
668 pde = pd_addr + pt_idx * 8;
669 if (((last_pde + 8 * count) != pde) ||
670 ((last_pt + incr * count) != pt)) {
673 radeon_vm_set_pages(rdev, &ib, last_pde,
674 last_pt, count, incr,
687 radeon_vm_set_pages(rdev, &ib, last_pde, last_pt, count,
688 incr, R600_PTE_VALID);
690 if (ib.length_dw != 0) {
691 radeon_asic_vm_pad_ib(rdev, &ib);
693 radeon_sync_resv(rdev, &ib.sync, pd->tbo.resv, false);
694 WARN_ON(ib.length_dw > ndw);
695 r = radeon_ib_schedule(rdev, &ib, NULL, false);
697 radeon_ib_free(rdev, &ib);
700 radeon_bo_fence(pd, ib.fence, false);
701 radeon_fence_unref(&vm->fence);
702 vm->fence = radeon_fence_ref(ib.fence);
703 radeon_fence_unref(&vm->last_flush);
705 radeon_ib_free(rdev, &ib);
711 * radeon_vm_frag_ptes - add fragment information to PTEs
713 * @rdev: radeon_device pointer
714 * @ib: IB for the update
715 * @pe_start: first PTE to handle
716 * @pe_end: last PTE to handle
717 * @addr: addr those PTEs should point to
718 * @flags: hw mapping flags
720 * Global and local mutex must be locked!
722 static void radeon_vm_frag_ptes(struct radeon_device *rdev,
723 struct radeon_ib *ib,
724 uint64_t pe_start, uint64_t pe_end,
725 uint64_t addr, uint32_t flags)
728 * The MC L1 TLB supports variable sized pages, based on a fragment
729 * field in the PTE. When this field is set to a non-zero value, page
730 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
731 * flags are considered valid for all PTEs within the fragment range
732 * and corresponding mappings are assumed to be physically contiguous.
734 * The L1 TLB can store a single PTE for the whole fragment,
735 * significantly increasing the space available for translation
736 * caching. This leads to large improvements in throughput when the
737 * TLB is under pressure.
739 * The L2 TLB distributes small and large fragments into two
740 * asymmetric partitions. The large fragment cache is significantly
741 * larger. Thus, we try to use large fragments wherever possible.
742 * Userspace can support this by aligning virtual base address and
743 * allocation size to the fragment size.
746 /* NI is optimized for 256KB fragments, SI and newer for 64KB */
747 uint64_t frag_flags = rdev->family == CHIP_CAYMAN ?
748 R600_PTE_FRAG_256KB : R600_PTE_FRAG_64KB;
749 uint64_t frag_align = rdev->family == CHIP_CAYMAN ? 0x200 : 0x80;
751 uint64_t frag_start = ALIGN(pe_start, frag_align);
752 uint64_t frag_end = pe_end & ~(frag_align - 1);
756 /* system pages are non continuously */
757 if ((flags & R600_PTE_SYSTEM) || !(flags & R600_PTE_VALID) ||
758 (frag_start >= frag_end)) {
760 count = (pe_end - pe_start) / 8;
761 radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
762 RADEON_GPU_PAGE_SIZE, flags);
766 /* handle the 4K area at the beginning */
767 if (pe_start != frag_start) {
768 count = (frag_start - pe_start) / 8;
769 radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
770 RADEON_GPU_PAGE_SIZE, flags);
771 addr += RADEON_GPU_PAGE_SIZE * count;
774 /* handle the area in the middle */
775 count = (frag_end - frag_start) / 8;
776 radeon_vm_set_pages(rdev, ib, frag_start, addr, count,
777 RADEON_GPU_PAGE_SIZE, flags | frag_flags);
779 /* handle the 4K area at the end */
780 if (frag_end != pe_end) {
781 addr += RADEON_GPU_PAGE_SIZE * count;
782 count = (pe_end - frag_end) / 8;
783 radeon_vm_set_pages(rdev, ib, frag_end, addr, count,
784 RADEON_GPU_PAGE_SIZE, flags);
789 * radeon_vm_update_ptes - make sure that page tables are valid
791 * @rdev: radeon_device pointer
793 * @start: start of GPU address range
794 * @end: end of GPU address range
795 * @dst: destination address to map to
796 * @flags: mapping flags
798 * Update the page tables in the range @start - @end (cayman+).
800 * Global and local mutex must be locked!
802 static void radeon_vm_update_ptes(struct radeon_device *rdev,
803 struct radeon_vm *vm,
804 struct radeon_ib *ib,
805 uint64_t start, uint64_t end,
806 uint64_t dst, uint32_t flags)
808 uint64_t mask = RADEON_VM_PTE_COUNT - 1;
809 uint64_t last_pte = ~0, last_dst = ~0;
813 /* walk over the address space and update the page tables */
814 for (addr = start; addr < end; ) {
815 uint64_t pt_idx = addr >> radeon_vm_block_size;
816 struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
820 radeon_sync_resv(rdev, &ib->sync, pt->tbo.resv, false);
822 if ((addr & ~mask) == (end & ~mask))
825 nptes = RADEON_VM_PTE_COUNT - (addr & mask);
827 pte = radeon_bo_gpu_offset(pt);
828 pte += (addr & mask) * 8;
830 if ((last_pte + 8 * count) != pte) {
833 radeon_vm_frag_ptes(rdev, ib, last_pte,
834 last_pte + 8 * count,
846 dst += nptes * RADEON_GPU_PAGE_SIZE;
850 radeon_vm_frag_ptes(rdev, ib, last_pte,
851 last_pte + 8 * count,
857 * radeon_vm_fence_pts - fence page tables after an update
860 * @start: start of GPU address range
861 * @end: end of GPU address range
862 * @fence: fence to use
864 * Fence the page tables in the range @start - @end (cayman+).
866 * Global and local mutex must be locked!
868 static void radeon_vm_fence_pts(struct radeon_vm *vm,
869 uint64_t start, uint64_t end,
870 struct radeon_fence *fence)
874 start >>= radeon_vm_block_size;
875 end >>= radeon_vm_block_size;
877 for (i = start; i <= end; ++i)
878 radeon_bo_fence(vm->page_tables[i].bo, fence, false);
882 * radeon_vm_bo_update - map a bo into the vm page table
884 * @rdev: radeon_device pointer
886 * @bo: radeon buffer object
889 * Fill in the page table entries for @bo (cayman+).
890 * Returns 0 for success, -EINVAL for failure.
892 * Object have to be reserved and mutex must be locked!
894 int radeon_vm_bo_update(struct radeon_device *rdev,
895 struct radeon_bo_va *bo_va,
896 struct ttm_mem_reg *mem)
898 struct radeon_vm *vm = bo_va->vm;
900 unsigned nptes, ncmds, ndw;
905 if (!bo_va->it.start) {
906 dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
911 list_del_init(&bo_va->vm_status);
913 bo_va->flags &= ~RADEON_VM_PAGE_VALID;
914 bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
915 bo_va->flags &= ~RADEON_VM_PAGE_SNOOPED;
916 if (bo_va->bo && radeon_ttm_tt_is_readonly(bo_va->bo->tbo.ttm))
917 bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE;
920 addr = mem->start << PAGE_SHIFT;
921 if (mem->mem_type != TTM_PL_SYSTEM) {
922 bo_va->flags |= RADEON_VM_PAGE_VALID;
924 if (mem->mem_type == TTM_PL_TT) {
925 bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
926 if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC)))
927 bo_va->flags |= RADEON_VM_PAGE_SNOOPED;
930 addr += rdev->vm_manager.vram_base_offset;
936 if (addr == bo_va->addr)
940 trace_radeon_vm_bo_update(bo_va);
942 nptes = bo_va->it.last - bo_va->it.start + 1;
944 /* reserve space for one command every (1 << BLOCK_SIZE) entries
945 or 2k dwords (whatever is smaller) */
946 ncmds = (nptes >> min(radeon_vm_block_size, 11)) + 1;
951 flags = radeon_vm_page_flags(bo_va->flags);
952 if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
953 /* only copy commands needed */
956 } else if (flags & R600_PTE_SYSTEM) {
957 /* header for write data commands */
960 /* body of write data command */
964 /* set page commands needed */
967 /* two extra commands for begin/end of fragment */
971 /* update too big for an IB */
975 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
980 radeon_vm_update_ptes(rdev, vm, &ib, bo_va->it.start,
981 bo_va->it.last + 1, addr,
982 radeon_vm_page_flags(bo_va->flags));
984 radeon_asic_vm_pad_ib(rdev, &ib);
985 WARN_ON(ib.length_dw > ndw);
987 r = radeon_ib_schedule(rdev, &ib, NULL, false);
989 radeon_ib_free(rdev, &ib);
992 radeon_vm_fence_pts(vm, bo_va->it.start, bo_va->it.last + 1, ib.fence);
993 radeon_fence_unref(&vm->fence);
994 vm->fence = radeon_fence_ref(ib.fence);
995 radeon_ib_free(rdev, &ib);
996 radeon_fence_unref(&vm->last_flush);
1002 * radeon_vm_clear_freed - clear freed BOs in the PT
1004 * @rdev: radeon_device pointer
1007 * Make sure all freed BOs are cleared in the PT.
1008 * Returns 0 for success.
1010 * PTs have to be reserved and mutex must be locked!
1012 int radeon_vm_clear_freed(struct radeon_device *rdev,
1013 struct radeon_vm *vm)
1015 struct radeon_bo_va *bo_va, *tmp;
1018 list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
1019 r = radeon_vm_bo_update(rdev, bo_va, NULL);
1020 radeon_bo_unref(&bo_va->bo);
1030 * radeon_vm_clear_invalids - clear invalidated BOs in the PT
1032 * @rdev: radeon_device pointer
1035 * Make sure all invalidated BOs are cleared in the PT.
1036 * Returns 0 for success.
1038 * PTs have to be reserved and mutex must be locked!
1040 int radeon_vm_clear_invalids(struct radeon_device *rdev,
1041 struct radeon_vm *vm)
1043 struct radeon_bo_va *bo_va, *tmp;
1046 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, vm_status) {
1047 r = radeon_vm_bo_update(rdev, bo_va, NULL);
1055 * radeon_vm_bo_rmv - remove a bo to a specific vm
1057 * @rdev: radeon_device pointer
1058 * @bo_va: requested bo_va
1060 * Remove @bo_va->bo from the requested vm (cayman+).
1062 * Object have to be reserved!
1064 void radeon_vm_bo_rmv(struct radeon_device *rdev,
1065 struct radeon_bo_va *bo_va)
1067 struct radeon_vm *vm = bo_va->vm;
1069 list_del(&bo_va->bo_list);
1071 mutex_lock(&vm->mutex);
1072 interval_tree_remove(&bo_va->it, &vm->va);
1073 list_del(&bo_va->vm_status);
1076 bo_va->bo = radeon_bo_ref(bo_va->bo);
1077 list_add(&bo_va->vm_status, &vm->freed);
1082 mutex_unlock(&vm->mutex);
1086 * radeon_vm_bo_invalidate - mark the bo as invalid
1088 * @rdev: radeon_device pointer
1090 * @bo: radeon buffer object
1092 * Mark @bo as invalid (cayman+).
1094 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1095 struct radeon_bo *bo)
1097 struct radeon_bo_va *bo_va;
1099 list_for_each_entry(bo_va, &bo->va, bo_list) {
1101 mutex_lock(&bo_va->vm->mutex);
1102 list_del(&bo_va->vm_status);
1103 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1104 mutex_unlock(&bo_va->vm->mutex);
1110 * radeon_vm_init - initialize a vm instance
1112 * @rdev: radeon_device pointer
1115 * Init @vm fields (cayman+).
1117 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
1119 const unsigned align = min(RADEON_VM_PTB_ALIGN_SIZE,
1120 RADEON_VM_PTE_COUNT * 8);
1121 unsigned pd_size, pd_entries, pts_size;
1125 vm->ib_bo_va = NULL;
1127 vm->last_flush = NULL;
1128 vm->last_id_use = NULL;
1129 mutex_init(&vm->mutex);
1131 INIT_LIST_HEAD(&vm->invalidated);
1132 INIT_LIST_HEAD(&vm->freed);
1134 pd_size = radeon_vm_directory_size(rdev);
1135 pd_entries = radeon_vm_num_pdes(rdev);
1137 /* allocate page table array */
1138 pts_size = pd_entries * sizeof(struct radeon_vm_pt);
1139 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
1140 if (vm->page_tables == NULL) {
1141 DRM_ERROR("Cannot allocate memory for page table array\n");
1145 r = radeon_bo_create(rdev, pd_size, align, true,
1146 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
1147 NULL, &vm->page_directory);
1151 r = radeon_vm_clear_bo(rdev, vm->page_directory);
1153 radeon_bo_unref(&vm->page_directory);
1154 vm->page_directory = NULL;
1162 * radeon_vm_fini - tear down a vm instance
1164 * @rdev: radeon_device pointer
1167 * Tear down @vm (cayman+).
1168 * Unbind the VM and remove all bos from the vm bo list
1170 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
1172 struct radeon_bo_va *bo_va, *tmp;
1175 if (!RB_EMPTY_ROOT(&vm->va)) {
1176 dev_err(rdev->dev, "still active bo inside vm\n");
1178 rbtree_postorder_for_each_entry_safe(bo_va, tmp, &vm->va, it.rb) {
1179 interval_tree_remove(&bo_va->it, &vm->va);
1180 r = radeon_bo_reserve(bo_va->bo, false);
1182 list_del_init(&bo_va->bo_list);
1183 radeon_bo_unreserve(bo_va->bo);
1187 list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
1188 radeon_bo_unref(&bo_va->bo);
1192 for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
1193 radeon_bo_unref(&vm->page_tables[i].bo);
1194 kfree(vm->page_tables);
1196 radeon_bo_unref(&vm->page_directory);
1198 radeon_fence_unref(&vm->fence);
1199 radeon_fence_unref(&vm->last_flush);
1200 radeon_fence_unref(&vm->last_id_use);
1202 mutex_destroy(&vm->mutex);