2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/radeon_drm.h>
31 #include "radeon_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * radeon_vm_num_pde - return the number of page directory entries
56 * @rdev: radeon_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size;
66 * radeon_vm_directory_size - returns the size of the page directory in bytes
68 * @rdev: radeon_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned radeon_vm_directory_size(struct radeon_device *rdev)
74 return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8);
78 * radeon_vm_manager_init - init the vm manager
80 * @rdev: radeon_device pointer
82 * Init the vm manager (cayman+).
83 * Returns 0 for success, error for failure.
85 int radeon_vm_manager_init(struct radeon_device *rdev)
89 if (!rdev->vm_manager.enabled) {
90 r = radeon_asic_vm_init(rdev);
94 rdev->vm_manager.enabled = true;
100 * radeon_vm_manager_fini - tear down the vm manager
102 * @rdev: radeon_device pointer
104 * Tear down the VM manager (cayman+).
106 void radeon_vm_manager_fini(struct radeon_device *rdev)
110 if (!rdev->vm_manager.enabled)
113 for (i = 0; i < RADEON_NUM_VM; ++i)
114 radeon_fence_unref(&rdev->vm_manager.active[i]);
115 radeon_asic_vm_fini(rdev);
116 rdev->vm_manager.enabled = false;
120 * radeon_vm_get_bos - add the vm BOs to a validation list
122 * @vm: vm providing the BOs
123 * @head: head of validation list
125 * Add the page directory to the list of BOs to
126 * validate for command submission (cayman+).
128 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
129 struct radeon_vm *vm,
130 struct list_head *head)
132 struct radeon_cs_reloc *list;
135 list = kmalloc_array(vm->max_pde_used + 2,
136 sizeof(struct radeon_cs_reloc), GFP_KERNEL);
140 /* add the vm page table to the list */
142 list[0].robj = vm->page_directory;
143 list[0].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
144 list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
145 list[0].tv.bo = &vm->page_directory->tbo;
146 list[0].tiling_flags = 0;
148 list_add(&list[0].tv.head, head);
150 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
151 if (!vm->page_tables[i].bo)
154 list[idx].gobj = NULL;
155 list[idx].robj = vm->page_tables[i].bo;
156 list[idx].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
157 list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
158 list[idx].tv.bo = &list[idx].robj->tbo;
159 list[idx].tiling_flags = 0;
160 list[idx].handle = 0;
161 list_add(&list[idx++].tv.head, head);
168 * radeon_vm_grab_id - allocate the next free VMID
170 * @rdev: radeon_device pointer
171 * @vm: vm to allocate id for
172 * @ring: ring we want to submit job to
174 * Allocate an id for the vm (cayman+).
175 * Returns the fence we need to sync to (if any).
177 * Global and local mutex must be locked!
179 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
180 struct radeon_vm *vm, int ring)
182 struct radeon_fence *best[RADEON_NUM_RINGS] = {};
183 unsigned choices[2] = {};
186 /* check if the id is still valid */
187 if (vm->last_id_use && vm->last_id_use == rdev->vm_manager.active[vm->id])
190 /* we definately need to flush */
191 radeon_fence_unref(&vm->last_flush);
193 /* skip over VMID 0, since it is the system VM */
194 for (i = 1; i < rdev->vm_manager.nvm; ++i) {
195 struct radeon_fence *fence = rdev->vm_manager.active[i];
198 /* found a free one */
200 trace_radeon_vm_grab_id(vm->id, ring);
204 if (radeon_fence_is_earlier(fence, best[fence->ring])) {
205 best[fence->ring] = fence;
206 choices[fence->ring == ring ? 0 : 1] = i;
210 for (i = 0; i < 2; ++i) {
213 trace_radeon_vm_grab_id(vm->id, ring);
214 return rdev->vm_manager.active[choices[i]];
218 /* should never happen */
224 * radeon_vm_flush - hardware flush the vm
226 * @rdev: radeon_device pointer
227 * @vm: vm we want to flush
228 * @ring: ring to use for flush
230 * Flush the vm (cayman+).
232 * Global and local mutex must be locked!
234 void radeon_vm_flush(struct radeon_device *rdev,
235 struct radeon_vm *vm,
238 uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
240 /* if we can't remember our last VM flush then flush now! */
241 if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
242 trace_radeon_vm_flush(pd_addr, ring, vm->id);
243 vm->pd_gpu_addr = pd_addr;
244 radeon_ring_vm_flush(rdev, ring, vm);
249 * radeon_vm_fence - remember fence for vm
251 * @rdev: radeon_device pointer
252 * @vm: vm we want to fence
253 * @fence: fence to remember
255 * Fence the vm (cayman+).
256 * Set the fence used to protect page table and id.
258 * Global and local mutex must be locked!
260 void radeon_vm_fence(struct radeon_device *rdev,
261 struct radeon_vm *vm,
262 struct radeon_fence *fence)
264 radeon_fence_unref(&vm->fence);
265 vm->fence = radeon_fence_ref(fence);
267 radeon_fence_unref(&rdev->vm_manager.active[vm->id]);
268 rdev->vm_manager.active[vm->id] = radeon_fence_ref(fence);
270 radeon_fence_unref(&vm->last_id_use);
271 vm->last_id_use = radeon_fence_ref(fence);
273 /* we just flushed the VM, remember that */
275 vm->last_flush = radeon_fence_ref(fence);
279 * radeon_vm_bo_find - find the bo_va for a specific vm & bo
282 * @bo: requested buffer object
284 * Find @bo inside the requested vm (cayman+).
285 * Search inside the @bos vm list for the requested vm
286 * Returns the found bo_va or NULL if none is found
288 * Object has to be reserved!
290 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
291 struct radeon_bo *bo)
293 struct radeon_bo_va *bo_va;
295 list_for_each_entry(bo_va, &bo->va, bo_list) {
296 if (bo_va->vm == vm) {
304 * radeon_vm_bo_add - add a bo to a specific vm
306 * @rdev: radeon_device pointer
308 * @bo: radeon buffer object
310 * Add @bo into the requested vm (cayman+).
311 * Add @bo to the list of bos associated with the vm
312 * Returns newly added bo_va or NULL for failure
314 * Object has to be reserved!
316 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
317 struct radeon_vm *vm,
318 struct radeon_bo *bo)
320 struct radeon_bo_va *bo_va;
322 bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
332 bo_va->ref_count = 1;
333 INIT_LIST_HEAD(&bo_va->bo_list);
334 INIT_LIST_HEAD(&bo_va->vm_status);
336 mutex_lock(&vm->mutex);
337 list_add_tail(&bo_va->bo_list, &bo->va);
338 mutex_unlock(&vm->mutex);
344 * radeon_vm_set_pages - helper to call the right asic function
346 * @rdev: radeon_device pointer
347 * @ib: indirect buffer to fill with commands
348 * @pe: addr of the page entry
349 * @addr: dst addr to write into pe
350 * @count: number of page entries to update
351 * @incr: increase next addr by incr bytes
352 * @flags: hw access flags
354 * Traces the parameters and calls the right asic functions
355 * to setup the page table using the DMA.
357 static void radeon_vm_set_pages(struct radeon_device *rdev,
358 struct radeon_ib *ib,
360 uint64_t addr, unsigned count,
361 uint32_t incr, uint32_t flags)
363 trace_radeon_vm_set_page(pe, addr, count, incr, flags);
365 if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
366 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
367 radeon_asic_vm_copy_pages(rdev, ib, pe, src, count);
369 } else if ((flags & R600_PTE_SYSTEM) || (count < 3)) {
370 radeon_asic_vm_write_pages(rdev, ib, pe, addr,
374 radeon_asic_vm_set_pages(rdev, ib, pe, addr,
380 * radeon_vm_clear_bo - initially clear the page dir/table
382 * @rdev: radeon_device pointer
385 static int radeon_vm_clear_bo(struct radeon_device *rdev,
386 struct radeon_bo *bo)
388 struct ttm_validate_buffer tv;
389 struct ww_acquire_ctx ticket;
390 struct list_head head;
396 memset(&tv, 0, sizeof(tv));
399 INIT_LIST_HEAD(&head);
400 list_add(&tv.head, &head);
402 r = ttm_eu_reserve_buffers(&ticket, &head);
406 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
410 addr = radeon_bo_gpu_offset(bo);
411 entries = radeon_bo_size(bo) / 8;
413 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, 256);
419 radeon_vm_set_pages(rdev, &ib, addr, 0, entries, 0, 0);
420 radeon_asic_vm_pad_ib(rdev, &ib);
421 WARN_ON(ib.length_dw > 64);
423 r = radeon_ib_schedule(rdev, &ib, NULL);
427 ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
428 radeon_ib_free(rdev, &ib);
433 ttm_eu_backoff_reservation(&ticket, &head);
438 * radeon_vm_bo_set_addr - set bos virtual address inside a vm
440 * @rdev: radeon_device pointer
441 * @bo_va: bo_va to store the address
442 * @soffset: requested offset of the buffer in the VM address space
443 * @flags: attributes of pages (read/write/valid/etc.)
445 * Set offset of @bo_va (cayman+).
446 * Validate and set the offset requested within the vm address space.
447 * Returns 0 for success, error for failure.
449 * Object has to be reserved!
451 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
452 struct radeon_bo_va *bo_va,
456 uint64_t size = radeon_bo_size(bo_va->bo);
457 struct radeon_vm *vm = bo_va->vm;
458 unsigned last_pfn, pt_idx;
463 /* make sure object fit at this offset */
464 eoffset = soffset + size;
465 if (soffset >= eoffset) {
469 last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
470 if (last_pfn > rdev->vm_manager.max_pfn) {
471 dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n",
472 last_pfn, rdev->vm_manager.max_pfn);
477 eoffset = last_pfn = 0;
480 mutex_lock(&vm->mutex);
481 if (bo_va->it.start || bo_va->it.last) {
483 /* add a clone of the bo_va to clear the old address */
484 struct radeon_bo_va *tmp;
485 tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
486 tmp->it.start = bo_va->it.start;
487 tmp->it.last = bo_va->it.last;
489 tmp->addr = bo_va->addr;
490 tmp->bo = radeon_bo_ref(bo_va->bo);
491 list_add(&tmp->vm_status, &vm->freed);
494 interval_tree_remove(&bo_va->it, &vm->va);
499 soffset /= RADEON_GPU_PAGE_SIZE;
500 eoffset /= RADEON_GPU_PAGE_SIZE;
501 if (soffset || eoffset) {
502 struct interval_tree_node *it;
503 it = interval_tree_iter_first(&vm->va, soffset, eoffset - 1);
505 struct radeon_bo_va *tmp;
506 tmp = container_of(it, struct radeon_bo_va, it);
507 /* bo and tmp overlap, invalid offset */
508 dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with "
509 "(bo %p 0x%010lx 0x%010lx)\n", bo_va->bo,
510 soffset, tmp->bo, tmp->it.start, tmp->it.last);
511 mutex_unlock(&vm->mutex);
514 bo_va->it.start = soffset;
515 bo_va->it.last = eoffset - 1;
516 interval_tree_insert(&bo_va->it, &vm->va);
519 bo_va->flags = flags;
522 soffset >>= radeon_vm_block_size;
523 eoffset >>= radeon_vm_block_size;
525 BUG_ON(eoffset >= radeon_vm_num_pdes(rdev));
527 if (eoffset > vm->max_pde_used)
528 vm->max_pde_used = eoffset;
530 radeon_bo_unreserve(bo_va->bo);
532 /* walk over the address space and allocate the page tables */
533 for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) {
534 struct radeon_bo *pt;
536 if (vm->page_tables[pt_idx].bo)
539 /* drop mutex to allocate and clear page table */
540 mutex_unlock(&vm->mutex);
542 r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
543 RADEON_GPU_PAGE_SIZE, true,
544 RADEON_GEM_DOMAIN_VRAM, 0, NULL, &pt);
548 r = radeon_vm_clear_bo(rdev, pt);
550 radeon_bo_unref(&pt);
551 radeon_bo_reserve(bo_va->bo, false);
555 /* aquire mutex again */
556 mutex_lock(&vm->mutex);
557 if (vm->page_tables[pt_idx].bo) {
558 /* someone else allocated the pt in the meantime */
559 mutex_unlock(&vm->mutex);
560 radeon_bo_unref(&pt);
561 mutex_lock(&vm->mutex);
565 vm->page_tables[pt_idx].addr = 0;
566 vm->page_tables[pt_idx].bo = pt;
569 mutex_unlock(&vm->mutex);
570 return radeon_bo_reserve(bo_va->bo, false);
574 * radeon_vm_map_gart - get the physical address of a gart page
576 * @rdev: radeon_device pointer
577 * @addr: the unmapped addr
579 * Look up the physical address of the page that the pte resolves
581 * Returns the physical address of the page.
583 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
587 /* page table offset */
588 result = rdev->gart.pages_addr[addr >> PAGE_SHIFT];
590 /* in case cpu page size != gpu page size*/
591 result |= addr & (~PAGE_MASK);
597 * radeon_vm_page_flags - translate page flags to what the hw uses
599 * @flags: flags comming from userspace
601 * Translate the flags the userspace ABI uses to hw flags.
603 static uint32_t radeon_vm_page_flags(uint32_t flags)
605 uint32_t hw_flags = 0;
606 hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
607 hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
608 hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
609 if (flags & RADEON_VM_PAGE_SYSTEM) {
610 hw_flags |= R600_PTE_SYSTEM;
611 hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
617 * radeon_vm_update_pdes - make sure that page directory is valid
619 * @rdev: radeon_device pointer
621 * @start: start of GPU address range
622 * @end: end of GPU address range
624 * Allocates new page tables if necessary
625 * and updates the page directory (cayman+).
626 * Returns 0 for success, error for failure.
628 * Global and local mutex must be locked!
630 int radeon_vm_update_page_directory(struct radeon_device *rdev,
631 struct radeon_vm *vm)
633 struct radeon_bo *pd = vm->page_directory;
634 uint64_t pd_addr = radeon_bo_gpu_offset(pd);
635 uint32_t incr = RADEON_VM_PTE_COUNT * 8;
636 uint64_t last_pde = ~0, last_pt = ~0;
637 unsigned count = 0, pt_idx, ndw;
644 /* assume the worst case */
645 ndw += vm->max_pde_used * 6;
647 /* update too big for an IB */
651 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
656 /* walk over the address space and update the page directory */
657 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
658 struct radeon_bo *bo = vm->page_tables[pt_idx].bo;
664 pt = radeon_bo_gpu_offset(bo);
665 if (vm->page_tables[pt_idx].addr == pt)
667 vm->page_tables[pt_idx].addr = pt;
669 pde = pd_addr + pt_idx * 8;
670 if (((last_pde + 8 * count) != pde) ||
671 ((last_pt + incr * count) != pt)) {
674 radeon_vm_set_pages(rdev, &ib, last_pde,
675 last_pt, count, incr,
688 radeon_vm_set_pages(rdev, &ib, last_pde, last_pt, count,
689 incr, R600_PTE_VALID);
691 if (ib.length_dw != 0) {
692 radeon_asic_vm_pad_ib(rdev, &ib);
693 radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj);
694 radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use);
695 WARN_ON(ib.length_dw > ndw);
696 r = radeon_ib_schedule(rdev, &ib, NULL);
698 radeon_ib_free(rdev, &ib);
701 radeon_fence_unref(&vm->fence);
702 vm->fence = radeon_fence_ref(ib.fence);
703 radeon_fence_unref(&vm->last_flush);
705 radeon_ib_free(rdev, &ib);
711 * radeon_vm_frag_ptes - add fragment information to PTEs
713 * @rdev: radeon_device pointer
714 * @ib: IB for the update
715 * @pe_start: first PTE to handle
716 * @pe_end: last PTE to handle
717 * @addr: addr those PTEs should point to
718 * @flags: hw mapping flags
720 * Global and local mutex must be locked!
722 static void radeon_vm_frag_ptes(struct radeon_device *rdev,
723 struct radeon_ib *ib,
724 uint64_t pe_start, uint64_t pe_end,
725 uint64_t addr, uint32_t flags)
728 * The MC L1 TLB supports variable sized pages, based on a fragment
729 * field in the PTE. When this field is set to a non-zero value, page
730 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
731 * flags are considered valid for all PTEs within the fragment range
732 * and corresponding mappings are assumed to be physically contiguous.
734 * The L1 TLB can store a single PTE for the whole fragment,
735 * significantly increasing the space available for translation
736 * caching. This leads to large improvements in throughput when the
737 * TLB is under pressure.
739 * The L2 TLB distributes small and large fragments into two
740 * asymmetric partitions. The large fragment cache is significantly
741 * larger. Thus, we try to use large fragments wherever possible.
742 * Userspace can support this by aligning virtual base address and
743 * allocation size to the fragment size.
746 /* NI is optimized for 256KB fragments, SI and newer for 64KB */
747 uint64_t frag_flags = rdev->family == CHIP_CAYMAN ?
748 R600_PTE_FRAG_256KB : R600_PTE_FRAG_64KB;
749 uint64_t frag_align = rdev->family == CHIP_CAYMAN ? 0x200 : 0x80;
751 uint64_t frag_start = ALIGN(pe_start, frag_align);
752 uint64_t frag_end = pe_end & ~(frag_align - 1);
756 /* system pages are non continuously */
757 if ((flags & R600_PTE_SYSTEM) || !(flags & R600_PTE_VALID) ||
758 (frag_start >= frag_end)) {
760 count = (pe_end - pe_start) / 8;
761 radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
762 RADEON_GPU_PAGE_SIZE, flags);
766 /* handle the 4K area at the beginning */
767 if (pe_start != frag_start) {
768 count = (frag_start - pe_start) / 8;
769 radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
770 RADEON_GPU_PAGE_SIZE, flags);
771 addr += RADEON_GPU_PAGE_SIZE * count;
774 /* handle the area in the middle */
775 count = (frag_end - frag_start) / 8;
776 radeon_vm_set_pages(rdev, ib, frag_start, addr, count,
777 RADEON_GPU_PAGE_SIZE, flags | frag_flags);
779 /* handle the 4K area at the end */
780 if (frag_end != pe_end) {
781 addr += RADEON_GPU_PAGE_SIZE * count;
782 count = (pe_end - frag_end) / 8;
783 radeon_vm_set_pages(rdev, ib, frag_end, addr, count,
784 RADEON_GPU_PAGE_SIZE, flags);
789 * radeon_vm_update_ptes - make sure that page tables are valid
791 * @rdev: radeon_device pointer
793 * @start: start of GPU address range
794 * @end: end of GPU address range
795 * @dst: destination address to map to
796 * @flags: mapping flags
798 * Update the page tables in the range @start - @end (cayman+).
800 * Global and local mutex must be locked!
802 static void radeon_vm_update_ptes(struct radeon_device *rdev,
803 struct radeon_vm *vm,
804 struct radeon_ib *ib,
805 uint64_t start, uint64_t end,
806 uint64_t dst, uint32_t flags)
808 uint64_t mask = RADEON_VM_PTE_COUNT - 1;
809 uint64_t last_pte = ~0, last_dst = ~0;
813 /* walk over the address space and update the page tables */
814 for (addr = start; addr < end; ) {
815 uint64_t pt_idx = addr >> radeon_vm_block_size;
816 struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
820 radeon_semaphore_sync_to(ib->semaphore, pt->tbo.sync_obj);
822 if ((addr & ~mask) == (end & ~mask))
825 nptes = RADEON_VM_PTE_COUNT - (addr & mask);
827 pte = radeon_bo_gpu_offset(pt);
828 pte += (addr & mask) * 8;
830 if ((last_pte + 8 * count) != pte) {
833 radeon_vm_frag_ptes(rdev, ib, last_pte,
834 last_pte + 8 * count,
846 dst += nptes * RADEON_GPU_PAGE_SIZE;
850 radeon_vm_frag_ptes(rdev, ib, last_pte,
851 last_pte + 8 * count,
857 * radeon_vm_bo_update - map a bo into the vm page table
859 * @rdev: radeon_device pointer
861 * @bo: radeon buffer object
864 * Fill in the page table entries for @bo (cayman+).
865 * Returns 0 for success, -EINVAL for failure.
867 * Object have to be reserved and mutex must be locked!
869 int radeon_vm_bo_update(struct radeon_device *rdev,
870 struct radeon_bo_va *bo_va,
871 struct ttm_mem_reg *mem)
873 struct radeon_vm *vm = bo_va->vm;
875 unsigned nptes, ncmds, ndw;
880 if (!bo_va->it.start) {
881 dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
886 list_del_init(&bo_va->vm_status);
888 bo_va->flags &= ~RADEON_VM_PAGE_VALID;
889 bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
890 bo_va->flags &= ~RADEON_VM_PAGE_SNOOPED;
892 addr = mem->start << PAGE_SHIFT;
893 if (mem->mem_type != TTM_PL_SYSTEM) {
894 bo_va->flags |= RADEON_VM_PAGE_VALID;
896 if (mem->mem_type == TTM_PL_TT) {
897 bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
898 if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC)))
899 bo_va->flags |= RADEON_VM_PAGE_SNOOPED;
902 addr += rdev->vm_manager.vram_base_offset;
908 if (addr == bo_va->addr)
912 trace_radeon_vm_bo_update(bo_va);
914 nptes = bo_va->it.last - bo_va->it.start + 1;
916 /* reserve space for one command every (1 << BLOCK_SIZE) entries
917 or 2k dwords (whatever is smaller) */
918 ncmds = (nptes >> min(radeon_vm_block_size, 11)) + 1;
923 flags = radeon_vm_page_flags(bo_va->flags);
924 if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
925 /* only copy commands needed */
928 } else if (flags & R600_PTE_SYSTEM) {
929 /* header for write data commands */
932 /* body of write data command */
936 /* set page commands needed */
939 /* two extra commands for begin/end of fragment */
943 /* update too big for an IB */
947 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
952 radeon_vm_update_ptes(rdev, vm, &ib, bo_va->it.start,
953 bo_va->it.last + 1, addr,
954 radeon_vm_page_flags(bo_va->flags));
956 radeon_asic_vm_pad_ib(rdev, &ib);
957 WARN_ON(ib.length_dw > ndw);
959 radeon_semaphore_sync_to(ib.semaphore, vm->fence);
960 r = radeon_ib_schedule(rdev, &ib, NULL);
962 radeon_ib_free(rdev, &ib);
965 radeon_fence_unref(&vm->fence);
966 vm->fence = radeon_fence_ref(ib.fence);
967 radeon_ib_free(rdev, &ib);
968 radeon_fence_unref(&vm->last_flush);
974 * radeon_vm_clear_freed - clear freed BOs in the PT
976 * @rdev: radeon_device pointer
979 * Make sure all freed BOs are cleared in the PT.
980 * Returns 0 for success.
982 * PTs have to be reserved and mutex must be locked!
984 int radeon_vm_clear_freed(struct radeon_device *rdev,
985 struct radeon_vm *vm)
987 struct radeon_bo_va *bo_va, *tmp;
990 list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
991 r = radeon_vm_bo_update(rdev, bo_va, NULL);
992 radeon_bo_unref(&bo_va->bo);
1002 * radeon_vm_clear_invalids - clear invalidated BOs in the PT
1004 * @rdev: radeon_device pointer
1007 * Make sure all invalidated BOs are cleared in the PT.
1008 * Returns 0 for success.
1010 * PTs have to be reserved and mutex must be locked!
1012 int radeon_vm_clear_invalids(struct radeon_device *rdev,
1013 struct radeon_vm *vm)
1015 struct radeon_bo_va *bo_va, *tmp;
1018 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, vm_status) {
1019 r = radeon_vm_bo_update(rdev, bo_va, NULL);
1027 * radeon_vm_bo_rmv - remove a bo to a specific vm
1029 * @rdev: radeon_device pointer
1030 * @bo_va: requested bo_va
1032 * Remove @bo_va->bo from the requested vm (cayman+).
1034 * Object have to be reserved!
1036 void radeon_vm_bo_rmv(struct radeon_device *rdev,
1037 struct radeon_bo_va *bo_va)
1039 struct radeon_vm *vm = bo_va->vm;
1041 list_del(&bo_va->bo_list);
1043 mutex_lock(&vm->mutex);
1044 interval_tree_remove(&bo_va->it, &vm->va);
1045 list_del(&bo_va->vm_status);
1048 bo_va->bo = radeon_bo_ref(bo_va->bo);
1049 list_add(&bo_va->vm_status, &vm->freed);
1054 mutex_unlock(&vm->mutex);
1058 * radeon_vm_bo_invalidate - mark the bo as invalid
1060 * @rdev: radeon_device pointer
1062 * @bo: radeon buffer object
1064 * Mark @bo as invalid (cayman+).
1066 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1067 struct radeon_bo *bo)
1069 struct radeon_bo_va *bo_va;
1071 list_for_each_entry(bo_va, &bo->va, bo_list) {
1073 mutex_lock(&bo_va->vm->mutex);
1074 list_del(&bo_va->vm_status);
1075 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1076 mutex_unlock(&bo_va->vm->mutex);
1082 * radeon_vm_init - initialize a vm instance
1084 * @rdev: radeon_device pointer
1087 * Init @vm fields (cayman+).
1089 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
1091 const unsigned align = min(RADEON_VM_PTB_ALIGN_SIZE,
1092 RADEON_VM_PTE_COUNT * 8);
1093 unsigned pd_size, pd_entries, pts_size;
1097 vm->ib_bo_va = NULL;
1099 vm->last_flush = NULL;
1100 vm->last_id_use = NULL;
1101 mutex_init(&vm->mutex);
1103 INIT_LIST_HEAD(&vm->invalidated);
1104 INIT_LIST_HEAD(&vm->freed);
1106 pd_size = radeon_vm_directory_size(rdev);
1107 pd_entries = radeon_vm_num_pdes(rdev);
1109 /* allocate page table array */
1110 pts_size = pd_entries * sizeof(struct radeon_vm_pt);
1111 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
1112 if (vm->page_tables == NULL) {
1113 DRM_ERROR("Cannot allocate memory for page table array\n");
1117 r = radeon_bo_create(rdev, pd_size, align, true,
1118 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
1119 &vm->page_directory);
1123 r = radeon_vm_clear_bo(rdev, vm->page_directory);
1125 radeon_bo_unref(&vm->page_directory);
1126 vm->page_directory = NULL;
1134 * radeon_vm_fini - tear down a vm instance
1136 * @rdev: radeon_device pointer
1139 * Tear down @vm (cayman+).
1140 * Unbind the VM and remove all bos from the vm bo list
1142 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
1144 struct radeon_bo_va *bo_va, *tmp;
1147 if (!RB_EMPTY_ROOT(&vm->va)) {
1148 dev_err(rdev->dev, "still active bo inside vm\n");
1150 rbtree_postorder_for_each_entry_safe(bo_va, tmp, &vm->va, it.rb) {
1151 interval_tree_remove(&bo_va->it, &vm->va);
1152 r = radeon_bo_reserve(bo_va->bo, false);
1154 list_del_init(&bo_va->bo_list);
1155 radeon_bo_unreserve(bo_va->bo);
1159 list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
1160 radeon_bo_unref(&bo_va->bo);
1164 for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
1165 radeon_bo_unref(&vm->page_tables[i].bo);
1166 kfree(vm->page_tables);
1168 radeon_bo_unref(&vm->page_directory);
1170 radeon_fence_unref(&vm->fence);
1171 radeon_fence_unref(&vm->last_flush);
1172 radeon_fence_unref(&vm->last_id_use);
1174 mutex_destroy(&vm->mutex);