2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/radeon_drm.h>
31 #include "radeon_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * radeon_vm_num_pde - return the number of page directory entries
56 * @rdev: radeon_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size;
66 * radeon_vm_directory_size - returns the size of the page directory in bytes
68 * @rdev: radeon_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned radeon_vm_directory_size(struct radeon_device *rdev)
74 return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8);
78 * radeon_vm_manager_init - init the vm manager
80 * @rdev: radeon_device pointer
82 * Init the vm manager (cayman+).
83 * Returns 0 for success, error for failure.
85 int radeon_vm_manager_init(struct radeon_device *rdev)
89 if (!rdev->vm_manager.enabled) {
90 r = radeon_asic_vm_init(rdev);
94 rdev->vm_manager.enabled = true;
100 * radeon_vm_manager_fini - tear down the vm manager
102 * @rdev: radeon_device pointer
104 * Tear down the VM manager (cayman+).
106 void radeon_vm_manager_fini(struct radeon_device *rdev)
110 if (!rdev->vm_manager.enabled)
113 for (i = 0; i < RADEON_NUM_VM; ++i)
114 radeon_fence_unref(&rdev->vm_manager.active[i]);
115 radeon_asic_vm_fini(rdev);
116 rdev->vm_manager.enabled = false;
120 * radeon_vm_get_bos - add the vm BOs to a validation list
122 * @vm: vm providing the BOs
123 * @head: head of validation list
125 * Add the page directory to the list of BOs to
126 * validate for command submission (cayman+).
128 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
129 struct radeon_vm *vm,
130 struct list_head *head)
132 struct radeon_cs_reloc *list;
135 list = kmalloc_array(vm->max_pde_used + 2,
136 sizeof(struct radeon_cs_reloc), GFP_KERNEL);
140 /* add the vm page table to the list */
142 list[0].robj = vm->page_directory;
143 list[0].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
144 list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
145 list[0].tv.bo = &vm->page_directory->tbo;
146 list[0].tiling_flags = 0;
148 list_add(&list[0].tv.head, head);
150 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
151 if (!vm->page_tables[i].bo)
154 list[idx].gobj = NULL;
155 list[idx].robj = vm->page_tables[i].bo;
156 list[idx].prefered_domains = RADEON_GEM_DOMAIN_VRAM;
157 list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
158 list[idx].tv.bo = &list[idx].robj->tbo;
159 list[idx].tiling_flags = 0;
160 list[idx].handle = 0;
161 list_add(&list[idx++].tv.head, head);
168 * radeon_vm_grab_id - allocate the next free VMID
170 * @rdev: radeon_device pointer
171 * @vm: vm to allocate id for
172 * @ring: ring we want to submit job to
174 * Allocate an id for the vm (cayman+).
175 * Returns the fence we need to sync to (if any).
177 * Global and local mutex must be locked!
179 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
180 struct radeon_vm *vm, int ring)
182 struct radeon_fence *best[RADEON_NUM_RINGS] = {};
183 unsigned choices[2] = {};
186 /* check if the id is still valid */
187 if (vm->last_id_use && vm->last_id_use == rdev->vm_manager.active[vm->id])
190 /* we definately need to flush */
191 radeon_fence_unref(&vm->last_flush);
193 /* skip over VMID 0, since it is the system VM */
194 for (i = 1; i < rdev->vm_manager.nvm; ++i) {
195 struct radeon_fence *fence = rdev->vm_manager.active[i];
198 /* found a free one */
200 trace_radeon_vm_grab_id(vm->id, ring);
204 if (radeon_fence_is_earlier(fence, best[fence->ring])) {
205 best[fence->ring] = fence;
206 choices[fence->ring == ring ? 0 : 1] = i;
210 for (i = 0; i < 2; ++i) {
213 trace_radeon_vm_grab_id(vm->id, ring);
214 return rdev->vm_manager.active[choices[i]];
218 /* should never happen */
224 * radeon_vm_flush - hardware flush the vm
226 * @rdev: radeon_device pointer
227 * @vm: vm we want to flush
228 * @ring: ring to use for flush
230 * Flush the vm (cayman+).
232 * Global and local mutex must be locked!
234 void radeon_vm_flush(struct radeon_device *rdev,
235 struct radeon_vm *vm,
238 uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
240 /* if we can't remember our last VM flush then flush now! */
241 /* XXX figure out why we have to flush all the time before CIK */
242 if (rdev->family < CHIP_BONAIRE ||
243 !vm->last_flush || pd_addr != vm->pd_gpu_addr) {
244 trace_radeon_vm_flush(pd_addr, ring, vm->id);
245 vm->pd_gpu_addr = pd_addr;
246 radeon_ring_vm_flush(rdev, ring, vm);
251 * radeon_vm_fence - remember fence for vm
253 * @rdev: radeon_device pointer
254 * @vm: vm we want to fence
255 * @fence: fence to remember
257 * Fence the vm (cayman+).
258 * Set the fence used to protect page table and id.
260 * Global and local mutex must be locked!
262 void radeon_vm_fence(struct radeon_device *rdev,
263 struct radeon_vm *vm,
264 struct radeon_fence *fence)
266 radeon_fence_unref(&vm->fence);
267 vm->fence = radeon_fence_ref(fence);
269 radeon_fence_unref(&rdev->vm_manager.active[vm->id]);
270 rdev->vm_manager.active[vm->id] = radeon_fence_ref(fence);
272 radeon_fence_unref(&vm->last_id_use);
273 vm->last_id_use = radeon_fence_ref(fence);
275 /* we just flushed the VM, remember that */
277 vm->last_flush = radeon_fence_ref(fence);
281 * radeon_vm_bo_find - find the bo_va for a specific vm & bo
284 * @bo: requested buffer object
286 * Find @bo inside the requested vm (cayman+).
287 * Search inside the @bos vm list for the requested vm
288 * Returns the found bo_va or NULL if none is found
290 * Object has to be reserved!
292 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
293 struct radeon_bo *bo)
295 struct radeon_bo_va *bo_va;
297 list_for_each_entry(bo_va, &bo->va, bo_list) {
298 if (bo_va->vm == vm) {
306 * radeon_vm_bo_add - add a bo to a specific vm
308 * @rdev: radeon_device pointer
310 * @bo: radeon buffer object
312 * Add @bo into the requested vm (cayman+).
313 * Add @bo to the list of bos associated with the vm
314 * Returns newly added bo_va or NULL for failure
316 * Object has to be reserved!
318 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
319 struct radeon_vm *vm,
320 struct radeon_bo *bo)
322 struct radeon_bo_va *bo_va;
324 bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
334 bo_va->ref_count = 1;
335 INIT_LIST_HEAD(&bo_va->bo_list);
336 INIT_LIST_HEAD(&bo_va->vm_status);
338 mutex_lock(&vm->mutex);
339 list_add_tail(&bo_va->bo_list, &bo->va);
340 mutex_unlock(&vm->mutex);
346 * radeon_vm_set_pages - helper to call the right asic function
348 * @rdev: radeon_device pointer
349 * @ib: indirect buffer to fill with commands
350 * @pe: addr of the page entry
351 * @addr: dst addr to write into pe
352 * @count: number of page entries to update
353 * @incr: increase next addr by incr bytes
354 * @flags: hw access flags
356 * Traces the parameters and calls the right asic functions
357 * to setup the page table using the DMA.
359 static void radeon_vm_set_pages(struct radeon_device *rdev,
360 struct radeon_ib *ib,
362 uint64_t addr, unsigned count,
363 uint32_t incr, uint32_t flags)
365 trace_radeon_vm_set_page(pe, addr, count, incr, flags);
367 if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
368 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
369 radeon_asic_vm_copy_pages(rdev, ib, pe, src, count);
371 } else if ((flags & R600_PTE_SYSTEM) || (count < 3)) {
372 radeon_asic_vm_write_pages(rdev, ib, pe, addr,
376 radeon_asic_vm_set_pages(rdev, ib, pe, addr,
382 * radeon_vm_clear_bo - initially clear the page dir/table
384 * @rdev: radeon_device pointer
387 static int radeon_vm_clear_bo(struct radeon_device *rdev,
388 struct radeon_bo *bo)
390 struct ttm_validate_buffer tv;
391 struct ww_acquire_ctx ticket;
392 struct list_head head;
398 memset(&tv, 0, sizeof(tv));
401 INIT_LIST_HEAD(&head);
402 list_add(&tv.head, &head);
404 r = ttm_eu_reserve_buffers(&ticket, &head);
408 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
412 addr = radeon_bo_gpu_offset(bo);
413 entries = radeon_bo_size(bo) / 8;
415 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, 256);
421 radeon_vm_set_pages(rdev, &ib, addr, 0, entries, 0, 0);
422 radeon_asic_vm_pad_ib(rdev, &ib);
423 WARN_ON(ib.length_dw > 64);
425 r = radeon_ib_schedule(rdev, &ib, NULL);
429 ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
430 radeon_ib_free(rdev, &ib);
435 ttm_eu_backoff_reservation(&ticket, &head);
440 * radeon_vm_bo_set_addr - set bos virtual address inside a vm
442 * @rdev: radeon_device pointer
443 * @bo_va: bo_va to store the address
444 * @soffset: requested offset of the buffer in the VM address space
445 * @flags: attributes of pages (read/write/valid/etc.)
447 * Set offset of @bo_va (cayman+).
448 * Validate and set the offset requested within the vm address space.
449 * Returns 0 for success, error for failure.
451 * Object has to be reserved!
453 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
454 struct radeon_bo_va *bo_va,
458 uint64_t size = radeon_bo_size(bo_va->bo);
459 struct radeon_vm *vm = bo_va->vm;
460 unsigned last_pfn, pt_idx;
465 /* make sure object fit at this offset */
466 eoffset = soffset + size;
467 if (soffset >= eoffset) {
471 last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
472 if (last_pfn > rdev->vm_manager.max_pfn) {
473 dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n",
474 last_pfn, rdev->vm_manager.max_pfn);
479 eoffset = last_pfn = 0;
482 mutex_lock(&vm->mutex);
483 if (bo_va->it.start || bo_va->it.last) {
485 /* add a clone of the bo_va to clear the old address */
486 struct radeon_bo_va *tmp;
487 tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
489 mutex_unlock(&vm->mutex);
492 tmp->it.start = bo_va->it.start;
493 tmp->it.last = bo_va->it.last;
495 tmp->addr = bo_va->addr;
496 tmp->bo = radeon_bo_ref(bo_va->bo);
497 list_add(&tmp->vm_status, &vm->freed);
500 interval_tree_remove(&bo_va->it, &vm->va);
505 soffset /= RADEON_GPU_PAGE_SIZE;
506 eoffset /= RADEON_GPU_PAGE_SIZE;
507 if (soffset || eoffset) {
508 struct interval_tree_node *it;
509 it = interval_tree_iter_first(&vm->va, soffset, eoffset - 1);
511 struct radeon_bo_va *tmp;
512 tmp = container_of(it, struct radeon_bo_va, it);
513 /* bo and tmp overlap, invalid offset */
514 dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with "
515 "(bo %p 0x%010lx 0x%010lx)\n", bo_va->bo,
516 soffset, tmp->bo, tmp->it.start, tmp->it.last);
517 mutex_unlock(&vm->mutex);
520 bo_va->it.start = soffset;
521 bo_va->it.last = eoffset - 1;
522 interval_tree_insert(&bo_va->it, &vm->va);
525 bo_va->flags = flags;
528 soffset >>= radeon_vm_block_size;
529 eoffset >>= radeon_vm_block_size;
531 BUG_ON(eoffset >= radeon_vm_num_pdes(rdev));
533 if (eoffset > vm->max_pde_used)
534 vm->max_pde_used = eoffset;
536 radeon_bo_unreserve(bo_va->bo);
538 /* walk over the address space and allocate the page tables */
539 for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) {
540 struct radeon_bo *pt;
542 if (vm->page_tables[pt_idx].bo)
545 /* drop mutex to allocate and clear page table */
546 mutex_unlock(&vm->mutex);
548 r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
549 RADEON_GPU_PAGE_SIZE, true,
550 RADEON_GEM_DOMAIN_VRAM, 0, NULL, &pt);
554 r = radeon_vm_clear_bo(rdev, pt);
556 radeon_bo_unref(&pt);
557 radeon_bo_reserve(bo_va->bo, false);
561 /* aquire mutex again */
562 mutex_lock(&vm->mutex);
563 if (vm->page_tables[pt_idx].bo) {
564 /* someone else allocated the pt in the meantime */
565 mutex_unlock(&vm->mutex);
566 radeon_bo_unref(&pt);
567 mutex_lock(&vm->mutex);
571 vm->page_tables[pt_idx].addr = 0;
572 vm->page_tables[pt_idx].bo = pt;
575 mutex_unlock(&vm->mutex);
576 return radeon_bo_reserve(bo_va->bo, false);
580 * radeon_vm_map_gart - get the physical address of a gart page
582 * @rdev: radeon_device pointer
583 * @addr: the unmapped addr
585 * Look up the physical address of the page that the pte resolves
587 * Returns the physical address of the page.
589 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
593 /* page table offset */
594 result = rdev->gart.pages_addr[addr >> PAGE_SHIFT];
596 /* in case cpu page size != gpu page size*/
597 result |= addr & (~PAGE_MASK);
603 * radeon_vm_page_flags - translate page flags to what the hw uses
605 * @flags: flags comming from userspace
607 * Translate the flags the userspace ABI uses to hw flags.
609 static uint32_t radeon_vm_page_flags(uint32_t flags)
611 uint32_t hw_flags = 0;
612 hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
613 hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
614 hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
615 if (flags & RADEON_VM_PAGE_SYSTEM) {
616 hw_flags |= R600_PTE_SYSTEM;
617 hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
623 * radeon_vm_update_pdes - make sure that page directory is valid
625 * @rdev: radeon_device pointer
627 * @start: start of GPU address range
628 * @end: end of GPU address range
630 * Allocates new page tables if necessary
631 * and updates the page directory (cayman+).
632 * Returns 0 for success, error for failure.
634 * Global and local mutex must be locked!
636 int radeon_vm_update_page_directory(struct radeon_device *rdev,
637 struct radeon_vm *vm)
639 struct radeon_bo *pd = vm->page_directory;
640 uint64_t pd_addr = radeon_bo_gpu_offset(pd);
641 uint32_t incr = RADEON_VM_PTE_COUNT * 8;
642 uint64_t last_pde = ~0, last_pt = ~0;
643 unsigned count = 0, pt_idx, ndw;
650 /* assume the worst case */
651 ndw += vm->max_pde_used * 6;
653 /* update too big for an IB */
657 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
662 /* walk over the address space and update the page directory */
663 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
664 struct radeon_bo *bo = vm->page_tables[pt_idx].bo;
670 pt = radeon_bo_gpu_offset(bo);
671 if (vm->page_tables[pt_idx].addr == pt)
673 vm->page_tables[pt_idx].addr = pt;
675 pde = pd_addr + pt_idx * 8;
676 if (((last_pde + 8 * count) != pde) ||
677 ((last_pt + incr * count) != pt)) {
680 radeon_vm_set_pages(rdev, &ib, last_pde,
681 last_pt, count, incr,
694 radeon_vm_set_pages(rdev, &ib, last_pde, last_pt, count,
695 incr, R600_PTE_VALID);
697 if (ib.length_dw != 0) {
698 radeon_asic_vm_pad_ib(rdev, &ib);
699 radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj);
700 radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use);
701 WARN_ON(ib.length_dw > ndw);
702 r = radeon_ib_schedule(rdev, &ib, NULL);
704 radeon_ib_free(rdev, &ib);
707 radeon_fence_unref(&vm->fence);
708 vm->fence = radeon_fence_ref(ib.fence);
709 radeon_fence_unref(&vm->last_flush);
711 radeon_ib_free(rdev, &ib);
717 * radeon_vm_frag_ptes - add fragment information to PTEs
719 * @rdev: radeon_device pointer
720 * @ib: IB for the update
721 * @pe_start: first PTE to handle
722 * @pe_end: last PTE to handle
723 * @addr: addr those PTEs should point to
724 * @flags: hw mapping flags
726 * Global and local mutex must be locked!
728 static void radeon_vm_frag_ptes(struct radeon_device *rdev,
729 struct radeon_ib *ib,
730 uint64_t pe_start, uint64_t pe_end,
731 uint64_t addr, uint32_t flags)
734 * The MC L1 TLB supports variable sized pages, based on a fragment
735 * field in the PTE. When this field is set to a non-zero value, page
736 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
737 * flags are considered valid for all PTEs within the fragment range
738 * and corresponding mappings are assumed to be physically contiguous.
740 * The L1 TLB can store a single PTE for the whole fragment,
741 * significantly increasing the space available for translation
742 * caching. This leads to large improvements in throughput when the
743 * TLB is under pressure.
745 * The L2 TLB distributes small and large fragments into two
746 * asymmetric partitions. The large fragment cache is significantly
747 * larger. Thus, we try to use large fragments wherever possible.
748 * Userspace can support this by aligning virtual base address and
749 * allocation size to the fragment size.
752 /* NI is optimized for 256KB fragments, SI and newer for 64KB */
753 uint64_t frag_flags = rdev->family == CHIP_CAYMAN ?
754 R600_PTE_FRAG_256KB : R600_PTE_FRAG_64KB;
755 uint64_t frag_align = rdev->family == CHIP_CAYMAN ? 0x200 : 0x80;
757 uint64_t frag_start = ALIGN(pe_start, frag_align);
758 uint64_t frag_end = pe_end & ~(frag_align - 1);
762 /* system pages are non continuously */
763 if ((flags & R600_PTE_SYSTEM) || !(flags & R600_PTE_VALID) ||
764 (frag_start >= frag_end)) {
766 count = (pe_end - pe_start) / 8;
767 radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
768 RADEON_GPU_PAGE_SIZE, flags);
772 /* handle the 4K area at the beginning */
773 if (pe_start != frag_start) {
774 count = (frag_start - pe_start) / 8;
775 radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
776 RADEON_GPU_PAGE_SIZE, flags);
777 addr += RADEON_GPU_PAGE_SIZE * count;
780 /* handle the area in the middle */
781 count = (frag_end - frag_start) / 8;
782 radeon_vm_set_pages(rdev, ib, frag_start, addr, count,
783 RADEON_GPU_PAGE_SIZE, flags | frag_flags);
785 /* handle the 4K area at the end */
786 if (frag_end != pe_end) {
787 addr += RADEON_GPU_PAGE_SIZE * count;
788 count = (pe_end - frag_end) / 8;
789 radeon_vm_set_pages(rdev, ib, frag_end, addr, count,
790 RADEON_GPU_PAGE_SIZE, flags);
795 * radeon_vm_update_ptes - make sure that page tables are valid
797 * @rdev: radeon_device pointer
799 * @start: start of GPU address range
800 * @end: end of GPU address range
801 * @dst: destination address to map to
802 * @flags: mapping flags
804 * Update the page tables in the range @start - @end (cayman+).
806 * Global and local mutex must be locked!
808 static void radeon_vm_update_ptes(struct radeon_device *rdev,
809 struct radeon_vm *vm,
810 struct radeon_ib *ib,
811 uint64_t start, uint64_t end,
812 uint64_t dst, uint32_t flags)
814 uint64_t mask = RADEON_VM_PTE_COUNT - 1;
815 uint64_t last_pte = ~0, last_dst = ~0;
819 /* walk over the address space and update the page tables */
820 for (addr = start; addr < end; ) {
821 uint64_t pt_idx = addr >> radeon_vm_block_size;
822 struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
826 radeon_semaphore_sync_to(ib->semaphore, pt->tbo.sync_obj);
828 if ((addr & ~mask) == (end & ~mask))
831 nptes = RADEON_VM_PTE_COUNT - (addr & mask);
833 pte = radeon_bo_gpu_offset(pt);
834 pte += (addr & mask) * 8;
836 if ((last_pte + 8 * count) != pte) {
839 radeon_vm_frag_ptes(rdev, ib, last_pte,
840 last_pte + 8 * count,
852 dst += nptes * RADEON_GPU_PAGE_SIZE;
856 radeon_vm_frag_ptes(rdev, ib, last_pte,
857 last_pte + 8 * count,
863 * radeon_vm_bo_update - map a bo into the vm page table
865 * @rdev: radeon_device pointer
867 * @bo: radeon buffer object
870 * Fill in the page table entries for @bo (cayman+).
871 * Returns 0 for success, -EINVAL for failure.
873 * Object have to be reserved and mutex must be locked!
875 int radeon_vm_bo_update(struct radeon_device *rdev,
876 struct radeon_bo_va *bo_va,
877 struct ttm_mem_reg *mem)
879 struct radeon_vm *vm = bo_va->vm;
881 unsigned nptes, ncmds, ndw;
886 if (!bo_va->it.start) {
887 dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
892 list_del_init(&bo_va->vm_status);
894 bo_va->flags &= ~RADEON_VM_PAGE_VALID;
895 bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
896 bo_va->flags &= ~RADEON_VM_PAGE_SNOOPED;
898 addr = mem->start << PAGE_SHIFT;
899 if (mem->mem_type != TTM_PL_SYSTEM) {
900 bo_va->flags |= RADEON_VM_PAGE_VALID;
902 if (mem->mem_type == TTM_PL_TT) {
903 bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
904 if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC)))
905 bo_va->flags |= RADEON_VM_PAGE_SNOOPED;
908 addr += rdev->vm_manager.vram_base_offset;
914 if (addr == bo_va->addr)
918 trace_radeon_vm_bo_update(bo_va);
920 nptes = bo_va->it.last - bo_va->it.start + 1;
922 /* reserve space for one command every (1 << BLOCK_SIZE) entries
923 or 2k dwords (whatever is smaller) */
924 ncmds = (nptes >> min(radeon_vm_block_size, 11)) + 1;
929 flags = radeon_vm_page_flags(bo_va->flags);
930 if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
931 /* only copy commands needed */
934 } else if (flags & R600_PTE_SYSTEM) {
935 /* header for write data commands */
938 /* body of write data command */
942 /* set page commands needed */
945 /* two extra commands for begin/end of fragment */
949 /* update too big for an IB */
953 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
958 radeon_vm_update_ptes(rdev, vm, &ib, bo_va->it.start,
959 bo_va->it.last + 1, addr,
960 radeon_vm_page_flags(bo_va->flags));
962 radeon_asic_vm_pad_ib(rdev, &ib);
963 WARN_ON(ib.length_dw > ndw);
965 radeon_semaphore_sync_to(ib.semaphore, vm->fence);
966 r = radeon_ib_schedule(rdev, &ib, NULL);
968 radeon_ib_free(rdev, &ib);
971 radeon_fence_unref(&vm->fence);
972 vm->fence = radeon_fence_ref(ib.fence);
973 radeon_ib_free(rdev, &ib);
974 radeon_fence_unref(&vm->last_flush);
980 * radeon_vm_clear_freed - clear freed BOs in the PT
982 * @rdev: radeon_device pointer
985 * Make sure all freed BOs are cleared in the PT.
986 * Returns 0 for success.
988 * PTs have to be reserved and mutex must be locked!
990 int radeon_vm_clear_freed(struct radeon_device *rdev,
991 struct radeon_vm *vm)
993 struct radeon_bo_va *bo_va, *tmp;
996 list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
997 r = radeon_vm_bo_update(rdev, bo_va, NULL);
998 radeon_bo_unref(&bo_va->bo);
1008 * radeon_vm_clear_invalids - clear invalidated BOs in the PT
1010 * @rdev: radeon_device pointer
1013 * Make sure all invalidated BOs are cleared in the PT.
1014 * Returns 0 for success.
1016 * PTs have to be reserved and mutex must be locked!
1018 int radeon_vm_clear_invalids(struct radeon_device *rdev,
1019 struct radeon_vm *vm)
1021 struct radeon_bo_va *bo_va, *tmp;
1024 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, vm_status) {
1025 r = radeon_vm_bo_update(rdev, bo_va, NULL);
1033 * radeon_vm_bo_rmv - remove a bo to a specific vm
1035 * @rdev: radeon_device pointer
1036 * @bo_va: requested bo_va
1038 * Remove @bo_va->bo from the requested vm (cayman+).
1040 * Object have to be reserved!
1042 void radeon_vm_bo_rmv(struct radeon_device *rdev,
1043 struct radeon_bo_va *bo_va)
1045 struct radeon_vm *vm = bo_va->vm;
1047 list_del(&bo_va->bo_list);
1049 mutex_lock(&vm->mutex);
1050 interval_tree_remove(&bo_va->it, &vm->va);
1051 list_del(&bo_va->vm_status);
1054 bo_va->bo = radeon_bo_ref(bo_va->bo);
1055 list_add(&bo_va->vm_status, &vm->freed);
1060 mutex_unlock(&vm->mutex);
1064 * radeon_vm_bo_invalidate - mark the bo as invalid
1066 * @rdev: radeon_device pointer
1068 * @bo: radeon buffer object
1070 * Mark @bo as invalid (cayman+).
1072 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1073 struct radeon_bo *bo)
1075 struct radeon_bo_va *bo_va;
1077 list_for_each_entry(bo_va, &bo->va, bo_list) {
1079 mutex_lock(&bo_va->vm->mutex);
1080 list_del(&bo_va->vm_status);
1081 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1082 mutex_unlock(&bo_va->vm->mutex);
1088 * radeon_vm_init - initialize a vm instance
1090 * @rdev: radeon_device pointer
1093 * Init @vm fields (cayman+).
1095 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
1097 const unsigned align = min(RADEON_VM_PTB_ALIGN_SIZE,
1098 RADEON_VM_PTE_COUNT * 8);
1099 unsigned pd_size, pd_entries, pts_size;
1103 vm->ib_bo_va = NULL;
1105 vm->last_flush = NULL;
1106 vm->last_id_use = NULL;
1107 mutex_init(&vm->mutex);
1109 INIT_LIST_HEAD(&vm->invalidated);
1110 INIT_LIST_HEAD(&vm->freed);
1112 pd_size = radeon_vm_directory_size(rdev);
1113 pd_entries = radeon_vm_num_pdes(rdev);
1115 /* allocate page table array */
1116 pts_size = pd_entries * sizeof(struct radeon_vm_pt);
1117 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
1118 if (vm->page_tables == NULL) {
1119 DRM_ERROR("Cannot allocate memory for page table array\n");
1123 r = radeon_bo_create(rdev, pd_size, align, true,
1124 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
1125 &vm->page_directory);
1129 r = radeon_vm_clear_bo(rdev, vm->page_directory);
1131 radeon_bo_unref(&vm->page_directory);
1132 vm->page_directory = NULL;
1140 * radeon_vm_fini - tear down a vm instance
1142 * @rdev: radeon_device pointer
1145 * Tear down @vm (cayman+).
1146 * Unbind the VM and remove all bos from the vm bo list
1148 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
1150 struct radeon_bo_va *bo_va, *tmp;
1153 if (!RB_EMPTY_ROOT(&vm->va)) {
1154 dev_err(rdev->dev, "still active bo inside vm\n");
1156 rbtree_postorder_for_each_entry_safe(bo_va, tmp, &vm->va, it.rb) {
1157 interval_tree_remove(&bo_va->it, &vm->va);
1158 r = radeon_bo_reserve(bo_va->bo, false);
1160 list_del_init(&bo_va->bo_list);
1161 radeon_bo_unreserve(bo_va->bo);
1165 list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
1166 radeon_bo_unref(&bo_va->bo);
1170 for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
1171 radeon_bo_unref(&vm->page_tables[i].bo);
1172 kfree(vm->page_tables);
1174 radeon_bo_unref(&vm->page_directory);
1176 radeon_fence_unref(&vm->fence);
1177 radeon_fence_unref(&vm->last_flush);
1178 radeon_fence_unref(&vm->last_id_use);
1180 mutex_destroy(&vm->mutex);