2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "radeon_reg.h"
33 #include "rs600_reg_safe.h"
35 /* rs600 depends on : */
36 void r100_hdp_reset(struct radeon_device *rdev);
37 int r100_gui_wait_for_idle(struct radeon_device *rdev);
38 int r300_mc_wait_for_idle(struct radeon_device *rdev);
39 void r420_pipes_init(struct radeon_device *rdev);
41 /* This files gather functions specifics to :
44 * Some of these functions might be used by newer ASICs.
46 void rs600_gpu_init(struct radeon_device *rdev);
47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48 void rs600_disable_vga(struct radeon_device *rdev);
54 void rs600_gart_tlb_flush(struct radeon_device *rdev)
58 tmp = RREG32_MC(RS600_MC_PT0_CNTL);
59 tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
60 WREG32_MC(RS600_MC_PT0_CNTL, tmp);
62 tmp = RREG32_MC(RS600_MC_PT0_CNTL);
63 tmp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
64 WREG32_MC(RS600_MC_PT0_CNTL, tmp);
66 tmp = RREG32_MC(RS600_MC_PT0_CNTL);
67 tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
68 WREG32_MC(RS600_MC_PT0_CNTL, tmp);
69 tmp = RREG32_MC(RS600_MC_PT0_CNTL);
72 int rs600_gart_init(struct radeon_device *rdev)
76 if (rdev->gart.table.vram.robj) {
77 WARN(1, "RS600 GART already initialized.\n");
80 /* Initialize common gart structure */
81 r = radeon_gart_init(rdev);
85 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
86 return radeon_gart_table_vram_alloc(rdev);
89 int rs600_gart_enable(struct radeon_device *rdev)
94 if (rdev->gart.table.vram.robj == NULL) {
95 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
98 r = radeon_gart_table_vram_pin(rdev);
101 /* FIXME: setup default page */
102 WREG32_MC(RS600_MC_PT0_CNTL,
103 (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
104 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
105 for (i = 0; i < 19; i++) {
106 WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL + i,
107 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
108 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
109 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE |
110 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
111 RS600_ENABLE_FRAGMENT_PROCESSING |
112 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
115 /* System context map to GART space */
116 WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_location);
117 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
118 WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, tmp);
120 /* enable first context */
121 WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_location);
122 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
123 WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, tmp);
124 WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL,
125 (RS600_ENABLE_PAGE_TABLE | RS600_PAGE_TABLE_TYPE_FLAT));
126 /* disable all other contexts */
127 for (i = 1; i < 8; i++) {
128 WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
131 /* setup the page table */
132 WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
133 rdev->gart.table_addr);
134 WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
136 /* enable page tables */
137 tmp = RREG32_MC(RS600_MC_PT0_CNTL);
138 WREG32_MC(RS600_MC_PT0_CNTL, (tmp | RS600_ENABLE_PT));
139 tmp = RREG32_MC(RS600_MC_CNTL1);
140 WREG32_MC(RS600_MC_CNTL1, (tmp | RS600_ENABLE_PAGE_TABLES));
141 rs600_gart_tlb_flush(rdev);
142 rdev->gart.ready = true;
146 void rs600_gart_disable(struct radeon_device *rdev)
150 /* FIXME: disable out of gart access */
151 WREG32_MC(RS600_MC_PT0_CNTL, 0);
152 tmp = RREG32_MC(RS600_MC_CNTL1);
153 tmp &= ~RS600_ENABLE_PAGE_TABLES;
154 WREG32_MC(RS600_MC_CNTL1, tmp);
155 if (rdev->gart.table.vram.robj) {
156 radeon_object_kunmap(rdev->gart.table.vram.robj);
157 radeon_object_unpin(rdev->gart.table.vram.robj);
161 void rs600_gart_fini(struct radeon_device *rdev)
163 rs600_gart_disable(rdev);
164 radeon_gart_table_vram_free(rdev);
165 radeon_gart_fini(rdev);
168 #define R600_PTE_VALID (1 << 0)
169 #define R600_PTE_SYSTEM (1 << 1)
170 #define R600_PTE_SNOOPED (1 << 2)
171 #define R600_PTE_READABLE (1 << 5)
172 #define R600_PTE_WRITEABLE (1 << 6)
174 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
176 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
178 if (i < 0 || i > rdev->gart.num_gpu_pages) {
181 addr = addr & 0xFFFFFFFFFFFFF000ULL;
182 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
183 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
184 writeq(addr, ((void __iomem *)ptr) + (i * 8));
192 void rs600_mc_disable_clients(struct radeon_device *rdev)
196 if (r100_gui_wait_for_idle(rdev)) {
197 printk(KERN_WARNING "Failed to wait GUI idle while "
198 "programming pipes. Bad things might happen.\n");
201 radeon_avivo_vga_render_disable(rdev);
203 tmp = RREG32(AVIVO_D1VGA_CONTROL);
204 WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
205 tmp = RREG32(AVIVO_D2VGA_CONTROL);
206 WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
208 tmp = RREG32(AVIVO_D1CRTC_CONTROL);
209 WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
210 tmp = RREG32(AVIVO_D2CRTC_CONTROL);
211 WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
213 /* make sure all previous write got through */
214 tmp = RREG32(AVIVO_D2CRTC_CONTROL);
219 int rs600_mc_init(struct radeon_device *rdev)
224 if (r100_debugfs_rbbm_init(rdev)) {
225 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
228 rs600_gpu_init(rdev);
229 rs600_gart_disable(rdev);
231 /* Setup GPU memory space */
232 rdev->mc.vram_location = 0xFFFFFFFFUL;
233 rdev->mc.gtt_location = 0xFFFFFFFFUL;
234 r = radeon_mc_setup(rdev);
239 /* Program GPU memory space */
240 /* Enable bus master */
241 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
242 WREG32(RADEON_BUS_CNTL, tmp);
243 /* FIXME: What does AGP means for such chipset ? */
244 WREG32_MC(RS600_MC_AGP_LOCATION, 0x0FFFFFFF);
245 /* FIXME: are this AGP reg in indirect MC range ? */
246 WREG32_MC(RS600_MC_AGP_BASE, 0);
247 WREG32_MC(RS600_MC_AGP_BASE_2, 0);
248 rs600_mc_disable_clients(rdev);
249 if (rs600_mc_wait_for_idle(rdev)) {
250 printk(KERN_WARNING "Failed to wait MC idle while "
251 "programming pipes. Bad things might happen.\n");
253 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
254 tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16);
255 tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16);
256 WREG32_MC(RS600_MC_FB_LOCATION, tmp);
257 WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
261 void rs600_mc_fini(struct radeon_device *rdev)
269 int rs600_irq_set(struct radeon_device *rdev)
272 uint32_t mode_int = 0;
274 if (rdev->irq.sw_int) {
275 tmp |= RADEON_SW_INT_ENABLE;
277 if (rdev->irq.crtc_vblank_int[0]) {
278 mode_int |= AVIVO_D1MODE_INT_MASK;
280 if (rdev->irq.crtc_vblank_int[1]) {
281 mode_int |= AVIVO_D2MODE_INT_MASK;
283 WREG32(RADEON_GEN_INT_CNTL, tmp);
284 WREG32(AVIVO_DxMODE_INT_MASK, mode_int);
288 static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
290 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
291 uint32_t irq_mask = RADEON_SW_INT_TEST;
293 if (irqs & AVIVO_DISPLAY_INT_STATUS) {
294 *r500_disp_int = RREG32(AVIVO_DISP_INTERRUPT_STATUS);
295 if (*r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
296 WREG32(AVIVO_D1MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
298 if (*r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
299 WREG32(AVIVO_D2MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
306 WREG32(RADEON_GEN_INT_STATUS, irqs);
308 return irqs & irq_mask;
311 int rs600_irq_process(struct radeon_device *rdev)
314 uint32_t r500_disp_int;
316 status = rs600_irq_ack(rdev, &r500_disp_int);
317 if (!status && !r500_disp_int) {
320 while (status || r500_disp_int) {
322 if (status & RADEON_SW_INT_TEST) {
323 radeon_fence_process(rdev);
325 /* Vertical blank interrupts */
326 if (r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
327 drm_handle_vblank(rdev->ddev, 0);
329 if (r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
330 drm_handle_vblank(rdev->ddev, 1);
332 status = rs600_irq_ack(rdev, &r500_disp_int);
337 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
340 return RREG32(AVIVO_D1CRTC_FRAME_COUNT);
342 return RREG32(AVIVO_D2CRTC_FRAME_COUNT);
347 * Global GPU functions
349 void rs600_disable_vga(struct radeon_device *rdev)
358 WREG32(0x308, (1 << 8));
359 WREG32(0x310, rdev->mc.vram_location);
363 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
368 for (i = 0; i < rdev->usec_timeout; i++) {
370 tmp = RREG32_MC(RS600_MC_STATUS);
371 if (tmp & RS600_MC_STATUS_IDLE) {
379 void rs600_errata(struct radeon_device *rdev)
381 rdev->pll_errata = 0;
384 void rs600_gpu_init(struct radeon_device *rdev)
386 /* FIXME: HDP same place on rs600 ? */
387 r100_hdp_reset(rdev);
388 rs600_disable_vga(rdev);
389 /* FIXME: is this correct ? */
390 r420_pipes_init(rdev);
391 if (rs600_mc_wait_for_idle(rdev)) {
392 printk(KERN_WARNING "Failed to wait MC idle while "
393 "programming pipes. Bad things might happen.\n");
401 void rs600_vram_info(struct radeon_device *rdev)
403 /* FIXME: to do or is these values sane ? */
404 rdev->mc.vram_is_ddr = true;
405 rdev->mc.vram_width = 128;
408 void rs600_bandwidth_update(struct radeon_device *rdev)
410 /* FIXME: implement, should this be like rs690 ? */
415 * Indirect registers accessor
417 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
421 WREG32(RS600_MC_INDEX,
422 ((reg & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0));
423 r = RREG32(RS600_MC_DATA);
427 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
429 WREG32(RS600_MC_INDEX,
430 RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 |
431 ((reg) & RS600_MC_ADDR_MASK));
432 WREG32(RS600_MC_DATA, v);
435 int rs600_init(struct radeon_device *rdev)
437 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
438 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);