drivers/gpu/drm/radeon/rs600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 /* RS600 / Radeon X1250/X1270 integrated GPU
  29  *
  30  * This file gather function specific to RS600 which is the IGP of
  31  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33  * the avivo one, bios is an atombios, 3D block are the one of the
  34  * R4XX family. The GART is different from the RS400 one and is very
  35  * close to the one of the R600 family (R600 likely being an evolution
  36  * of the RS600 GART block).
  37  */
  38 #include <drm/drmP.h>
  39 #include "radeon.h"
  40 #include "radeon_asic.h"
  41 #include "atom.h"
  42 #include "rs600d.h"
  43
  44 #include "rs600_reg_safe.h"
  45
  46 static void rs600_gpu_init(struct radeon_device *rdev);
  47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  48
  49 static const u32 crtc_offsets[2] =
  50 {
  51         0,
  52         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  53 };
  54
  55 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
  56 {
  57         if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
  58                 return true;
  59         else
  60                 return false;
  61 }
  62
  63 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
  64 {
  65         u32 pos1, pos2;
  66
  67         pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
  68         pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
  69
  70         if (pos1 != pos2)
  71                 return true;
  72         else
  73                 return false;
  74 }
  75
  76 /**
  77  * avivo_wait_for_vblank - vblank wait asic callback.
  78  *
  79  * @rdev: radeon_device pointer
  80  * @crtc: crtc to wait for vblank on
  81  *
  82  * Wait for vblank on the requested crtc (r5xx-r7xx).
  83  */
  84 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
  85 {
  86         unsigned i = 0;
  87
  88         if (crtc >= rdev->num_crtc)
  89                 return;
  90
  91         if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
  92                 return;
  93
  94         /* depending on when we hit vblank, we may be close to active; if so,
  95          * wait for another frame.
  96          */
  97         while (avivo_is_in_vblank(rdev, crtc)) {
  98                 if (i++ % 100 == 0) {
  99                         if (!avivo_is_counter_moving(rdev, crtc))
 100                                 break;
 101                 }
 102         }
 103
 104         while (!avivo_is_in_vblank(rdev, crtc)) {
 105                 if (i++ % 100 == 0) {
 106                         if (!avivo_is_counter_moving(rdev, crtc))
 107                                 break;
 108                 }
 109         }
 110 }
 111
 112 u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 113 {
 114         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 115         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
 116         int i;
 117
 118         /* Lock the graphics update lock */
 119         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
 120         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 121
 122         /* update the scanout addresses */
 123         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 124                (u32)crtc_base);
 125         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 126                (u32)crtc_base);
 127
 128         /* Wait for update_pending to go high. */
 129         for (i = 0; i < rdev->usec_timeout; i++) {
 130                 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
 131                         break;
 132                 udelay(1);
 133         }
 134         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 135
 136         /* Unlock the lock, so double-buffering can take place inside vblank */
 137         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
 138         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 139
 140         /* Return current update_pending status: */
 141         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
 142 }
 143
 144 void avivo_program_fmt(struct drm_encoder *encoder)
 145 {
 146         struct drm_device *dev = encoder->dev;
 147         struct radeon_device *rdev = dev->dev_private;
 148         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 149         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 150         int bpc = 0;
 151         u32 tmp = 0;
 152         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
 153
 154         if (connector) {
 155                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 156                 bpc = radeon_get_monitor_bpc(connector);
 157                 dither = radeon_connector->dither;
 158         }
 159
 160         /* LVDS FMT is set up by atom */
 161         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 162                 return;
 163
 164         if (bpc == 0)
 165                 return;
 166
 167         switch (bpc) {
 168         case 6:
 169                 if (dither == RADEON_FMT_DITHER_ENABLE)
 170                         /* XXX sort out optimal dither settings */
 171                         tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
 172                 else
 173                         tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
 174                 break;
 175         case 8:
 176                 if (dither == RADEON_FMT_DITHER_ENABLE)
 177                         /* XXX sort out optimal dither settings */
 178                         tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
 179                                 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
 180                 else
 181                         tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
 182                                 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
 183                 break;
 184         case 10:
 185         default:
 186                 /* not needed */
 187                 break;
 188         }
 189
 190         switch (radeon_encoder->encoder_id) {
 191         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 192                 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
 193                 break;
 194         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 195                 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
 196                 break;
 197         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 198                 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
 199                 break;
 200         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 201                 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
 202                 break;
 203         default:
 204                 break;
 205         }
 206 }
 207
 208 void rs600_pm_misc(struct radeon_device *rdev)
 209 {
 210         int requested_index = rdev->pm.requested_power_state_index;
 211         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 212         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 213         u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
 214         u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
 215
 216         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 217                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 218                         tmp = RREG32(voltage->gpio.reg);
 219                         if (voltage->active_high)
 220                                 tmp |= voltage->gpio.mask;
 221                         else
 222                                 tmp &= ~(voltage->gpio.mask);
 223                         WREG32(voltage->gpio.reg, tmp);
 224                         if (voltage->delay)
 225                                 udelay(voltage->delay);
 226                 } else {
 227                         tmp = RREG32(voltage->gpio.reg);
 228                         if (voltage->active_high)
 229                                 tmp &= ~voltage->gpio.mask;
 230                         else
 231                                 tmp |= voltage->gpio.mask;
 232                         WREG32(voltage->gpio.reg, tmp);
 233                         if (voltage->delay)
 234                                 udelay(voltage->delay);
 235                 }
 236         } else if (voltage->type == VOLTAGE_VDDC)
 237                 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
 238
 239         dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
 240         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
 241         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
 242         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 243                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
 244                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
 245                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
 246                 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
 247                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
 248                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
 249                 }
 250         } else {
 251                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
 252                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
 253         }
 254         WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
 255
 256         dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
 257         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 258                 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
 259                 if (voltage->delay) {
 260                         dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
 261                         dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
 262                 } else
 263                         dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
 264         } else
 265                 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
 266         WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
 267
 268         hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
 269         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 270                 hdp_dyn_cntl &= ~HDP_FORCEON;
 271         else
 272                 hdp_dyn_cntl |= HDP_FORCEON;
 273         WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
 274 #if 0
 275         /* mc_host_dyn seems to cause hangs from time to time */
 276         mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
 277         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
 278                 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
 279         else
 280                 mc_host_dyn_cntl |= MC_HOST_FORCEON;
 281         WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
 282 #endif
 283         dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
 284         if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
 285                 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
 286         else
 287                 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
 288         WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
 289
 290         /* set pcie lanes */
 291         if ((rdev->flags & RADEON_IS_PCIE) &&
 292             !(rdev->flags & RADEON_IS_IGP) &&
 293             rdev->asic->pm.set_pcie_lanes &&
 294             (ps->pcie_lanes !=
 295              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 296                 radeon_set_pcie_lanes(rdev,
 297                                       ps->pcie_lanes);
 298                 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
 299         }
 300 }
 301
 302 void rs600_pm_prepare(struct radeon_device *rdev)
 303 {
 304         struct drm_device *ddev = rdev->ddev;
 305         struct drm_crtc *crtc;
 306         struct radeon_crtc *radeon_crtc;
 307         u32 tmp;
 308
 309         /* disable any active CRTCs */
 310         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 311                 radeon_crtc = to_radeon_crtc(crtc);
 312                 if (radeon_crtc->enabled) {
 313                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 314                         tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 315                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 316                 }
 317         }
 318 }
 319
 320 void rs600_pm_finish(struct radeon_device *rdev)
 321 {
 322         struct drm_device *ddev = rdev->ddev;
 323         struct drm_crtc *crtc;
 324         struct radeon_crtc *radeon_crtc;
 325         u32 tmp;
 326
 327         /* enable any active CRTCs */
 328         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 329                 radeon_crtc = to_radeon_crtc(crtc);
 330                 if (radeon_crtc->enabled) {
 331                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 332                         tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 333                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 334                 }
 335         }
 336 }
 337
 338 /* hpd for digital panel detect/disconnect */
 339 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 340 {
 341         u32 tmp;
 342         bool connected = false;
 343
 344         switch (hpd) {
 345         case RADEON_HPD_1:
 346                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
 347                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
 348                         connected = true;
 349                 break;
 350         case RADEON_HPD_2:
 351                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
 352                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
 353                         connected = true;
 354                 break;
 355         default:
 356                 break;
 357         }
 358         return connected;
 359 }
 360
 361 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 362                             enum radeon_hpd_id hpd)
 363 {
 364         u32 tmp;
 365         bool connected = rs600_hpd_sense(rdev, hpd);
 366
 367         switch (hpd) {
 368         case RADEON_HPD_1:
 369                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 370                 if (connected)
 371                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 372                 else
 373                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 374                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 375                 break;
 376         case RADEON_HPD_2:
 377                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 378                 if (connected)
 379                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 380                 else
 381                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 382                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 383                 break;
 384         default:
 385                 break;
 386         }
 387 }
 388
 389 void rs600_hpd_init(struct radeon_device *rdev)
 390 {
 391         struct drm_device *dev = rdev->ddev;
 392         struct drm_connector *connector;
 393         unsigned enable = 0;
 394
 395         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 396                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 397                 switch (radeon_connector->hpd.hpd) {
 398                 case RADEON_HPD_1:
 399                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 400                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
 401                         break;
 402                 case RADEON_HPD_2:
 403                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 404                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
 405                         break;
 406                 default:
 407                         break;
 408                 }
 409                 enable |= 1 << radeon_connector->hpd.hpd;
 410                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 411         }
 412         radeon_irq_kms_enable_hpd(rdev, enable);
 413 }
 414
 415 void rs600_hpd_fini(struct radeon_device *rdev)
 416 {
 417         struct drm_device *dev = rdev->ddev;
 418         struct drm_connector *connector;
 419         unsigned disable = 0;
 420
 421         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 422                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 423                 switch (radeon_connector->hpd.hpd) {
 424                 case RADEON_HPD_1:
 425                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 426                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
 427                         break;
 428                 case RADEON_HPD_2:
 429                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 430                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
 431                         break;
 432                 default:
 433                         break;
 434                 }
 435                 disable |= 1 << radeon_connector->hpd.hpd;
 436         }
 437         radeon_irq_kms_disable_hpd(rdev, disable);
 438 }
 439
 440 int rs600_asic_reset(struct radeon_device *rdev)
 441 {
 442         struct rv515_mc_save save;
 443         u32 status, tmp;
 444         int ret = 0;
 445
 446         status = RREG32(R_000E40_RBBM_STATUS);
 447         if (!G_000E40_GUI_ACTIVE(status)) {
 448                 return 0;
 449         }
 450         /* Stops all mc clients */
 451         rv515_mc_stop(rdev, &save);
 452         status = RREG32(R_000E40_RBBM_STATUS);
 453         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 454         /* stop CP */
 455         WREG32(RADEON_CP_CSQ_CNTL, 0);
 456         tmp = RREG32(RADEON_CP_RB_CNTL);
 457         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 458         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 459         WREG32(RADEON_CP_RB_WPTR, 0);
 460         WREG32(RADEON_CP_RB_CNTL, tmp);
 461         pci_save_state(rdev->pdev);
 462         /* disable bus mastering */
 463         pci_clear_master(rdev->pdev);
 464         mdelay(1);
 465         /* reset GA+VAP */
 466         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 467                                         S_0000F0_SOFT_RESET_GA(1));
 468         RREG32(R_0000F0_RBBM_SOFT_RESET);
 469         mdelay(500);
 470         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 471         mdelay(1);
 472         status = RREG32(R_000E40_RBBM_STATUS);
 473         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 474         /* reset CP */
 475         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 476         RREG32(R_0000F0_RBBM_SOFT_RESET);
 477         mdelay(500);
 478         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 479         mdelay(1);
 480         status = RREG32(R_000E40_RBBM_STATUS);
 481         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 482         /* reset MC */
 483         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
 484         RREG32(R_0000F0_RBBM_SOFT_RESET);
 485         mdelay(500);
 486         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 487         mdelay(1);
 488         status = RREG32(R_000E40_RBBM_STATUS);
 489         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 490         /* restore PCI & busmastering */
 491         pci_restore_state(rdev->pdev);
 492         /* Check if GPU is idle */
 493         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 494                 dev_err(rdev->dev, "failed to reset GPU\n");
 495                 ret = -1;
 496         } else
 497                 dev_info(rdev->dev, "GPU reset succeed\n");
 498         rv515_mc_resume(rdev, &save);
 499         return ret;
 500 }
 501
 502 /*
 503  * GART.
 504  */
 505 void rs600_gart_tlb_flush(struct radeon_device *rdev)
 506 {
 507         uint32_t tmp;
 508
 509         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 510         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 511         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 512
 513         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 514         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
 515         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 516
 517         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 518         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 519         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 520         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 521 }
 522
 523 static int rs600_gart_init(struct radeon_device *rdev)
 524 {
 525         int r;
 526
 527         if (rdev->gart.robj) {
 528                 WARN(1, "RS600 GART already initialized\n");
 529                 return 0;
 530         }
 531         /* Initialize common gart structure */
 532         r = radeon_gart_init(rdev);
 533         if (r) {
 534                 return r;
 535         }
 536         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 537         return radeon_gart_table_vram_alloc(rdev);
 538 }
 539
 540 static int rs600_gart_enable(struct radeon_device *rdev)
 541 {
 542         u32 tmp;
 543         int r, i;
 544
 545         if (rdev->gart.robj == NULL) {
 546                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 547                 return -EINVAL;
 548         }
 549         r = radeon_gart_table_vram_pin(rdev);
 550         if (r)
 551                 return r;
 552         radeon_gart_restore(rdev);
 553         /* Enable bus master */
 554         tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 555         WREG32(RADEON_BUS_CNTL, tmp);
 556         /* FIXME: setup default page */
 557         WREG32_MC(R_000100_MC_PT0_CNTL,
 558                   (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
 559                    S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 560
 561         for (i = 0; i < 19; i++) {
 562                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
 563                           S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
 564                           S_00016C_SYSTEM_ACCESS_MODE_MASK(
 565                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
 566                           S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
 567                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
 568                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
 569                           S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
 570                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
 571         }
 572         /* enable first context */
 573         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
 574                   S_000102_ENABLE_PAGE_TABLE(1) |
 575                   S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 576
 577         /* disable all other contexts */
 578         for (i = 1; i < 8; i++)
 579                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 580
 581         /* setup the page table */
 582         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 583                   rdev->gart.table_addr);
 584         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
 585         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
 586         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 587
 588         /* System context maps to VRAM space */
 589         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
 590         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 591
 592         /* enable page tables */
 593         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 594         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
 595         tmp = RREG32_MC(R_000009_MC_CNTL1);
 596         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
 597         rs600_gart_tlb_flush(rdev);
 598         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 599                  (unsigned)(rdev->mc.gtt_size >> 20),
 600                  (unsigned long long)rdev->gart.table_addr);
 601         rdev->gart.ready = true;
 602         return 0;
 603 }
 604
 605 static void rs600_gart_disable(struct radeon_device *rdev)
 606 {
 607         u32 tmp;
 608
 609         /* FIXME: disable out of gart access */
 610         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
 611         tmp = RREG32_MC(R_000009_MC_CNTL1);
 612         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
 613         radeon_gart_table_vram_unpin(rdev);
 614 }
 615
 616 static void rs600_gart_fini(struct radeon_device *rdev)
 617 {
 618         radeon_gart_fini(rdev);
 619         rs600_gart_disable(rdev);
 620         radeon_gart_table_vram_free(rdev);
 621 }
 622
 623 #define R600_PTE_VALID     (1 << 0)
 624 #define R600_PTE_SYSTEM    (1 << 1)
 625 #define R600_PTE_SNOOPED   (1 << 2)
 626 #define R600_PTE_READABLE  (1 << 5)
 627 #define R600_PTE_WRITEABLE (1 << 6)
 628
 629 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 630 {
 631         void __iomem *ptr = (void *)rdev->gart.ptr;
 632
 633         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 634                 return -EINVAL;
 635         }
 636         addr = addr & 0xFFFFFFFFFFFFF000ULL;
 637         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 638         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 639         writeq(addr, ptr + (i * 8));
 640         return 0;
 641 }
 642
 643 int rs600_irq_set(struct radeon_device *rdev)
 644 {
 645         uint32_t tmp = 0;
 646         uint32_t mode_int = 0;
 647         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
 648                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 649         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
 650                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 651         u32 hdmi0;
 652         if (ASIC_IS_DCE2(rdev))
 653                 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
 654                         ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 655         else
 656                 hdmi0 = 0;
 657
 658         if (!rdev->irq.installed) {
 659                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 660                 WREG32(R_000040_GEN_INT_CNTL, 0);
 661                 return -EINVAL;
 662         }
 663         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 664                 tmp |= S_000040_SW_INT_EN(1);
 665         }
 666         if (rdev->irq.crtc_vblank_int[0] ||
 667             atomic_read(&rdev->irq.pflip[0])) {
 668                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
 669         }
 670         if (rdev->irq.crtc_vblank_int[1] ||
 671             atomic_read(&rdev->irq.pflip[1])) {
 672                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
 673         }
 674         if (rdev->irq.hpd[0]) {
 675                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 676         }
 677         if (rdev->irq.hpd[1]) {
 678                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 679         }
 680         if (rdev->irq.afmt[0]) {
 681                 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 682         }
 683         WREG32(R_000040_GEN_INT_CNTL, tmp);
 684         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
 685         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
 686         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
 687         if (ASIC_IS_DCE2(rdev))
 688                 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 689         return 0;
 690 }
 691
 692 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
 693 {
 694         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
 695         uint32_t irq_mask = S_000044_SW_INT(1);
 696         u32 tmp;
 697
 698         if (G_000044_DISPLAY_INT_STAT(irqs)) {
 699                 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
 700                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 701                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
 702                                 S_006534_D1MODE_VBLANK_ACK(1));
 703                 }
 704                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 705                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
 706                                 S_006D34_D2MODE_VBLANK_ACK(1));
 707                 }
 708                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 709                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 710                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
 711                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 712                 }
 713                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 714                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 715                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
 716                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 717                 }
 718         } else {
 719                 rdev->irq.stat_regs.r500.disp_int = 0;
 720         }
 721
 722         if (ASIC_IS_DCE2(rdev)) {
 723                 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
 724                         S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
 725                 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
 726                         tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
 727                         tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
 728                         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
 729                 }
 730         } else
 731                 rdev->irq.stat_regs.r500.hdmi0_status = 0;
 732
 733         if (irqs) {
 734                 WREG32(R_000044_GEN_INT_STATUS, irqs);
 735         }
 736         return irqs & irq_mask;
 737 }
 738
 739 void rs600_irq_disable(struct radeon_device *rdev)
 740 {
 741         u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
 742                 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 743         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 744         WREG32(R_000040_GEN_INT_CNTL, 0);
 745         WREG32(R_006540_DxMODE_INT_MASK, 0);
 746         /* Wait and acknowledge irq */
 747         mdelay(1);
 748         rs600_irq_ack(rdev);
 749 }
 750
 751 int rs600_irq_process(struct radeon_device *rdev)
 752 {
 753         u32 status, msi_rearm;
 754         bool queue_hotplug = false;
 755         bool queue_hdmi = false;
 756
 757         status = rs600_irq_ack(rdev);
 758         if (!status &&
 759             !rdev->irq.stat_regs.r500.disp_int &&
 760             !rdev->irq.stat_regs.r500.hdmi0_status) {
 761                 return IRQ_NONE;
 762         }
 763         while (status ||
 764                rdev->irq.stat_regs.r500.disp_int ||
 765                rdev->irq.stat_regs.r500.hdmi0_status) {
 766                 /* SW interrupt */
 767                 if (G_000044_SW_INT(status)) {
 768                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 769                 }
 770                 /* Vertical blank interrupts */
 771                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 772                         if (rdev->irq.crtc_vblank_int[0]) {
 773                                 drm_handle_vblank(rdev->ddev, 0);
 774                                 rdev->pm.vblank_sync = true;
 775                                 wake_up(&rdev->irq.vblank_queue);
 776                         }
 777                         if (atomic_read(&rdev->irq.pflip[0]))
 778                                 radeon_crtc_handle_flip(rdev, 0);
 779                 }
 780                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 781                         if (rdev->irq.crtc_vblank_int[1]) {
 782                                 drm_handle_vblank(rdev->ddev, 1);
 783                                 rdev->pm.vblank_sync = true;
 784                                 wake_up(&rdev->irq.vblank_queue);
 785                         }
 786                         if (atomic_read(&rdev->irq.pflip[1]))
 787                                 radeon_crtc_handle_flip(rdev, 1);
 788                 }
 789                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 790                         queue_hotplug = true;
 791                         DRM_DEBUG("HPD1\n");
 792                 }
 793                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 794                         queue_hotplug = true;
 795                         DRM_DEBUG("HPD2\n");
 796                 }
 797                 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
 798                         queue_hdmi = true;
 799                         DRM_DEBUG("HDMI0\n");
 800                 }
 801                 status = rs600_irq_ack(rdev);
 802         }
 803         if (queue_hotplug)
 804                 schedule_work(&rdev->hotplug_work);
 805         if (queue_hdmi)
 806                 schedule_work(&rdev->audio_work);
 807         if (rdev->msi_enabled) {
 808                 switch (rdev->family) {
 809                 case CHIP_RS600:
 810                 case CHIP_RS690:
 811                 case CHIP_RS740:
 812                         msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
 813                         WREG32(RADEON_BUS_CNTL, msi_rearm);
 814                         WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
 815                         break;
 816                 default:
 817                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 818                         break;
 819                 }
 820         }
 821         return IRQ_HANDLED;
 822 }
 823
 824 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
 825 {
 826         if (crtc == 0)
 827                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
 828         else
 829                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
 830 }
 831
 832 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
 833 {
 834         unsigned i;
 835
 836         for (i = 0; i < rdev->usec_timeout; i++) {
 837                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
 838                         return 0;
 839                 udelay(1);
 840         }
 841         return -1;
 842 }
 843
 844 static void rs600_gpu_init(struct radeon_device *rdev)
 845 {
 846         r420_pipes_init(rdev);
 847         /* Wait for mc idle */
 848         if (rs600_mc_wait_for_idle(rdev))
 849                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 850 }
 851
 852 static void rs600_mc_init(struct radeon_device *rdev)
 853 {
 854         u64 base;
 855
 856         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
 857         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 858         rdev->mc.vram_is_ddr = true;
 859         rdev->mc.vram_width = 128;
 860         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 861         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 862         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 863         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 864         base = RREG32_MC(R_000004_MC_FB_LOCATION);
 865         base = G_000004_MC_FB_START(base) << 16;
 866         radeon_vram_location(rdev, &rdev->mc, base);
 867         rdev->mc.gtt_base_align = 0;
 868         radeon_gtt_location(rdev, &rdev->mc);
 869         radeon_update_bandwidth_info(rdev);
 870 }
 871
 872 void rs600_bandwidth_update(struct radeon_device *rdev)
 873 {
 874         struct drm_display_mode *mode0 = NULL;
 875         struct drm_display_mode *mode1 = NULL;
 876         u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
 877         /* FIXME: implement full support */
 878
 879         radeon_update_display_priority(rdev);
 880
 881         if (rdev->mode_info.crtcs[0]->base.enabled)
 882                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 883         if (rdev->mode_info.crtcs[1]->base.enabled)
 884                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 885
 886         rs690_line_buffer_adjust(rdev, mode0, mode1);
 887
 888         if (rdev->disp_priority == 2) {
 889                 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
 890                 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
 891                 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 892                 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 893                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 894                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 895                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 896                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 897         }
 898 }
 899
 900 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 901 {
 902         unsigned long flags;
 903         u32 r;
 904
 905         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 906         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 907                 S_000070_MC_IND_CITF_ARB0(1));
 908         r = RREG32(R_000074_MC_IND_DATA);
 909         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 910         return r;
 911 }
 912
 913 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 914 {
 915         unsigned long flags;
 916
 917         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 918         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 919                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
 920         WREG32(R_000074_MC_IND_DATA, v);
 921         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 922 }
 923
 924 static void rs600_debugfs(struct radeon_device *rdev)
 925 {
 926         if (r100_debugfs_rbbm_init(rdev))
 927                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 928 }
 929
 930 void rs600_set_safe_registers(struct radeon_device *rdev)
 931 {
 932         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
 933         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
 934 }
 935
 936 static void rs600_mc_program(struct radeon_device *rdev)
 937 {
 938         struct rv515_mc_save save;
 939
 940         /* Stops all mc clients */
 941         rv515_mc_stop(rdev, &save);
 942
 943         /* Wait for mc idle */
 944         if (rs600_mc_wait_for_idle(rdev))
 945                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 946
 947         /* FIXME: What does AGP means for such chipset ? */
 948         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
 949         WREG32_MC(R_000006_AGP_BASE, 0);
 950         WREG32_MC(R_000007_AGP_BASE_2, 0);
 951         /* Program MC */
 952         WREG32_MC(R_000004_MC_FB_LOCATION,
 953                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
 954                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
 955         WREG32(R_000134_HDP_FB_LOCATION,
 956                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 957
 958         rv515_mc_resume(rdev, &save);
 959 }
 960
 961 static int rs600_startup(struct radeon_device *rdev)
 962 {
 963         int r;
 964
 965         rs600_mc_program(rdev);
 966         /* Resume clock */
 967         rv515_clock_startup(rdev);
 968         /* Initialize GPU configuration (# pipes, ...) */
 969         rs600_gpu_init(rdev);
 970         /* Initialize GART (initialize after TTM so we can allocate
 971          * memory through TTM but finalize after TTM) */
 972         r = rs600_gart_enable(rdev);
 973         if (r)
 974                 return r;
 975
 976         /* allocate wb buffer */
 977         r = radeon_wb_init(rdev);
 978         if (r)
 979                 return r;
 980
 981         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 982         if (r) {
 983                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 984                 return r;
 985         }
 986
 987         /* Enable IRQ */
 988         if (!rdev->irq.installed) {
 989                 r = radeon_irq_kms_init(rdev);
 990                 if (r)
 991                         return r;
 992         }
 993
 994         rs600_irq_set(rdev);
 995         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 996         /* 1M ring buffer */
 997         r = r100_cp_init(rdev, 1024 * 1024);
 998         if (r) {
 999                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1000                 return r;
1001         }
1002
1003         r = radeon_ib_pool_init(rdev);
1004         if (r) {
1005                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1006                 return r;
1007         }
1008
1009         r = r600_audio_init(rdev);
1010         if (r) {
1011                 dev_err(rdev->dev, "failed initializing audio\n");
1012                 return r;
1013         }
1014
1015         return 0;
1016 }
1017
1018 int rs600_resume(struct radeon_device *rdev)
1019 {
1020         int r;
1021
1022         /* Make sur GART are not working */
1023         rs600_gart_disable(rdev);
1024         /* Resume clock before doing reset */
1025         rv515_clock_startup(rdev);
1026         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1027         if (radeon_asic_reset(rdev)) {
1028                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1029                         RREG32(R_000E40_RBBM_STATUS),
1030                         RREG32(R_0007C0_CP_STAT));
1031         }
1032         /* post */
1033         atom_asic_init(rdev->mode_info.atom_context);
1034         /* Resume clock after posting */
1035         rv515_clock_startup(rdev);
1036         /* Initialize surface registers */
1037         radeon_surface_init(rdev);
1038
1039         rdev->accel_working = true;
1040         r = rs600_startup(rdev);
1041         if (r) {
1042                 rdev->accel_working = false;
1043         }
1044         return r;
1045 }
1046
1047 int rs600_suspend(struct radeon_device *rdev)
1048 {
1049         radeon_pm_suspend(rdev);
1050         r600_audio_fini(rdev);
1051         r100_cp_disable(rdev);
1052         radeon_wb_disable(rdev);
1053         rs600_irq_disable(rdev);
1054         rs600_gart_disable(rdev);
1055         return 0;
1056 }
1057
1058 void rs600_fini(struct radeon_device *rdev)
1059 {
1060         radeon_pm_fini(rdev);
1061         r600_audio_fini(rdev);
1062         r100_cp_fini(rdev);
1063         radeon_wb_fini(rdev);
1064         radeon_ib_pool_fini(rdev);
1065         radeon_gem_fini(rdev);
1066         rs600_gart_fini(rdev);
1067         radeon_irq_kms_fini(rdev);
1068         radeon_fence_driver_fini(rdev);
1069         radeon_bo_fini(rdev);
1070         radeon_atombios_fini(rdev);
1071         kfree(rdev->bios);
1072         rdev->bios = NULL;
1073 }
1074
1075 int rs600_init(struct radeon_device *rdev)
1076 {
1077         int r;
1078
1079         /* Disable VGA */
1080         rv515_vga_render_disable(rdev);
1081         /* Initialize scratch registers */
1082         radeon_scratch_init(rdev);
1083         /* Initialize surface registers */
1084         radeon_surface_init(rdev);
1085         /* restore some register to sane defaults */
1086         r100_restore_sanity(rdev);
1087         /* BIOS */
1088         if (!radeon_get_bios(rdev)) {
1089                 if (ASIC_IS_AVIVO(rdev))
1090                         return -EINVAL;
1091         }
1092         if (rdev->is_atom_bios) {
1093                 r = radeon_atombios_init(rdev);
1094                 if (r)
1095                         return r;
1096         } else {
1097                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1098                 return -EINVAL;
1099         }
1100         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1101         if (radeon_asic_reset(rdev)) {
1102                 dev_warn(rdev->dev,
1103                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1104                         RREG32(R_000E40_RBBM_STATUS),
1105                         RREG32(R_0007C0_CP_STAT));
1106         }
1107         /* check if cards are posted or not */
1108         if (radeon_boot_test_post_card(rdev) == false)
1109                 return -EINVAL;
1110
1111         /* Initialize clocks */
1112         radeon_get_clock_info(rdev->ddev);
1113         /* initialize memory controller */
1114         rs600_mc_init(rdev);
1115         rs600_debugfs(rdev);
1116         /* Fence driver */
1117         r = radeon_fence_driver_init(rdev);
1118         if (r)
1119                 return r;
1120         /* Memory manager */
1121         r = radeon_bo_init(rdev);
1122         if (r)
1123                 return r;
1124         r = rs600_gart_init(rdev);
1125         if (r)
1126                 return r;
1127         rs600_set_safe_registers(rdev);
1128
1129         /* Initialize power management */
1130         radeon_pm_init(rdev);
1131
1132         rdev->accel_working = true;
1133         r = rs600_startup(rdev);
1134         if (r) {
1135                 /* Somethings want wront with the accel init stop accel */
1136                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1137                 r100_cp_fini(rdev);
1138                 radeon_wb_fini(rdev);
1139                 radeon_ib_pool_fini(rdev);
1140                 rs600_gart_fini(rdev);
1141                 radeon_irq_kms_fini(rdev);
1142                 rdev->accel_working = false;
1143         }
1144         return 0;
1145 }